if_stge.c revision 257176
1160641Syongari/* $NetBSD: if_stge.c,v 1.32 2005/12/11 12:22:49 christos Exp $ */ 2160641Syongari 3160641Syongari/*- 4160641Syongari * Copyright (c) 2001 The NetBSD Foundation, Inc. 5160641Syongari * All rights reserved. 6160641Syongari * 7160641Syongari * This code is derived from software contributed to The NetBSD Foundation 8160641Syongari * by Jason R. Thorpe. 9160641Syongari * 10160641Syongari * Redistribution and use in source and binary forms, with or without 11160641Syongari * modification, are permitted provided that the following conditions 12160641Syongari * are met: 13160641Syongari * 1. Redistributions of source code must retain the above copyright 14160641Syongari * notice, this list of conditions and the following disclaimer. 15160641Syongari * 2. Redistributions in binary form must reproduce the above copyright 16160641Syongari * notice, this list of conditions and the following disclaimer in the 17160641Syongari * documentation and/or other materials provided with the distribution. 18160641Syongari * 19160641Syongari * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20160641Syongari * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21160641Syongari * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22160641Syongari * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23160641Syongari * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24160641Syongari * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25160641Syongari * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26160641Syongari * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27160641Syongari * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28160641Syongari * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29160641Syongari * POSSIBILITY OF SUCH DAMAGE. 30160641Syongari */ 31160641Syongari 32160641Syongari/* 33160641Syongari * Device driver for the Sundance Tech. TC9021 10/100/1000 34160641Syongari * Ethernet controller. 35160641Syongari */ 36160641Syongari 37160641Syongari#include <sys/cdefs.h> 38160641Syongari__FBSDID("$FreeBSD: head/sys/dev/stge/if_stge.c 257176 2013-10-26 17:58:36Z glebius $"); 39160641Syongari 40160641Syongari#ifdef HAVE_KERNEL_OPTION_HEADERS 41160641Syongari#include "opt_device_polling.h" 42160641Syongari#endif 43160641Syongari 44160641Syongari#include <sys/param.h> 45160641Syongari#include <sys/systm.h> 46160641Syongari#include <sys/endian.h> 47160641Syongari#include <sys/mbuf.h> 48160641Syongari#include <sys/malloc.h> 49160641Syongari#include <sys/kernel.h> 50160641Syongari#include <sys/module.h> 51160641Syongari#include <sys/socket.h> 52160641Syongari#include <sys/sockio.h> 53160641Syongari#include <sys/sysctl.h> 54160641Syongari#include <sys/taskqueue.h> 55160641Syongari 56160641Syongari#include <net/bpf.h> 57160641Syongari#include <net/ethernet.h> 58160641Syongari#include <net/if.h> 59257176Sglebius#include <net/if_var.h> 60160641Syongari#include <net/if_dl.h> 61160641Syongari#include <net/if_media.h> 62160641Syongari#include <net/if_types.h> 63160641Syongari#include <net/if_vlan_var.h> 64160641Syongari 65160641Syongari#include <machine/bus.h> 66160641Syongari#include <machine/resource.h> 67160641Syongari#include <sys/bus.h> 68160641Syongari#include <sys/rman.h> 69160641Syongari 70160641Syongari#include <dev/mii/mii.h> 71226995Smarius#include <dev/mii/mii_bitbang.h> 72160641Syongari#include <dev/mii/miivar.h> 73160641Syongari 74160641Syongari#include <dev/pci/pcireg.h> 75160641Syongari#include <dev/pci/pcivar.h> 76160641Syongari 77160641Syongari#include <dev/stge/if_stgereg.h> 78160641Syongari 79160641Syongari#define STGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 80160641Syongari 81160641SyongariMODULE_DEPEND(stge, pci, 1, 1, 1); 82160641SyongariMODULE_DEPEND(stge, ether, 1, 1, 1); 83160641SyongariMODULE_DEPEND(stge, miibus, 1, 1, 1); 84160641Syongari 85160641Syongari/* "device miibus" required. See GENERIC if you get errors here. */ 86160641Syongari#include "miibus_if.h" 87160641Syongari 88160641Syongari/* 89160641Syongari * Devices supported by this driver. 90160641Syongari */ 91226995Smariusstatic const struct stge_product { 92160641Syongari uint16_t stge_vendorid; 93160641Syongari uint16_t stge_deviceid; 94160641Syongari const char *stge_name; 95242625Sdim} stge_products[] = { 96160641Syongari { VENDOR_SUNDANCETI, DEVICEID_SUNDANCETI_ST1023, 97160641Syongari "Sundance ST-1023 Gigabit Ethernet" }, 98160641Syongari 99160641Syongari { VENDOR_SUNDANCETI, DEVICEID_SUNDANCETI_ST2021, 100160641Syongari "Sundance ST-2021 Gigabit Ethernet" }, 101160641Syongari 102160641Syongari { VENDOR_TAMARACK, DEVICEID_TAMARACK_TC9021, 103160641Syongari "Tamarack TC9021 Gigabit Ethernet" }, 104160641Syongari 105160641Syongari { VENDOR_TAMARACK, DEVICEID_TAMARACK_TC9021_ALT, 106160641Syongari "Tamarack TC9021 Gigabit Ethernet" }, 107160641Syongari 108160641Syongari /* 109160641Syongari * The Sundance sample boards use the Sundance vendor ID, 110160641Syongari * but the Tamarack product ID. 111160641Syongari */ 112160641Syongari { VENDOR_SUNDANCETI, DEVICEID_TAMARACK_TC9021, 113160641Syongari "Sundance TC9021 Gigabit Ethernet" }, 114160641Syongari 115160641Syongari { VENDOR_SUNDANCETI, DEVICEID_TAMARACK_TC9021_ALT, 116160641Syongari "Sundance TC9021 Gigabit Ethernet" }, 117160641Syongari 118160641Syongari { VENDOR_DLINK, DEVICEID_DLINK_DL4000, 119160641Syongari "D-Link DL-4000 Gigabit Ethernet" }, 120160641Syongari 121160641Syongari { VENDOR_ANTARES, DEVICEID_ANTARES_TC9021, 122160641Syongari "Antares Gigabit Ethernet" } 123160641Syongari}; 124160641Syongari 125160641Syongaristatic int stge_probe(device_t); 126160641Syongaristatic int stge_attach(device_t); 127160641Syongaristatic int stge_detach(device_t); 128173839Syongaristatic int stge_shutdown(device_t); 129160641Syongaristatic int stge_suspend(device_t); 130160641Syongaristatic int stge_resume(device_t); 131160641Syongari 132160641Syongaristatic int stge_encap(struct stge_softc *, struct mbuf **); 133160641Syongaristatic void stge_start(struct ifnet *); 134160641Syongaristatic void stge_start_locked(struct ifnet *); 135169157Syongaristatic void stge_watchdog(struct stge_softc *); 136160641Syongaristatic int stge_ioctl(struct ifnet *, u_long, caddr_t); 137160641Syongaristatic void stge_init(void *); 138160641Syongaristatic void stge_init_locked(struct stge_softc *); 139160641Syongaristatic void stge_vlan_setup(struct stge_softc *); 140160641Syongaristatic void stge_stop(struct stge_softc *); 141160641Syongaristatic void stge_start_tx(struct stge_softc *); 142160641Syongaristatic void stge_start_rx(struct stge_softc *); 143160641Syongaristatic void stge_stop_tx(struct stge_softc *); 144160641Syongaristatic void stge_stop_rx(struct stge_softc *); 145160641Syongari 146160641Syongaristatic void stge_reset(struct stge_softc *, uint32_t); 147160641Syongaristatic int stge_eeprom_wait(struct stge_softc *); 148160641Syongaristatic void stge_read_eeprom(struct stge_softc *, int, uint16_t *); 149160641Syongaristatic void stge_tick(void *); 150160641Syongaristatic void stge_stats_update(struct stge_softc *); 151160641Syongaristatic void stge_set_filter(struct stge_softc *); 152160641Syongaristatic void stge_set_multi(struct stge_softc *); 153160641Syongari 154160641Syongaristatic void stge_link_task(void *, int); 155160641Syongaristatic void stge_intr(void *); 156160641Syongaristatic __inline int stge_tx_error(struct stge_softc *); 157160641Syongaristatic void stge_txeof(struct stge_softc *); 158193096Sattiliostatic int stge_rxeof(struct stge_softc *); 159160641Syongaristatic __inline void stge_discard_rxbuf(struct stge_softc *, int); 160160641Syongaristatic int stge_newbuf(struct stge_softc *, int); 161160641Syongari#ifndef __NO_STRICT_ALIGNMENT 162160641Syongaristatic __inline struct mbuf *stge_fixup_rx(struct stge_softc *, struct mbuf *); 163160641Syongari#endif 164160641Syongari 165160641Syongaristatic int stge_miibus_readreg(device_t, int, int); 166160641Syongaristatic int stge_miibus_writereg(device_t, int, int, int); 167160641Syongaristatic void stge_miibus_statchg(device_t); 168160641Syongaristatic int stge_mediachange(struct ifnet *); 169160641Syongaristatic void stge_mediastatus(struct ifnet *, struct ifmediareq *); 170160641Syongari 171160641Syongaristatic void stge_dmamap_cb(void *, bus_dma_segment_t *, int, int); 172160641Syongaristatic int stge_dma_alloc(struct stge_softc *); 173160641Syongaristatic void stge_dma_free(struct stge_softc *); 174160641Syongaristatic void stge_dma_wait(struct stge_softc *); 175160641Syongaristatic void stge_init_tx_ring(struct stge_softc *); 176160641Syongaristatic int stge_init_rx_ring(struct stge_softc *); 177160641Syongari#ifdef DEVICE_POLLING 178193096Sattiliostatic int stge_poll(struct ifnet *, enum poll_cmd, int); 179160641Syongari#endif 180160641Syongari 181175315Syongaristatic void stge_setwol(struct stge_softc *); 182160641Syongaristatic int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 183160641Syongaristatic int sysctl_hw_stge_rxint_nframe(SYSCTL_HANDLER_ARGS); 184160641Syongaristatic int sysctl_hw_stge_rxint_dmawait(SYSCTL_HANDLER_ARGS); 185160641Syongari 186226995Smarius/* 187226995Smarius * MII bit-bang glue 188226995Smarius */ 189226995Smariusstatic uint32_t stge_mii_bitbang_read(device_t); 190226995Smariusstatic void stge_mii_bitbang_write(device_t, uint32_t); 191226995Smarius 192226995Smariusstatic const struct mii_bitbang_ops stge_mii_bitbang_ops = { 193226995Smarius stge_mii_bitbang_read, 194226995Smarius stge_mii_bitbang_write, 195226995Smarius { 196226995Smarius PC_MgmtData, /* MII_BIT_MDO */ 197226995Smarius PC_MgmtData, /* MII_BIT_MDI */ 198226995Smarius PC_MgmtClk, /* MII_BIT_MDC */ 199226995Smarius PC_MgmtDir, /* MII_BIT_DIR_HOST_PHY */ 200226995Smarius 0, /* MII_BIT_DIR_PHY_HOST */ 201226995Smarius } 202226995Smarius}; 203226995Smarius 204160641Syongaristatic device_method_t stge_methods[] = { 205160641Syongari /* Device interface */ 206160641Syongari DEVMETHOD(device_probe, stge_probe), 207160641Syongari DEVMETHOD(device_attach, stge_attach), 208160641Syongari DEVMETHOD(device_detach, stge_detach), 209160641Syongari DEVMETHOD(device_shutdown, stge_shutdown), 210160641Syongari DEVMETHOD(device_suspend, stge_suspend), 211160641Syongari DEVMETHOD(device_resume, stge_resume), 212160641Syongari 213160641Syongari /* MII interface */ 214160641Syongari DEVMETHOD(miibus_readreg, stge_miibus_readreg), 215160641Syongari DEVMETHOD(miibus_writereg, stge_miibus_writereg), 216160641Syongari DEVMETHOD(miibus_statchg, stge_miibus_statchg), 217160641Syongari 218227848Smarius DEVMETHOD_END 219160641Syongari}; 220160641Syongari 221160641Syongaristatic driver_t stge_driver = { 222160641Syongari "stge", 223160641Syongari stge_methods, 224160641Syongari sizeof(struct stge_softc) 225160641Syongari}; 226160641Syongari 227160641Syongaristatic devclass_t stge_devclass; 228160641Syongari 229160641SyongariDRIVER_MODULE(stge, pci, stge_driver, stge_devclass, 0, 0); 230160641SyongariDRIVER_MODULE(miibus, stge, miibus_driver, miibus_devclass, 0, 0); 231160641Syongari 232160641Syongaristatic struct resource_spec stge_res_spec_io[] = { 233160641Syongari { SYS_RES_IOPORT, PCIR_BAR(0), RF_ACTIVE }, 234160641Syongari { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 235160641Syongari { -1, 0, 0 } 236160641Syongari}; 237160641Syongari 238160641Syongaristatic struct resource_spec stge_res_spec_mem[] = { 239160641Syongari { SYS_RES_MEMORY, PCIR_BAR(1), RF_ACTIVE }, 240160641Syongari { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 241160641Syongari { -1, 0, 0 } 242160641Syongari}; 243160641Syongari 244160641Syongari/* 245226995Smarius * stge_mii_bitbang_read: [mii bit-bang interface function] 246226995Smarius * 247226995Smarius * Read the MII serial port for the MII bit-bang module. 248160641Syongari */ 249226995Smariusstatic uint32_t 250226995Smariusstge_mii_bitbang_read(device_t dev) 251160641Syongari{ 252226995Smarius struct stge_softc *sc; 253226995Smarius uint32_t val; 254160641Syongari 255226995Smarius sc = device_get_softc(dev); 256160641Syongari 257226995Smarius val = CSR_READ_1(sc, STGE_PhyCtrl); 258226995Smarius CSR_BARRIER(sc, STGE_PhyCtrl, 1, 259226995Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 260226995Smarius return (val); 261160641Syongari} 262160641Syongari 263160641Syongari/* 264226995Smarius * stge_mii_bitbang_write: [mii big-bang interface function] 265226995Smarius * 266226995Smarius * Write the MII serial port for the MII bit-bang module. 267160641Syongari */ 268160641Syongaristatic void 269226995Smariusstge_mii_bitbang_write(device_t dev, uint32_t val) 270160641Syongari{ 271226995Smarius struct stge_softc *sc; 272160641Syongari 273226995Smarius sc = device_get_softc(dev); 274160641Syongari 275226995Smarius CSR_WRITE_1(sc, STGE_PhyCtrl, val); 276226995Smarius CSR_BARRIER(sc, STGE_PhyCtrl, 1, 277226995Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 278160641Syongari} 279160641Syongari 280160641Syongari/* 281160641Syongari * sc_miibus_readreg: [mii interface function] 282160641Syongari * 283160641Syongari * Read a PHY register on the MII of the TC9021. 284160641Syongari */ 285160641Syongaristatic int 286160641Syongaristge_miibus_readreg(device_t dev, int phy, int reg) 287160641Syongari{ 288160641Syongari struct stge_softc *sc; 289226995Smarius int error, val; 290160641Syongari 291160641Syongari sc = device_get_softc(dev); 292160641Syongari 293160641Syongari if (reg == STGE_PhyCtrl) { 294160641Syongari /* XXX allow ip1000phy read STGE_PhyCtrl register. */ 295160641Syongari STGE_MII_LOCK(sc); 296160641Syongari error = CSR_READ_1(sc, STGE_PhyCtrl); 297160641Syongari STGE_MII_UNLOCK(sc); 298160641Syongari return (error); 299160641Syongari } 300160641Syongari 301160641Syongari STGE_MII_LOCK(sc); 302226995Smarius val = mii_bitbang_readreg(dev, &stge_mii_bitbang_ops, phy, reg); 303160641Syongari STGE_MII_UNLOCK(sc); 304226995Smarius return (val); 305160641Syongari} 306160641Syongari 307160641Syongari/* 308160641Syongari * stge_miibus_writereg: [mii interface function] 309160641Syongari * 310160641Syongari * Write a PHY register on the MII of the TC9021. 311160641Syongari */ 312160641Syongaristatic int 313160641Syongaristge_miibus_writereg(device_t dev, int phy, int reg, int val) 314160641Syongari{ 315160641Syongari struct stge_softc *sc; 316160641Syongari 317160641Syongari sc = device_get_softc(dev); 318160641Syongari 319160641Syongari STGE_MII_LOCK(sc); 320226995Smarius mii_bitbang_writereg(dev, &stge_mii_bitbang_ops, phy, reg, val); 321160641Syongari STGE_MII_UNLOCK(sc); 322160641Syongari return (0); 323160641Syongari} 324160641Syongari 325160641Syongari/* 326160641Syongari * stge_miibus_statchg: [mii interface function] 327160641Syongari * 328160641Syongari * Callback from MII layer when media changes. 329160641Syongari */ 330160641Syongaristatic void 331160641Syongaristge_miibus_statchg(device_t dev) 332160641Syongari{ 333160641Syongari struct stge_softc *sc; 334160641Syongari 335160641Syongari sc = device_get_softc(dev); 336160641Syongari taskqueue_enqueue(taskqueue_swi, &sc->sc_link_task); 337160641Syongari} 338160641Syongari 339160641Syongari/* 340160641Syongari * stge_mediastatus: [ifmedia interface function] 341160641Syongari * 342160641Syongari * Get the current interface media status. 343160641Syongari */ 344160641Syongaristatic void 345160641Syongaristge_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 346160641Syongari{ 347160641Syongari struct stge_softc *sc; 348160641Syongari struct mii_data *mii; 349160641Syongari 350160641Syongari sc = ifp->if_softc; 351160641Syongari mii = device_get_softc(sc->sc_miibus); 352160641Syongari 353160641Syongari mii_pollstat(mii); 354160641Syongari ifmr->ifm_status = mii->mii_media_status; 355160641Syongari ifmr->ifm_active = mii->mii_media_active; 356160641Syongari} 357160641Syongari 358160641Syongari/* 359160641Syongari * stge_mediachange: [ifmedia interface function] 360160641Syongari * 361160641Syongari * Set hardware to newly-selected media. 362160641Syongari */ 363160641Syongaristatic int 364160641Syongaristge_mediachange(struct ifnet *ifp) 365160641Syongari{ 366160641Syongari struct stge_softc *sc; 367160641Syongari struct mii_data *mii; 368160641Syongari 369160641Syongari sc = ifp->if_softc; 370160641Syongari mii = device_get_softc(sc->sc_miibus); 371160641Syongari mii_mediachg(mii); 372160641Syongari 373160641Syongari return (0); 374160641Syongari} 375160641Syongari 376160641Syongaristatic int 377160641Syongaristge_eeprom_wait(struct stge_softc *sc) 378160641Syongari{ 379160641Syongari int i; 380160641Syongari 381160641Syongari for (i = 0; i < STGE_TIMEOUT; i++) { 382160641Syongari DELAY(1000); 383160641Syongari if ((CSR_READ_2(sc, STGE_EepromCtrl) & EC_EepromBusy) == 0) 384160641Syongari return (0); 385160641Syongari } 386160641Syongari return (1); 387160641Syongari} 388160641Syongari 389160641Syongari/* 390160641Syongari * stge_read_eeprom: 391160641Syongari * 392160641Syongari * Read data from the serial EEPROM. 393160641Syongari */ 394160641Syongaristatic void 395160641Syongaristge_read_eeprom(struct stge_softc *sc, int offset, uint16_t *data) 396160641Syongari{ 397160641Syongari 398160641Syongari if (stge_eeprom_wait(sc)) 399160641Syongari device_printf(sc->sc_dev, "EEPROM failed to come ready\n"); 400160641Syongari 401160641Syongari CSR_WRITE_2(sc, STGE_EepromCtrl, 402160641Syongari EC_EepromAddress(offset) | EC_EepromOpcode(EC_OP_RR)); 403160641Syongari if (stge_eeprom_wait(sc)) 404160641Syongari device_printf(sc->sc_dev, "EEPROM read timed out\n"); 405160641Syongari *data = CSR_READ_2(sc, STGE_EepromData); 406160641Syongari} 407160641Syongari 408160641Syongari 409160641Syongaristatic int 410160641Syongaristge_probe(device_t dev) 411160641Syongari{ 412226995Smarius const struct stge_product *sp; 413160641Syongari int i; 414160641Syongari uint16_t vendor, devid; 415160641Syongari 416160641Syongari vendor = pci_get_vendor(dev); 417160641Syongari devid = pci_get_device(dev); 418160641Syongari sp = stge_products; 419160641Syongari for (i = 0; i < sizeof(stge_products)/sizeof(stge_products[0]); 420160641Syongari i++, sp++) { 421160641Syongari if (vendor == sp->stge_vendorid && 422160641Syongari devid == sp->stge_deviceid) { 423160641Syongari device_set_desc(dev, sp->stge_name); 424160641Syongari return (BUS_PROBE_DEFAULT); 425160641Syongari } 426160641Syongari } 427160641Syongari 428160641Syongari return (ENXIO); 429160641Syongari} 430160641Syongari 431160641Syongaristatic int 432160641Syongaristge_attach(device_t dev) 433160641Syongari{ 434160641Syongari struct stge_softc *sc; 435160641Syongari struct ifnet *ifp; 436160641Syongari uint8_t enaddr[ETHER_ADDR_LEN]; 437213893Smarius int error, flags, i; 438160641Syongari uint16_t cmd; 439160641Syongari uint32_t val; 440160641Syongari 441160641Syongari error = 0; 442160641Syongari sc = device_get_softc(dev); 443160641Syongari sc->sc_dev = dev; 444160641Syongari 445160641Syongari mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 446160641Syongari MTX_DEF); 447160641Syongari mtx_init(&sc->sc_mii_mtx, "stge_mii_mutex", NULL, MTX_DEF); 448160641Syongari callout_init_mtx(&sc->sc_tick_ch, &sc->sc_mtx, 0); 449160641Syongari TASK_INIT(&sc->sc_link_task, 0, stge_link_task, sc); 450160641Syongari 451160641Syongari /* 452160641Syongari * Map the device. 453160641Syongari */ 454160641Syongari pci_enable_busmaster(dev); 455160641Syongari cmd = pci_read_config(dev, PCIR_COMMAND, 2); 456160641Syongari val = pci_read_config(dev, PCIR_BAR(1), 4); 457254263Sscottl if (PCI_BAR_IO(val)) 458160641Syongari sc->sc_spec = stge_res_spec_mem; 459160641Syongari else { 460160641Syongari val = pci_read_config(dev, PCIR_BAR(0), 4); 461254263Sscottl if (!PCI_BAR_IO(val)) { 462160641Syongari device_printf(sc->sc_dev, "couldn't locate IO BAR\n"); 463160641Syongari error = ENXIO; 464160641Syongari goto fail; 465160641Syongari } 466160641Syongari sc->sc_spec = stge_res_spec_io; 467160641Syongari } 468160641Syongari error = bus_alloc_resources(dev, sc->sc_spec, sc->sc_res); 469160641Syongari if (error != 0) { 470160641Syongari device_printf(dev, "couldn't allocate %s resources\n", 471160641Syongari sc->sc_spec == stge_res_spec_mem ? "memory" : "I/O"); 472160641Syongari goto fail; 473160641Syongari } 474160641Syongari sc->sc_rev = pci_get_revid(dev); 475160641Syongari 476160641Syongari SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 477160641Syongari SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 478160641Syongari "rxint_nframe", CTLTYPE_INT|CTLFLAG_RW, &sc->sc_rxint_nframe, 0, 479160641Syongari sysctl_hw_stge_rxint_nframe, "I", "stge rx interrupt nframe"); 480160641Syongari 481160641Syongari SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 482160641Syongari SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 483160641Syongari "rxint_dmawait", CTLTYPE_INT|CTLFLAG_RW, &sc->sc_rxint_dmawait, 0, 484160641Syongari sysctl_hw_stge_rxint_dmawait, "I", "stge rx interrupt dmawait"); 485160641Syongari 486160641Syongari /* Pull in device tunables. */ 487160641Syongari sc->sc_rxint_nframe = STGE_RXINT_NFRAME_DEFAULT; 488160641Syongari error = resource_int_value(device_get_name(dev), device_get_unit(dev), 489160641Syongari "rxint_nframe", &sc->sc_rxint_nframe); 490160641Syongari if (error == 0) { 491160641Syongari if (sc->sc_rxint_nframe < STGE_RXINT_NFRAME_MIN || 492160641Syongari sc->sc_rxint_nframe > STGE_RXINT_NFRAME_MAX) { 493160641Syongari device_printf(dev, "rxint_nframe value out of range; " 494160641Syongari "using default: %d\n", STGE_RXINT_NFRAME_DEFAULT); 495160641Syongari sc->sc_rxint_nframe = STGE_RXINT_NFRAME_DEFAULT; 496160641Syongari } 497160641Syongari } 498160641Syongari 499160641Syongari sc->sc_rxint_dmawait = STGE_RXINT_DMAWAIT_DEFAULT; 500160641Syongari error = resource_int_value(device_get_name(dev), device_get_unit(dev), 501160641Syongari "rxint_dmawait", &sc->sc_rxint_dmawait); 502160641Syongari if (error == 0) { 503160641Syongari if (sc->sc_rxint_dmawait < STGE_RXINT_DMAWAIT_MIN || 504160641Syongari sc->sc_rxint_dmawait > STGE_RXINT_DMAWAIT_MAX) { 505160641Syongari device_printf(dev, "rxint_dmawait value out of range; " 506160641Syongari "using default: %d\n", STGE_RXINT_DMAWAIT_DEFAULT); 507160641Syongari sc->sc_rxint_dmawait = STGE_RXINT_DMAWAIT_DEFAULT; 508160641Syongari } 509160641Syongari } 510160641Syongari 511160641Syongari if ((error = stge_dma_alloc(sc) != 0)) 512160641Syongari goto fail; 513160641Syongari 514160641Syongari /* 515160641Syongari * Determine if we're copper or fiber. It affects how we 516160641Syongari * reset the card. 517160641Syongari */ 518160641Syongari if (CSR_READ_4(sc, STGE_AsicCtrl) & AC_PhyMedia) 519160641Syongari sc->sc_usefiber = 1; 520160641Syongari else 521160641Syongari sc->sc_usefiber = 0; 522160641Syongari 523160641Syongari /* Load LED configuration from EEPROM. */ 524160641Syongari stge_read_eeprom(sc, STGE_EEPROM_LEDMode, &sc->sc_led); 525160641Syongari 526160641Syongari /* 527160641Syongari * Reset the chip to a known state. 528160641Syongari */ 529160641Syongari STGE_LOCK(sc); 530160641Syongari stge_reset(sc, STGE_RESET_FULL); 531160641Syongari STGE_UNLOCK(sc); 532160641Syongari 533160641Syongari /* 534160641Syongari * Reading the station address from the EEPROM doesn't seem 535160641Syongari * to work, at least on my sample boards. Instead, since 536160641Syongari * the reset sequence does AutoInit, read it from the station 537160641Syongari * address registers. For Sundance 1023 you can only read it 538160641Syongari * from EEPROM. 539160641Syongari */ 540160641Syongari if (pci_get_device(dev) != DEVICEID_SUNDANCETI_ST1023) { 541160641Syongari uint16_t v; 542160641Syongari 543160641Syongari v = CSR_READ_2(sc, STGE_StationAddress0); 544160641Syongari enaddr[0] = v & 0xff; 545160641Syongari enaddr[1] = v >> 8; 546160641Syongari v = CSR_READ_2(sc, STGE_StationAddress1); 547160641Syongari enaddr[2] = v & 0xff; 548160641Syongari enaddr[3] = v >> 8; 549160641Syongari v = CSR_READ_2(sc, STGE_StationAddress2); 550160641Syongari enaddr[4] = v & 0xff; 551160641Syongari enaddr[5] = v >> 8; 552160641Syongari sc->sc_stge1023 = 0; 553160641Syongari } else { 554160641Syongari uint16_t myaddr[ETHER_ADDR_LEN / 2]; 555160641Syongari for (i = 0; i <ETHER_ADDR_LEN / 2; i++) { 556160641Syongari stge_read_eeprom(sc, STGE_EEPROM_StationAddress0 + i, 557160641Syongari &myaddr[i]); 558160641Syongari myaddr[i] = le16toh(myaddr[i]); 559160641Syongari } 560160641Syongari bcopy(myaddr, enaddr, sizeof(enaddr)); 561160641Syongari sc->sc_stge1023 = 1; 562160641Syongari } 563160641Syongari 564160641Syongari ifp = sc->sc_ifp = if_alloc(IFT_ETHER); 565160641Syongari if (ifp == NULL) { 566160641Syongari device_printf(sc->sc_dev, "failed to if_alloc()\n"); 567160641Syongari error = ENXIO; 568160641Syongari goto fail; 569160641Syongari } 570160641Syongari 571160641Syongari ifp->if_softc = sc; 572160641Syongari if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 573160641Syongari ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 574160641Syongari ifp->if_ioctl = stge_ioctl; 575160641Syongari ifp->if_start = stge_start; 576160641Syongari ifp->if_init = stge_init; 577160641Syongari ifp->if_snd.ifq_drv_maxlen = STGE_TX_RING_CNT - 1; 578160641Syongari IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 579160641Syongari IFQ_SET_READY(&ifp->if_snd); 580160641Syongari /* Revision B3 and earlier chips have checksum bug. */ 581160641Syongari if (sc->sc_rev >= 0x0c) { 582160641Syongari ifp->if_hwassist = STGE_CSUM_FEATURES; 583160641Syongari ifp->if_capabilities = IFCAP_HWCSUM; 584160641Syongari } else { 585160641Syongari ifp->if_hwassist = 0; 586160641Syongari ifp->if_capabilities = 0; 587160641Syongari } 588175315Syongari ifp->if_capabilities |= IFCAP_WOL_MAGIC; 589160641Syongari ifp->if_capenable = ifp->if_capabilities; 590160641Syongari 591160641Syongari /* 592160641Syongari * Read some important bits from the PhyCtrl register. 593160641Syongari */ 594160641Syongari sc->sc_PhyCtrl = CSR_READ_1(sc, STGE_PhyCtrl) & 595160641Syongari (PC_PhyDuplexPolarity | PC_PhyLnkPolarity); 596160641Syongari 597160641Syongari /* Set up MII bus. */ 598215297Smarius flags = MIIF_DOPAUSE; 599213893Smarius if (sc->sc_rev >= 0x40 && sc->sc_rev <= 0x4e) 600213893Smarius flags |= MIIF_MACPRIV0; 601213893Smarius error = mii_attach(sc->sc_dev, &sc->sc_miibus, ifp, stge_mediachange, 602213893Smarius stge_mediastatus, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 603213893Smarius flags); 604213893Smarius if (error != 0) { 605213893Smarius device_printf(sc->sc_dev, "attaching PHYs failed\n"); 606160641Syongari goto fail; 607160641Syongari } 608160641Syongari 609160641Syongari ether_ifattach(ifp, enaddr); 610160641Syongari 611160641Syongari /* VLAN capability setup */ 612160641Syongari ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 613160641Syongari if (sc->sc_rev >= 0x0c) 614160641Syongari ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 615160641Syongari ifp->if_capenable = ifp->if_capabilities; 616160641Syongari#ifdef DEVICE_POLLING 617160641Syongari ifp->if_capabilities |= IFCAP_POLLING; 618160641Syongari#endif 619160641Syongari /* 620160641Syongari * Tell the upper layer(s) we support long frames. 621160641Syongari * Must appear after the call to ether_ifattach() because 622160641Syongari * ether_ifattach() sets ifi_hdrlen to the default value. 623160641Syongari */ 624160641Syongari ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 625160641Syongari 626160641Syongari /* 627160641Syongari * The manual recommends disabling early transmit, so we 628160641Syongari * do. It's disabled anyway, if using IP checksumming, 629160641Syongari * since the entire packet must be in the FIFO in order 630160641Syongari * for the chip to perform the checksum. 631160641Syongari */ 632160641Syongari sc->sc_txthresh = 0x0fff; 633160641Syongari 634160641Syongari /* 635160641Syongari * Disable MWI if the PCI layer tells us to. 636160641Syongari */ 637160641Syongari sc->sc_DMACtrl = 0; 638160641Syongari if ((cmd & PCIM_CMD_MWRICEN) == 0) 639160641Syongari sc->sc_DMACtrl |= DMAC_MWIDisable; 640160641Syongari 641160641Syongari /* 642160641Syongari * Hookup IRQ 643160641Syongari */ 644160641Syongari error = bus_setup_intr(dev, sc->sc_res[1], INTR_TYPE_NET | INTR_MPSAFE, 645166901Spiso NULL, stge_intr, sc, &sc->sc_ih); 646160641Syongari if (error != 0) { 647160641Syongari ether_ifdetach(ifp); 648160641Syongari device_printf(sc->sc_dev, "couldn't set up IRQ\n"); 649160641Syongari sc->sc_ifp = NULL; 650160641Syongari goto fail; 651160641Syongari } 652160641Syongari 653160641Syongarifail: 654160641Syongari if (error != 0) 655160641Syongari stge_detach(dev); 656160641Syongari 657160641Syongari return (error); 658160641Syongari} 659160641Syongari 660160641Syongaristatic int 661160641Syongaristge_detach(device_t dev) 662160641Syongari{ 663160641Syongari struct stge_softc *sc; 664160641Syongari struct ifnet *ifp; 665160641Syongari 666160641Syongari sc = device_get_softc(dev); 667160641Syongari 668160641Syongari ifp = sc->sc_ifp; 669160641Syongari#ifdef DEVICE_POLLING 670160641Syongari if (ifp && ifp->if_capenable & IFCAP_POLLING) 671160641Syongari ether_poll_deregister(ifp); 672160641Syongari#endif 673160641Syongari if (device_is_attached(dev)) { 674160641Syongari STGE_LOCK(sc); 675160641Syongari /* XXX */ 676160641Syongari sc->sc_detach = 1; 677160641Syongari stge_stop(sc); 678160641Syongari STGE_UNLOCK(sc); 679160641Syongari callout_drain(&sc->sc_tick_ch); 680160641Syongari taskqueue_drain(taskqueue_swi, &sc->sc_link_task); 681160641Syongari ether_ifdetach(ifp); 682160641Syongari } 683160641Syongari 684160641Syongari if (sc->sc_miibus != NULL) { 685160641Syongari device_delete_child(dev, sc->sc_miibus); 686160641Syongari sc->sc_miibus = NULL; 687160641Syongari } 688160641Syongari bus_generic_detach(dev); 689160641Syongari stge_dma_free(sc); 690160641Syongari 691160641Syongari if (ifp != NULL) { 692160641Syongari if_free(ifp); 693160641Syongari sc->sc_ifp = NULL; 694160641Syongari } 695160641Syongari 696160641Syongari if (sc->sc_ih) { 697160641Syongari bus_teardown_intr(dev, sc->sc_res[1], sc->sc_ih); 698160641Syongari sc->sc_ih = NULL; 699160641Syongari } 700160641Syongari bus_release_resources(dev, sc->sc_spec, sc->sc_res); 701160641Syongari 702160641Syongari mtx_destroy(&sc->sc_mii_mtx); 703160641Syongari mtx_destroy(&sc->sc_mtx); 704160641Syongari 705160641Syongari return (0); 706160641Syongari} 707160641Syongari 708160641Syongaristruct stge_dmamap_arg { 709160641Syongari bus_addr_t stge_busaddr; 710160641Syongari}; 711160641Syongari 712160641Syongaristatic void 713160641Syongaristge_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 714160641Syongari{ 715160641Syongari struct stge_dmamap_arg *ctx; 716160641Syongari 717160641Syongari if (error != 0) 718160641Syongari return; 719160641Syongari 720160641Syongari ctx = (struct stge_dmamap_arg *)arg; 721160641Syongari ctx->stge_busaddr = segs[0].ds_addr; 722160641Syongari} 723160641Syongari 724160641Syongaristatic int 725160641Syongaristge_dma_alloc(struct stge_softc *sc) 726160641Syongari{ 727160641Syongari struct stge_dmamap_arg ctx; 728160641Syongari struct stge_txdesc *txd; 729160641Syongari struct stge_rxdesc *rxd; 730160641Syongari int error, i; 731160641Syongari 732160641Syongari /* create parent tag. */ 733166165Smarius error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev),/* parent */ 734160641Syongari 1, 0, /* algnmnt, boundary */ 735160641Syongari STGE_DMA_MAXADDR, /* lowaddr */ 736160641Syongari BUS_SPACE_MAXADDR, /* highaddr */ 737160641Syongari NULL, NULL, /* filter, filterarg */ 738160641Syongari BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 739160641Syongari 0, /* nsegments */ 740160641Syongari BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 741160641Syongari 0, /* flags */ 742160641Syongari NULL, NULL, /* lockfunc, lockarg */ 743160641Syongari &sc->sc_cdata.stge_parent_tag); 744160641Syongari if (error != 0) { 745160641Syongari device_printf(sc->sc_dev, "failed to create parent DMA tag\n"); 746160641Syongari goto fail; 747160641Syongari } 748160641Syongari /* create tag for Tx ring. */ 749160641Syongari error = bus_dma_tag_create(sc->sc_cdata.stge_parent_tag,/* parent */ 750160641Syongari STGE_RING_ALIGN, 0, /* algnmnt, boundary */ 751160641Syongari BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 752160641Syongari BUS_SPACE_MAXADDR, /* highaddr */ 753160641Syongari NULL, NULL, /* filter, filterarg */ 754160641Syongari STGE_TX_RING_SZ, /* maxsize */ 755160641Syongari 1, /* nsegments */ 756160641Syongari STGE_TX_RING_SZ, /* maxsegsize */ 757160641Syongari 0, /* flags */ 758160641Syongari NULL, NULL, /* lockfunc, lockarg */ 759160641Syongari &sc->sc_cdata.stge_tx_ring_tag); 760160641Syongari if (error != 0) { 761160641Syongari device_printf(sc->sc_dev, 762160641Syongari "failed to allocate Tx ring DMA tag\n"); 763160641Syongari goto fail; 764160641Syongari } 765160641Syongari 766160641Syongari /* create tag for Rx ring. */ 767160641Syongari error = bus_dma_tag_create(sc->sc_cdata.stge_parent_tag,/* parent */ 768160641Syongari STGE_RING_ALIGN, 0, /* algnmnt, boundary */ 769160641Syongari BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 770160641Syongari BUS_SPACE_MAXADDR, /* highaddr */ 771160641Syongari NULL, NULL, /* filter, filterarg */ 772160641Syongari STGE_RX_RING_SZ, /* maxsize */ 773160641Syongari 1, /* nsegments */ 774160641Syongari STGE_RX_RING_SZ, /* maxsegsize */ 775160641Syongari 0, /* flags */ 776160641Syongari NULL, NULL, /* lockfunc, lockarg */ 777160641Syongari &sc->sc_cdata.stge_rx_ring_tag); 778160641Syongari if (error != 0) { 779160641Syongari device_printf(sc->sc_dev, 780160641Syongari "failed to allocate Rx ring DMA tag\n"); 781160641Syongari goto fail; 782160641Syongari } 783160641Syongari 784160641Syongari /* create tag for Tx buffers. */ 785160641Syongari error = bus_dma_tag_create(sc->sc_cdata.stge_parent_tag,/* parent */ 786160641Syongari 1, 0, /* algnmnt, boundary */ 787160641Syongari BUS_SPACE_MAXADDR, /* lowaddr */ 788160641Syongari BUS_SPACE_MAXADDR, /* highaddr */ 789160641Syongari NULL, NULL, /* filter, filterarg */ 790160641Syongari MCLBYTES * STGE_MAXTXSEGS, /* maxsize */ 791160641Syongari STGE_MAXTXSEGS, /* nsegments */ 792160641Syongari MCLBYTES, /* maxsegsize */ 793160641Syongari 0, /* flags */ 794160641Syongari NULL, NULL, /* lockfunc, lockarg */ 795160641Syongari &sc->sc_cdata.stge_tx_tag); 796160641Syongari if (error != 0) { 797160641Syongari device_printf(sc->sc_dev, "failed to allocate Tx DMA tag\n"); 798160641Syongari goto fail; 799160641Syongari } 800160641Syongari 801160641Syongari /* create tag for Rx buffers. */ 802160641Syongari error = bus_dma_tag_create(sc->sc_cdata.stge_parent_tag,/* parent */ 803160641Syongari 1, 0, /* algnmnt, boundary */ 804160641Syongari BUS_SPACE_MAXADDR, /* lowaddr */ 805160641Syongari BUS_SPACE_MAXADDR, /* highaddr */ 806160641Syongari NULL, NULL, /* filter, filterarg */ 807160641Syongari MCLBYTES, /* maxsize */ 808160641Syongari 1, /* nsegments */ 809160641Syongari MCLBYTES, /* maxsegsize */ 810160641Syongari 0, /* flags */ 811160641Syongari NULL, NULL, /* lockfunc, lockarg */ 812160641Syongari &sc->sc_cdata.stge_rx_tag); 813160641Syongari if (error != 0) { 814160641Syongari device_printf(sc->sc_dev, "failed to allocate Rx DMA tag\n"); 815160641Syongari goto fail; 816160641Syongari } 817160641Syongari 818160641Syongari /* allocate DMA'able memory and load the DMA map for Tx ring. */ 819160641Syongari error = bus_dmamem_alloc(sc->sc_cdata.stge_tx_ring_tag, 820219545Smarius (void **)&sc->sc_rdata.stge_tx_ring, BUS_DMA_NOWAIT | 821219545Smarius BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->sc_cdata.stge_tx_ring_map); 822160641Syongari if (error != 0) { 823160641Syongari device_printf(sc->sc_dev, 824160641Syongari "failed to allocate DMA'able memory for Tx ring\n"); 825160641Syongari goto fail; 826160641Syongari } 827160641Syongari 828160641Syongari ctx.stge_busaddr = 0; 829160641Syongari error = bus_dmamap_load(sc->sc_cdata.stge_tx_ring_tag, 830160641Syongari sc->sc_cdata.stge_tx_ring_map, sc->sc_rdata.stge_tx_ring, 831160641Syongari STGE_TX_RING_SZ, stge_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 832160641Syongari if (error != 0 || ctx.stge_busaddr == 0) { 833160641Syongari device_printf(sc->sc_dev, 834160641Syongari "failed to load DMA'able memory for Tx ring\n"); 835160641Syongari goto fail; 836160641Syongari } 837160641Syongari sc->sc_rdata.stge_tx_ring_paddr = ctx.stge_busaddr; 838160641Syongari 839160641Syongari /* allocate DMA'able memory and load the DMA map for Rx ring. */ 840160641Syongari error = bus_dmamem_alloc(sc->sc_cdata.stge_rx_ring_tag, 841219545Smarius (void **)&sc->sc_rdata.stge_rx_ring, BUS_DMA_NOWAIT | 842219545Smarius BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->sc_cdata.stge_rx_ring_map); 843160641Syongari if (error != 0) { 844160641Syongari device_printf(sc->sc_dev, 845160641Syongari "failed to allocate DMA'able memory for Rx ring\n"); 846160641Syongari goto fail; 847160641Syongari } 848160641Syongari 849160641Syongari ctx.stge_busaddr = 0; 850160641Syongari error = bus_dmamap_load(sc->sc_cdata.stge_rx_ring_tag, 851160641Syongari sc->sc_cdata.stge_rx_ring_map, sc->sc_rdata.stge_rx_ring, 852160641Syongari STGE_RX_RING_SZ, stge_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 853160641Syongari if (error != 0 || ctx.stge_busaddr == 0) { 854160641Syongari device_printf(sc->sc_dev, 855160641Syongari "failed to load DMA'able memory for Rx ring\n"); 856160641Syongari goto fail; 857160641Syongari } 858160641Syongari sc->sc_rdata.stge_rx_ring_paddr = ctx.stge_busaddr; 859160641Syongari 860160641Syongari /* create DMA maps for Tx buffers. */ 861160641Syongari for (i = 0; i < STGE_TX_RING_CNT; i++) { 862160641Syongari txd = &sc->sc_cdata.stge_txdesc[i]; 863160641Syongari txd->tx_m = NULL; 864160641Syongari txd->tx_dmamap = 0; 865160641Syongari error = bus_dmamap_create(sc->sc_cdata.stge_tx_tag, 0, 866160641Syongari &txd->tx_dmamap); 867160641Syongari if (error != 0) { 868160641Syongari device_printf(sc->sc_dev, 869160641Syongari "failed to create Tx dmamap\n"); 870160641Syongari goto fail; 871160641Syongari } 872160641Syongari } 873160641Syongari /* create DMA maps for Rx buffers. */ 874160641Syongari if ((error = bus_dmamap_create(sc->sc_cdata.stge_rx_tag, 0, 875160641Syongari &sc->sc_cdata.stge_rx_sparemap)) != 0) { 876160641Syongari device_printf(sc->sc_dev, "failed to create spare Rx dmamap\n"); 877160641Syongari goto fail; 878160641Syongari } 879160641Syongari for (i = 0; i < STGE_RX_RING_CNT; i++) { 880160641Syongari rxd = &sc->sc_cdata.stge_rxdesc[i]; 881160641Syongari rxd->rx_m = NULL; 882160641Syongari rxd->rx_dmamap = 0; 883160641Syongari error = bus_dmamap_create(sc->sc_cdata.stge_rx_tag, 0, 884160641Syongari &rxd->rx_dmamap); 885160641Syongari if (error != 0) { 886160641Syongari device_printf(sc->sc_dev, 887160641Syongari "failed to create Rx dmamap\n"); 888160641Syongari goto fail; 889160641Syongari } 890160641Syongari } 891160641Syongari 892160641Syongarifail: 893160641Syongari return (error); 894160641Syongari} 895160641Syongari 896160641Syongaristatic void 897160641Syongaristge_dma_free(struct stge_softc *sc) 898160641Syongari{ 899160641Syongari struct stge_txdesc *txd; 900160641Syongari struct stge_rxdesc *rxd; 901160641Syongari int i; 902160641Syongari 903160641Syongari /* Tx ring */ 904160641Syongari if (sc->sc_cdata.stge_tx_ring_tag) { 905160641Syongari if (sc->sc_cdata.stge_tx_ring_map) 906160641Syongari bus_dmamap_unload(sc->sc_cdata.stge_tx_ring_tag, 907160641Syongari sc->sc_cdata.stge_tx_ring_map); 908160641Syongari if (sc->sc_cdata.stge_tx_ring_map && 909160641Syongari sc->sc_rdata.stge_tx_ring) 910160641Syongari bus_dmamem_free(sc->sc_cdata.stge_tx_ring_tag, 911160641Syongari sc->sc_rdata.stge_tx_ring, 912160641Syongari sc->sc_cdata.stge_tx_ring_map); 913160641Syongari sc->sc_rdata.stge_tx_ring = NULL; 914160641Syongari sc->sc_cdata.stge_tx_ring_map = 0; 915160641Syongari bus_dma_tag_destroy(sc->sc_cdata.stge_tx_ring_tag); 916160641Syongari sc->sc_cdata.stge_tx_ring_tag = NULL; 917160641Syongari } 918160641Syongari /* Rx ring */ 919160641Syongari if (sc->sc_cdata.stge_rx_ring_tag) { 920160641Syongari if (sc->sc_cdata.stge_rx_ring_map) 921160641Syongari bus_dmamap_unload(sc->sc_cdata.stge_rx_ring_tag, 922160641Syongari sc->sc_cdata.stge_rx_ring_map); 923160641Syongari if (sc->sc_cdata.stge_rx_ring_map && 924160641Syongari sc->sc_rdata.stge_rx_ring) 925160641Syongari bus_dmamem_free(sc->sc_cdata.stge_rx_ring_tag, 926160641Syongari sc->sc_rdata.stge_rx_ring, 927160641Syongari sc->sc_cdata.stge_rx_ring_map); 928160641Syongari sc->sc_rdata.stge_rx_ring = NULL; 929160641Syongari sc->sc_cdata.stge_rx_ring_map = 0; 930160641Syongari bus_dma_tag_destroy(sc->sc_cdata.stge_rx_ring_tag); 931160641Syongari sc->sc_cdata.stge_rx_ring_tag = NULL; 932160641Syongari } 933160641Syongari /* Tx buffers */ 934160641Syongari if (sc->sc_cdata.stge_tx_tag) { 935160641Syongari for (i = 0; i < STGE_TX_RING_CNT; i++) { 936160641Syongari txd = &sc->sc_cdata.stge_txdesc[i]; 937160641Syongari if (txd->tx_dmamap) { 938160641Syongari bus_dmamap_destroy(sc->sc_cdata.stge_tx_tag, 939160641Syongari txd->tx_dmamap); 940160641Syongari txd->tx_dmamap = 0; 941160641Syongari } 942160641Syongari } 943160641Syongari bus_dma_tag_destroy(sc->sc_cdata.stge_tx_tag); 944160641Syongari sc->sc_cdata.stge_tx_tag = NULL; 945160641Syongari } 946160641Syongari /* Rx buffers */ 947160641Syongari if (sc->sc_cdata.stge_rx_tag) { 948160641Syongari for (i = 0; i < STGE_RX_RING_CNT; i++) { 949160641Syongari rxd = &sc->sc_cdata.stge_rxdesc[i]; 950160641Syongari if (rxd->rx_dmamap) { 951160641Syongari bus_dmamap_destroy(sc->sc_cdata.stge_rx_tag, 952160641Syongari rxd->rx_dmamap); 953160641Syongari rxd->rx_dmamap = 0; 954160641Syongari } 955160641Syongari } 956160641Syongari if (sc->sc_cdata.stge_rx_sparemap) { 957160641Syongari bus_dmamap_destroy(sc->sc_cdata.stge_rx_tag, 958160641Syongari sc->sc_cdata.stge_rx_sparemap); 959160641Syongari sc->sc_cdata.stge_rx_sparemap = 0; 960160641Syongari } 961160641Syongari bus_dma_tag_destroy(sc->sc_cdata.stge_rx_tag); 962160641Syongari sc->sc_cdata.stge_rx_tag = NULL; 963160641Syongari } 964160641Syongari 965160641Syongari if (sc->sc_cdata.stge_parent_tag) { 966160641Syongari bus_dma_tag_destroy(sc->sc_cdata.stge_parent_tag); 967160641Syongari sc->sc_cdata.stge_parent_tag = NULL; 968160641Syongari } 969160641Syongari} 970160641Syongari 971160641Syongari/* 972160641Syongari * stge_shutdown: 973160641Syongari * 974160641Syongari * Make sure the interface is stopped at reboot time. 975160641Syongari */ 976173839Syongaristatic int 977160641Syongaristge_shutdown(device_t dev) 978160641Syongari{ 979160641Syongari 980175315Syongari return (stge_suspend(dev)); 981175315Syongari} 982160641Syongari 983175315Syongaristatic void 984175315Syongaristge_setwol(struct stge_softc *sc) 985175315Syongari{ 986175315Syongari struct ifnet *ifp; 987175315Syongari uint8_t v; 988173839Syongari 989175315Syongari STGE_LOCK_ASSERT(sc); 990175315Syongari 991175315Syongari ifp = sc->sc_ifp; 992175315Syongari v = CSR_READ_1(sc, STGE_WakeEvent); 993175315Syongari /* Disable all WOL bits. */ 994175315Syongari v &= ~(WE_WakePktEnable | WE_MagicPktEnable | WE_LinkEventEnable | 995175315Syongari WE_WakeOnLanEnable); 996175315Syongari if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 997175315Syongari v |= WE_MagicPktEnable | WE_WakeOnLanEnable; 998175315Syongari CSR_WRITE_1(sc, STGE_WakeEvent, v); 999175315Syongari /* Reset Tx and prevent transmission. */ 1000175315Syongari CSR_WRITE_4(sc, STGE_AsicCtrl, 1001175315Syongari CSR_READ_4(sc, STGE_AsicCtrl) | AC_TxReset); 1002175315Syongari /* 1003175315Syongari * TC9021 automatically reset link speed to 100Mbps when it's put 1004175315Syongari * into sleep so there is no need to try to resetting link speed. 1005175315Syongari */ 1006160641Syongari} 1007160641Syongari 1008160641Syongaristatic int 1009160641Syongaristge_suspend(device_t dev) 1010160641Syongari{ 1011160641Syongari struct stge_softc *sc; 1012160641Syongari 1013160641Syongari sc = device_get_softc(dev); 1014160641Syongari 1015160641Syongari STGE_LOCK(sc); 1016160641Syongari stge_stop(sc); 1017160641Syongari sc->sc_suspended = 1; 1018175315Syongari stge_setwol(sc); 1019160641Syongari STGE_UNLOCK(sc); 1020160641Syongari 1021160641Syongari return (0); 1022160641Syongari} 1023160641Syongari 1024160641Syongaristatic int 1025160641Syongaristge_resume(device_t dev) 1026160641Syongari{ 1027160641Syongari struct stge_softc *sc; 1028160641Syongari struct ifnet *ifp; 1029175315Syongari uint8_t v; 1030160641Syongari 1031160641Syongari sc = device_get_softc(dev); 1032160641Syongari 1033160641Syongari STGE_LOCK(sc); 1034175315Syongari /* 1035175315Syongari * Clear WOL bits, so special frames wouldn't interfere 1036175315Syongari * normal Rx operation anymore. 1037175315Syongari */ 1038175315Syongari v = CSR_READ_1(sc, STGE_WakeEvent); 1039175315Syongari v &= ~(WE_WakePktEnable | WE_MagicPktEnable | WE_LinkEventEnable | 1040175315Syongari WE_WakeOnLanEnable); 1041175315Syongari CSR_WRITE_1(sc, STGE_WakeEvent, v); 1042160641Syongari ifp = sc->sc_ifp; 1043160641Syongari if (ifp->if_flags & IFF_UP) 1044160641Syongari stge_init_locked(sc); 1045160641Syongari 1046160641Syongari sc->sc_suspended = 0; 1047160641Syongari STGE_UNLOCK(sc); 1048160641Syongari 1049160641Syongari return (0); 1050160641Syongari} 1051160641Syongari 1052160641Syongaristatic void 1053160641Syongaristge_dma_wait(struct stge_softc *sc) 1054160641Syongari{ 1055160641Syongari int i; 1056160641Syongari 1057160641Syongari for (i = 0; i < STGE_TIMEOUT; i++) { 1058160641Syongari DELAY(2); 1059160641Syongari if ((CSR_READ_4(sc, STGE_DMACtrl) & DMAC_TxDMAInProg) == 0) 1060160641Syongari break; 1061160641Syongari } 1062160641Syongari 1063160641Syongari if (i == STGE_TIMEOUT) 1064160641Syongari device_printf(sc->sc_dev, "DMA wait timed out\n"); 1065160641Syongari} 1066160641Syongari 1067160641Syongaristatic int 1068160641Syongaristge_encap(struct stge_softc *sc, struct mbuf **m_head) 1069160641Syongari{ 1070160641Syongari struct stge_txdesc *txd; 1071160641Syongari struct stge_tfd *tfd; 1072161235Syongari struct mbuf *m; 1073160641Syongari bus_dma_segment_t txsegs[STGE_MAXTXSEGS]; 1074160641Syongari int error, i, nsegs, si; 1075160641Syongari uint64_t csum_flags, tfc; 1076160641Syongari 1077160641Syongari STGE_LOCK_ASSERT(sc); 1078160641Syongari 1079160641Syongari if ((txd = STAILQ_FIRST(&sc->sc_cdata.stge_txfreeq)) == NULL) 1080160641Syongari return (ENOBUFS); 1081160641Syongari 1082160641Syongari error = bus_dmamap_load_mbuf_sg(sc->sc_cdata.stge_tx_tag, 1083161235Syongari txd->tx_dmamap, *m_head, txsegs, &nsegs, 0); 1084160641Syongari if (error == EFBIG) { 1085243857Sglebius m = m_collapse(*m_head, M_NOWAIT, STGE_MAXTXSEGS); 1086161235Syongari if (m == NULL) { 1087161235Syongari m_freem(*m_head); 1088161235Syongari *m_head = NULL; 1089160641Syongari return (ENOMEM); 1090160641Syongari } 1091161235Syongari *m_head = m; 1092160641Syongari error = bus_dmamap_load_mbuf_sg(sc->sc_cdata.stge_tx_tag, 1093161235Syongari txd->tx_dmamap, *m_head, txsegs, &nsegs, 0); 1094160641Syongari if (error != 0) { 1095161235Syongari m_freem(*m_head); 1096161235Syongari *m_head = NULL; 1097160641Syongari return (error); 1098160641Syongari } 1099160641Syongari } else if (error != 0) 1100160641Syongari return (error); 1101160641Syongari if (nsegs == 0) { 1102161235Syongari m_freem(*m_head); 1103161235Syongari *m_head = NULL; 1104160641Syongari return (EIO); 1105160641Syongari } 1106160641Syongari 1107161235Syongari m = *m_head; 1108160641Syongari csum_flags = 0; 1109160641Syongari if ((m->m_pkthdr.csum_flags & STGE_CSUM_FEATURES) != 0) { 1110160641Syongari if (m->m_pkthdr.csum_flags & CSUM_IP) 1111160641Syongari csum_flags |= TFD_IPChecksumEnable; 1112160641Syongari if (m->m_pkthdr.csum_flags & CSUM_TCP) 1113160641Syongari csum_flags |= TFD_TCPChecksumEnable; 1114160641Syongari else if (m->m_pkthdr.csum_flags & CSUM_UDP) 1115160641Syongari csum_flags |= TFD_UDPChecksumEnable; 1116160641Syongari } 1117160641Syongari 1118160641Syongari si = sc->sc_cdata.stge_tx_prod; 1119160641Syongari tfd = &sc->sc_rdata.stge_tx_ring[si]; 1120160641Syongari for (i = 0; i < nsegs; i++) 1121160641Syongari tfd->tfd_frags[i].frag_word0 = 1122160641Syongari htole64(FRAG_ADDR(txsegs[i].ds_addr) | 1123160641Syongari FRAG_LEN(txsegs[i].ds_len)); 1124160641Syongari sc->sc_cdata.stge_tx_cnt++; 1125160641Syongari 1126160641Syongari tfc = TFD_FrameId(si) | TFD_WordAlign(TFD_WordAlign_disable) | 1127160641Syongari TFD_FragCount(nsegs) | csum_flags; 1128160641Syongari if (sc->sc_cdata.stge_tx_cnt >= STGE_TX_HIWAT) 1129160641Syongari tfc |= TFD_TxDMAIndicate; 1130160641Syongari 1131160641Syongari /* Update producer index. */ 1132160641Syongari sc->sc_cdata.stge_tx_prod = (si + 1) % STGE_TX_RING_CNT; 1133160641Syongari 1134160641Syongari /* Check if we have a VLAN tag to insert. */ 1135162375Sandre if (m->m_flags & M_VLANTAG) 1136162375Sandre tfc |= (TFD_VLANTagInsert | TFD_VID(m->m_pkthdr.ether_vtag)); 1137160641Syongari tfd->tfd_control = htole64(tfc); 1138160641Syongari 1139160641Syongari /* Update Tx Queue. */ 1140160641Syongari STAILQ_REMOVE_HEAD(&sc->sc_cdata.stge_txfreeq, tx_q); 1141160641Syongari STAILQ_INSERT_TAIL(&sc->sc_cdata.stge_txbusyq, txd, tx_q); 1142160641Syongari txd->tx_m = m; 1143160641Syongari 1144160641Syongari /* Sync descriptors. */ 1145160641Syongari bus_dmamap_sync(sc->sc_cdata.stge_tx_tag, txd->tx_dmamap, 1146160641Syongari BUS_DMASYNC_PREWRITE); 1147160641Syongari bus_dmamap_sync(sc->sc_cdata.stge_tx_ring_tag, 1148160641Syongari sc->sc_cdata.stge_tx_ring_map, 1149160641Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1150160641Syongari 1151160641Syongari return (0); 1152160641Syongari} 1153160641Syongari 1154160641Syongari/* 1155160641Syongari * stge_start: [ifnet interface function] 1156160641Syongari * 1157160641Syongari * Start packet transmission on the interface. 1158160641Syongari */ 1159160641Syongaristatic void 1160160641Syongaristge_start(struct ifnet *ifp) 1161160641Syongari{ 1162160641Syongari struct stge_softc *sc; 1163160641Syongari 1164160641Syongari sc = ifp->if_softc; 1165160641Syongari STGE_LOCK(sc); 1166160641Syongari stge_start_locked(ifp); 1167160641Syongari STGE_UNLOCK(sc); 1168160641Syongari} 1169160641Syongari 1170160641Syongaristatic void 1171160641Syongaristge_start_locked(struct ifnet *ifp) 1172160641Syongari{ 1173160641Syongari struct stge_softc *sc; 1174160641Syongari struct mbuf *m_head; 1175160641Syongari int enq; 1176160641Syongari 1177160641Syongari sc = ifp->if_softc; 1178160641Syongari 1179160641Syongari STGE_LOCK_ASSERT(sc); 1180160641Syongari 1181160641Syongari if ((ifp->if_drv_flags & (IFF_DRV_RUNNING|IFF_DRV_OACTIVE)) != 1182169158Syongari IFF_DRV_RUNNING || sc->sc_link == 0) 1183160641Syongari return; 1184160641Syongari 1185160641Syongari for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) { 1186160641Syongari if (sc->sc_cdata.stge_tx_cnt >= STGE_TX_HIWAT) { 1187160641Syongari ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1188160641Syongari break; 1189160641Syongari } 1190160641Syongari 1191160641Syongari IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1192160641Syongari if (m_head == NULL) 1193160641Syongari break; 1194160641Syongari /* 1195160641Syongari * Pack the data into the transmit ring. If we 1196160641Syongari * don't have room, set the OACTIVE flag and wait 1197160641Syongari * for the NIC to drain the ring. 1198160641Syongari */ 1199160641Syongari if (stge_encap(sc, &m_head)) { 1200160641Syongari if (m_head == NULL) 1201160641Syongari break; 1202160641Syongari IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1203160641Syongari ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1204160641Syongari break; 1205160641Syongari } 1206160641Syongari 1207160641Syongari enq++; 1208160641Syongari /* 1209160641Syongari * If there's a BPF listener, bounce a copy of this frame 1210160641Syongari * to him. 1211160641Syongari */ 1212167190Scsjp ETHER_BPF_MTAP(ifp, m_head); 1213160641Syongari } 1214160641Syongari 1215160641Syongari if (enq > 0) { 1216160641Syongari /* Transmit */ 1217160641Syongari CSR_WRITE_4(sc, STGE_DMACtrl, DMAC_TxDMAPollNow); 1218160641Syongari 1219160641Syongari /* Set a timeout in case the chip goes out to lunch. */ 1220169157Syongari sc->sc_watchdog_timer = 5; 1221160641Syongari } 1222160641Syongari} 1223160641Syongari 1224160641Syongari/* 1225169157Syongari * stge_watchdog: 1226160641Syongari * 1227160641Syongari * Watchdog timer handler. 1228160641Syongari */ 1229160641Syongaristatic void 1230169157Syongaristge_watchdog(struct stge_softc *sc) 1231160641Syongari{ 1232169157Syongari struct ifnet *ifp; 1233160641Syongari 1234169157Syongari STGE_LOCK_ASSERT(sc); 1235160641Syongari 1236169157Syongari if (sc->sc_watchdog_timer == 0 || --sc->sc_watchdog_timer) 1237169157Syongari return; 1238169157Syongari 1239169157Syongari ifp = sc->sc_ifp; 1240160641Syongari if_printf(sc->sc_ifp, "device timeout\n"); 1241160641Syongari ifp->if_oerrors++; 1242212972Syongari ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1243160641Syongari stge_init_locked(sc); 1244169159Syongari if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1245169159Syongari stge_start_locked(ifp); 1246160641Syongari} 1247160641Syongari 1248160641Syongari/* 1249160641Syongari * stge_ioctl: [ifnet interface function] 1250160641Syongari * 1251160641Syongari * Handle control requests from the operator. 1252160641Syongari */ 1253160641Syongaristatic int 1254160641Syongaristge_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1255160641Syongari{ 1256160641Syongari struct stge_softc *sc; 1257160641Syongari struct ifreq *ifr; 1258160641Syongari struct mii_data *mii; 1259160641Syongari int error, mask; 1260160641Syongari 1261160641Syongari sc = ifp->if_softc; 1262160641Syongari ifr = (struct ifreq *)data; 1263160641Syongari error = 0; 1264160641Syongari switch (cmd) { 1265160641Syongari case SIOCSIFMTU: 1266160641Syongari if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > STGE_JUMBO_MTU) 1267160641Syongari error = EINVAL; 1268160641Syongari else if (ifp->if_mtu != ifr->ifr_mtu) { 1269160641Syongari ifp->if_mtu = ifr->ifr_mtu; 1270160641Syongari STGE_LOCK(sc); 1271212972Syongari if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1272212972Syongari ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1273212972Syongari stge_init_locked(sc); 1274212972Syongari } 1275160641Syongari STGE_UNLOCK(sc); 1276160641Syongari } 1277160641Syongari break; 1278160641Syongari case SIOCSIFFLAGS: 1279160641Syongari STGE_LOCK(sc); 1280160641Syongari if ((ifp->if_flags & IFF_UP) != 0) { 1281160641Syongari if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1282160641Syongari if (((ifp->if_flags ^ sc->sc_if_flags) 1283160641Syongari & IFF_PROMISC) != 0) 1284160641Syongari stge_set_filter(sc); 1285160641Syongari } else { 1286160641Syongari if (sc->sc_detach == 0) 1287160641Syongari stge_init_locked(sc); 1288160641Syongari } 1289160641Syongari } else { 1290160641Syongari if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1291160641Syongari stge_stop(sc); 1292160641Syongari } 1293160641Syongari sc->sc_if_flags = ifp->if_flags; 1294160641Syongari STGE_UNLOCK(sc); 1295160641Syongari break; 1296160641Syongari case SIOCADDMULTI: 1297160641Syongari case SIOCDELMULTI: 1298160641Syongari STGE_LOCK(sc); 1299160641Syongari if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1300160641Syongari stge_set_multi(sc); 1301160641Syongari STGE_UNLOCK(sc); 1302160641Syongari break; 1303160641Syongari case SIOCSIFMEDIA: 1304160641Syongari case SIOCGIFMEDIA: 1305160641Syongari mii = device_get_softc(sc->sc_miibus); 1306160641Syongari error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1307160641Syongari break; 1308160641Syongari case SIOCSIFCAP: 1309160641Syongari mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1310160641Syongari#ifdef DEVICE_POLLING 1311160641Syongari if ((mask & IFCAP_POLLING) != 0) { 1312160641Syongari if ((ifr->ifr_reqcap & IFCAP_POLLING) != 0) { 1313160641Syongari error = ether_poll_register(stge_poll, ifp); 1314160641Syongari if (error != 0) 1315160641Syongari break; 1316160641Syongari STGE_LOCK(sc); 1317160641Syongari CSR_WRITE_2(sc, STGE_IntEnable, 0); 1318160641Syongari ifp->if_capenable |= IFCAP_POLLING; 1319160641Syongari STGE_UNLOCK(sc); 1320160641Syongari } else { 1321160641Syongari error = ether_poll_deregister(ifp); 1322160641Syongari if (error != 0) 1323160641Syongari break; 1324160641Syongari STGE_LOCK(sc); 1325160641Syongari CSR_WRITE_2(sc, STGE_IntEnable, 1326160641Syongari sc->sc_IntEnable); 1327160641Syongari ifp->if_capenable &= ~IFCAP_POLLING; 1328160641Syongari STGE_UNLOCK(sc); 1329160641Syongari } 1330160641Syongari } 1331160641Syongari#endif 1332160641Syongari if ((mask & IFCAP_HWCSUM) != 0) { 1333160641Syongari ifp->if_capenable ^= IFCAP_HWCSUM; 1334160641Syongari if ((IFCAP_HWCSUM & ifp->if_capenable) != 0 && 1335160641Syongari (IFCAP_HWCSUM & ifp->if_capabilities) != 0) 1336160641Syongari ifp->if_hwassist = STGE_CSUM_FEATURES; 1337160641Syongari else 1338160641Syongari ifp->if_hwassist = 0; 1339160641Syongari } 1340175315Syongari if ((mask & IFCAP_WOL) != 0 && 1341175315Syongari (ifp->if_capabilities & IFCAP_WOL) != 0) { 1342175315Syongari if ((mask & IFCAP_WOL_MAGIC) != 0) 1343175315Syongari ifp->if_capenable ^= IFCAP_WOL_MAGIC; 1344175315Syongari } 1345160641Syongari if ((mask & IFCAP_VLAN_HWTAGGING) != 0) { 1346160641Syongari ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1347160641Syongari if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1348160641Syongari STGE_LOCK(sc); 1349160641Syongari stge_vlan_setup(sc); 1350160641Syongari STGE_UNLOCK(sc); 1351160641Syongari } 1352160641Syongari } 1353160641Syongari VLAN_CAPABILITIES(ifp); 1354160641Syongari break; 1355160641Syongari default: 1356160641Syongari error = ether_ioctl(ifp, cmd, data); 1357160641Syongari break; 1358160641Syongari } 1359160641Syongari 1360160641Syongari return (error); 1361160641Syongari} 1362160641Syongari 1363160641Syongaristatic void 1364160641Syongaristge_link_task(void *arg, int pending) 1365160641Syongari{ 1366160641Syongari struct stge_softc *sc; 1367169158Syongari struct mii_data *mii; 1368160641Syongari uint32_t v, ac; 1369160641Syongari int i; 1370160641Syongari 1371160641Syongari sc = (struct stge_softc *)arg; 1372160641Syongari STGE_LOCK(sc); 1373169158Syongari 1374169158Syongari mii = device_get_softc(sc->sc_miibus); 1375169158Syongari if (mii->mii_media_status & IFM_ACTIVE) { 1376169158Syongari if (IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1377169158Syongari sc->sc_link = 1; 1378169158Syongari } else 1379169158Syongari sc->sc_link = 0; 1380169158Syongari 1381169158Syongari sc->sc_MACCtrl = 0; 1382169158Syongari if (((mii->mii_media_active & IFM_GMASK) & IFM_FDX) != 0) 1383169158Syongari sc->sc_MACCtrl |= MC_DuplexSelect; 1384215297Smarius if (((mii->mii_media_active & IFM_GMASK) & IFM_ETH_RXPAUSE) != 0) 1385169158Syongari sc->sc_MACCtrl |= MC_RxFlowControlEnable; 1386215297Smarius if (((mii->mii_media_active & IFM_GMASK) & IFM_ETH_TXPAUSE) != 0) 1387169158Syongari sc->sc_MACCtrl |= MC_TxFlowControlEnable; 1388160641Syongari /* 1389160641Syongari * Update STGE_MACCtrl register depending on link status. 1390160641Syongari * (duplex, flow control etc) 1391160641Syongari */ 1392160641Syongari v = ac = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 1393160641Syongari v &= ~(MC_DuplexSelect|MC_RxFlowControlEnable|MC_TxFlowControlEnable); 1394160641Syongari v |= sc->sc_MACCtrl; 1395160641Syongari CSR_WRITE_4(sc, STGE_MACCtrl, v); 1396160641Syongari if (((ac ^ sc->sc_MACCtrl) & MC_DuplexSelect) != 0) { 1397160641Syongari /* Duplex setting changed, reset Tx/Rx functions. */ 1398160641Syongari ac = CSR_READ_4(sc, STGE_AsicCtrl); 1399160641Syongari ac |= AC_TxReset | AC_RxReset; 1400160641Syongari CSR_WRITE_4(sc, STGE_AsicCtrl, ac); 1401160641Syongari for (i = 0; i < STGE_TIMEOUT; i++) { 1402160641Syongari DELAY(100); 1403160641Syongari if ((CSR_READ_4(sc, STGE_AsicCtrl) & AC_ResetBusy) == 0) 1404160641Syongari break; 1405160641Syongari } 1406160641Syongari if (i == STGE_TIMEOUT) 1407160641Syongari device_printf(sc->sc_dev, "reset failed to complete\n"); 1408160641Syongari } 1409160641Syongari STGE_UNLOCK(sc); 1410160641Syongari} 1411160641Syongari 1412160641Syongaristatic __inline int 1413160641Syongaristge_tx_error(struct stge_softc *sc) 1414160641Syongari{ 1415160641Syongari uint32_t txstat; 1416160641Syongari int error; 1417160641Syongari 1418160641Syongari for (error = 0;;) { 1419160641Syongari txstat = CSR_READ_4(sc, STGE_TxStatus); 1420160641Syongari if ((txstat & TS_TxComplete) == 0) 1421160641Syongari break; 1422160641Syongari /* Tx underrun */ 1423160641Syongari if ((txstat & TS_TxUnderrun) != 0) { 1424160641Syongari /* 1425160641Syongari * XXX 1426160641Syongari * There should be a more better way to recover 1427160641Syongari * from Tx underrun instead of a full reset. 1428160641Syongari */ 1429160641Syongari if (sc->sc_nerr++ < STGE_MAXERR) 1430160641Syongari device_printf(sc->sc_dev, "Tx underrun, " 1431160641Syongari "resetting...\n"); 1432160641Syongari if (sc->sc_nerr == STGE_MAXERR) 1433160641Syongari device_printf(sc->sc_dev, "too many errors; " 1434160641Syongari "not reporting any more\n"); 1435160641Syongari error = -1; 1436160641Syongari break; 1437160641Syongari } 1438160641Syongari /* Maximum/Late collisions, Re-enable Tx MAC. */ 1439160641Syongari if ((txstat & (TS_MaxCollisions|TS_LateCollision)) != 0) 1440160641Syongari CSR_WRITE_4(sc, STGE_MACCtrl, 1441160641Syongari (CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK) | 1442160641Syongari MC_TxEnable); 1443160641Syongari } 1444160641Syongari 1445160641Syongari return (error); 1446160641Syongari} 1447160641Syongari 1448160641Syongari/* 1449160641Syongari * stge_intr: 1450160641Syongari * 1451160641Syongari * Interrupt service routine. 1452160641Syongari */ 1453160641Syongaristatic void 1454160641Syongaristge_intr(void *arg) 1455160641Syongari{ 1456160641Syongari struct stge_softc *sc; 1457160641Syongari struct ifnet *ifp; 1458160641Syongari int reinit; 1459160641Syongari uint16_t status; 1460160641Syongari 1461160641Syongari sc = (struct stge_softc *)arg; 1462160641Syongari ifp = sc->sc_ifp; 1463160641Syongari 1464160641Syongari STGE_LOCK(sc); 1465160641Syongari 1466160641Syongari#ifdef DEVICE_POLLING 1467160641Syongari if ((ifp->if_capenable & IFCAP_POLLING) != 0) 1468160641Syongari goto done_locked; 1469160641Syongari#endif 1470160641Syongari status = CSR_READ_2(sc, STGE_IntStatus); 1471160641Syongari if (sc->sc_suspended || (status & IS_InterruptStatus) == 0) 1472160641Syongari goto done_locked; 1473160641Syongari 1474160641Syongari /* Disable interrupts. */ 1475160641Syongari for (reinit = 0;;) { 1476160641Syongari status = CSR_READ_2(sc, STGE_IntStatusAck); 1477160641Syongari status &= sc->sc_IntEnable; 1478160641Syongari if (status == 0) 1479160641Syongari break; 1480160641Syongari /* Host interface errors. */ 1481160641Syongari if ((status & IS_HostError) != 0) { 1482160641Syongari device_printf(sc->sc_dev, 1483160641Syongari "Host interface error, resetting...\n"); 1484160641Syongari reinit = 1; 1485160641Syongari goto force_init; 1486160641Syongari } 1487160641Syongari 1488160641Syongari /* Receive interrupts. */ 1489160641Syongari if ((status & IS_RxDMAComplete) != 0) { 1490160641Syongari stge_rxeof(sc); 1491160641Syongari if ((status & IS_RFDListEnd) != 0) 1492160641Syongari CSR_WRITE_4(sc, STGE_DMACtrl, 1493160641Syongari DMAC_RxDMAPollNow); 1494160641Syongari } 1495160641Syongari 1496160641Syongari /* Transmit interrupts. */ 1497160641Syongari if ((status & (IS_TxDMAComplete | IS_TxComplete)) != 0) 1498160641Syongari stge_txeof(sc); 1499160641Syongari 1500160641Syongari /* Transmission errors.*/ 1501160641Syongari if ((status & IS_TxComplete) != 0) { 1502160641Syongari if ((reinit = stge_tx_error(sc)) != 0) 1503160641Syongari break; 1504160641Syongari } 1505160641Syongari } 1506160641Syongari 1507160641Syongariforce_init: 1508212972Syongari if (reinit != 0) { 1509212972Syongari ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1510160641Syongari stge_init_locked(sc); 1511212972Syongari } 1512160641Syongari 1513160641Syongari /* Re-enable interrupts. */ 1514160641Syongari CSR_WRITE_2(sc, STGE_IntEnable, sc->sc_IntEnable); 1515160641Syongari 1516160641Syongari /* Try to get more packets going. */ 1517160641Syongari if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1518160641Syongari stge_start_locked(ifp); 1519160641Syongari 1520160641Syongaridone_locked: 1521160641Syongari STGE_UNLOCK(sc); 1522160641Syongari} 1523160641Syongari 1524160641Syongari/* 1525160641Syongari * stge_txeof: 1526160641Syongari * 1527160641Syongari * Helper; handle transmit interrupts. 1528160641Syongari */ 1529160641Syongaristatic void 1530160641Syongaristge_txeof(struct stge_softc *sc) 1531160641Syongari{ 1532160641Syongari struct ifnet *ifp; 1533160641Syongari struct stge_txdesc *txd; 1534160641Syongari uint64_t control; 1535160641Syongari int cons; 1536160641Syongari 1537160641Syongari STGE_LOCK_ASSERT(sc); 1538160641Syongari 1539160641Syongari ifp = sc->sc_ifp; 1540160641Syongari 1541160641Syongari txd = STAILQ_FIRST(&sc->sc_cdata.stge_txbusyq); 1542160641Syongari if (txd == NULL) 1543160641Syongari return; 1544160641Syongari bus_dmamap_sync(sc->sc_cdata.stge_tx_ring_tag, 1545160641Syongari sc->sc_cdata.stge_tx_ring_map, BUS_DMASYNC_POSTREAD); 1546160641Syongari 1547160641Syongari /* 1548160641Syongari * Go through our Tx list and free mbufs for those 1549160641Syongari * frames which have been transmitted. 1550160641Syongari */ 1551160641Syongari for (cons = sc->sc_cdata.stge_tx_cons;; 1552160641Syongari cons = (cons + 1) % STGE_TX_RING_CNT) { 1553160641Syongari if (sc->sc_cdata.stge_tx_cnt <= 0) 1554160641Syongari break; 1555160641Syongari control = le64toh(sc->sc_rdata.stge_tx_ring[cons].tfd_control); 1556160641Syongari if ((control & TFD_TFDDone) == 0) 1557160641Syongari break; 1558160641Syongari sc->sc_cdata.stge_tx_cnt--; 1559160641Syongari ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1560160641Syongari 1561160641Syongari bus_dmamap_sync(sc->sc_cdata.stge_tx_tag, txd->tx_dmamap, 1562160641Syongari BUS_DMASYNC_POSTWRITE); 1563160641Syongari bus_dmamap_unload(sc->sc_cdata.stge_tx_tag, txd->tx_dmamap); 1564160641Syongari 1565160641Syongari /* Output counter is updated with statistics register */ 1566160641Syongari m_freem(txd->tx_m); 1567160641Syongari txd->tx_m = NULL; 1568160641Syongari STAILQ_REMOVE_HEAD(&sc->sc_cdata.stge_txbusyq, tx_q); 1569160641Syongari STAILQ_INSERT_TAIL(&sc->sc_cdata.stge_txfreeq, txd, tx_q); 1570160641Syongari txd = STAILQ_FIRST(&sc->sc_cdata.stge_txbusyq); 1571160641Syongari } 1572160641Syongari sc->sc_cdata.stge_tx_cons = cons; 1573160641Syongari if (sc->sc_cdata.stge_tx_cnt == 0) 1574169157Syongari sc->sc_watchdog_timer = 0; 1575160641Syongari 1576160641Syongari bus_dmamap_sync(sc->sc_cdata.stge_tx_ring_tag, 1577160641Syongari sc->sc_cdata.stge_tx_ring_map, 1578160641Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1579160641Syongari} 1580160641Syongari 1581160641Syongaristatic __inline void 1582160641Syongaristge_discard_rxbuf(struct stge_softc *sc, int idx) 1583160641Syongari{ 1584160641Syongari struct stge_rfd *rfd; 1585160641Syongari 1586160641Syongari rfd = &sc->sc_rdata.stge_rx_ring[idx]; 1587160641Syongari rfd->rfd_status = 0; 1588160641Syongari} 1589160641Syongari 1590160641Syongari#ifndef __NO_STRICT_ALIGNMENT 1591160641Syongari/* 1592160641Syongari * It seems that TC9021's DMA engine has alignment restrictions in 1593160641Syongari * DMA scatter operations. The first DMA segment has no address 1594160641Syongari * alignment restrictins but the rest should be aligned on 4(?) bytes 1595160641Syongari * boundary. Otherwise it would corrupt random memory. Since we don't 1596160641Syongari * know which one is used for the first segment in advance we simply 1597160641Syongari * don't align at all. 1598160641Syongari * To avoid copying over an entire frame to align, we allocate a new 1599160641Syongari * mbuf and copy ethernet header to the new mbuf. The new mbuf is 1600160641Syongari * prepended into the existing mbuf chain. 1601160641Syongari */ 1602160641Syongaristatic __inline struct mbuf * 1603160641Syongaristge_fixup_rx(struct stge_softc *sc, struct mbuf *m) 1604160641Syongari{ 1605160641Syongari struct mbuf *n; 1606160641Syongari 1607160641Syongari n = NULL; 1608160641Syongari if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 1609160641Syongari bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 1610160641Syongari m->m_data += ETHER_HDR_LEN; 1611160641Syongari n = m; 1612160641Syongari } else { 1613243857Sglebius MGETHDR(n, M_NOWAIT, MT_DATA); 1614160641Syongari if (n != NULL) { 1615160641Syongari bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 1616160641Syongari m->m_data += ETHER_HDR_LEN; 1617160641Syongari m->m_len -= ETHER_HDR_LEN; 1618160641Syongari n->m_len = ETHER_HDR_LEN; 1619160641Syongari M_MOVE_PKTHDR(n, m); 1620160641Syongari n->m_next = m; 1621160641Syongari } else 1622160641Syongari m_freem(m); 1623160641Syongari } 1624160641Syongari 1625160641Syongari return (n); 1626160641Syongari} 1627160641Syongari#endif 1628160641Syongari 1629160641Syongari/* 1630160641Syongari * stge_rxeof: 1631160641Syongari * 1632160641Syongari * Helper; handle receive interrupts. 1633160641Syongari */ 1634193096Sattiliostatic int 1635160641Syongaristge_rxeof(struct stge_softc *sc) 1636160641Syongari{ 1637160641Syongari struct ifnet *ifp; 1638160641Syongari struct stge_rxdesc *rxd; 1639160641Syongari struct mbuf *mp, *m; 1640160641Syongari uint64_t status64; 1641160641Syongari uint32_t status; 1642193096Sattilio int cons, prog, rx_npkts; 1643160641Syongari 1644160641Syongari STGE_LOCK_ASSERT(sc); 1645160641Syongari 1646193096Sattilio rx_npkts = 0; 1647160641Syongari ifp = sc->sc_ifp; 1648160641Syongari 1649160641Syongari bus_dmamap_sync(sc->sc_cdata.stge_rx_ring_tag, 1650160641Syongari sc->sc_cdata.stge_rx_ring_map, BUS_DMASYNC_POSTREAD); 1651160641Syongari 1652160641Syongari prog = 0; 1653160641Syongari for (cons = sc->sc_cdata.stge_rx_cons; prog < STGE_RX_RING_CNT; 1654160641Syongari prog++, cons = (cons + 1) % STGE_RX_RING_CNT) { 1655160641Syongari status64 = le64toh(sc->sc_rdata.stge_rx_ring[cons].rfd_status); 1656160641Syongari status = RFD_RxStatus(status64); 1657160641Syongari if ((status & RFD_RFDDone) == 0) 1658160641Syongari break; 1659160641Syongari#ifdef DEVICE_POLLING 1660160641Syongari if (ifp->if_capenable & IFCAP_POLLING) { 1661160641Syongari if (sc->sc_cdata.stge_rxcycles <= 0) 1662160641Syongari break; 1663160641Syongari sc->sc_cdata.stge_rxcycles--; 1664160641Syongari } 1665160641Syongari#endif 1666160641Syongari prog++; 1667160641Syongari rxd = &sc->sc_cdata.stge_rxdesc[cons]; 1668160641Syongari mp = rxd->rx_m; 1669160641Syongari 1670160641Syongari /* 1671160641Syongari * If the packet had an error, drop it. Note we count 1672160641Syongari * the error later in the periodic stats update. 1673160641Syongari */ 1674160641Syongari if ((status & RFD_FrameEnd) != 0 && (status & 1675160641Syongari (RFD_RxFIFOOverrun | RFD_RxRuntFrame | 1676160641Syongari RFD_RxAlignmentError | RFD_RxFCSError | 1677160641Syongari RFD_RxLengthError)) != 0) { 1678160641Syongari stge_discard_rxbuf(sc, cons); 1679160641Syongari if (sc->sc_cdata.stge_rxhead != NULL) { 1680160641Syongari m_freem(sc->sc_cdata.stge_rxhead); 1681160641Syongari STGE_RXCHAIN_RESET(sc); 1682160641Syongari } 1683160641Syongari continue; 1684160641Syongari } 1685160641Syongari /* 1686160641Syongari * Add a new receive buffer to the ring. 1687160641Syongari */ 1688160641Syongari if (stge_newbuf(sc, cons) != 0) { 1689160641Syongari ifp->if_iqdrops++; 1690160641Syongari stge_discard_rxbuf(sc, cons); 1691160641Syongari if (sc->sc_cdata.stge_rxhead != NULL) { 1692160641Syongari m_freem(sc->sc_cdata.stge_rxhead); 1693160641Syongari STGE_RXCHAIN_RESET(sc); 1694160641Syongari } 1695160641Syongari continue; 1696160641Syongari } 1697160641Syongari 1698160641Syongari if ((status & RFD_FrameEnd) != 0) 1699160641Syongari mp->m_len = RFD_RxDMAFrameLen(status) - 1700160641Syongari sc->sc_cdata.stge_rxlen; 1701160641Syongari sc->sc_cdata.stge_rxlen += mp->m_len; 1702160641Syongari 1703160641Syongari /* Chain mbufs. */ 1704160641Syongari if (sc->sc_cdata.stge_rxhead == NULL) { 1705160641Syongari sc->sc_cdata.stge_rxhead = mp; 1706160641Syongari sc->sc_cdata.stge_rxtail = mp; 1707160641Syongari } else { 1708160641Syongari mp->m_flags &= ~M_PKTHDR; 1709160641Syongari sc->sc_cdata.stge_rxtail->m_next = mp; 1710160641Syongari sc->sc_cdata.stge_rxtail = mp; 1711160641Syongari } 1712160641Syongari 1713160641Syongari if ((status & RFD_FrameEnd) != 0) { 1714160641Syongari m = sc->sc_cdata.stge_rxhead; 1715160641Syongari m->m_pkthdr.rcvif = ifp; 1716160641Syongari m->m_pkthdr.len = sc->sc_cdata.stge_rxlen; 1717160641Syongari 1718160641Syongari if (m->m_pkthdr.len > sc->sc_if_framesize) { 1719160641Syongari m_freem(m); 1720160641Syongari STGE_RXCHAIN_RESET(sc); 1721160641Syongari continue; 1722160641Syongari } 1723160641Syongari /* 1724160641Syongari * Set the incoming checksum information for 1725160641Syongari * the packet. 1726160641Syongari */ 1727160641Syongari if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) { 1728160641Syongari if ((status & RFD_IPDetected) != 0) { 1729160641Syongari m->m_pkthdr.csum_flags |= 1730160641Syongari CSUM_IP_CHECKED; 1731160641Syongari if ((status & RFD_IPError) == 0) 1732160641Syongari m->m_pkthdr.csum_flags |= 1733160641Syongari CSUM_IP_VALID; 1734160641Syongari } 1735160641Syongari if (((status & RFD_TCPDetected) != 0 && 1736160641Syongari (status & RFD_TCPError) == 0) || 1737160641Syongari ((status & RFD_UDPDetected) != 0 && 1738160641Syongari (status & RFD_UDPError) == 0)) { 1739160641Syongari m->m_pkthdr.csum_flags |= 1740160641Syongari (CSUM_DATA_VALID | CSUM_PSEUDO_HDR); 1741160641Syongari m->m_pkthdr.csum_data = 0xffff; 1742160641Syongari } 1743160641Syongari } 1744160641Syongari 1745160641Syongari#ifndef __NO_STRICT_ALIGNMENT 1746160641Syongari if (sc->sc_if_framesize > (MCLBYTES - ETHER_ALIGN)) { 1747160641Syongari if ((m = stge_fixup_rx(sc, m)) == NULL) { 1748160641Syongari STGE_RXCHAIN_RESET(sc); 1749160641Syongari continue; 1750160641Syongari } 1751160641Syongari } 1752160641Syongari#endif 1753160641Syongari /* Check for VLAN tagged packets. */ 1754160641Syongari if ((status & RFD_VLANDetected) != 0 && 1755162375Sandre (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) { 1756162375Sandre m->m_pkthdr.ether_vtag = RFD_TCI(status64); 1757162375Sandre m->m_flags |= M_VLANTAG; 1758162375Sandre } 1759160641Syongari 1760160641Syongari STGE_UNLOCK(sc); 1761160641Syongari /* Pass it on. */ 1762160641Syongari (*ifp->if_input)(ifp, m); 1763160641Syongari STGE_LOCK(sc); 1764193096Sattilio rx_npkts++; 1765160641Syongari 1766160641Syongari STGE_RXCHAIN_RESET(sc); 1767160641Syongari } 1768160641Syongari } 1769160641Syongari 1770160641Syongari if (prog > 0) { 1771160641Syongari /* Update the consumer index. */ 1772160641Syongari sc->sc_cdata.stge_rx_cons = cons; 1773160641Syongari bus_dmamap_sync(sc->sc_cdata.stge_rx_ring_tag, 1774160641Syongari sc->sc_cdata.stge_rx_ring_map, 1775160641Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1776160641Syongari } 1777193096Sattilio return (rx_npkts); 1778160641Syongari} 1779160641Syongari 1780160641Syongari#ifdef DEVICE_POLLING 1781193096Sattiliostatic int 1782160641Syongaristge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1783160641Syongari{ 1784160641Syongari struct stge_softc *sc; 1785160641Syongari uint16_t status; 1786193096Sattilio int rx_npkts; 1787160641Syongari 1788193096Sattilio rx_npkts = 0; 1789160641Syongari sc = ifp->if_softc; 1790160641Syongari STGE_LOCK(sc); 1791160641Syongari if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1792160641Syongari STGE_UNLOCK(sc); 1793193096Sattilio return (rx_npkts); 1794160641Syongari } 1795160641Syongari 1796160641Syongari sc->sc_cdata.stge_rxcycles = count; 1797193096Sattilio rx_npkts = stge_rxeof(sc); 1798160641Syongari stge_txeof(sc); 1799160641Syongari 1800160641Syongari if (cmd == POLL_AND_CHECK_STATUS) { 1801160641Syongari status = CSR_READ_2(sc, STGE_IntStatus); 1802160641Syongari status &= sc->sc_IntEnable; 1803160641Syongari if (status != 0) { 1804160641Syongari if ((status & IS_HostError) != 0) { 1805160641Syongari device_printf(sc->sc_dev, 1806160641Syongari "Host interface error, resetting...\n"); 1807212972Syongari ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1808160641Syongari stge_init_locked(sc); 1809160641Syongari } 1810160641Syongari if ((status & IS_TxComplete) != 0) { 1811212972Syongari if (stge_tx_error(sc) != 0) { 1812212972Syongari ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1813160641Syongari stge_init_locked(sc); 1814212972Syongari } 1815160641Syongari } 1816160641Syongari } 1817160641Syongari 1818160641Syongari } 1819160641Syongari 1820160641Syongari if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1821160641Syongari stge_start_locked(ifp); 1822160641Syongari 1823160641Syongari STGE_UNLOCK(sc); 1824193096Sattilio return (rx_npkts); 1825160641Syongari} 1826160641Syongari#endif /* DEVICE_POLLING */ 1827160641Syongari 1828160641Syongari/* 1829160641Syongari * stge_tick: 1830160641Syongari * 1831160641Syongari * One second timer, used to tick the MII. 1832160641Syongari */ 1833160641Syongaristatic void 1834160641Syongaristge_tick(void *arg) 1835160641Syongari{ 1836160641Syongari struct stge_softc *sc; 1837160641Syongari struct mii_data *mii; 1838160641Syongari 1839160641Syongari sc = (struct stge_softc *)arg; 1840160641Syongari 1841160641Syongari STGE_LOCK_ASSERT(sc); 1842160641Syongari 1843160641Syongari mii = device_get_softc(sc->sc_miibus); 1844160641Syongari mii_tick(mii); 1845160641Syongari 1846160641Syongari /* Update statistics counters. */ 1847160641Syongari stge_stats_update(sc); 1848160641Syongari 1849160641Syongari /* 1850160641Syongari * Relcaim any pending Tx descriptors to release mbufs in a 1851160641Syongari * timely manner as we don't generate Tx completion interrupts 1852160641Syongari * for every frame. This limits the delay to a maximum of one 1853160641Syongari * second. 1854160641Syongari */ 1855160641Syongari if (sc->sc_cdata.stge_tx_cnt != 0) 1856160641Syongari stge_txeof(sc); 1857160641Syongari 1858169157Syongari stge_watchdog(sc); 1859169157Syongari 1860160641Syongari callout_reset(&sc->sc_tick_ch, hz, stge_tick, sc); 1861160641Syongari} 1862160641Syongari 1863160641Syongari/* 1864160641Syongari * stge_stats_update: 1865160641Syongari * 1866160641Syongari * Read the TC9021 statistics counters. 1867160641Syongari */ 1868160641Syongaristatic void 1869160641Syongaristge_stats_update(struct stge_softc *sc) 1870160641Syongari{ 1871160641Syongari struct ifnet *ifp; 1872160641Syongari 1873160641Syongari STGE_LOCK_ASSERT(sc); 1874160641Syongari 1875160641Syongari ifp = sc->sc_ifp; 1876160641Syongari 1877160641Syongari CSR_READ_4(sc,STGE_OctetRcvOk); 1878160641Syongari 1879160641Syongari ifp->if_ipackets += CSR_READ_4(sc, STGE_FramesRcvdOk); 1880160641Syongari 1881160641Syongari ifp->if_ierrors += CSR_READ_2(sc, STGE_FramesLostRxErrors); 1882160641Syongari 1883160641Syongari CSR_READ_4(sc, STGE_OctetXmtdOk); 1884160641Syongari 1885160641Syongari ifp->if_opackets += CSR_READ_4(sc, STGE_FramesXmtdOk); 1886160641Syongari 1887160641Syongari ifp->if_collisions += 1888160641Syongari CSR_READ_4(sc, STGE_LateCollisions) + 1889160641Syongari CSR_READ_4(sc, STGE_MultiColFrames) + 1890160641Syongari CSR_READ_4(sc, STGE_SingleColFrames); 1891160641Syongari 1892160641Syongari ifp->if_oerrors += 1893160641Syongari CSR_READ_2(sc, STGE_FramesAbortXSColls) + 1894160641Syongari CSR_READ_2(sc, STGE_FramesWEXDeferal); 1895160641Syongari} 1896160641Syongari 1897160641Syongari/* 1898160641Syongari * stge_reset: 1899160641Syongari * 1900160641Syongari * Perform a soft reset on the TC9021. 1901160641Syongari */ 1902160641Syongaristatic void 1903160641Syongaristge_reset(struct stge_softc *sc, uint32_t how) 1904160641Syongari{ 1905160641Syongari uint32_t ac; 1906160641Syongari uint8_t v; 1907160641Syongari int i, dv; 1908160641Syongari 1909160641Syongari STGE_LOCK_ASSERT(sc); 1910160641Syongari 1911160641Syongari dv = 5000; 1912160641Syongari ac = CSR_READ_4(sc, STGE_AsicCtrl); 1913160641Syongari switch (how) { 1914160641Syongari case STGE_RESET_TX: 1915160641Syongari ac |= AC_TxReset | AC_FIFO; 1916160641Syongari dv = 100; 1917160641Syongari break; 1918160641Syongari case STGE_RESET_RX: 1919160641Syongari ac |= AC_RxReset | AC_FIFO; 1920160641Syongari dv = 100; 1921160641Syongari break; 1922160641Syongari case STGE_RESET_FULL: 1923160641Syongari default: 1924160641Syongari /* 1925160641Syongari * Only assert RstOut if we're fiber. We need GMII clocks 1926160641Syongari * to be present in order for the reset to complete on fiber 1927160641Syongari * cards. 1928160641Syongari */ 1929160641Syongari ac |= AC_GlobalReset | AC_RxReset | AC_TxReset | 1930160641Syongari AC_DMA | AC_FIFO | AC_Network | AC_Host | AC_AutoInit | 1931160641Syongari (sc->sc_usefiber ? AC_RstOut : 0); 1932160641Syongari break; 1933160641Syongari } 1934160641Syongari 1935160641Syongari CSR_WRITE_4(sc, STGE_AsicCtrl, ac); 1936160641Syongari 1937160641Syongari /* Account for reset problem at 10Mbps. */ 1938160641Syongari DELAY(dv); 1939160641Syongari 1940160641Syongari for (i = 0; i < STGE_TIMEOUT; i++) { 1941160641Syongari if ((CSR_READ_4(sc, STGE_AsicCtrl) & AC_ResetBusy) == 0) 1942160641Syongari break; 1943160641Syongari DELAY(dv); 1944160641Syongari } 1945160641Syongari 1946160641Syongari if (i == STGE_TIMEOUT) 1947160641Syongari device_printf(sc->sc_dev, "reset failed to complete\n"); 1948160641Syongari 1949160641Syongari /* Set LED, from Linux IPG driver. */ 1950160641Syongari ac = CSR_READ_4(sc, STGE_AsicCtrl); 1951160641Syongari ac &= ~(AC_LEDMode | AC_LEDSpeed | AC_LEDModeBit1); 1952160641Syongari if ((sc->sc_led & 0x01) != 0) 1953160641Syongari ac |= AC_LEDMode; 1954160641Syongari if ((sc->sc_led & 0x03) != 0) 1955160641Syongari ac |= AC_LEDModeBit1; 1956160641Syongari if ((sc->sc_led & 0x08) != 0) 1957160641Syongari ac |= AC_LEDSpeed; 1958160641Syongari CSR_WRITE_4(sc, STGE_AsicCtrl, ac); 1959160641Syongari 1960160641Syongari /* Set PHY, from Linux IPG driver */ 1961160641Syongari v = CSR_READ_1(sc, STGE_PhySet); 1962160641Syongari v &= ~(PS_MemLenb9b | PS_MemLen | PS_NonCompdet); 1963160641Syongari v |= ((sc->sc_led & 0x70) >> 4); 1964160641Syongari CSR_WRITE_1(sc, STGE_PhySet, v); 1965160641Syongari} 1966160641Syongari 1967160641Syongari/* 1968160641Syongari * stge_init: [ ifnet interface function ] 1969160641Syongari * 1970160641Syongari * Initialize the interface. 1971160641Syongari */ 1972160641Syongaristatic void 1973160641Syongaristge_init(void *xsc) 1974160641Syongari{ 1975160641Syongari struct stge_softc *sc; 1976160641Syongari 1977160641Syongari sc = (struct stge_softc *)xsc; 1978160641Syongari STGE_LOCK(sc); 1979160641Syongari stge_init_locked(sc); 1980160641Syongari STGE_UNLOCK(sc); 1981160641Syongari} 1982160641Syongari 1983160641Syongaristatic void 1984160641Syongaristge_init_locked(struct stge_softc *sc) 1985160641Syongari{ 1986160641Syongari struct ifnet *ifp; 1987160641Syongari struct mii_data *mii; 1988160641Syongari uint16_t eaddr[3]; 1989160641Syongari uint32_t v; 1990160641Syongari int error; 1991160641Syongari 1992160641Syongari STGE_LOCK_ASSERT(sc); 1993160641Syongari 1994160641Syongari ifp = sc->sc_ifp; 1995212972Syongari if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1996212972Syongari return; 1997160641Syongari mii = device_get_softc(sc->sc_miibus); 1998160641Syongari 1999160641Syongari /* 2000160641Syongari * Cancel any pending I/O. 2001160641Syongari */ 2002160641Syongari stge_stop(sc); 2003160641Syongari 2004175315Syongari /* 2005175315Syongari * Reset the chip to a known state. 2006175315Syongari */ 2007175315Syongari stge_reset(sc, STGE_RESET_FULL); 2008175315Syongari 2009160641Syongari /* Init descriptors. */ 2010160641Syongari error = stge_init_rx_ring(sc); 2011160641Syongari if (error != 0) { 2012160641Syongari device_printf(sc->sc_dev, 2013160641Syongari "initialization failed: no memory for rx buffers\n"); 2014160641Syongari stge_stop(sc); 2015160641Syongari goto out; 2016160641Syongari } 2017160641Syongari stge_init_tx_ring(sc); 2018160641Syongari 2019160641Syongari /* Set the station address. */ 2020160641Syongari bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 2021160641Syongari CSR_WRITE_2(sc, STGE_StationAddress0, htole16(eaddr[0])); 2022160641Syongari CSR_WRITE_2(sc, STGE_StationAddress1, htole16(eaddr[1])); 2023160641Syongari CSR_WRITE_2(sc, STGE_StationAddress2, htole16(eaddr[2])); 2024160641Syongari 2025160641Syongari /* 2026160641Syongari * Set the statistics masks. Disable all the RMON stats, 2027160641Syongari * and disable selected stats in the non-RMON stats registers. 2028160641Syongari */ 2029160641Syongari CSR_WRITE_4(sc, STGE_RMONStatisticsMask, 0xffffffff); 2030160641Syongari CSR_WRITE_4(sc, STGE_StatisticsMask, 2031160641Syongari (1U << 1) | (1U << 2) | (1U << 3) | (1U << 4) | (1U << 5) | 2032160641Syongari (1U << 6) | (1U << 7) | (1U << 8) | (1U << 9) | (1U << 10) | 2033160641Syongari (1U << 13) | (1U << 14) | (1U << 15) | (1U << 19) | (1U << 20) | 2034160641Syongari (1U << 21)); 2035160641Syongari 2036160641Syongari /* Set up the receive filter. */ 2037160641Syongari stge_set_filter(sc); 2038160641Syongari /* Program multicast filter. */ 2039160641Syongari stge_set_multi(sc); 2040160641Syongari 2041160641Syongari /* 2042160641Syongari * Give the transmit and receive ring to the chip. 2043160641Syongari */ 2044160641Syongari CSR_WRITE_4(sc, STGE_TFDListPtrHi, 2045160641Syongari STGE_ADDR_HI(STGE_TX_RING_ADDR(sc, 0))); 2046160641Syongari CSR_WRITE_4(sc, STGE_TFDListPtrLo, 2047160641Syongari STGE_ADDR_LO(STGE_TX_RING_ADDR(sc, 0))); 2048160641Syongari 2049160641Syongari CSR_WRITE_4(sc, STGE_RFDListPtrHi, 2050160641Syongari STGE_ADDR_HI(STGE_RX_RING_ADDR(sc, 0))); 2051160641Syongari CSR_WRITE_4(sc, STGE_RFDListPtrLo, 2052160641Syongari STGE_ADDR_LO(STGE_RX_RING_ADDR(sc, 0))); 2053160641Syongari 2054160641Syongari /* 2055160641Syongari * Initialize the Tx auto-poll period. It's OK to make this number 2056160641Syongari * large (255 is the max, but we use 127) -- we explicitly kick the 2057160641Syongari * transmit engine when there's actually a packet. 2058160641Syongari */ 2059160641Syongari CSR_WRITE_1(sc, STGE_TxDMAPollPeriod, 127); 2060160641Syongari 2061160641Syongari /* ..and the Rx auto-poll period. */ 2062160641Syongari CSR_WRITE_1(sc, STGE_RxDMAPollPeriod, 1); 2063160641Syongari 2064160641Syongari /* Initialize the Tx start threshold. */ 2065160641Syongari CSR_WRITE_2(sc, STGE_TxStartThresh, sc->sc_txthresh); 2066160641Syongari 2067160641Syongari /* Rx DMA thresholds, from Linux */ 2068160641Syongari CSR_WRITE_1(sc, STGE_RxDMABurstThresh, 0x30); 2069160641Syongari CSR_WRITE_1(sc, STGE_RxDMAUrgentThresh, 0x30); 2070160641Syongari 2071160641Syongari /* Rx early threhold, from Linux */ 2072160641Syongari CSR_WRITE_2(sc, STGE_RxEarlyThresh, 0x7ff); 2073160641Syongari 2074160641Syongari /* Tx DMA thresholds, from Linux */ 2075160641Syongari CSR_WRITE_1(sc, STGE_TxDMABurstThresh, 0x30); 2076160641Syongari CSR_WRITE_1(sc, STGE_TxDMAUrgentThresh, 0x04); 2077160641Syongari 2078160641Syongari /* 2079160641Syongari * Initialize the Rx DMA interrupt control register. We 2080160641Syongari * request an interrupt after every incoming packet, but 2081160641Syongari * defer it for sc_rxint_dmawait us. When the number of 2082160641Syongari * interrupts pending reaches STGE_RXINT_NFRAME, we stop 2083160641Syongari * deferring the interrupt, and signal it immediately. 2084160641Syongari */ 2085160641Syongari CSR_WRITE_4(sc, STGE_RxDMAIntCtrl, 2086160641Syongari RDIC_RxFrameCount(sc->sc_rxint_nframe) | 2087160641Syongari RDIC_RxDMAWaitTime(STGE_RXINT_USECS2TICK(sc->sc_rxint_dmawait))); 2088160641Syongari 2089160641Syongari /* 2090160641Syongari * Initialize the interrupt mask. 2091160641Syongari */ 2092160641Syongari sc->sc_IntEnable = IS_HostError | IS_TxComplete | 2093160641Syongari IS_TxDMAComplete | IS_RxDMAComplete | IS_RFDListEnd; 2094160641Syongari#ifdef DEVICE_POLLING 2095160641Syongari /* Disable interrupts if we are polling. */ 2096160641Syongari if ((ifp->if_capenable & IFCAP_POLLING) != 0) 2097160641Syongari CSR_WRITE_2(sc, STGE_IntEnable, 0); 2098160641Syongari else 2099160641Syongari#endif 2100160641Syongari CSR_WRITE_2(sc, STGE_IntEnable, sc->sc_IntEnable); 2101160641Syongari 2102160641Syongari /* 2103160641Syongari * Configure the DMA engine. 2104160641Syongari * XXX Should auto-tune TxBurstLimit. 2105160641Syongari */ 2106160641Syongari CSR_WRITE_4(sc, STGE_DMACtrl, sc->sc_DMACtrl | DMAC_TxBurstLimit(3)); 2107160641Syongari 2108160641Syongari /* 2109160641Syongari * Send a PAUSE frame when we reach 29,696 bytes in the Rx 2110160641Syongari * FIFO, and send an un-PAUSE frame when we reach 3056 bytes 2111160641Syongari * in the Rx FIFO. 2112160641Syongari */ 2113160641Syongari CSR_WRITE_2(sc, STGE_FlowOnTresh, 29696 / 16); 2114160641Syongari CSR_WRITE_2(sc, STGE_FlowOffThresh, 3056 / 16); 2115160641Syongari 2116160641Syongari /* 2117160641Syongari * Set the maximum frame size. 2118160641Syongari */ 2119160641Syongari sc->sc_if_framesize = ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 2120160641Syongari CSR_WRITE_2(sc, STGE_MaxFrameSize, sc->sc_if_framesize); 2121160641Syongari 2122160641Syongari /* 2123160641Syongari * Initialize MacCtrl -- do it before setting the media, 2124160641Syongari * as setting the media will actually program the register. 2125160641Syongari * 2126160641Syongari * Note: We have to poke the IFS value before poking 2127160641Syongari * anything else. 2128160641Syongari */ 2129160641Syongari /* Tx/Rx MAC should be disabled before programming IFS.*/ 2130160641Syongari CSR_WRITE_4(sc, STGE_MACCtrl, MC_IFSSelect(MC_IFS96bit)); 2131160641Syongari 2132160641Syongari stge_vlan_setup(sc); 2133160641Syongari 2134160641Syongari if (sc->sc_rev >= 6) { /* >= B.2 */ 2135160641Syongari /* Multi-frag frame bug work-around. */ 2136160641Syongari CSR_WRITE_2(sc, STGE_DebugCtrl, 2137160641Syongari CSR_READ_2(sc, STGE_DebugCtrl) | 0x0200); 2138160641Syongari 2139160641Syongari /* Tx Poll Now bug work-around. */ 2140160641Syongari CSR_WRITE_2(sc, STGE_DebugCtrl, 2141160641Syongari CSR_READ_2(sc, STGE_DebugCtrl) | 0x0010); 2142160641Syongari /* Tx Poll Now bug work-around. */ 2143160641Syongari CSR_WRITE_2(sc, STGE_DebugCtrl, 2144160641Syongari CSR_READ_2(sc, STGE_DebugCtrl) | 0x0020); 2145160641Syongari } 2146160641Syongari 2147160641Syongari v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 2148160641Syongari v |= MC_StatisticsEnable | MC_TxEnable | MC_RxEnable; 2149160641Syongari CSR_WRITE_4(sc, STGE_MACCtrl, v); 2150160641Syongari /* 2151160641Syongari * It seems that transmitting frames without checking the state of 2152160641Syongari * Rx/Tx MAC wedge the hardware. 2153160641Syongari */ 2154160641Syongari stge_start_tx(sc); 2155160641Syongari stge_start_rx(sc); 2156160641Syongari 2157169158Syongari sc->sc_link = 0; 2158160641Syongari /* 2159160641Syongari * Set the current media. 2160160641Syongari */ 2161160641Syongari mii_mediachg(mii); 2162160641Syongari 2163160641Syongari /* 2164160641Syongari * Start the one second MII clock. 2165160641Syongari */ 2166160641Syongari callout_reset(&sc->sc_tick_ch, hz, stge_tick, sc); 2167160641Syongari 2168160641Syongari /* 2169160641Syongari * ...all done! 2170160641Syongari */ 2171160641Syongari ifp->if_drv_flags |= IFF_DRV_RUNNING; 2172160641Syongari ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2173160641Syongari 2174160641Syongari out: 2175160641Syongari if (error != 0) 2176160641Syongari device_printf(sc->sc_dev, "interface not running\n"); 2177160641Syongari} 2178160641Syongari 2179160641Syongaristatic void 2180160641Syongaristge_vlan_setup(struct stge_softc *sc) 2181160641Syongari{ 2182160641Syongari struct ifnet *ifp; 2183160641Syongari uint32_t v; 2184160641Syongari 2185160641Syongari ifp = sc->sc_ifp; 2186160641Syongari /* 2187160641Syongari * The NIC always copy a VLAN tag regardless of STGE_MACCtrl 2188160641Syongari * MC_AutoVLANuntagging bit. 2189160641Syongari * MC_AutoVLANtagging bit selects which VLAN source to use 2190160641Syongari * between STGE_VLANTag and TFC. However TFC TFD_VLANTagInsert 2191160641Syongari * bit has priority over MC_AutoVLANtagging bit. So we always 2192160641Syongari * use TFC instead of STGE_VLANTag register. 2193160641Syongari */ 2194160641Syongari v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 2195160641Syongari if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 2196160641Syongari v |= MC_AutoVLANuntagging; 2197160641Syongari else 2198160641Syongari v &= ~MC_AutoVLANuntagging; 2199160641Syongari CSR_WRITE_4(sc, STGE_MACCtrl, v); 2200160641Syongari} 2201160641Syongari 2202160641Syongari/* 2203160641Syongari * Stop transmission on the interface. 2204160641Syongari */ 2205160641Syongaristatic void 2206160641Syongaristge_stop(struct stge_softc *sc) 2207160641Syongari{ 2208160641Syongari struct ifnet *ifp; 2209160641Syongari struct stge_txdesc *txd; 2210160641Syongari struct stge_rxdesc *rxd; 2211160641Syongari uint32_t v; 2212160641Syongari int i; 2213160641Syongari 2214160641Syongari STGE_LOCK_ASSERT(sc); 2215160641Syongari /* 2216160641Syongari * Stop the one second clock. 2217160641Syongari */ 2218160641Syongari callout_stop(&sc->sc_tick_ch); 2219169157Syongari sc->sc_watchdog_timer = 0; 2220160641Syongari 2221160641Syongari /* 2222160641Syongari * Disable interrupts. 2223160641Syongari */ 2224160641Syongari CSR_WRITE_2(sc, STGE_IntEnable, 0); 2225160641Syongari 2226160641Syongari /* 2227160641Syongari * Stop receiver, transmitter, and stats update. 2228160641Syongari */ 2229160641Syongari stge_stop_rx(sc); 2230160641Syongari stge_stop_tx(sc); 2231160641Syongari v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 2232160641Syongari v |= MC_StatisticsDisable; 2233160641Syongari CSR_WRITE_4(sc, STGE_MACCtrl, v); 2234160641Syongari 2235160641Syongari /* 2236160641Syongari * Stop the transmit and receive DMA. 2237160641Syongari */ 2238160641Syongari stge_dma_wait(sc); 2239160641Syongari CSR_WRITE_4(sc, STGE_TFDListPtrHi, 0); 2240160641Syongari CSR_WRITE_4(sc, STGE_TFDListPtrLo, 0); 2241160641Syongari CSR_WRITE_4(sc, STGE_RFDListPtrHi, 0); 2242160641Syongari CSR_WRITE_4(sc, STGE_RFDListPtrLo, 0); 2243160641Syongari 2244160641Syongari /* 2245160641Syongari * Free RX and TX mbufs still in the queues. 2246160641Syongari */ 2247160641Syongari for (i = 0; i < STGE_RX_RING_CNT; i++) { 2248160641Syongari rxd = &sc->sc_cdata.stge_rxdesc[i]; 2249160641Syongari if (rxd->rx_m != NULL) { 2250160641Syongari bus_dmamap_sync(sc->sc_cdata.stge_rx_tag, 2251160641Syongari rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 2252160641Syongari bus_dmamap_unload(sc->sc_cdata.stge_rx_tag, 2253160641Syongari rxd->rx_dmamap); 2254160641Syongari m_freem(rxd->rx_m); 2255160641Syongari rxd->rx_m = NULL; 2256160641Syongari } 2257160641Syongari } 2258160641Syongari for (i = 0; i < STGE_TX_RING_CNT; i++) { 2259160641Syongari txd = &sc->sc_cdata.stge_txdesc[i]; 2260160641Syongari if (txd->tx_m != NULL) { 2261160641Syongari bus_dmamap_sync(sc->sc_cdata.stge_tx_tag, 2262160641Syongari txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2263160641Syongari bus_dmamap_unload(sc->sc_cdata.stge_tx_tag, 2264160641Syongari txd->tx_dmamap); 2265160641Syongari m_freem(txd->tx_m); 2266160641Syongari txd->tx_m = NULL; 2267160641Syongari } 2268160641Syongari } 2269160641Syongari 2270160641Syongari /* 2271160641Syongari * Mark the interface down and cancel the watchdog timer. 2272160641Syongari */ 2273160641Syongari ifp = sc->sc_ifp; 2274160641Syongari ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2275169158Syongari sc->sc_link = 0; 2276160641Syongari} 2277160641Syongari 2278160641Syongaristatic void 2279160641Syongaristge_start_tx(struct stge_softc *sc) 2280160641Syongari{ 2281160641Syongari uint32_t v; 2282160641Syongari int i; 2283160641Syongari 2284160641Syongari v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 2285160641Syongari if ((v & MC_TxEnabled) != 0) 2286160641Syongari return; 2287160641Syongari v |= MC_TxEnable; 2288160641Syongari CSR_WRITE_4(sc, STGE_MACCtrl, v); 2289160641Syongari CSR_WRITE_1(sc, STGE_TxDMAPollPeriod, 127); 2290160641Syongari for (i = STGE_TIMEOUT; i > 0; i--) { 2291160641Syongari DELAY(10); 2292160641Syongari v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 2293160641Syongari if ((v & MC_TxEnabled) != 0) 2294160641Syongari break; 2295160641Syongari } 2296160641Syongari if (i == 0) 2297160641Syongari device_printf(sc->sc_dev, "Starting Tx MAC timed out\n"); 2298160641Syongari} 2299160641Syongari 2300160641Syongaristatic void 2301160641Syongaristge_start_rx(struct stge_softc *sc) 2302160641Syongari{ 2303160641Syongari uint32_t v; 2304160641Syongari int i; 2305160641Syongari 2306160641Syongari v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 2307160641Syongari if ((v & MC_RxEnabled) != 0) 2308160641Syongari return; 2309160641Syongari v |= MC_RxEnable; 2310160641Syongari CSR_WRITE_4(sc, STGE_MACCtrl, v); 2311160641Syongari CSR_WRITE_1(sc, STGE_RxDMAPollPeriod, 1); 2312160641Syongari for (i = STGE_TIMEOUT; i > 0; i--) { 2313160641Syongari DELAY(10); 2314160641Syongari v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 2315160641Syongari if ((v & MC_RxEnabled) != 0) 2316160641Syongari break; 2317160641Syongari } 2318160641Syongari if (i == 0) 2319160641Syongari device_printf(sc->sc_dev, "Starting Rx MAC timed out\n"); 2320160641Syongari} 2321160641Syongari 2322160641Syongaristatic void 2323160641Syongaristge_stop_tx(struct stge_softc *sc) 2324160641Syongari{ 2325160641Syongari uint32_t v; 2326160641Syongari int i; 2327160641Syongari 2328160641Syongari v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 2329160641Syongari if ((v & MC_TxEnabled) == 0) 2330160641Syongari return; 2331160641Syongari v |= MC_TxDisable; 2332160641Syongari CSR_WRITE_4(sc, STGE_MACCtrl, v); 2333160641Syongari for (i = STGE_TIMEOUT; i > 0; i--) { 2334160641Syongari DELAY(10); 2335160641Syongari v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 2336160641Syongari if ((v & MC_TxEnabled) == 0) 2337160641Syongari break; 2338160641Syongari } 2339160641Syongari if (i == 0) 2340160641Syongari device_printf(sc->sc_dev, "Stopping Tx MAC timed out\n"); 2341160641Syongari} 2342160641Syongari 2343160641Syongaristatic void 2344160641Syongaristge_stop_rx(struct stge_softc *sc) 2345160641Syongari{ 2346160641Syongari uint32_t v; 2347160641Syongari int i; 2348160641Syongari 2349160641Syongari v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 2350160641Syongari if ((v & MC_RxEnabled) == 0) 2351160641Syongari return; 2352160641Syongari v |= MC_RxDisable; 2353160641Syongari CSR_WRITE_4(sc, STGE_MACCtrl, v); 2354160641Syongari for (i = STGE_TIMEOUT; i > 0; i--) { 2355160641Syongari DELAY(10); 2356160641Syongari v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 2357160641Syongari if ((v & MC_RxEnabled) == 0) 2358160641Syongari break; 2359160641Syongari } 2360160641Syongari if (i == 0) 2361160641Syongari device_printf(sc->sc_dev, "Stopping Rx MAC timed out\n"); 2362160641Syongari} 2363160641Syongari 2364160641Syongaristatic void 2365160641Syongaristge_init_tx_ring(struct stge_softc *sc) 2366160641Syongari{ 2367160641Syongari struct stge_ring_data *rd; 2368160641Syongari struct stge_txdesc *txd; 2369160641Syongari bus_addr_t addr; 2370160641Syongari int i; 2371160641Syongari 2372160641Syongari STAILQ_INIT(&sc->sc_cdata.stge_txfreeq); 2373160641Syongari STAILQ_INIT(&sc->sc_cdata.stge_txbusyq); 2374160641Syongari 2375160641Syongari sc->sc_cdata.stge_tx_prod = 0; 2376160641Syongari sc->sc_cdata.stge_tx_cons = 0; 2377160641Syongari sc->sc_cdata.stge_tx_cnt = 0; 2378160641Syongari 2379160641Syongari rd = &sc->sc_rdata; 2380160641Syongari bzero(rd->stge_tx_ring, STGE_TX_RING_SZ); 2381160641Syongari for (i = 0; i < STGE_TX_RING_CNT; i++) { 2382160641Syongari if (i == (STGE_TX_RING_CNT - 1)) 2383160641Syongari addr = STGE_TX_RING_ADDR(sc, 0); 2384160641Syongari else 2385160641Syongari addr = STGE_TX_RING_ADDR(sc, i + 1); 2386160641Syongari rd->stge_tx_ring[i].tfd_next = htole64(addr); 2387160641Syongari rd->stge_tx_ring[i].tfd_control = htole64(TFD_TFDDone); 2388160641Syongari txd = &sc->sc_cdata.stge_txdesc[i]; 2389160641Syongari STAILQ_INSERT_TAIL(&sc->sc_cdata.stge_txfreeq, txd, tx_q); 2390160641Syongari } 2391160641Syongari 2392160641Syongari bus_dmamap_sync(sc->sc_cdata.stge_tx_ring_tag, 2393160641Syongari sc->sc_cdata.stge_tx_ring_map, 2394160641Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2395160641Syongari 2396160641Syongari} 2397160641Syongari 2398160641Syongaristatic int 2399160641Syongaristge_init_rx_ring(struct stge_softc *sc) 2400160641Syongari{ 2401160641Syongari struct stge_ring_data *rd; 2402160641Syongari bus_addr_t addr; 2403160641Syongari int i; 2404160641Syongari 2405160641Syongari sc->sc_cdata.stge_rx_cons = 0; 2406160641Syongari STGE_RXCHAIN_RESET(sc); 2407160641Syongari 2408160641Syongari rd = &sc->sc_rdata; 2409160641Syongari bzero(rd->stge_rx_ring, STGE_RX_RING_SZ); 2410160641Syongari for (i = 0; i < STGE_RX_RING_CNT; i++) { 2411160641Syongari if (stge_newbuf(sc, i) != 0) 2412160641Syongari return (ENOBUFS); 2413160641Syongari if (i == (STGE_RX_RING_CNT - 1)) 2414160641Syongari addr = STGE_RX_RING_ADDR(sc, 0); 2415160641Syongari else 2416160641Syongari addr = STGE_RX_RING_ADDR(sc, i + 1); 2417160641Syongari rd->stge_rx_ring[i].rfd_next = htole64(addr); 2418160641Syongari rd->stge_rx_ring[i].rfd_status = 0; 2419160641Syongari } 2420160641Syongari 2421160641Syongari bus_dmamap_sync(sc->sc_cdata.stge_rx_ring_tag, 2422160641Syongari sc->sc_cdata.stge_rx_ring_map, 2423160641Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2424160641Syongari 2425160641Syongari return (0); 2426160641Syongari} 2427160641Syongari 2428160641Syongari/* 2429160641Syongari * stge_newbuf: 2430160641Syongari * 2431160641Syongari * Add a receive buffer to the indicated descriptor. 2432160641Syongari */ 2433160641Syongaristatic int 2434160641Syongaristge_newbuf(struct stge_softc *sc, int idx) 2435160641Syongari{ 2436160641Syongari struct stge_rxdesc *rxd; 2437160641Syongari struct stge_rfd *rfd; 2438160641Syongari struct mbuf *m; 2439160641Syongari bus_dma_segment_t segs[1]; 2440160641Syongari bus_dmamap_t map; 2441160641Syongari int nsegs; 2442160641Syongari 2443243857Sglebius m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 2444160641Syongari if (m == NULL) 2445160641Syongari return (ENOBUFS); 2446160641Syongari m->m_len = m->m_pkthdr.len = MCLBYTES; 2447160641Syongari /* 2448160641Syongari * The hardware requires 4bytes aligned DMA address when JUMBO 2449160641Syongari * frame is used. 2450160641Syongari */ 2451160641Syongari if (sc->sc_if_framesize <= (MCLBYTES - ETHER_ALIGN)) 2452160641Syongari m_adj(m, ETHER_ALIGN); 2453160641Syongari 2454160641Syongari if (bus_dmamap_load_mbuf_sg(sc->sc_cdata.stge_rx_tag, 2455160641Syongari sc->sc_cdata.stge_rx_sparemap, m, segs, &nsegs, 0) != 0) { 2456160641Syongari m_freem(m); 2457160641Syongari return (ENOBUFS); 2458160641Syongari } 2459160641Syongari KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 2460160641Syongari 2461160641Syongari rxd = &sc->sc_cdata.stge_rxdesc[idx]; 2462160641Syongari if (rxd->rx_m != NULL) { 2463160641Syongari bus_dmamap_sync(sc->sc_cdata.stge_rx_tag, rxd->rx_dmamap, 2464160641Syongari BUS_DMASYNC_POSTREAD); 2465160641Syongari bus_dmamap_unload(sc->sc_cdata.stge_rx_tag, rxd->rx_dmamap); 2466160641Syongari } 2467160641Syongari map = rxd->rx_dmamap; 2468160641Syongari rxd->rx_dmamap = sc->sc_cdata.stge_rx_sparemap; 2469160641Syongari sc->sc_cdata.stge_rx_sparemap = map; 2470160641Syongari bus_dmamap_sync(sc->sc_cdata.stge_rx_tag, rxd->rx_dmamap, 2471160641Syongari BUS_DMASYNC_PREREAD); 2472160641Syongari rxd->rx_m = m; 2473160641Syongari 2474160641Syongari rfd = &sc->sc_rdata.stge_rx_ring[idx]; 2475160641Syongari rfd->rfd_frag.frag_word0 = 2476160641Syongari htole64(FRAG_ADDR(segs[0].ds_addr) | FRAG_LEN(segs[0].ds_len)); 2477160641Syongari rfd->rfd_status = 0; 2478160641Syongari 2479160641Syongari return (0); 2480160641Syongari} 2481160641Syongari 2482160641Syongari/* 2483160641Syongari * stge_set_filter: 2484160641Syongari * 2485160641Syongari * Set up the receive filter. 2486160641Syongari */ 2487160641Syongaristatic void 2488160641Syongaristge_set_filter(struct stge_softc *sc) 2489160641Syongari{ 2490160641Syongari struct ifnet *ifp; 2491160641Syongari uint16_t mode; 2492160641Syongari 2493160641Syongari STGE_LOCK_ASSERT(sc); 2494160641Syongari 2495160641Syongari ifp = sc->sc_ifp; 2496160641Syongari 2497160641Syongari mode = CSR_READ_2(sc, STGE_ReceiveMode); 2498160641Syongari mode |= RM_ReceiveUnicast; 2499160641Syongari if ((ifp->if_flags & IFF_BROADCAST) != 0) 2500160641Syongari mode |= RM_ReceiveBroadcast; 2501160641Syongari else 2502160641Syongari mode &= ~RM_ReceiveBroadcast; 2503160641Syongari if ((ifp->if_flags & IFF_PROMISC) != 0) 2504160641Syongari mode |= RM_ReceiveAllFrames; 2505160641Syongari else 2506160641Syongari mode &= ~RM_ReceiveAllFrames; 2507160641Syongari 2508160641Syongari CSR_WRITE_2(sc, STGE_ReceiveMode, mode); 2509160641Syongari} 2510160641Syongari 2511160641Syongaristatic void 2512160641Syongaristge_set_multi(struct stge_softc *sc) 2513160641Syongari{ 2514160641Syongari struct ifnet *ifp; 2515160641Syongari struct ifmultiaddr *ifma; 2516160641Syongari uint32_t crc; 2517160641Syongari uint32_t mchash[2]; 2518160641Syongari uint16_t mode; 2519160641Syongari int count; 2520160641Syongari 2521160641Syongari STGE_LOCK_ASSERT(sc); 2522160641Syongari 2523160641Syongari ifp = sc->sc_ifp; 2524160641Syongari 2525160641Syongari mode = CSR_READ_2(sc, STGE_ReceiveMode); 2526160641Syongari if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 2527160641Syongari if ((ifp->if_flags & IFF_PROMISC) != 0) 2528160641Syongari mode |= RM_ReceiveAllFrames; 2529160641Syongari else if ((ifp->if_flags & IFF_ALLMULTI) != 0) 2530160641Syongari mode |= RM_ReceiveMulticast; 2531160641Syongari CSR_WRITE_2(sc, STGE_ReceiveMode, mode); 2532160641Syongari return; 2533160641Syongari } 2534160641Syongari 2535160641Syongari /* clear existing filters. */ 2536160641Syongari CSR_WRITE_4(sc, STGE_HashTable0, 0); 2537160641Syongari CSR_WRITE_4(sc, STGE_HashTable1, 0); 2538160641Syongari 2539160641Syongari /* 2540160641Syongari * Set up the multicast address filter by passing all multicast 2541160641Syongari * addresses through a CRC generator, and then using the low-order 2542160641Syongari * 6 bits as an index into the 64 bit multicast hash table. The 2543160641Syongari * high order bits select the register, while the rest of the bits 2544160641Syongari * select the bit within the register. 2545160641Syongari */ 2546160641Syongari 2547160641Syongari bzero(mchash, sizeof(mchash)); 2548160641Syongari 2549160641Syongari count = 0; 2550195049Srwatson if_maddr_rlock(sc->sc_ifp); 2551160641Syongari TAILQ_FOREACH(ifma, &sc->sc_ifp->if_multiaddrs, ifma_link) { 2552160641Syongari if (ifma->ifma_addr->sa_family != AF_LINK) 2553160641Syongari continue; 2554160641Syongari crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) 2555160641Syongari ifma->ifma_addr), ETHER_ADDR_LEN); 2556160641Syongari 2557160641Syongari /* Just want the 6 least significant bits. */ 2558160641Syongari crc &= 0x3f; 2559160641Syongari 2560160641Syongari /* Set the corresponding bit in the hash table. */ 2561160641Syongari mchash[crc >> 5] |= 1 << (crc & 0x1f); 2562160641Syongari count++; 2563160641Syongari } 2564195049Srwatson if_maddr_runlock(ifp); 2565160641Syongari 2566160641Syongari mode &= ~(RM_ReceiveMulticast | RM_ReceiveAllFrames); 2567160641Syongari if (count > 0) 2568160641Syongari mode |= RM_ReceiveMulticastHash; 2569160641Syongari else 2570160641Syongari mode &= ~RM_ReceiveMulticastHash; 2571160641Syongari 2572160641Syongari CSR_WRITE_4(sc, STGE_HashTable0, mchash[0]); 2573160641Syongari CSR_WRITE_4(sc, STGE_HashTable1, mchash[1]); 2574160641Syongari CSR_WRITE_2(sc, STGE_ReceiveMode, mode); 2575160641Syongari} 2576160641Syongari 2577160641Syongaristatic int 2578160641Syongarisysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 2579160641Syongari{ 2580160641Syongari int error, value; 2581160641Syongari 2582160641Syongari if (!arg1) 2583160641Syongari return (EINVAL); 2584160641Syongari value = *(int *)arg1; 2585160641Syongari error = sysctl_handle_int(oidp, &value, 0, req); 2586160641Syongari if (error || !req->newptr) 2587160641Syongari return (error); 2588160641Syongari if (value < low || value > high) 2589160641Syongari return (EINVAL); 2590160641Syongari *(int *)arg1 = value; 2591160641Syongari 2592160641Syongari return (0); 2593160641Syongari} 2594160641Syongari 2595160641Syongaristatic int 2596160641Syongarisysctl_hw_stge_rxint_nframe(SYSCTL_HANDLER_ARGS) 2597160641Syongari{ 2598160641Syongari return (sysctl_int_range(oidp, arg1, arg2, req, 2599160641Syongari STGE_RXINT_NFRAME_MIN, STGE_RXINT_NFRAME_MAX)); 2600160641Syongari} 2601160641Syongari 2602160641Syongaristatic int 2603160641Syongarisysctl_hw_stge_rxint_dmawait(SYSCTL_HANDLER_ARGS) 2604160641Syongari{ 2605160641Syongari return (sysctl_int_range(oidp, arg1, arg2, req, 2606160641Syongari STGE_RXINT_DMAWAIT_MIN, STGE_RXINT_DMAWAIT_MAX)); 2607160641Syongari} 2608