if_stge.c revision 175315
1/* $NetBSD: if_stge.c,v 1.32 2005/12/11 12:22:49 christos Exp $ */ 2 3/*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39/* 40 * Device driver for the Sundance Tech. TC9021 10/100/1000 41 * Ethernet controller. 42 */ 43 44#include <sys/cdefs.h> 45__FBSDID("$FreeBSD: head/sys/dev/stge/if_stge.c 175315 2008-01-14 07:16:48Z yongari $"); 46 47#ifdef HAVE_KERNEL_OPTION_HEADERS 48#include "opt_device_polling.h" 49#endif 50 51#include <sys/param.h> 52#include <sys/systm.h> 53#include <sys/endian.h> 54#include <sys/mbuf.h> 55#include <sys/malloc.h> 56#include <sys/kernel.h> 57#include <sys/module.h> 58#include <sys/socket.h> 59#include <sys/sockio.h> 60#include <sys/sysctl.h> 61#include <sys/taskqueue.h> 62 63#include <net/bpf.h> 64#include <net/ethernet.h> 65#include <net/if.h> 66#include <net/if_dl.h> 67#include <net/if_media.h> 68#include <net/if_types.h> 69#include <net/if_vlan_var.h> 70 71#include <machine/bus.h> 72#include <machine/resource.h> 73#include <sys/bus.h> 74#include <sys/rman.h> 75 76#include <dev/mii/mii.h> 77#include <dev/mii/miivar.h> 78 79#include <dev/pci/pcireg.h> 80#include <dev/pci/pcivar.h> 81 82#include <dev/stge/if_stgereg.h> 83 84#define STGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 85 86MODULE_DEPEND(stge, pci, 1, 1, 1); 87MODULE_DEPEND(stge, ether, 1, 1, 1); 88MODULE_DEPEND(stge, miibus, 1, 1, 1); 89 90/* "device miibus" required. See GENERIC if you get errors here. */ 91#include "miibus_if.h" 92 93/* 94 * Devices supported by this driver. 95 */ 96static struct stge_product { 97 uint16_t stge_vendorid; 98 uint16_t stge_deviceid; 99 const char *stge_name; 100} stge_products[] = { 101 { VENDOR_SUNDANCETI, DEVICEID_SUNDANCETI_ST1023, 102 "Sundance ST-1023 Gigabit Ethernet" }, 103 104 { VENDOR_SUNDANCETI, DEVICEID_SUNDANCETI_ST2021, 105 "Sundance ST-2021 Gigabit Ethernet" }, 106 107 { VENDOR_TAMARACK, DEVICEID_TAMARACK_TC9021, 108 "Tamarack TC9021 Gigabit Ethernet" }, 109 110 { VENDOR_TAMARACK, DEVICEID_TAMARACK_TC9021_ALT, 111 "Tamarack TC9021 Gigabit Ethernet" }, 112 113 /* 114 * The Sundance sample boards use the Sundance vendor ID, 115 * but the Tamarack product ID. 116 */ 117 { VENDOR_SUNDANCETI, DEVICEID_TAMARACK_TC9021, 118 "Sundance TC9021 Gigabit Ethernet" }, 119 120 { VENDOR_SUNDANCETI, DEVICEID_TAMARACK_TC9021_ALT, 121 "Sundance TC9021 Gigabit Ethernet" }, 122 123 { VENDOR_DLINK, DEVICEID_DLINK_DL4000, 124 "D-Link DL-4000 Gigabit Ethernet" }, 125 126 { VENDOR_ANTARES, DEVICEID_ANTARES_TC9021, 127 "Antares Gigabit Ethernet" } 128}; 129 130static int stge_probe(device_t); 131static int stge_attach(device_t); 132static int stge_detach(device_t); 133static int stge_shutdown(device_t); 134static int stge_suspend(device_t); 135static int stge_resume(device_t); 136 137static int stge_encap(struct stge_softc *, struct mbuf **); 138static void stge_start(struct ifnet *); 139static void stge_start_locked(struct ifnet *); 140static void stge_watchdog(struct stge_softc *); 141static int stge_ioctl(struct ifnet *, u_long, caddr_t); 142static void stge_init(void *); 143static void stge_init_locked(struct stge_softc *); 144static void stge_vlan_setup(struct stge_softc *); 145static void stge_stop(struct stge_softc *); 146static void stge_start_tx(struct stge_softc *); 147static void stge_start_rx(struct stge_softc *); 148static void stge_stop_tx(struct stge_softc *); 149static void stge_stop_rx(struct stge_softc *); 150 151static void stge_reset(struct stge_softc *, uint32_t); 152static int stge_eeprom_wait(struct stge_softc *); 153static void stge_read_eeprom(struct stge_softc *, int, uint16_t *); 154static void stge_tick(void *); 155static void stge_stats_update(struct stge_softc *); 156static void stge_set_filter(struct stge_softc *); 157static void stge_set_multi(struct stge_softc *); 158 159static void stge_link_task(void *, int); 160static void stge_intr(void *); 161static __inline int stge_tx_error(struct stge_softc *); 162static void stge_txeof(struct stge_softc *); 163static void stge_rxeof(struct stge_softc *); 164static __inline void stge_discard_rxbuf(struct stge_softc *, int); 165static int stge_newbuf(struct stge_softc *, int); 166#ifndef __NO_STRICT_ALIGNMENT 167static __inline struct mbuf *stge_fixup_rx(struct stge_softc *, struct mbuf *); 168#endif 169 170static void stge_mii_sync(struct stge_softc *); 171static void stge_mii_send(struct stge_softc *, uint32_t, int); 172static int stge_mii_readreg(struct stge_softc *, struct stge_mii_frame *); 173static int stge_mii_writereg(struct stge_softc *, struct stge_mii_frame *); 174static int stge_miibus_readreg(device_t, int, int); 175static int stge_miibus_writereg(device_t, int, int, int); 176static void stge_miibus_statchg(device_t); 177static int stge_mediachange(struct ifnet *); 178static void stge_mediastatus(struct ifnet *, struct ifmediareq *); 179 180static void stge_dmamap_cb(void *, bus_dma_segment_t *, int, int); 181static int stge_dma_alloc(struct stge_softc *); 182static void stge_dma_free(struct stge_softc *); 183static void stge_dma_wait(struct stge_softc *); 184static void stge_init_tx_ring(struct stge_softc *); 185static int stge_init_rx_ring(struct stge_softc *); 186#ifdef DEVICE_POLLING 187static void stge_poll(struct ifnet *, enum poll_cmd, int); 188#endif 189 190static void stge_setwol(struct stge_softc *); 191static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 192static int sysctl_hw_stge_rxint_nframe(SYSCTL_HANDLER_ARGS); 193static int sysctl_hw_stge_rxint_dmawait(SYSCTL_HANDLER_ARGS); 194 195static device_method_t stge_methods[] = { 196 /* Device interface */ 197 DEVMETHOD(device_probe, stge_probe), 198 DEVMETHOD(device_attach, stge_attach), 199 DEVMETHOD(device_detach, stge_detach), 200 DEVMETHOD(device_shutdown, stge_shutdown), 201 DEVMETHOD(device_suspend, stge_suspend), 202 DEVMETHOD(device_resume, stge_resume), 203 204 /* MII interface */ 205 DEVMETHOD(miibus_readreg, stge_miibus_readreg), 206 DEVMETHOD(miibus_writereg, stge_miibus_writereg), 207 DEVMETHOD(miibus_statchg, stge_miibus_statchg), 208 209 { 0, 0 } 210 211}; 212 213static driver_t stge_driver = { 214 "stge", 215 stge_methods, 216 sizeof(struct stge_softc) 217}; 218 219static devclass_t stge_devclass; 220 221DRIVER_MODULE(stge, pci, stge_driver, stge_devclass, 0, 0); 222DRIVER_MODULE(miibus, stge, miibus_driver, miibus_devclass, 0, 0); 223 224static struct resource_spec stge_res_spec_io[] = { 225 { SYS_RES_IOPORT, PCIR_BAR(0), RF_ACTIVE }, 226 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 227 { -1, 0, 0 } 228}; 229 230static struct resource_spec stge_res_spec_mem[] = { 231 { SYS_RES_MEMORY, PCIR_BAR(1), RF_ACTIVE }, 232 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 233 { -1, 0, 0 } 234}; 235 236#define MII_SET(x) \ 237 CSR_WRITE_1(sc, STGE_PhyCtrl, CSR_READ_1(sc, STGE_PhyCtrl) | (x)) 238#define MII_CLR(x) \ 239 CSR_WRITE_1(sc, STGE_PhyCtrl, CSR_READ_1(sc, STGE_PhyCtrl) & ~(x)) 240 241/* 242 * Sync the PHYs by setting data bit and strobing the clock 32 times. 243 */ 244static void 245stge_mii_sync(struct stge_softc *sc) 246{ 247 int i; 248 249 MII_SET(PC_MgmtDir | PC_MgmtData); 250 251 for (i = 0; i < 32; i++) { 252 MII_SET(PC_MgmtClk); 253 DELAY(1); 254 MII_CLR(PC_MgmtClk); 255 DELAY(1); 256 } 257} 258 259/* 260 * Clock a series of bits through the MII. 261 */ 262static void 263stge_mii_send(struct stge_softc *sc, uint32_t bits, int cnt) 264{ 265 int i; 266 267 MII_CLR(PC_MgmtClk); 268 269 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 270 if (bits & i) 271 MII_SET(PC_MgmtData); 272 else 273 MII_CLR(PC_MgmtData); 274 DELAY(1); 275 MII_CLR(PC_MgmtClk); 276 DELAY(1); 277 MII_SET(PC_MgmtClk); 278 } 279} 280 281/* 282 * Read an PHY register through the MII. 283 */ 284static int 285stge_mii_readreg(struct stge_softc *sc, struct stge_mii_frame *frame) 286{ 287 int i, ack; 288 289 /* 290 * Set up frame for RX. 291 */ 292 frame->mii_stdelim = STGE_MII_STARTDELIM; 293 frame->mii_opcode = STGE_MII_READOP; 294 frame->mii_turnaround = 0; 295 frame->mii_data = 0; 296 297 CSR_WRITE_1(sc, STGE_PhyCtrl, 0 | sc->sc_PhyCtrl); 298 /* 299 * Turn on data xmit. 300 */ 301 MII_SET(PC_MgmtDir); 302 303 stge_mii_sync(sc); 304 305 /* 306 * Send command/address info. 307 */ 308 stge_mii_send(sc, frame->mii_stdelim, 2); 309 stge_mii_send(sc, frame->mii_opcode, 2); 310 stge_mii_send(sc, frame->mii_phyaddr, 5); 311 stge_mii_send(sc, frame->mii_regaddr, 5); 312 313 /* Turn off xmit. */ 314 MII_CLR(PC_MgmtDir); 315 316 /* Idle bit */ 317 MII_CLR((PC_MgmtClk | PC_MgmtData)); 318 DELAY(1); 319 MII_SET(PC_MgmtClk); 320 DELAY(1); 321 322 /* Check for ack */ 323 MII_CLR(PC_MgmtClk); 324 DELAY(1); 325 ack = CSR_READ_1(sc, STGE_PhyCtrl) & PC_MgmtData; 326 MII_SET(PC_MgmtClk); 327 DELAY(1); 328 329 /* 330 * Now try reading data bits. If the ack failed, we still 331 * need to clock through 16 cycles to keep the PHY(s) in sync. 332 */ 333 if (ack) { 334 for(i = 0; i < 16; i++) { 335 MII_CLR(PC_MgmtClk); 336 DELAY(1); 337 MII_SET(PC_MgmtClk); 338 DELAY(1); 339 } 340 goto fail; 341 } 342 343 for (i = 0x8000; i; i >>= 1) { 344 MII_CLR(PC_MgmtClk); 345 DELAY(1); 346 if (!ack) { 347 if (CSR_READ_1(sc, STGE_PhyCtrl) & PC_MgmtData) 348 frame->mii_data |= i; 349 DELAY(1); 350 } 351 MII_SET(PC_MgmtClk); 352 DELAY(1); 353 } 354 355fail: 356 MII_CLR(PC_MgmtClk); 357 DELAY(1); 358 MII_SET(PC_MgmtClk); 359 DELAY(1); 360 361 if (ack) 362 return(1); 363 return(0); 364} 365 366/* 367 * Write to a PHY register through the MII. 368 */ 369static int 370stge_mii_writereg(struct stge_softc *sc, struct stge_mii_frame *frame) 371{ 372 373 /* 374 * Set up frame for TX. 375 */ 376 frame->mii_stdelim = STGE_MII_STARTDELIM; 377 frame->mii_opcode = STGE_MII_WRITEOP; 378 frame->mii_turnaround = STGE_MII_TURNAROUND; 379 380 /* 381 * Turn on data output. 382 */ 383 MII_SET(PC_MgmtDir); 384 385 stge_mii_sync(sc); 386 387 stge_mii_send(sc, frame->mii_stdelim, 2); 388 stge_mii_send(sc, frame->mii_opcode, 2); 389 stge_mii_send(sc, frame->mii_phyaddr, 5); 390 stge_mii_send(sc, frame->mii_regaddr, 5); 391 stge_mii_send(sc, frame->mii_turnaround, 2); 392 stge_mii_send(sc, frame->mii_data, 16); 393 394 /* Idle bit. */ 395 MII_SET(PC_MgmtClk); 396 DELAY(1); 397 MII_CLR(PC_MgmtClk); 398 DELAY(1); 399 400 /* 401 * Turn off xmit. 402 */ 403 MII_CLR(PC_MgmtDir); 404 405 return(0); 406} 407 408/* 409 * sc_miibus_readreg: [mii interface function] 410 * 411 * Read a PHY register on the MII of the TC9021. 412 */ 413static int 414stge_miibus_readreg(device_t dev, int phy, int reg) 415{ 416 struct stge_softc *sc; 417 struct stge_mii_frame frame; 418 int error; 419 420 sc = device_get_softc(dev); 421 422 if (reg == STGE_PhyCtrl) { 423 /* XXX allow ip1000phy read STGE_PhyCtrl register. */ 424 STGE_MII_LOCK(sc); 425 error = CSR_READ_1(sc, STGE_PhyCtrl); 426 STGE_MII_UNLOCK(sc); 427 return (error); 428 } 429 bzero(&frame, sizeof(frame)); 430 frame.mii_phyaddr = phy; 431 frame.mii_regaddr = reg; 432 433 STGE_MII_LOCK(sc); 434 error = stge_mii_readreg(sc, &frame); 435 STGE_MII_UNLOCK(sc); 436 437 if (error != 0) { 438 /* Don't show errors for PHY probe request */ 439 if (reg != 1) 440 device_printf(sc->sc_dev, "phy read fail\n"); 441 return (0); 442 } 443 return (frame.mii_data); 444} 445 446/* 447 * stge_miibus_writereg: [mii interface function] 448 * 449 * Write a PHY register on the MII of the TC9021. 450 */ 451static int 452stge_miibus_writereg(device_t dev, int phy, int reg, int val) 453{ 454 struct stge_softc *sc; 455 struct stge_mii_frame frame; 456 int error; 457 458 sc = device_get_softc(dev); 459 460 bzero(&frame, sizeof(frame)); 461 frame.mii_phyaddr = phy; 462 frame.mii_regaddr = reg; 463 frame.mii_data = val; 464 465 STGE_MII_LOCK(sc); 466 error = stge_mii_writereg(sc, &frame); 467 STGE_MII_UNLOCK(sc); 468 469 if (error != 0) 470 device_printf(sc->sc_dev, "phy write fail\n"); 471 return (0); 472} 473 474/* 475 * stge_miibus_statchg: [mii interface function] 476 * 477 * Callback from MII layer when media changes. 478 */ 479static void 480stge_miibus_statchg(device_t dev) 481{ 482 struct stge_softc *sc; 483 484 sc = device_get_softc(dev); 485 taskqueue_enqueue(taskqueue_swi, &sc->sc_link_task); 486} 487 488/* 489 * stge_mediastatus: [ifmedia interface function] 490 * 491 * Get the current interface media status. 492 */ 493static void 494stge_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 495{ 496 struct stge_softc *sc; 497 struct mii_data *mii; 498 499 sc = ifp->if_softc; 500 mii = device_get_softc(sc->sc_miibus); 501 502 mii_pollstat(mii); 503 ifmr->ifm_status = mii->mii_media_status; 504 ifmr->ifm_active = mii->mii_media_active; 505} 506 507/* 508 * stge_mediachange: [ifmedia interface function] 509 * 510 * Set hardware to newly-selected media. 511 */ 512static int 513stge_mediachange(struct ifnet *ifp) 514{ 515 struct stge_softc *sc; 516 struct mii_data *mii; 517 518 sc = ifp->if_softc; 519 mii = device_get_softc(sc->sc_miibus); 520 mii_mediachg(mii); 521 522 return (0); 523} 524 525static int 526stge_eeprom_wait(struct stge_softc *sc) 527{ 528 int i; 529 530 for (i = 0; i < STGE_TIMEOUT; i++) { 531 DELAY(1000); 532 if ((CSR_READ_2(sc, STGE_EepromCtrl) & EC_EepromBusy) == 0) 533 return (0); 534 } 535 return (1); 536} 537 538/* 539 * stge_read_eeprom: 540 * 541 * Read data from the serial EEPROM. 542 */ 543static void 544stge_read_eeprom(struct stge_softc *sc, int offset, uint16_t *data) 545{ 546 547 if (stge_eeprom_wait(sc)) 548 device_printf(sc->sc_dev, "EEPROM failed to come ready\n"); 549 550 CSR_WRITE_2(sc, STGE_EepromCtrl, 551 EC_EepromAddress(offset) | EC_EepromOpcode(EC_OP_RR)); 552 if (stge_eeprom_wait(sc)) 553 device_printf(sc->sc_dev, "EEPROM read timed out\n"); 554 *data = CSR_READ_2(sc, STGE_EepromData); 555} 556 557 558static int 559stge_probe(device_t dev) 560{ 561 struct stge_product *sp; 562 int i; 563 uint16_t vendor, devid; 564 565 vendor = pci_get_vendor(dev); 566 devid = pci_get_device(dev); 567 sp = stge_products; 568 for (i = 0; i < sizeof(stge_products)/sizeof(stge_products[0]); 569 i++, sp++) { 570 if (vendor == sp->stge_vendorid && 571 devid == sp->stge_deviceid) { 572 device_set_desc(dev, sp->stge_name); 573 return (BUS_PROBE_DEFAULT); 574 } 575 } 576 577 return (ENXIO); 578} 579 580static int 581stge_attach(device_t dev) 582{ 583 struct stge_softc *sc; 584 struct ifnet *ifp; 585 uint8_t enaddr[ETHER_ADDR_LEN]; 586 int error, i; 587 uint16_t cmd; 588 uint32_t val; 589 590 error = 0; 591 sc = device_get_softc(dev); 592 sc->sc_dev = dev; 593 594 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 595 MTX_DEF); 596 mtx_init(&sc->sc_mii_mtx, "stge_mii_mutex", NULL, MTX_DEF); 597 callout_init_mtx(&sc->sc_tick_ch, &sc->sc_mtx, 0); 598 TASK_INIT(&sc->sc_link_task, 0, stge_link_task, sc); 599 600 /* 601 * Map the device. 602 */ 603 pci_enable_busmaster(dev); 604 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 605 val = pci_read_config(dev, PCIR_BAR(1), 4); 606 if ((val & 0x01) != 0) 607 sc->sc_spec = stge_res_spec_mem; 608 else { 609 val = pci_read_config(dev, PCIR_BAR(0), 4); 610 if ((val & 0x01) == 0) { 611 device_printf(sc->sc_dev, "couldn't locate IO BAR\n"); 612 error = ENXIO; 613 goto fail; 614 } 615 sc->sc_spec = stge_res_spec_io; 616 } 617 error = bus_alloc_resources(dev, sc->sc_spec, sc->sc_res); 618 if (error != 0) { 619 device_printf(dev, "couldn't allocate %s resources\n", 620 sc->sc_spec == stge_res_spec_mem ? "memory" : "I/O"); 621 goto fail; 622 } 623 sc->sc_rev = pci_get_revid(dev); 624 625 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 626 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 627 "rxint_nframe", CTLTYPE_INT|CTLFLAG_RW, &sc->sc_rxint_nframe, 0, 628 sysctl_hw_stge_rxint_nframe, "I", "stge rx interrupt nframe"); 629 630 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 631 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 632 "rxint_dmawait", CTLTYPE_INT|CTLFLAG_RW, &sc->sc_rxint_dmawait, 0, 633 sysctl_hw_stge_rxint_dmawait, "I", "stge rx interrupt dmawait"); 634 635 /* Pull in device tunables. */ 636 sc->sc_rxint_nframe = STGE_RXINT_NFRAME_DEFAULT; 637 error = resource_int_value(device_get_name(dev), device_get_unit(dev), 638 "rxint_nframe", &sc->sc_rxint_nframe); 639 if (error == 0) { 640 if (sc->sc_rxint_nframe < STGE_RXINT_NFRAME_MIN || 641 sc->sc_rxint_nframe > STGE_RXINT_NFRAME_MAX) { 642 device_printf(dev, "rxint_nframe value out of range; " 643 "using default: %d\n", STGE_RXINT_NFRAME_DEFAULT); 644 sc->sc_rxint_nframe = STGE_RXINT_NFRAME_DEFAULT; 645 } 646 } 647 648 sc->sc_rxint_dmawait = STGE_RXINT_DMAWAIT_DEFAULT; 649 error = resource_int_value(device_get_name(dev), device_get_unit(dev), 650 "rxint_dmawait", &sc->sc_rxint_dmawait); 651 if (error == 0) { 652 if (sc->sc_rxint_dmawait < STGE_RXINT_DMAWAIT_MIN || 653 sc->sc_rxint_dmawait > STGE_RXINT_DMAWAIT_MAX) { 654 device_printf(dev, "rxint_dmawait value out of range; " 655 "using default: %d\n", STGE_RXINT_DMAWAIT_DEFAULT); 656 sc->sc_rxint_dmawait = STGE_RXINT_DMAWAIT_DEFAULT; 657 } 658 } 659 660 if ((error = stge_dma_alloc(sc) != 0)) 661 goto fail; 662 663 /* 664 * Determine if we're copper or fiber. It affects how we 665 * reset the card. 666 */ 667 if (CSR_READ_4(sc, STGE_AsicCtrl) & AC_PhyMedia) 668 sc->sc_usefiber = 1; 669 else 670 sc->sc_usefiber = 0; 671 672 /* Load LED configuration from EEPROM. */ 673 stge_read_eeprom(sc, STGE_EEPROM_LEDMode, &sc->sc_led); 674 675 /* 676 * Reset the chip to a known state. 677 */ 678 STGE_LOCK(sc); 679 stge_reset(sc, STGE_RESET_FULL); 680 STGE_UNLOCK(sc); 681 682 /* 683 * Reading the station address from the EEPROM doesn't seem 684 * to work, at least on my sample boards. Instead, since 685 * the reset sequence does AutoInit, read it from the station 686 * address registers. For Sundance 1023 you can only read it 687 * from EEPROM. 688 */ 689 if (pci_get_device(dev) != DEVICEID_SUNDANCETI_ST1023) { 690 uint16_t v; 691 692 v = CSR_READ_2(sc, STGE_StationAddress0); 693 enaddr[0] = v & 0xff; 694 enaddr[1] = v >> 8; 695 v = CSR_READ_2(sc, STGE_StationAddress1); 696 enaddr[2] = v & 0xff; 697 enaddr[3] = v >> 8; 698 v = CSR_READ_2(sc, STGE_StationAddress2); 699 enaddr[4] = v & 0xff; 700 enaddr[5] = v >> 8; 701 sc->sc_stge1023 = 0; 702 } else { 703 uint16_t myaddr[ETHER_ADDR_LEN / 2]; 704 for (i = 0; i <ETHER_ADDR_LEN / 2; i++) { 705 stge_read_eeprom(sc, STGE_EEPROM_StationAddress0 + i, 706 &myaddr[i]); 707 myaddr[i] = le16toh(myaddr[i]); 708 } 709 bcopy(myaddr, enaddr, sizeof(enaddr)); 710 sc->sc_stge1023 = 1; 711 } 712 713 ifp = sc->sc_ifp = if_alloc(IFT_ETHER); 714 if (ifp == NULL) { 715 device_printf(sc->sc_dev, "failed to if_alloc()\n"); 716 error = ENXIO; 717 goto fail; 718 } 719 720 ifp->if_softc = sc; 721 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 722 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 723 ifp->if_ioctl = stge_ioctl; 724 ifp->if_start = stge_start; 725 ifp->if_timer = 0; 726 ifp->if_watchdog = NULL; 727 ifp->if_init = stge_init; 728 ifp->if_mtu = ETHERMTU; 729 ifp->if_snd.ifq_drv_maxlen = STGE_TX_RING_CNT - 1; 730 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 731 IFQ_SET_READY(&ifp->if_snd); 732 /* Revision B3 and earlier chips have checksum bug. */ 733 if (sc->sc_rev >= 0x0c) { 734 ifp->if_hwassist = STGE_CSUM_FEATURES; 735 ifp->if_capabilities = IFCAP_HWCSUM; 736 } else { 737 ifp->if_hwassist = 0; 738 ifp->if_capabilities = 0; 739 } 740 ifp->if_capabilities |= IFCAP_WOL_MAGIC; 741 ifp->if_capenable = ifp->if_capabilities; 742 743 /* 744 * Read some important bits from the PhyCtrl register. 745 */ 746 sc->sc_PhyCtrl = CSR_READ_1(sc, STGE_PhyCtrl) & 747 (PC_PhyDuplexPolarity | PC_PhyLnkPolarity); 748 749 /* Set up MII bus. */ 750 if ((error = mii_phy_probe(sc->sc_dev, &sc->sc_miibus, stge_mediachange, 751 stge_mediastatus)) != 0) { 752 device_printf(sc->sc_dev, "no PHY found!\n"); 753 goto fail; 754 } 755 756 ether_ifattach(ifp, enaddr); 757 758 /* VLAN capability setup */ 759 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 760 if (sc->sc_rev >= 0x0c) 761 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 762 ifp->if_capenable = ifp->if_capabilities; 763#ifdef DEVICE_POLLING 764 ifp->if_capabilities |= IFCAP_POLLING; 765#endif 766 /* 767 * Tell the upper layer(s) we support long frames. 768 * Must appear after the call to ether_ifattach() because 769 * ether_ifattach() sets ifi_hdrlen to the default value. 770 */ 771 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 772 773 /* 774 * The manual recommends disabling early transmit, so we 775 * do. It's disabled anyway, if using IP checksumming, 776 * since the entire packet must be in the FIFO in order 777 * for the chip to perform the checksum. 778 */ 779 sc->sc_txthresh = 0x0fff; 780 781 /* 782 * Disable MWI if the PCI layer tells us to. 783 */ 784 sc->sc_DMACtrl = 0; 785 if ((cmd & PCIM_CMD_MWRICEN) == 0) 786 sc->sc_DMACtrl |= DMAC_MWIDisable; 787 788 /* 789 * Hookup IRQ 790 */ 791 error = bus_setup_intr(dev, sc->sc_res[1], INTR_TYPE_NET | INTR_MPSAFE, 792 NULL, stge_intr, sc, &sc->sc_ih); 793 if (error != 0) { 794 ether_ifdetach(ifp); 795 device_printf(sc->sc_dev, "couldn't set up IRQ\n"); 796 sc->sc_ifp = NULL; 797 goto fail; 798 } 799 800fail: 801 if (error != 0) 802 stge_detach(dev); 803 804 return (error); 805} 806 807static int 808stge_detach(device_t dev) 809{ 810 struct stge_softc *sc; 811 struct ifnet *ifp; 812 813 sc = device_get_softc(dev); 814 815 ifp = sc->sc_ifp; 816#ifdef DEVICE_POLLING 817 if (ifp && ifp->if_capenable & IFCAP_POLLING) 818 ether_poll_deregister(ifp); 819#endif 820 if (device_is_attached(dev)) { 821 STGE_LOCK(sc); 822 /* XXX */ 823 sc->sc_detach = 1; 824 stge_stop(sc); 825 STGE_UNLOCK(sc); 826 callout_drain(&sc->sc_tick_ch); 827 taskqueue_drain(taskqueue_swi, &sc->sc_link_task); 828 ether_ifdetach(ifp); 829 } 830 831 if (sc->sc_miibus != NULL) { 832 device_delete_child(dev, sc->sc_miibus); 833 sc->sc_miibus = NULL; 834 } 835 bus_generic_detach(dev); 836 stge_dma_free(sc); 837 838 if (ifp != NULL) { 839 if_free(ifp); 840 sc->sc_ifp = NULL; 841 } 842 843 if (sc->sc_ih) { 844 bus_teardown_intr(dev, sc->sc_res[1], sc->sc_ih); 845 sc->sc_ih = NULL; 846 } 847 bus_release_resources(dev, sc->sc_spec, sc->sc_res); 848 849 mtx_destroy(&sc->sc_mii_mtx); 850 mtx_destroy(&sc->sc_mtx); 851 852 return (0); 853} 854 855struct stge_dmamap_arg { 856 bus_addr_t stge_busaddr; 857}; 858 859static void 860stge_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 861{ 862 struct stge_dmamap_arg *ctx; 863 864 if (error != 0) 865 return; 866 867 ctx = (struct stge_dmamap_arg *)arg; 868 ctx->stge_busaddr = segs[0].ds_addr; 869} 870 871static int 872stge_dma_alloc(struct stge_softc *sc) 873{ 874 struct stge_dmamap_arg ctx; 875 struct stge_txdesc *txd; 876 struct stge_rxdesc *rxd; 877 int error, i; 878 879 /* create parent tag. */ 880 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev),/* parent */ 881 1, 0, /* algnmnt, boundary */ 882 STGE_DMA_MAXADDR, /* lowaddr */ 883 BUS_SPACE_MAXADDR, /* highaddr */ 884 NULL, NULL, /* filter, filterarg */ 885 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 886 0, /* nsegments */ 887 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 888 0, /* flags */ 889 NULL, NULL, /* lockfunc, lockarg */ 890 &sc->sc_cdata.stge_parent_tag); 891 if (error != 0) { 892 device_printf(sc->sc_dev, "failed to create parent DMA tag\n"); 893 goto fail; 894 } 895 /* create tag for Tx ring. */ 896 error = bus_dma_tag_create(sc->sc_cdata.stge_parent_tag,/* parent */ 897 STGE_RING_ALIGN, 0, /* algnmnt, boundary */ 898 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 899 BUS_SPACE_MAXADDR, /* highaddr */ 900 NULL, NULL, /* filter, filterarg */ 901 STGE_TX_RING_SZ, /* maxsize */ 902 1, /* nsegments */ 903 STGE_TX_RING_SZ, /* maxsegsize */ 904 0, /* flags */ 905 NULL, NULL, /* lockfunc, lockarg */ 906 &sc->sc_cdata.stge_tx_ring_tag); 907 if (error != 0) { 908 device_printf(sc->sc_dev, 909 "failed to allocate Tx ring DMA tag\n"); 910 goto fail; 911 } 912 913 /* create tag for Rx ring. */ 914 error = bus_dma_tag_create(sc->sc_cdata.stge_parent_tag,/* parent */ 915 STGE_RING_ALIGN, 0, /* algnmnt, boundary */ 916 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 917 BUS_SPACE_MAXADDR, /* highaddr */ 918 NULL, NULL, /* filter, filterarg */ 919 STGE_RX_RING_SZ, /* maxsize */ 920 1, /* nsegments */ 921 STGE_RX_RING_SZ, /* maxsegsize */ 922 0, /* flags */ 923 NULL, NULL, /* lockfunc, lockarg */ 924 &sc->sc_cdata.stge_rx_ring_tag); 925 if (error != 0) { 926 device_printf(sc->sc_dev, 927 "failed to allocate Rx ring DMA tag\n"); 928 goto fail; 929 } 930 931 /* create tag for Tx buffers. */ 932 error = bus_dma_tag_create(sc->sc_cdata.stge_parent_tag,/* parent */ 933 1, 0, /* algnmnt, boundary */ 934 BUS_SPACE_MAXADDR, /* lowaddr */ 935 BUS_SPACE_MAXADDR, /* highaddr */ 936 NULL, NULL, /* filter, filterarg */ 937 MCLBYTES * STGE_MAXTXSEGS, /* maxsize */ 938 STGE_MAXTXSEGS, /* nsegments */ 939 MCLBYTES, /* maxsegsize */ 940 0, /* flags */ 941 NULL, NULL, /* lockfunc, lockarg */ 942 &sc->sc_cdata.stge_tx_tag); 943 if (error != 0) { 944 device_printf(sc->sc_dev, "failed to allocate Tx DMA tag\n"); 945 goto fail; 946 } 947 948 /* create tag for Rx buffers. */ 949 error = bus_dma_tag_create(sc->sc_cdata.stge_parent_tag,/* parent */ 950 1, 0, /* algnmnt, boundary */ 951 BUS_SPACE_MAXADDR, /* lowaddr */ 952 BUS_SPACE_MAXADDR, /* highaddr */ 953 NULL, NULL, /* filter, filterarg */ 954 MCLBYTES, /* maxsize */ 955 1, /* nsegments */ 956 MCLBYTES, /* maxsegsize */ 957 0, /* flags */ 958 NULL, NULL, /* lockfunc, lockarg */ 959 &sc->sc_cdata.stge_rx_tag); 960 if (error != 0) { 961 device_printf(sc->sc_dev, "failed to allocate Rx DMA tag\n"); 962 goto fail; 963 } 964 965 /* allocate DMA'able memory and load the DMA map for Tx ring. */ 966 error = bus_dmamem_alloc(sc->sc_cdata.stge_tx_ring_tag, 967 (void **)&sc->sc_rdata.stge_tx_ring, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 968 &sc->sc_cdata.stge_tx_ring_map); 969 if (error != 0) { 970 device_printf(sc->sc_dev, 971 "failed to allocate DMA'able memory for Tx ring\n"); 972 goto fail; 973 } 974 975 ctx.stge_busaddr = 0; 976 error = bus_dmamap_load(sc->sc_cdata.stge_tx_ring_tag, 977 sc->sc_cdata.stge_tx_ring_map, sc->sc_rdata.stge_tx_ring, 978 STGE_TX_RING_SZ, stge_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 979 if (error != 0 || ctx.stge_busaddr == 0) { 980 device_printf(sc->sc_dev, 981 "failed to load DMA'able memory for Tx ring\n"); 982 goto fail; 983 } 984 sc->sc_rdata.stge_tx_ring_paddr = ctx.stge_busaddr; 985 986 /* allocate DMA'able memory and load the DMA map for Rx ring. */ 987 error = bus_dmamem_alloc(sc->sc_cdata.stge_rx_ring_tag, 988 (void **)&sc->sc_rdata.stge_rx_ring, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 989 &sc->sc_cdata.stge_rx_ring_map); 990 if (error != 0) { 991 device_printf(sc->sc_dev, 992 "failed to allocate DMA'able memory for Rx ring\n"); 993 goto fail; 994 } 995 996 ctx.stge_busaddr = 0; 997 error = bus_dmamap_load(sc->sc_cdata.stge_rx_ring_tag, 998 sc->sc_cdata.stge_rx_ring_map, sc->sc_rdata.stge_rx_ring, 999 STGE_RX_RING_SZ, stge_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 1000 if (error != 0 || ctx.stge_busaddr == 0) { 1001 device_printf(sc->sc_dev, 1002 "failed to load DMA'able memory for Rx ring\n"); 1003 goto fail; 1004 } 1005 sc->sc_rdata.stge_rx_ring_paddr = ctx.stge_busaddr; 1006 1007 /* create DMA maps for Tx buffers. */ 1008 for (i = 0; i < STGE_TX_RING_CNT; i++) { 1009 txd = &sc->sc_cdata.stge_txdesc[i]; 1010 txd->tx_m = NULL; 1011 txd->tx_dmamap = 0; 1012 error = bus_dmamap_create(sc->sc_cdata.stge_tx_tag, 0, 1013 &txd->tx_dmamap); 1014 if (error != 0) { 1015 device_printf(sc->sc_dev, 1016 "failed to create Tx dmamap\n"); 1017 goto fail; 1018 } 1019 } 1020 /* create DMA maps for Rx buffers. */ 1021 if ((error = bus_dmamap_create(sc->sc_cdata.stge_rx_tag, 0, 1022 &sc->sc_cdata.stge_rx_sparemap)) != 0) { 1023 device_printf(sc->sc_dev, "failed to create spare Rx dmamap\n"); 1024 goto fail; 1025 } 1026 for (i = 0; i < STGE_RX_RING_CNT; i++) { 1027 rxd = &sc->sc_cdata.stge_rxdesc[i]; 1028 rxd->rx_m = NULL; 1029 rxd->rx_dmamap = 0; 1030 error = bus_dmamap_create(sc->sc_cdata.stge_rx_tag, 0, 1031 &rxd->rx_dmamap); 1032 if (error != 0) { 1033 device_printf(sc->sc_dev, 1034 "failed to create Rx dmamap\n"); 1035 goto fail; 1036 } 1037 } 1038 1039fail: 1040 return (error); 1041} 1042 1043static void 1044stge_dma_free(struct stge_softc *sc) 1045{ 1046 struct stge_txdesc *txd; 1047 struct stge_rxdesc *rxd; 1048 int i; 1049 1050 /* Tx ring */ 1051 if (sc->sc_cdata.stge_tx_ring_tag) { 1052 if (sc->sc_cdata.stge_tx_ring_map) 1053 bus_dmamap_unload(sc->sc_cdata.stge_tx_ring_tag, 1054 sc->sc_cdata.stge_tx_ring_map); 1055 if (sc->sc_cdata.stge_tx_ring_map && 1056 sc->sc_rdata.stge_tx_ring) 1057 bus_dmamem_free(sc->sc_cdata.stge_tx_ring_tag, 1058 sc->sc_rdata.stge_tx_ring, 1059 sc->sc_cdata.stge_tx_ring_map); 1060 sc->sc_rdata.stge_tx_ring = NULL; 1061 sc->sc_cdata.stge_tx_ring_map = 0; 1062 bus_dma_tag_destroy(sc->sc_cdata.stge_tx_ring_tag); 1063 sc->sc_cdata.stge_tx_ring_tag = NULL; 1064 } 1065 /* Rx ring */ 1066 if (sc->sc_cdata.stge_rx_ring_tag) { 1067 if (sc->sc_cdata.stge_rx_ring_map) 1068 bus_dmamap_unload(sc->sc_cdata.stge_rx_ring_tag, 1069 sc->sc_cdata.stge_rx_ring_map); 1070 if (sc->sc_cdata.stge_rx_ring_map && 1071 sc->sc_rdata.stge_rx_ring) 1072 bus_dmamem_free(sc->sc_cdata.stge_rx_ring_tag, 1073 sc->sc_rdata.stge_rx_ring, 1074 sc->sc_cdata.stge_rx_ring_map); 1075 sc->sc_rdata.stge_rx_ring = NULL; 1076 sc->sc_cdata.stge_rx_ring_map = 0; 1077 bus_dma_tag_destroy(sc->sc_cdata.stge_rx_ring_tag); 1078 sc->sc_cdata.stge_rx_ring_tag = NULL; 1079 } 1080 /* Tx buffers */ 1081 if (sc->sc_cdata.stge_tx_tag) { 1082 for (i = 0; i < STGE_TX_RING_CNT; i++) { 1083 txd = &sc->sc_cdata.stge_txdesc[i]; 1084 if (txd->tx_dmamap) { 1085 bus_dmamap_destroy(sc->sc_cdata.stge_tx_tag, 1086 txd->tx_dmamap); 1087 txd->tx_dmamap = 0; 1088 } 1089 } 1090 bus_dma_tag_destroy(sc->sc_cdata.stge_tx_tag); 1091 sc->sc_cdata.stge_tx_tag = NULL; 1092 } 1093 /* Rx buffers */ 1094 if (sc->sc_cdata.stge_rx_tag) { 1095 for (i = 0; i < STGE_RX_RING_CNT; i++) { 1096 rxd = &sc->sc_cdata.stge_rxdesc[i]; 1097 if (rxd->rx_dmamap) { 1098 bus_dmamap_destroy(sc->sc_cdata.stge_rx_tag, 1099 rxd->rx_dmamap); 1100 rxd->rx_dmamap = 0; 1101 } 1102 } 1103 if (sc->sc_cdata.stge_rx_sparemap) { 1104 bus_dmamap_destroy(sc->sc_cdata.stge_rx_tag, 1105 sc->sc_cdata.stge_rx_sparemap); 1106 sc->sc_cdata.stge_rx_sparemap = 0; 1107 } 1108 bus_dma_tag_destroy(sc->sc_cdata.stge_rx_tag); 1109 sc->sc_cdata.stge_rx_tag = NULL; 1110 } 1111 1112 if (sc->sc_cdata.stge_parent_tag) { 1113 bus_dma_tag_destroy(sc->sc_cdata.stge_parent_tag); 1114 sc->sc_cdata.stge_parent_tag = NULL; 1115 } 1116} 1117 1118/* 1119 * stge_shutdown: 1120 * 1121 * Make sure the interface is stopped at reboot time. 1122 */ 1123static int 1124stge_shutdown(device_t dev) 1125{ 1126 1127 return (stge_suspend(dev)); 1128} 1129 1130static void 1131stge_setwol(struct stge_softc *sc) 1132{ 1133 struct ifnet *ifp; 1134 uint8_t v; 1135 1136 STGE_LOCK_ASSERT(sc); 1137 1138 ifp = sc->sc_ifp; 1139 v = CSR_READ_1(sc, STGE_WakeEvent); 1140 /* Disable all WOL bits. */ 1141 v &= ~(WE_WakePktEnable | WE_MagicPktEnable | WE_LinkEventEnable | 1142 WE_WakeOnLanEnable); 1143 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 1144 v |= WE_MagicPktEnable | WE_WakeOnLanEnable; 1145 CSR_WRITE_1(sc, STGE_WakeEvent, v); 1146 /* Reset Tx and prevent transmission. */ 1147 CSR_WRITE_4(sc, STGE_AsicCtrl, 1148 CSR_READ_4(sc, STGE_AsicCtrl) | AC_TxReset); 1149 /* 1150 * TC9021 automatically reset link speed to 100Mbps when it's put 1151 * into sleep so there is no need to try to resetting link speed. 1152 */ 1153} 1154 1155static int 1156stge_suspend(device_t dev) 1157{ 1158 struct stge_softc *sc; 1159 1160 sc = device_get_softc(dev); 1161 1162 STGE_LOCK(sc); 1163 stge_stop(sc); 1164 sc->sc_suspended = 1; 1165 stge_setwol(sc); 1166 STGE_UNLOCK(sc); 1167 1168 return (0); 1169} 1170 1171static int 1172stge_resume(device_t dev) 1173{ 1174 struct stge_softc *sc; 1175 struct ifnet *ifp; 1176 uint8_t v; 1177 1178 sc = device_get_softc(dev); 1179 1180 STGE_LOCK(sc); 1181 /* 1182 * Clear WOL bits, so special frames wouldn't interfere 1183 * normal Rx operation anymore. 1184 */ 1185 v = CSR_READ_1(sc, STGE_WakeEvent); 1186 v &= ~(WE_WakePktEnable | WE_MagicPktEnable | WE_LinkEventEnable | 1187 WE_WakeOnLanEnable); 1188 CSR_WRITE_1(sc, STGE_WakeEvent, v); 1189 ifp = sc->sc_ifp; 1190 if (ifp->if_flags & IFF_UP) 1191 stge_init_locked(sc); 1192 1193 sc->sc_suspended = 0; 1194 STGE_UNLOCK(sc); 1195 1196 return (0); 1197} 1198 1199static void 1200stge_dma_wait(struct stge_softc *sc) 1201{ 1202 int i; 1203 1204 for (i = 0; i < STGE_TIMEOUT; i++) { 1205 DELAY(2); 1206 if ((CSR_READ_4(sc, STGE_DMACtrl) & DMAC_TxDMAInProg) == 0) 1207 break; 1208 } 1209 1210 if (i == STGE_TIMEOUT) 1211 device_printf(sc->sc_dev, "DMA wait timed out\n"); 1212} 1213 1214static int 1215stge_encap(struct stge_softc *sc, struct mbuf **m_head) 1216{ 1217 struct stge_txdesc *txd; 1218 struct stge_tfd *tfd; 1219 struct mbuf *m; 1220 bus_dma_segment_t txsegs[STGE_MAXTXSEGS]; 1221 int error, i, nsegs, si; 1222 uint64_t csum_flags, tfc; 1223 1224 STGE_LOCK_ASSERT(sc); 1225 1226 if ((txd = STAILQ_FIRST(&sc->sc_cdata.stge_txfreeq)) == NULL) 1227 return (ENOBUFS); 1228 1229 error = bus_dmamap_load_mbuf_sg(sc->sc_cdata.stge_tx_tag, 1230 txd->tx_dmamap, *m_head, txsegs, &nsegs, 0); 1231 if (error == EFBIG) { 1232 m = m_defrag(*m_head, M_DONTWAIT); 1233 if (m == NULL) { 1234 m_freem(*m_head); 1235 *m_head = NULL; 1236 return (ENOMEM); 1237 } 1238 *m_head = m; 1239 error = bus_dmamap_load_mbuf_sg(sc->sc_cdata.stge_tx_tag, 1240 txd->tx_dmamap, *m_head, txsegs, &nsegs, 0); 1241 if (error != 0) { 1242 m_freem(*m_head); 1243 *m_head = NULL; 1244 return (error); 1245 } 1246 } else if (error != 0) 1247 return (error); 1248 if (nsegs == 0) { 1249 m_freem(*m_head); 1250 *m_head = NULL; 1251 return (EIO); 1252 } 1253 1254 m = *m_head; 1255 csum_flags = 0; 1256 if ((m->m_pkthdr.csum_flags & STGE_CSUM_FEATURES) != 0) { 1257 if (m->m_pkthdr.csum_flags & CSUM_IP) 1258 csum_flags |= TFD_IPChecksumEnable; 1259 if (m->m_pkthdr.csum_flags & CSUM_TCP) 1260 csum_flags |= TFD_TCPChecksumEnable; 1261 else if (m->m_pkthdr.csum_flags & CSUM_UDP) 1262 csum_flags |= TFD_UDPChecksumEnable; 1263 } 1264 1265 si = sc->sc_cdata.stge_tx_prod; 1266 tfd = &sc->sc_rdata.stge_tx_ring[si]; 1267 for (i = 0; i < nsegs; i++) 1268 tfd->tfd_frags[i].frag_word0 = 1269 htole64(FRAG_ADDR(txsegs[i].ds_addr) | 1270 FRAG_LEN(txsegs[i].ds_len)); 1271 sc->sc_cdata.stge_tx_cnt++; 1272 1273 tfc = TFD_FrameId(si) | TFD_WordAlign(TFD_WordAlign_disable) | 1274 TFD_FragCount(nsegs) | csum_flags; 1275 if (sc->sc_cdata.stge_tx_cnt >= STGE_TX_HIWAT) 1276 tfc |= TFD_TxDMAIndicate; 1277 1278 /* Update producer index. */ 1279 sc->sc_cdata.stge_tx_prod = (si + 1) % STGE_TX_RING_CNT; 1280 1281 /* Check if we have a VLAN tag to insert. */ 1282 if (m->m_flags & M_VLANTAG) 1283 tfc |= (TFD_VLANTagInsert | TFD_VID(m->m_pkthdr.ether_vtag)); 1284 tfd->tfd_control = htole64(tfc); 1285 1286 /* Update Tx Queue. */ 1287 STAILQ_REMOVE_HEAD(&sc->sc_cdata.stge_txfreeq, tx_q); 1288 STAILQ_INSERT_TAIL(&sc->sc_cdata.stge_txbusyq, txd, tx_q); 1289 txd->tx_m = m; 1290 1291 /* Sync descriptors. */ 1292 bus_dmamap_sync(sc->sc_cdata.stge_tx_tag, txd->tx_dmamap, 1293 BUS_DMASYNC_PREWRITE); 1294 bus_dmamap_sync(sc->sc_cdata.stge_tx_ring_tag, 1295 sc->sc_cdata.stge_tx_ring_map, 1296 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1297 1298 return (0); 1299} 1300 1301/* 1302 * stge_start: [ifnet interface function] 1303 * 1304 * Start packet transmission on the interface. 1305 */ 1306static void 1307stge_start(struct ifnet *ifp) 1308{ 1309 struct stge_softc *sc; 1310 1311 sc = ifp->if_softc; 1312 STGE_LOCK(sc); 1313 stge_start_locked(ifp); 1314 STGE_UNLOCK(sc); 1315} 1316 1317static void 1318stge_start_locked(struct ifnet *ifp) 1319{ 1320 struct stge_softc *sc; 1321 struct mbuf *m_head; 1322 int enq; 1323 1324 sc = ifp->if_softc; 1325 1326 STGE_LOCK_ASSERT(sc); 1327 1328 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING|IFF_DRV_OACTIVE)) != 1329 IFF_DRV_RUNNING || sc->sc_link == 0) 1330 return; 1331 1332 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) { 1333 if (sc->sc_cdata.stge_tx_cnt >= STGE_TX_HIWAT) { 1334 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1335 break; 1336 } 1337 1338 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1339 if (m_head == NULL) 1340 break; 1341 /* 1342 * Pack the data into the transmit ring. If we 1343 * don't have room, set the OACTIVE flag and wait 1344 * for the NIC to drain the ring. 1345 */ 1346 if (stge_encap(sc, &m_head)) { 1347 if (m_head == NULL) 1348 break; 1349 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1350 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1351 break; 1352 } 1353 1354 enq++; 1355 /* 1356 * If there's a BPF listener, bounce a copy of this frame 1357 * to him. 1358 */ 1359 ETHER_BPF_MTAP(ifp, m_head); 1360 } 1361 1362 if (enq > 0) { 1363 /* Transmit */ 1364 CSR_WRITE_4(sc, STGE_DMACtrl, DMAC_TxDMAPollNow); 1365 1366 /* Set a timeout in case the chip goes out to lunch. */ 1367 sc->sc_watchdog_timer = 5; 1368 } 1369} 1370 1371/* 1372 * stge_watchdog: 1373 * 1374 * Watchdog timer handler. 1375 */ 1376static void 1377stge_watchdog(struct stge_softc *sc) 1378{ 1379 struct ifnet *ifp; 1380 1381 STGE_LOCK_ASSERT(sc); 1382 1383 if (sc->sc_watchdog_timer == 0 || --sc->sc_watchdog_timer) 1384 return; 1385 1386 ifp = sc->sc_ifp; 1387 if_printf(sc->sc_ifp, "device timeout\n"); 1388 ifp->if_oerrors++; 1389 stge_init_locked(sc); 1390 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1391 stge_start_locked(ifp); 1392} 1393 1394/* 1395 * stge_ioctl: [ifnet interface function] 1396 * 1397 * Handle control requests from the operator. 1398 */ 1399static int 1400stge_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1401{ 1402 struct stge_softc *sc; 1403 struct ifreq *ifr; 1404 struct mii_data *mii; 1405 int error, mask; 1406 1407 sc = ifp->if_softc; 1408 ifr = (struct ifreq *)data; 1409 error = 0; 1410 switch (cmd) { 1411 case SIOCSIFMTU: 1412 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > STGE_JUMBO_MTU) 1413 error = EINVAL; 1414 else if (ifp->if_mtu != ifr->ifr_mtu) { 1415 ifp->if_mtu = ifr->ifr_mtu; 1416 STGE_LOCK(sc); 1417 stge_init_locked(sc); 1418 STGE_UNLOCK(sc); 1419 } 1420 break; 1421 case SIOCSIFFLAGS: 1422 STGE_LOCK(sc); 1423 if ((ifp->if_flags & IFF_UP) != 0) { 1424 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1425 if (((ifp->if_flags ^ sc->sc_if_flags) 1426 & IFF_PROMISC) != 0) 1427 stge_set_filter(sc); 1428 } else { 1429 if (sc->sc_detach == 0) 1430 stge_init_locked(sc); 1431 } 1432 } else { 1433 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1434 stge_stop(sc); 1435 } 1436 sc->sc_if_flags = ifp->if_flags; 1437 STGE_UNLOCK(sc); 1438 break; 1439 case SIOCADDMULTI: 1440 case SIOCDELMULTI: 1441 STGE_LOCK(sc); 1442 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1443 stge_set_multi(sc); 1444 STGE_UNLOCK(sc); 1445 break; 1446 case SIOCSIFMEDIA: 1447 case SIOCGIFMEDIA: 1448 mii = device_get_softc(sc->sc_miibus); 1449 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1450 break; 1451 case SIOCSIFCAP: 1452 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1453#ifdef DEVICE_POLLING 1454 if ((mask & IFCAP_POLLING) != 0) { 1455 if ((ifr->ifr_reqcap & IFCAP_POLLING) != 0) { 1456 error = ether_poll_register(stge_poll, ifp); 1457 if (error != 0) 1458 break; 1459 STGE_LOCK(sc); 1460 CSR_WRITE_2(sc, STGE_IntEnable, 0); 1461 ifp->if_capenable |= IFCAP_POLLING; 1462 STGE_UNLOCK(sc); 1463 } else { 1464 error = ether_poll_deregister(ifp); 1465 if (error != 0) 1466 break; 1467 STGE_LOCK(sc); 1468 CSR_WRITE_2(sc, STGE_IntEnable, 1469 sc->sc_IntEnable); 1470 ifp->if_capenable &= ~IFCAP_POLLING; 1471 STGE_UNLOCK(sc); 1472 } 1473 } 1474#endif 1475 if ((mask & IFCAP_HWCSUM) != 0) { 1476 ifp->if_capenable ^= IFCAP_HWCSUM; 1477 if ((IFCAP_HWCSUM & ifp->if_capenable) != 0 && 1478 (IFCAP_HWCSUM & ifp->if_capabilities) != 0) 1479 ifp->if_hwassist = STGE_CSUM_FEATURES; 1480 else 1481 ifp->if_hwassist = 0; 1482 } 1483 if ((mask & IFCAP_WOL) != 0 && 1484 (ifp->if_capabilities & IFCAP_WOL) != 0) { 1485 if ((mask & IFCAP_WOL_MAGIC) != 0) 1486 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 1487 } 1488 if ((mask & IFCAP_VLAN_HWTAGGING) != 0) { 1489 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1490 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1491 STGE_LOCK(sc); 1492 stge_vlan_setup(sc); 1493 STGE_UNLOCK(sc); 1494 } 1495 } 1496 VLAN_CAPABILITIES(ifp); 1497 break; 1498 default: 1499 error = ether_ioctl(ifp, cmd, data); 1500 break; 1501 } 1502 1503 return (error); 1504} 1505 1506static void 1507stge_link_task(void *arg, int pending) 1508{ 1509 struct stge_softc *sc; 1510 struct mii_data *mii; 1511 uint32_t v, ac; 1512 int i; 1513 1514 sc = (struct stge_softc *)arg; 1515 STGE_LOCK(sc); 1516 1517 mii = device_get_softc(sc->sc_miibus); 1518 if (mii->mii_media_status & IFM_ACTIVE) { 1519 if (IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1520 sc->sc_link = 1; 1521 } else 1522 sc->sc_link = 0; 1523 1524 sc->sc_MACCtrl = 0; 1525 if (((mii->mii_media_active & IFM_GMASK) & IFM_FDX) != 0) 1526 sc->sc_MACCtrl |= MC_DuplexSelect; 1527 if (((mii->mii_media_active & IFM_GMASK) & IFM_FLAG0) != 0) 1528 sc->sc_MACCtrl |= MC_RxFlowControlEnable; 1529 if (((mii->mii_media_active & IFM_GMASK) & IFM_FLAG1) != 0) 1530 sc->sc_MACCtrl |= MC_TxFlowControlEnable; 1531 /* 1532 * Update STGE_MACCtrl register depending on link status. 1533 * (duplex, flow control etc) 1534 */ 1535 v = ac = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 1536 v &= ~(MC_DuplexSelect|MC_RxFlowControlEnable|MC_TxFlowControlEnable); 1537 v |= sc->sc_MACCtrl; 1538 CSR_WRITE_4(sc, STGE_MACCtrl, v); 1539 if (((ac ^ sc->sc_MACCtrl) & MC_DuplexSelect) != 0) { 1540 /* Duplex setting changed, reset Tx/Rx functions. */ 1541 ac = CSR_READ_4(sc, STGE_AsicCtrl); 1542 ac |= AC_TxReset | AC_RxReset; 1543 CSR_WRITE_4(sc, STGE_AsicCtrl, ac); 1544 for (i = 0; i < STGE_TIMEOUT; i++) { 1545 DELAY(100); 1546 if ((CSR_READ_4(sc, STGE_AsicCtrl) & AC_ResetBusy) == 0) 1547 break; 1548 } 1549 if (i == STGE_TIMEOUT) 1550 device_printf(sc->sc_dev, "reset failed to complete\n"); 1551 } 1552 STGE_UNLOCK(sc); 1553} 1554 1555static __inline int 1556stge_tx_error(struct stge_softc *sc) 1557{ 1558 uint32_t txstat; 1559 int error; 1560 1561 for (error = 0;;) { 1562 txstat = CSR_READ_4(sc, STGE_TxStatus); 1563 if ((txstat & TS_TxComplete) == 0) 1564 break; 1565 /* Tx underrun */ 1566 if ((txstat & TS_TxUnderrun) != 0) { 1567 /* 1568 * XXX 1569 * There should be a more better way to recover 1570 * from Tx underrun instead of a full reset. 1571 */ 1572 if (sc->sc_nerr++ < STGE_MAXERR) 1573 device_printf(sc->sc_dev, "Tx underrun, " 1574 "resetting...\n"); 1575 if (sc->sc_nerr == STGE_MAXERR) 1576 device_printf(sc->sc_dev, "too many errors; " 1577 "not reporting any more\n"); 1578 error = -1; 1579 break; 1580 } 1581 /* Maximum/Late collisions, Re-enable Tx MAC. */ 1582 if ((txstat & (TS_MaxCollisions|TS_LateCollision)) != 0) 1583 CSR_WRITE_4(sc, STGE_MACCtrl, 1584 (CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK) | 1585 MC_TxEnable); 1586 } 1587 1588 return (error); 1589} 1590 1591/* 1592 * stge_intr: 1593 * 1594 * Interrupt service routine. 1595 */ 1596static void 1597stge_intr(void *arg) 1598{ 1599 struct stge_softc *sc; 1600 struct ifnet *ifp; 1601 int reinit; 1602 uint16_t status; 1603 1604 sc = (struct stge_softc *)arg; 1605 ifp = sc->sc_ifp; 1606 1607 STGE_LOCK(sc); 1608 1609#ifdef DEVICE_POLLING 1610 if ((ifp->if_capenable & IFCAP_POLLING) != 0) 1611 goto done_locked; 1612#endif 1613 status = CSR_READ_2(sc, STGE_IntStatus); 1614 if (sc->sc_suspended || (status & IS_InterruptStatus) == 0) 1615 goto done_locked; 1616 1617 /* Disable interrupts. */ 1618 for (reinit = 0;;) { 1619 status = CSR_READ_2(sc, STGE_IntStatusAck); 1620 status &= sc->sc_IntEnable; 1621 if (status == 0) 1622 break; 1623 /* Host interface errors. */ 1624 if ((status & IS_HostError) != 0) { 1625 device_printf(sc->sc_dev, 1626 "Host interface error, resetting...\n"); 1627 reinit = 1; 1628 goto force_init; 1629 } 1630 1631 /* Receive interrupts. */ 1632 if ((status & IS_RxDMAComplete) != 0) { 1633 stge_rxeof(sc); 1634 if ((status & IS_RFDListEnd) != 0) 1635 CSR_WRITE_4(sc, STGE_DMACtrl, 1636 DMAC_RxDMAPollNow); 1637 } 1638 1639 /* Transmit interrupts. */ 1640 if ((status & (IS_TxDMAComplete | IS_TxComplete)) != 0) 1641 stge_txeof(sc); 1642 1643 /* Transmission errors.*/ 1644 if ((status & IS_TxComplete) != 0) { 1645 if ((reinit = stge_tx_error(sc)) != 0) 1646 break; 1647 } 1648 } 1649 1650force_init: 1651 if (reinit != 0) 1652 stge_init_locked(sc); 1653 1654 /* Re-enable interrupts. */ 1655 CSR_WRITE_2(sc, STGE_IntEnable, sc->sc_IntEnable); 1656 1657 /* Try to get more packets going. */ 1658 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1659 stge_start_locked(ifp); 1660 1661done_locked: 1662 STGE_UNLOCK(sc); 1663} 1664 1665/* 1666 * stge_txeof: 1667 * 1668 * Helper; handle transmit interrupts. 1669 */ 1670static void 1671stge_txeof(struct stge_softc *sc) 1672{ 1673 struct ifnet *ifp; 1674 struct stge_txdesc *txd; 1675 uint64_t control; 1676 int cons; 1677 1678 STGE_LOCK_ASSERT(sc); 1679 1680 ifp = sc->sc_ifp; 1681 1682 txd = STAILQ_FIRST(&sc->sc_cdata.stge_txbusyq); 1683 if (txd == NULL) 1684 return; 1685 bus_dmamap_sync(sc->sc_cdata.stge_tx_ring_tag, 1686 sc->sc_cdata.stge_tx_ring_map, BUS_DMASYNC_POSTREAD); 1687 1688 /* 1689 * Go through our Tx list and free mbufs for those 1690 * frames which have been transmitted. 1691 */ 1692 for (cons = sc->sc_cdata.stge_tx_cons;; 1693 cons = (cons + 1) % STGE_TX_RING_CNT) { 1694 if (sc->sc_cdata.stge_tx_cnt <= 0) 1695 break; 1696 control = le64toh(sc->sc_rdata.stge_tx_ring[cons].tfd_control); 1697 if ((control & TFD_TFDDone) == 0) 1698 break; 1699 sc->sc_cdata.stge_tx_cnt--; 1700 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1701 1702 bus_dmamap_sync(sc->sc_cdata.stge_tx_tag, txd->tx_dmamap, 1703 BUS_DMASYNC_POSTWRITE); 1704 bus_dmamap_unload(sc->sc_cdata.stge_tx_tag, txd->tx_dmamap); 1705 1706 /* Output counter is updated with statistics register */ 1707 m_freem(txd->tx_m); 1708 txd->tx_m = NULL; 1709 STAILQ_REMOVE_HEAD(&sc->sc_cdata.stge_txbusyq, tx_q); 1710 STAILQ_INSERT_TAIL(&sc->sc_cdata.stge_txfreeq, txd, tx_q); 1711 txd = STAILQ_FIRST(&sc->sc_cdata.stge_txbusyq); 1712 } 1713 sc->sc_cdata.stge_tx_cons = cons; 1714 if (sc->sc_cdata.stge_tx_cnt == 0) 1715 sc->sc_watchdog_timer = 0; 1716 1717 bus_dmamap_sync(sc->sc_cdata.stge_tx_ring_tag, 1718 sc->sc_cdata.stge_tx_ring_map, 1719 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1720} 1721 1722static __inline void 1723stge_discard_rxbuf(struct stge_softc *sc, int idx) 1724{ 1725 struct stge_rfd *rfd; 1726 1727 rfd = &sc->sc_rdata.stge_rx_ring[idx]; 1728 rfd->rfd_status = 0; 1729} 1730 1731#ifndef __NO_STRICT_ALIGNMENT 1732/* 1733 * It seems that TC9021's DMA engine has alignment restrictions in 1734 * DMA scatter operations. The first DMA segment has no address 1735 * alignment restrictins but the rest should be aligned on 4(?) bytes 1736 * boundary. Otherwise it would corrupt random memory. Since we don't 1737 * know which one is used for the first segment in advance we simply 1738 * don't align at all. 1739 * To avoid copying over an entire frame to align, we allocate a new 1740 * mbuf and copy ethernet header to the new mbuf. The new mbuf is 1741 * prepended into the existing mbuf chain. 1742 */ 1743static __inline struct mbuf * 1744stge_fixup_rx(struct stge_softc *sc, struct mbuf *m) 1745{ 1746 struct mbuf *n; 1747 1748 n = NULL; 1749 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 1750 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 1751 m->m_data += ETHER_HDR_LEN; 1752 n = m; 1753 } else { 1754 MGETHDR(n, M_DONTWAIT, MT_DATA); 1755 if (n != NULL) { 1756 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 1757 m->m_data += ETHER_HDR_LEN; 1758 m->m_len -= ETHER_HDR_LEN; 1759 n->m_len = ETHER_HDR_LEN; 1760 M_MOVE_PKTHDR(n, m); 1761 n->m_next = m; 1762 } else 1763 m_freem(m); 1764 } 1765 1766 return (n); 1767} 1768#endif 1769 1770/* 1771 * stge_rxeof: 1772 * 1773 * Helper; handle receive interrupts. 1774 */ 1775static void 1776stge_rxeof(struct stge_softc *sc) 1777{ 1778 struct ifnet *ifp; 1779 struct stge_rxdesc *rxd; 1780 struct mbuf *mp, *m; 1781 uint64_t status64; 1782 uint32_t status; 1783 int cons, prog; 1784 1785 STGE_LOCK_ASSERT(sc); 1786 1787 ifp = sc->sc_ifp; 1788 1789 bus_dmamap_sync(sc->sc_cdata.stge_rx_ring_tag, 1790 sc->sc_cdata.stge_rx_ring_map, BUS_DMASYNC_POSTREAD); 1791 1792 prog = 0; 1793 for (cons = sc->sc_cdata.stge_rx_cons; prog < STGE_RX_RING_CNT; 1794 prog++, cons = (cons + 1) % STGE_RX_RING_CNT) { 1795 status64 = le64toh(sc->sc_rdata.stge_rx_ring[cons].rfd_status); 1796 status = RFD_RxStatus(status64); 1797 if ((status & RFD_RFDDone) == 0) 1798 break; 1799#ifdef DEVICE_POLLING 1800 if (ifp->if_capenable & IFCAP_POLLING) { 1801 if (sc->sc_cdata.stge_rxcycles <= 0) 1802 break; 1803 sc->sc_cdata.stge_rxcycles--; 1804 } 1805#endif 1806 prog++; 1807 rxd = &sc->sc_cdata.stge_rxdesc[cons]; 1808 mp = rxd->rx_m; 1809 1810 /* 1811 * If the packet had an error, drop it. Note we count 1812 * the error later in the periodic stats update. 1813 */ 1814 if ((status & RFD_FrameEnd) != 0 && (status & 1815 (RFD_RxFIFOOverrun | RFD_RxRuntFrame | 1816 RFD_RxAlignmentError | RFD_RxFCSError | 1817 RFD_RxLengthError)) != 0) { 1818 stge_discard_rxbuf(sc, cons); 1819 if (sc->sc_cdata.stge_rxhead != NULL) { 1820 m_freem(sc->sc_cdata.stge_rxhead); 1821 STGE_RXCHAIN_RESET(sc); 1822 } 1823 continue; 1824 } 1825 /* 1826 * Add a new receive buffer to the ring. 1827 */ 1828 if (stge_newbuf(sc, cons) != 0) { 1829 ifp->if_iqdrops++; 1830 stge_discard_rxbuf(sc, cons); 1831 if (sc->sc_cdata.stge_rxhead != NULL) { 1832 m_freem(sc->sc_cdata.stge_rxhead); 1833 STGE_RXCHAIN_RESET(sc); 1834 } 1835 continue; 1836 } 1837 1838 if ((status & RFD_FrameEnd) != 0) 1839 mp->m_len = RFD_RxDMAFrameLen(status) - 1840 sc->sc_cdata.stge_rxlen; 1841 sc->sc_cdata.stge_rxlen += mp->m_len; 1842 1843 /* Chain mbufs. */ 1844 if (sc->sc_cdata.stge_rxhead == NULL) { 1845 sc->sc_cdata.stge_rxhead = mp; 1846 sc->sc_cdata.stge_rxtail = mp; 1847 } else { 1848 mp->m_flags &= ~M_PKTHDR; 1849 sc->sc_cdata.stge_rxtail->m_next = mp; 1850 sc->sc_cdata.stge_rxtail = mp; 1851 } 1852 1853 if ((status & RFD_FrameEnd) != 0) { 1854 m = sc->sc_cdata.stge_rxhead; 1855 m->m_pkthdr.rcvif = ifp; 1856 m->m_pkthdr.len = sc->sc_cdata.stge_rxlen; 1857 1858 if (m->m_pkthdr.len > sc->sc_if_framesize) { 1859 m_freem(m); 1860 STGE_RXCHAIN_RESET(sc); 1861 continue; 1862 } 1863 /* 1864 * Set the incoming checksum information for 1865 * the packet. 1866 */ 1867 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) { 1868 if ((status & RFD_IPDetected) != 0) { 1869 m->m_pkthdr.csum_flags |= 1870 CSUM_IP_CHECKED; 1871 if ((status & RFD_IPError) == 0) 1872 m->m_pkthdr.csum_flags |= 1873 CSUM_IP_VALID; 1874 } 1875 if (((status & RFD_TCPDetected) != 0 && 1876 (status & RFD_TCPError) == 0) || 1877 ((status & RFD_UDPDetected) != 0 && 1878 (status & RFD_UDPError) == 0)) { 1879 m->m_pkthdr.csum_flags |= 1880 (CSUM_DATA_VALID | CSUM_PSEUDO_HDR); 1881 m->m_pkthdr.csum_data = 0xffff; 1882 } 1883 } 1884 1885#ifndef __NO_STRICT_ALIGNMENT 1886 if (sc->sc_if_framesize > (MCLBYTES - ETHER_ALIGN)) { 1887 if ((m = stge_fixup_rx(sc, m)) == NULL) { 1888 STGE_RXCHAIN_RESET(sc); 1889 continue; 1890 } 1891 } 1892#endif 1893 /* Check for VLAN tagged packets. */ 1894 if ((status & RFD_VLANDetected) != 0 && 1895 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) { 1896 m->m_pkthdr.ether_vtag = RFD_TCI(status64); 1897 m->m_flags |= M_VLANTAG; 1898 } 1899 1900 STGE_UNLOCK(sc); 1901 /* Pass it on. */ 1902 (*ifp->if_input)(ifp, m); 1903 STGE_LOCK(sc); 1904 1905 STGE_RXCHAIN_RESET(sc); 1906 } 1907 } 1908 1909 if (prog > 0) { 1910 /* Update the consumer index. */ 1911 sc->sc_cdata.stge_rx_cons = cons; 1912 bus_dmamap_sync(sc->sc_cdata.stge_rx_ring_tag, 1913 sc->sc_cdata.stge_rx_ring_map, 1914 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1915 } 1916} 1917 1918#ifdef DEVICE_POLLING 1919static void 1920stge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1921{ 1922 struct stge_softc *sc; 1923 uint16_t status; 1924 1925 sc = ifp->if_softc; 1926 STGE_LOCK(sc); 1927 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1928 STGE_UNLOCK(sc); 1929 return; 1930 } 1931 1932 sc->sc_cdata.stge_rxcycles = count; 1933 stge_rxeof(sc); 1934 stge_txeof(sc); 1935 1936 if (cmd == POLL_AND_CHECK_STATUS) { 1937 status = CSR_READ_2(sc, STGE_IntStatus); 1938 status &= sc->sc_IntEnable; 1939 if (status != 0) { 1940 if ((status & IS_HostError) != 0) { 1941 device_printf(sc->sc_dev, 1942 "Host interface error, resetting...\n"); 1943 stge_init_locked(sc); 1944 } 1945 if ((status & IS_TxComplete) != 0) { 1946 if (stge_tx_error(sc) != 0) 1947 stge_init_locked(sc); 1948 } 1949 } 1950 1951 } 1952 1953 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1954 stge_start_locked(ifp); 1955 1956 STGE_UNLOCK(sc); 1957} 1958#endif /* DEVICE_POLLING */ 1959 1960/* 1961 * stge_tick: 1962 * 1963 * One second timer, used to tick the MII. 1964 */ 1965static void 1966stge_tick(void *arg) 1967{ 1968 struct stge_softc *sc; 1969 struct mii_data *mii; 1970 1971 sc = (struct stge_softc *)arg; 1972 1973 STGE_LOCK_ASSERT(sc); 1974 1975 mii = device_get_softc(sc->sc_miibus); 1976 mii_tick(mii); 1977 1978 /* Update statistics counters. */ 1979 stge_stats_update(sc); 1980 1981 /* 1982 * Relcaim any pending Tx descriptors to release mbufs in a 1983 * timely manner as we don't generate Tx completion interrupts 1984 * for every frame. This limits the delay to a maximum of one 1985 * second. 1986 */ 1987 if (sc->sc_cdata.stge_tx_cnt != 0) 1988 stge_txeof(sc); 1989 1990 stge_watchdog(sc); 1991 1992 callout_reset(&sc->sc_tick_ch, hz, stge_tick, sc); 1993} 1994 1995/* 1996 * stge_stats_update: 1997 * 1998 * Read the TC9021 statistics counters. 1999 */ 2000static void 2001stge_stats_update(struct stge_softc *sc) 2002{ 2003 struct ifnet *ifp; 2004 2005 STGE_LOCK_ASSERT(sc); 2006 2007 ifp = sc->sc_ifp; 2008 2009 CSR_READ_4(sc,STGE_OctetRcvOk); 2010 2011 ifp->if_ipackets += CSR_READ_4(sc, STGE_FramesRcvdOk); 2012 2013 ifp->if_ierrors += CSR_READ_2(sc, STGE_FramesLostRxErrors); 2014 2015 CSR_READ_4(sc, STGE_OctetXmtdOk); 2016 2017 ifp->if_opackets += CSR_READ_4(sc, STGE_FramesXmtdOk); 2018 2019 ifp->if_collisions += 2020 CSR_READ_4(sc, STGE_LateCollisions) + 2021 CSR_READ_4(sc, STGE_MultiColFrames) + 2022 CSR_READ_4(sc, STGE_SingleColFrames); 2023 2024 ifp->if_oerrors += 2025 CSR_READ_2(sc, STGE_FramesAbortXSColls) + 2026 CSR_READ_2(sc, STGE_FramesWEXDeferal); 2027} 2028 2029/* 2030 * stge_reset: 2031 * 2032 * Perform a soft reset on the TC9021. 2033 */ 2034static void 2035stge_reset(struct stge_softc *sc, uint32_t how) 2036{ 2037 uint32_t ac; 2038 uint8_t v; 2039 int i, dv; 2040 2041 STGE_LOCK_ASSERT(sc); 2042 2043 dv = 5000; 2044 ac = CSR_READ_4(sc, STGE_AsicCtrl); 2045 switch (how) { 2046 case STGE_RESET_TX: 2047 ac |= AC_TxReset | AC_FIFO; 2048 dv = 100; 2049 break; 2050 case STGE_RESET_RX: 2051 ac |= AC_RxReset | AC_FIFO; 2052 dv = 100; 2053 break; 2054 case STGE_RESET_FULL: 2055 default: 2056 /* 2057 * Only assert RstOut if we're fiber. We need GMII clocks 2058 * to be present in order for the reset to complete on fiber 2059 * cards. 2060 */ 2061 ac |= AC_GlobalReset | AC_RxReset | AC_TxReset | 2062 AC_DMA | AC_FIFO | AC_Network | AC_Host | AC_AutoInit | 2063 (sc->sc_usefiber ? AC_RstOut : 0); 2064 break; 2065 } 2066 2067 CSR_WRITE_4(sc, STGE_AsicCtrl, ac); 2068 2069 /* Account for reset problem at 10Mbps. */ 2070 DELAY(dv); 2071 2072 for (i = 0; i < STGE_TIMEOUT; i++) { 2073 if ((CSR_READ_4(sc, STGE_AsicCtrl) & AC_ResetBusy) == 0) 2074 break; 2075 DELAY(dv); 2076 } 2077 2078 if (i == STGE_TIMEOUT) 2079 device_printf(sc->sc_dev, "reset failed to complete\n"); 2080 2081 /* Set LED, from Linux IPG driver. */ 2082 ac = CSR_READ_4(sc, STGE_AsicCtrl); 2083 ac &= ~(AC_LEDMode | AC_LEDSpeed | AC_LEDModeBit1); 2084 if ((sc->sc_led & 0x01) != 0) 2085 ac |= AC_LEDMode; 2086 if ((sc->sc_led & 0x03) != 0) 2087 ac |= AC_LEDModeBit1; 2088 if ((sc->sc_led & 0x08) != 0) 2089 ac |= AC_LEDSpeed; 2090 CSR_WRITE_4(sc, STGE_AsicCtrl, ac); 2091 2092 /* Set PHY, from Linux IPG driver */ 2093 v = CSR_READ_1(sc, STGE_PhySet); 2094 v &= ~(PS_MemLenb9b | PS_MemLen | PS_NonCompdet); 2095 v |= ((sc->sc_led & 0x70) >> 4); 2096 CSR_WRITE_1(sc, STGE_PhySet, v); 2097} 2098 2099/* 2100 * stge_init: [ ifnet interface function ] 2101 * 2102 * Initialize the interface. 2103 */ 2104static void 2105stge_init(void *xsc) 2106{ 2107 struct stge_softc *sc; 2108 2109 sc = (struct stge_softc *)xsc; 2110 STGE_LOCK(sc); 2111 stge_init_locked(sc); 2112 STGE_UNLOCK(sc); 2113} 2114 2115static void 2116stge_init_locked(struct stge_softc *sc) 2117{ 2118 struct ifnet *ifp; 2119 struct mii_data *mii; 2120 uint16_t eaddr[3]; 2121 uint32_t v; 2122 int error; 2123 2124 STGE_LOCK_ASSERT(sc); 2125 2126 ifp = sc->sc_ifp; 2127 mii = device_get_softc(sc->sc_miibus); 2128 2129 /* 2130 * Cancel any pending I/O. 2131 */ 2132 stge_stop(sc); 2133 2134 /* 2135 * Reset the chip to a known state. 2136 */ 2137 stge_reset(sc, STGE_RESET_FULL); 2138 2139 /* Init descriptors. */ 2140 error = stge_init_rx_ring(sc); 2141 if (error != 0) { 2142 device_printf(sc->sc_dev, 2143 "initialization failed: no memory for rx buffers\n"); 2144 stge_stop(sc); 2145 goto out; 2146 } 2147 stge_init_tx_ring(sc); 2148 2149 /* Set the station address. */ 2150 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 2151 CSR_WRITE_2(sc, STGE_StationAddress0, htole16(eaddr[0])); 2152 CSR_WRITE_2(sc, STGE_StationAddress1, htole16(eaddr[1])); 2153 CSR_WRITE_2(sc, STGE_StationAddress2, htole16(eaddr[2])); 2154 2155 /* 2156 * Set the statistics masks. Disable all the RMON stats, 2157 * and disable selected stats in the non-RMON stats registers. 2158 */ 2159 CSR_WRITE_4(sc, STGE_RMONStatisticsMask, 0xffffffff); 2160 CSR_WRITE_4(sc, STGE_StatisticsMask, 2161 (1U << 1) | (1U << 2) | (1U << 3) | (1U << 4) | (1U << 5) | 2162 (1U << 6) | (1U << 7) | (1U << 8) | (1U << 9) | (1U << 10) | 2163 (1U << 13) | (1U << 14) | (1U << 15) | (1U << 19) | (1U << 20) | 2164 (1U << 21)); 2165 2166 /* Set up the receive filter. */ 2167 stge_set_filter(sc); 2168 /* Program multicast filter. */ 2169 stge_set_multi(sc); 2170 2171 /* 2172 * Give the transmit and receive ring to the chip. 2173 */ 2174 CSR_WRITE_4(sc, STGE_TFDListPtrHi, 2175 STGE_ADDR_HI(STGE_TX_RING_ADDR(sc, 0))); 2176 CSR_WRITE_4(sc, STGE_TFDListPtrLo, 2177 STGE_ADDR_LO(STGE_TX_RING_ADDR(sc, 0))); 2178 2179 CSR_WRITE_4(sc, STGE_RFDListPtrHi, 2180 STGE_ADDR_HI(STGE_RX_RING_ADDR(sc, 0))); 2181 CSR_WRITE_4(sc, STGE_RFDListPtrLo, 2182 STGE_ADDR_LO(STGE_RX_RING_ADDR(sc, 0))); 2183 2184 /* 2185 * Initialize the Tx auto-poll period. It's OK to make this number 2186 * large (255 is the max, but we use 127) -- we explicitly kick the 2187 * transmit engine when there's actually a packet. 2188 */ 2189 CSR_WRITE_1(sc, STGE_TxDMAPollPeriod, 127); 2190 2191 /* ..and the Rx auto-poll period. */ 2192 CSR_WRITE_1(sc, STGE_RxDMAPollPeriod, 1); 2193 2194 /* Initialize the Tx start threshold. */ 2195 CSR_WRITE_2(sc, STGE_TxStartThresh, sc->sc_txthresh); 2196 2197 /* Rx DMA thresholds, from Linux */ 2198 CSR_WRITE_1(sc, STGE_RxDMABurstThresh, 0x30); 2199 CSR_WRITE_1(sc, STGE_RxDMAUrgentThresh, 0x30); 2200 2201 /* Rx early threhold, from Linux */ 2202 CSR_WRITE_2(sc, STGE_RxEarlyThresh, 0x7ff); 2203 2204 /* Tx DMA thresholds, from Linux */ 2205 CSR_WRITE_1(sc, STGE_TxDMABurstThresh, 0x30); 2206 CSR_WRITE_1(sc, STGE_TxDMAUrgentThresh, 0x04); 2207 2208 /* 2209 * Initialize the Rx DMA interrupt control register. We 2210 * request an interrupt after every incoming packet, but 2211 * defer it for sc_rxint_dmawait us. When the number of 2212 * interrupts pending reaches STGE_RXINT_NFRAME, we stop 2213 * deferring the interrupt, and signal it immediately. 2214 */ 2215 CSR_WRITE_4(sc, STGE_RxDMAIntCtrl, 2216 RDIC_RxFrameCount(sc->sc_rxint_nframe) | 2217 RDIC_RxDMAWaitTime(STGE_RXINT_USECS2TICK(sc->sc_rxint_dmawait))); 2218 2219 /* 2220 * Initialize the interrupt mask. 2221 */ 2222 sc->sc_IntEnable = IS_HostError | IS_TxComplete | 2223 IS_TxDMAComplete | IS_RxDMAComplete | IS_RFDListEnd; 2224#ifdef DEVICE_POLLING 2225 /* Disable interrupts if we are polling. */ 2226 if ((ifp->if_capenable & IFCAP_POLLING) != 0) 2227 CSR_WRITE_2(sc, STGE_IntEnable, 0); 2228 else 2229#endif 2230 CSR_WRITE_2(sc, STGE_IntEnable, sc->sc_IntEnable); 2231 2232 /* 2233 * Configure the DMA engine. 2234 * XXX Should auto-tune TxBurstLimit. 2235 */ 2236 CSR_WRITE_4(sc, STGE_DMACtrl, sc->sc_DMACtrl | DMAC_TxBurstLimit(3)); 2237 2238 /* 2239 * Send a PAUSE frame when we reach 29,696 bytes in the Rx 2240 * FIFO, and send an un-PAUSE frame when we reach 3056 bytes 2241 * in the Rx FIFO. 2242 */ 2243 CSR_WRITE_2(sc, STGE_FlowOnTresh, 29696 / 16); 2244 CSR_WRITE_2(sc, STGE_FlowOffThresh, 3056 / 16); 2245 2246 /* 2247 * Set the maximum frame size. 2248 */ 2249 sc->sc_if_framesize = ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 2250 CSR_WRITE_2(sc, STGE_MaxFrameSize, sc->sc_if_framesize); 2251 2252 /* 2253 * Initialize MacCtrl -- do it before setting the media, 2254 * as setting the media will actually program the register. 2255 * 2256 * Note: We have to poke the IFS value before poking 2257 * anything else. 2258 */ 2259 /* Tx/Rx MAC should be disabled before programming IFS.*/ 2260 CSR_WRITE_4(sc, STGE_MACCtrl, MC_IFSSelect(MC_IFS96bit)); 2261 2262 stge_vlan_setup(sc); 2263 2264 if (sc->sc_rev >= 6) { /* >= B.2 */ 2265 /* Multi-frag frame bug work-around. */ 2266 CSR_WRITE_2(sc, STGE_DebugCtrl, 2267 CSR_READ_2(sc, STGE_DebugCtrl) | 0x0200); 2268 2269 /* Tx Poll Now bug work-around. */ 2270 CSR_WRITE_2(sc, STGE_DebugCtrl, 2271 CSR_READ_2(sc, STGE_DebugCtrl) | 0x0010); 2272 /* Tx Poll Now bug work-around. */ 2273 CSR_WRITE_2(sc, STGE_DebugCtrl, 2274 CSR_READ_2(sc, STGE_DebugCtrl) | 0x0020); 2275 } 2276 2277 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 2278 v |= MC_StatisticsEnable | MC_TxEnable | MC_RxEnable; 2279 CSR_WRITE_4(sc, STGE_MACCtrl, v); 2280 /* 2281 * It seems that transmitting frames without checking the state of 2282 * Rx/Tx MAC wedge the hardware. 2283 */ 2284 stge_start_tx(sc); 2285 stge_start_rx(sc); 2286 2287 sc->sc_link = 0; 2288 /* 2289 * Set the current media. 2290 */ 2291 mii_mediachg(mii); 2292 2293 /* 2294 * Start the one second MII clock. 2295 */ 2296 callout_reset(&sc->sc_tick_ch, hz, stge_tick, sc); 2297 2298 /* 2299 * ...all done! 2300 */ 2301 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2302 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2303 2304 out: 2305 if (error != 0) 2306 device_printf(sc->sc_dev, "interface not running\n"); 2307} 2308 2309static void 2310stge_vlan_setup(struct stge_softc *sc) 2311{ 2312 struct ifnet *ifp; 2313 uint32_t v; 2314 2315 ifp = sc->sc_ifp; 2316 /* 2317 * The NIC always copy a VLAN tag regardless of STGE_MACCtrl 2318 * MC_AutoVLANuntagging bit. 2319 * MC_AutoVLANtagging bit selects which VLAN source to use 2320 * between STGE_VLANTag and TFC. However TFC TFD_VLANTagInsert 2321 * bit has priority over MC_AutoVLANtagging bit. So we always 2322 * use TFC instead of STGE_VLANTag register. 2323 */ 2324 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 2325 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 2326 v |= MC_AutoVLANuntagging; 2327 else 2328 v &= ~MC_AutoVLANuntagging; 2329 CSR_WRITE_4(sc, STGE_MACCtrl, v); 2330} 2331 2332/* 2333 * Stop transmission on the interface. 2334 */ 2335static void 2336stge_stop(struct stge_softc *sc) 2337{ 2338 struct ifnet *ifp; 2339 struct stge_txdesc *txd; 2340 struct stge_rxdesc *rxd; 2341 uint32_t v; 2342 int i; 2343 2344 STGE_LOCK_ASSERT(sc); 2345 /* 2346 * Stop the one second clock. 2347 */ 2348 callout_stop(&sc->sc_tick_ch); 2349 sc->sc_watchdog_timer = 0; 2350 2351 /* 2352 * Disable interrupts. 2353 */ 2354 CSR_WRITE_2(sc, STGE_IntEnable, 0); 2355 2356 /* 2357 * Stop receiver, transmitter, and stats update. 2358 */ 2359 stge_stop_rx(sc); 2360 stge_stop_tx(sc); 2361 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 2362 v |= MC_StatisticsDisable; 2363 CSR_WRITE_4(sc, STGE_MACCtrl, v); 2364 2365 /* 2366 * Stop the transmit and receive DMA. 2367 */ 2368 stge_dma_wait(sc); 2369 CSR_WRITE_4(sc, STGE_TFDListPtrHi, 0); 2370 CSR_WRITE_4(sc, STGE_TFDListPtrLo, 0); 2371 CSR_WRITE_4(sc, STGE_RFDListPtrHi, 0); 2372 CSR_WRITE_4(sc, STGE_RFDListPtrLo, 0); 2373 2374 /* 2375 * Free RX and TX mbufs still in the queues. 2376 */ 2377 for (i = 0; i < STGE_RX_RING_CNT; i++) { 2378 rxd = &sc->sc_cdata.stge_rxdesc[i]; 2379 if (rxd->rx_m != NULL) { 2380 bus_dmamap_sync(sc->sc_cdata.stge_rx_tag, 2381 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 2382 bus_dmamap_unload(sc->sc_cdata.stge_rx_tag, 2383 rxd->rx_dmamap); 2384 m_freem(rxd->rx_m); 2385 rxd->rx_m = NULL; 2386 } 2387 } 2388 for (i = 0; i < STGE_TX_RING_CNT; i++) { 2389 txd = &sc->sc_cdata.stge_txdesc[i]; 2390 if (txd->tx_m != NULL) { 2391 bus_dmamap_sync(sc->sc_cdata.stge_tx_tag, 2392 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2393 bus_dmamap_unload(sc->sc_cdata.stge_tx_tag, 2394 txd->tx_dmamap); 2395 m_freem(txd->tx_m); 2396 txd->tx_m = NULL; 2397 } 2398 } 2399 2400 /* 2401 * Mark the interface down and cancel the watchdog timer. 2402 */ 2403 ifp = sc->sc_ifp; 2404 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2405 sc->sc_link = 0; 2406} 2407 2408static void 2409stge_start_tx(struct stge_softc *sc) 2410{ 2411 uint32_t v; 2412 int i; 2413 2414 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 2415 if ((v & MC_TxEnabled) != 0) 2416 return; 2417 v |= MC_TxEnable; 2418 CSR_WRITE_4(sc, STGE_MACCtrl, v); 2419 CSR_WRITE_1(sc, STGE_TxDMAPollPeriod, 127); 2420 for (i = STGE_TIMEOUT; i > 0; i--) { 2421 DELAY(10); 2422 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 2423 if ((v & MC_TxEnabled) != 0) 2424 break; 2425 } 2426 if (i == 0) 2427 device_printf(sc->sc_dev, "Starting Tx MAC timed out\n"); 2428} 2429 2430static void 2431stge_start_rx(struct stge_softc *sc) 2432{ 2433 uint32_t v; 2434 int i; 2435 2436 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 2437 if ((v & MC_RxEnabled) != 0) 2438 return; 2439 v |= MC_RxEnable; 2440 CSR_WRITE_4(sc, STGE_MACCtrl, v); 2441 CSR_WRITE_1(sc, STGE_RxDMAPollPeriod, 1); 2442 for (i = STGE_TIMEOUT; i > 0; i--) { 2443 DELAY(10); 2444 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 2445 if ((v & MC_RxEnabled) != 0) 2446 break; 2447 } 2448 if (i == 0) 2449 device_printf(sc->sc_dev, "Starting Rx MAC timed out\n"); 2450} 2451 2452static void 2453stge_stop_tx(struct stge_softc *sc) 2454{ 2455 uint32_t v; 2456 int i; 2457 2458 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 2459 if ((v & MC_TxEnabled) == 0) 2460 return; 2461 v |= MC_TxDisable; 2462 CSR_WRITE_4(sc, STGE_MACCtrl, v); 2463 for (i = STGE_TIMEOUT; i > 0; i--) { 2464 DELAY(10); 2465 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 2466 if ((v & MC_TxEnabled) == 0) 2467 break; 2468 } 2469 if (i == 0) 2470 device_printf(sc->sc_dev, "Stopping Tx MAC timed out\n"); 2471} 2472 2473static void 2474stge_stop_rx(struct stge_softc *sc) 2475{ 2476 uint32_t v; 2477 int i; 2478 2479 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 2480 if ((v & MC_RxEnabled) == 0) 2481 return; 2482 v |= MC_RxDisable; 2483 CSR_WRITE_4(sc, STGE_MACCtrl, v); 2484 for (i = STGE_TIMEOUT; i > 0; i--) { 2485 DELAY(10); 2486 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 2487 if ((v & MC_RxEnabled) == 0) 2488 break; 2489 } 2490 if (i == 0) 2491 device_printf(sc->sc_dev, "Stopping Rx MAC timed out\n"); 2492} 2493 2494static void 2495stge_init_tx_ring(struct stge_softc *sc) 2496{ 2497 struct stge_ring_data *rd; 2498 struct stge_txdesc *txd; 2499 bus_addr_t addr; 2500 int i; 2501 2502 STAILQ_INIT(&sc->sc_cdata.stge_txfreeq); 2503 STAILQ_INIT(&sc->sc_cdata.stge_txbusyq); 2504 2505 sc->sc_cdata.stge_tx_prod = 0; 2506 sc->sc_cdata.stge_tx_cons = 0; 2507 sc->sc_cdata.stge_tx_cnt = 0; 2508 2509 rd = &sc->sc_rdata; 2510 bzero(rd->stge_tx_ring, STGE_TX_RING_SZ); 2511 for (i = 0; i < STGE_TX_RING_CNT; i++) { 2512 if (i == (STGE_TX_RING_CNT - 1)) 2513 addr = STGE_TX_RING_ADDR(sc, 0); 2514 else 2515 addr = STGE_TX_RING_ADDR(sc, i + 1); 2516 rd->stge_tx_ring[i].tfd_next = htole64(addr); 2517 rd->stge_tx_ring[i].tfd_control = htole64(TFD_TFDDone); 2518 txd = &sc->sc_cdata.stge_txdesc[i]; 2519 STAILQ_INSERT_TAIL(&sc->sc_cdata.stge_txfreeq, txd, tx_q); 2520 } 2521 2522 bus_dmamap_sync(sc->sc_cdata.stge_tx_ring_tag, 2523 sc->sc_cdata.stge_tx_ring_map, 2524 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2525 2526} 2527 2528static int 2529stge_init_rx_ring(struct stge_softc *sc) 2530{ 2531 struct stge_ring_data *rd; 2532 bus_addr_t addr; 2533 int i; 2534 2535 sc->sc_cdata.stge_rx_cons = 0; 2536 STGE_RXCHAIN_RESET(sc); 2537 2538 rd = &sc->sc_rdata; 2539 bzero(rd->stge_rx_ring, STGE_RX_RING_SZ); 2540 for (i = 0; i < STGE_RX_RING_CNT; i++) { 2541 if (stge_newbuf(sc, i) != 0) 2542 return (ENOBUFS); 2543 if (i == (STGE_RX_RING_CNT - 1)) 2544 addr = STGE_RX_RING_ADDR(sc, 0); 2545 else 2546 addr = STGE_RX_RING_ADDR(sc, i + 1); 2547 rd->stge_rx_ring[i].rfd_next = htole64(addr); 2548 rd->stge_rx_ring[i].rfd_status = 0; 2549 } 2550 2551 bus_dmamap_sync(sc->sc_cdata.stge_rx_ring_tag, 2552 sc->sc_cdata.stge_rx_ring_map, 2553 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2554 2555 return (0); 2556} 2557 2558/* 2559 * stge_newbuf: 2560 * 2561 * Add a receive buffer to the indicated descriptor. 2562 */ 2563static int 2564stge_newbuf(struct stge_softc *sc, int idx) 2565{ 2566 struct stge_rxdesc *rxd; 2567 struct stge_rfd *rfd; 2568 struct mbuf *m; 2569 bus_dma_segment_t segs[1]; 2570 bus_dmamap_t map; 2571 int nsegs; 2572 2573 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2574 if (m == NULL) 2575 return (ENOBUFS); 2576 m->m_len = m->m_pkthdr.len = MCLBYTES; 2577 /* 2578 * The hardware requires 4bytes aligned DMA address when JUMBO 2579 * frame is used. 2580 */ 2581 if (sc->sc_if_framesize <= (MCLBYTES - ETHER_ALIGN)) 2582 m_adj(m, ETHER_ALIGN); 2583 2584 if (bus_dmamap_load_mbuf_sg(sc->sc_cdata.stge_rx_tag, 2585 sc->sc_cdata.stge_rx_sparemap, m, segs, &nsegs, 0) != 0) { 2586 m_freem(m); 2587 return (ENOBUFS); 2588 } 2589 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 2590 2591 rxd = &sc->sc_cdata.stge_rxdesc[idx]; 2592 if (rxd->rx_m != NULL) { 2593 bus_dmamap_sync(sc->sc_cdata.stge_rx_tag, rxd->rx_dmamap, 2594 BUS_DMASYNC_POSTREAD); 2595 bus_dmamap_unload(sc->sc_cdata.stge_rx_tag, rxd->rx_dmamap); 2596 } 2597 map = rxd->rx_dmamap; 2598 rxd->rx_dmamap = sc->sc_cdata.stge_rx_sparemap; 2599 sc->sc_cdata.stge_rx_sparemap = map; 2600 bus_dmamap_sync(sc->sc_cdata.stge_rx_tag, rxd->rx_dmamap, 2601 BUS_DMASYNC_PREREAD); 2602 rxd->rx_m = m; 2603 2604 rfd = &sc->sc_rdata.stge_rx_ring[idx]; 2605 rfd->rfd_frag.frag_word0 = 2606 htole64(FRAG_ADDR(segs[0].ds_addr) | FRAG_LEN(segs[0].ds_len)); 2607 rfd->rfd_status = 0; 2608 2609 return (0); 2610} 2611 2612/* 2613 * stge_set_filter: 2614 * 2615 * Set up the receive filter. 2616 */ 2617static void 2618stge_set_filter(struct stge_softc *sc) 2619{ 2620 struct ifnet *ifp; 2621 uint16_t mode; 2622 2623 STGE_LOCK_ASSERT(sc); 2624 2625 ifp = sc->sc_ifp; 2626 2627 mode = CSR_READ_2(sc, STGE_ReceiveMode); 2628 mode |= RM_ReceiveUnicast; 2629 if ((ifp->if_flags & IFF_BROADCAST) != 0) 2630 mode |= RM_ReceiveBroadcast; 2631 else 2632 mode &= ~RM_ReceiveBroadcast; 2633 if ((ifp->if_flags & IFF_PROMISC) != 0) 2634 mode |= RM_ReceiveAllFrames; 2635 else 2636 mode &= ~RM_ReceiveAllFrames; 2637 2638 CSR_WRITE_2(sc, STGE_ReceiveMode, mode); 2639} 2640 2641static void 2642stge_set_multi(struct stge_softc *sc) 2643{ 2644 struct ifnet *ifp; 2645 struct ifmultiaddr *ifma; 2646 uint32_t crc; 2647 uint32_t mchash[2]; 2648 uint16_t mode; 2649 int count; 2650 2651 STGE_LOCK_ASSERT(sc); 2652 2653 ifp = sc->sc_ifp; 2654 2655 mode = CSR_READ_2(sc, STGE_ReceiveMode); 2656 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 2657 if ((ifp->if_flags & IFF_PROMISC) != 0) 2658 mode |= RM_ReceiveAllFrames; 2659 else if ((ifp->if_flags & IFF_ALLMULTI) != 0) 2660 mode |= RM_ReceiveMulticast; 2661 CSR_WRITE_2(sc, STGE_ReceiveMode, mode); 2662 return; 2663 } 2664 2665 /* clear existing filters. */ 2666 CSR_WRITE_4(sc, STGE_HashTable0, 0); 2667 CSR_WRITE_4(sc, STGE_HashTable1, 0); 2668 2669 /* 2670 * Set up the multicast address filter by passing all multicast 2671 * addresses through a CRC generator, and then using the low-order 2672 * 6 bits as an index into the 64 bit multicast hash table. The 2673 * high order bits select the register, while the rest of the bits 2674 * select the bit within the register. 2675 */ 2676 2677 bzero(mchash, sizeof(mchash)); 2678 2679 count = 0; 2680 IF_ADDR_LOCK(sc->sc_ifp); 2681 TAILQ_FOREACH(ifma, &sc->sc_ifp->if_multiaddrs, ifma_link) { 2682 if (ifma->ifma_addr->sa_family != AF_LINK) 2683 continue; 2684 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) 2685 ifma->ifma_addr), ETHER_ADDR_LEN); 2686 2687 /* Just want the 6 least significant bits. */ 2688 crc &= 0x3f; 2689 2690 /* Set the corresponding bit in the hash table. */ 2691 mchash[crc >> 5] |= 1 << (crc & 0x1f); 2692 count++; 2693 } 2694 IF_ADDR_UNLOCK(ifp); 2695 2696 mode &= ~(RM_ReceiveMulticast | RM_ReceiveAllFrames); 2697 if (count > 0) 2698 mode |= RM_ReceiveMulticastHash; 2699 else 2700 mode &= ~RM_ReceiveMulticastHash; 2701 2702 CSR_WRITE_4(sc, STGE_HashTable0, mchash[0]); 2703 CSR_WRITE_4(sc, STGE_HashTable1, mchash[1]); 2704 CSR_WRITE_2(sc, STGE_ReceiveMode, mode); 2705} 2706 2707static int 2708sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 2709{ 2710 int error, value; 2711 2712 if (!arg1) 2713 return (EINVAL); 2714 value = *(int *)arg1; 2715 error = sysctl_handle_int(oidp, &value, 0, req); 2716 if (error || !req->newptr) 2717 return (error); 2718 if (value < low || value > high) 2719 return (EINVAL); 2720 *(int *)arg1 = value; 2721 2722 return (0); 2723} 2724 2725static int 2726sysctl_hw_stge_rxint_nframe(SYSCTL_HANDLER_ARGS) 2727{ 2728 return (sysctl_int_range(oidp, arg1, arg2, req, 2729 STGE_RXINT_NFRAME_MIN, STGE_RXINT_NFRAME_MAX)); 2730} 2731 2732static int 2733sysctl_hw_stge_rxint_dmawait(SYSCTL_HANDLER_ARGS) 2734{ 2735 return (sysctl_int_range(oidp, arg1, arg2, req, 2736 STGE_RXINT_DMAWAIT_MIN, STGE_RXINT_DMAWAIT_MAX)); 2737} 2738