if_stge.c revision 161235
1160641Syongari/* $NetBSD: if_stge.c,v 1.32 2005/12/11 12:22:49 christos Exp $ */ 2160641Syongari 3160641Syongari/*- 4160641Syongari * Copyright (c) 2001 The NetBSD Foundation, Inc. 5160641Syongari * All rights reserved. 6160641Syongari * 7160641Syongari * This code is derived from software contributed to The NetBSD Foundation 8160641Syongari * by Jason R. Thorpe. 9160641Syongari * 10160641Syongari * Redistribution and use in source and binary forms, with or without 11160641Syongari * modification, are permitted provided that the following conditions 12160641Syongari * are met: 13160641Syongari * 1. Redistributions of source code must retain the above copyright 14160641Syongari * notice, this list of conditions and the following disclaimer. 15160641Syongari * 2. Redistributions in binary form must reproduce the above copyright 16160641Syongari * notice, this list of conditions and the following disclaimer in the 17160641Syongari * documentation and/or other materials provided with the distribution. 18160641Syongari * 3. All advertising materials mentioning features or use of this software 19160641Syongari * must display the following acknowledgement: 20160641Syongari * This product includes software developed by the NetBSD 21160641Syongari * Foundation, Inc. and its contributors. 22160641Syongari * 4. Neither the name of The NetBSD Foundation nor the names of its 23160641Syongari * contributors may be used to endorse or promote products derived 24160641Syongari * from this software without specific prior written permission. 25160641Syongari * 26160641Syongari * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27160641Syongari * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28160641Syongari * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29160641Syongari * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30160641Syongari * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31160641Syongari * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32160641Syongari * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33160641Syongari * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34160641Syongari * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35160641Syongari * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36160641Syongari * POSSIBILITY OF SUCH DAMAGE. 37160641Syongari */ 38160641Syongari 39160641Syongari/* 40160641Syongari * Device driver for the Sundance Tech. TC9021 10/100/1000 41160641Syongari * Ethernet controller. 42160641Syongari */ 43160641Syongari 44160641Syongari#include <sys/cdefs.h> 45160641Syongari__FBSDID("$FreeBSD: head/sys/dev/stge/if_stge.c 161235 2006-08-12 01:24:37Z yongari $"); 46160641Syongari 47160641Syongari#ifdef HAVE_KERNEL_OPTION_HEADERS 48160641Syongari#include "opt_device_polling.h" 49160641Syongari#endif 50160641Syongari 51160641Syongari#include <sys/param.h> 52160641Syongari#include <sys/systm.h> 53160641Syongari#include <sys/endian.h> 54160641Syongari#include <sys/mbuf.h> 55160641Syongari#include <sys/malloc.h> 56160641Syongari#include <sys/kernel.h> 57160641Syongari#include <sys/module.h> 58160641Syongari#include <sys/socket.h> 59160641Syongari#include <sys/sockio.h> 60160641Syongari#include <sys/sysctl.h> 61160641Syongari#include <sys/taskqueue.h> 62160641Syongari 63160641Syongari#include <net/bpf.h> 64160641Syongari#include <net/ethernet.h> 65160641Syongari#include <net/if.h> 66160641Syongari#include <net/if_dl.h> 67160641Syongari#include <net/if_media.h> 68160641Syongari#include <net/if_types.h> 69160641Syongari#include <net/if_vlan_var.h> 70160641Syongari 71160641Syongari#include <machine/bus.h> 72160641Syongari#include <machine/resource.h> 73160641Syongari#include <sys/bus.h> 74160641Syongari#include <sys/rman.h> 75160641Syongari 76160641Syongari#include <dev/mii/mii.h> 77160641Syongari#include <dev/mii/miivar.h> 78160641Syongari 79160641Syongari#include <dev/pci/pcireg.h> 80160641Syongari#include <dev/pci/pcivar.h> 81160641Syongari 82160641Syongari#include <dev/stge/if_stgereg.h> 83160641Syongari 84160641Syongari#define STGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 85160641Syongari 86160641SyongariMODULE_DEPEND(stge, pci, 1, 1, 1); 87160641SyongariMODULE_DEPEND(stge, ether, 1, 1, 1); 88160641SyongariMODULE_DEPEND(stge, miibus, 1, 1, 1); 89160641Syongari 90160641Syongari/* "device miibus" required. See GENERIC if you get errors here. */ 91160641Syongari#include "miibus_if.h" 92160641Syongari 93160641Syongari/* 94160641Syongari * Devices supported by this driver. 95160641Syongari */ 96160641Syongaristatic struct stge_product { 97160641Syongari uint16_t stge_vendorid; 98160641Syongari uint16_t stge_deviceid; 99160641Syongari const char *stge_name; 100160641Syongari} stge_products[] = { 101160641Syongari { VENDOR_SUNDANCETI, DEVICEID_SUNDANCETI_ST1023, 102160641Syongari "Sundance ST-1023 Gigabit Ethernet" }, 103160641Syongari 104160641Syongari { VENDOR_SUNDANCETI, DEVICEID_SUNDANCETI_ST2021, 105160641Syongari "Sundance ST-2021 Gigabit Ethernet" }, 106160641Syongari 107160641Syongari { VENDOR_TAMARACK, DEVICEID_TAMARACK_TC9021, 108160641Syongari "Tamarack TC9021 Gigabit Ethernet" }, 109160641Syongari 110160641Syongari { VENDOR_TAMARACK, DEVICEID_TAMARACK_TC9021_ALT, 111160641Syongari "Tamarack TC9021 Gigabit Ethernet" }, 112160641Syongari 113160641Syongari /* 114160641Syongari * The Sundance sample boards use the Sundance vendor ID, 115160641Syongari * but the Tamarack product ID. 116160641Syongari */ 117160641Syongari { VENDOR_SUNDANCETI, DEVICEID_TAMARACK_TC9021, 118160641Syongari "Sundance TC9021 Gigabit Ethernet" }, 119160641Syongari 120160641Syongari { VENDOR_SUNDANCETI, DEVICEID_TAMARACK_TC9021_ALT, 121160641Syongari "Sundance TC9021 Gigabit Ethernet" }, 122160641Syongari 123160641Syongari { VENDOR_DLINK, DEVICEID_DLINK_DL4000, 124160641Syongari "D-Link DL-4000 Gigabit Ethernet" }, 125160641Syongari 126160641Syongari { VENDOR_ANTARES, DEVICEID_ANTARES_TC9021, 127160641Syongari "Antares Gigabit Ethernet" } 128160641Syongari}; 129160641Syongari 130160641Syongaristatic int stge_probe(device_t); 131160641Syongaristatic int stge_attach(device_t); 132160641Syongaristatic int stge_detach(device_t); 133160641Syongaristatic void stge_shutdown(device_t); 134160641Syongaristatic int stge_suspend(device_t); 135160641Syongaristatic int stge_resume(device_t); 136160641Syongari 137160641Syongaristatic int stge_encap(struct stge_softc *, struct mbuf **); 138160641Syongaristatic void stge_start(struct ifnet *); 139160641Syongaristatic void stge_start_locked(struct ifnet *); 140160641Syongaristatic void stge_watchdog(struct ifnet *); 141160641Syongaristatic int stge_ioctl(struct ifnet *, u_long, caddr_t); 142160641Syongaristatic void stge_init(void *); 143160641Syongaristatic void stge_init_locked(struct stge_softc *); 144160641Syongaristatic void stge_vlan_setup(struct stge_softc *); 145160641Syongaristatic void stge_stop(struct stge_softc *); 146160641Syongaristatic void stge_start_tx(struct stge_softc *); 147160641Syongaristatic void stge_start_rx(struct stge_softc *); 148160641Syongaristatic void stge_stop_tx(struct stge_softc *); 149160641Syongaristatic void stge_stop_rx(struct stge_softc *); 150160641Syongari 151160641Syongaristatic void stge_reset(struct stge_softc *, uint32_t); 152160641Syongaristatic int stge_eeprom_wait(struct stge_softc *); 153160641Syongaristatic void stge_read_eeprom(struct stge_softc *, int, uint16_t *); 154160641Syongaristatic void stge_tick(void *); 155160641Syongaristatic void stge_stats_update(struct stge_softc *); 156160641Syongaristatic void stge_set_filter(struct stge_softc *); 157160641Syongaristatic void stge_set_multi(struct stge_softc *); 158160641Syongari 159160641Syongaristatic void stge_link_task(void *, int); 160160641Syongaristatic void stge_intr(void *); 161160641Syongaristatic __inline int stge_tx_error(struct stge_softc *); 162160641Syongaristatic void stge_txeof(struct stge_softc *); 163160641Syongaristatic void stge_rxeof(struct stge_softc *); 164160641Syongaristatic __inline void stge_discard_rxbuf(struct stge_softc *, int); 165160641Syongaristatic int stge_newbuf(struct stge_softc *, int); 166160641Syongari#ifndef __NO_STRICT_ALIGNMENT 167160641Syongaristatic __inline struct mbuf *stge_fixup_rx(struct stge_softc *, struct mbuf *); 168160641Syongari#endif 169160641Syongari 170160641Syongaristatic void stge_mii_sync(struct stge_softc *); 171160641Syongaristatic void stge_mii_send(struct stge_softc *, uint32_t, int); 172160641Syongaristatic int stge_mii_readreg(struct stge_softc *, struct stge_mii_frame *); 173160641Syongaristatic int stge_mii_writereg(struct stge_softc *, struct stge_mii_frame *); 174160641Syongaristatic int stge_miibus_readreg(device_t, int, int); 175160641Syongaristatic int stge_miibus_writereg(device_t, int, int, int); 176160641Syongaristatic void stge_miibus_statchg(device_t); 177160641Syongaristatic int stge_mediachange(struct ifnet *); 178160641Syongaristatic void stge_mediastatus(struct ifnet *, struct ifmediareq *); 179160641Syongari 180160641Syongaristatic void stge_dmamap_cb(void *, bus_dma_segment_t *, int, int); 181160641Syongaristatic int stge_dma_alloc(struct stge_softc *); 182160641Syongaristatic void stge_dma_free(struct stge_softc *); 183160641Syongaristatic void stge_dma_wait(struct stge_softc *); 184160641Syongaristatic void stge_init_tx_ring(struct stge_softc *); 185160641Syongaristatic int stge_init_rx_ring(struct stge_softc *); 186160641Syongari#ifdef DEVICE_POLLING 187160641Syongaristatic void stge_poll(struct ifnet *, enum poll_cmd, int); 188160641Syongari#endif 189160641Syongari 190160641Syongaristatic int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 191160641Syongaristatic int sysctl_hw_stge_rxint_nframe(SYSCTL_HANDLER_ARGS); 192160641Syongaristatic int sysctl_hw_stge_rxint_dmawait(SYSCTL_HANDLER_ARGS); 193160641Syongari 194160641Syongaristatic device_method_t stge_methods[] = { 195160641Syongari /* Device interface */ 196160641Syongari DEVMETHOD(device_probe, stge_probe), 197160641Syongari DEVMETHOD(device_attach, stge_attach), 198160641Syongari DEVMETHOD(device_detach, stge_detach), 199160641Syongari DEVMETHOD(device_shutdown, stge_shutdown), 200160641Syongari DEVMETHOD(device_suspend, stge_suspend), 201160641Syongari DEVMETHOD(device_resume, stge_resume), 202160641Syongari 203160641Syongari /* MII interface */ 204160641Syongari DEVMETHOD(miibus_readreg, stge_miibus_readreg), 205160641Syongari DEVMETHOD(miibus_writereg, stge_miibus_writereg), 206160641Syongari DEVMETHOD(miibus_statchg, stge_miibus_statchg), 207160641Syongari 208160641Syongari { 0, 0 } 209160641Syongari 210160641Syongari}; 211160641Syongari 212160641Syongaristatic driver_t stge_driver = { 213160641Syongari "stge", 214160641Syongari stge_methods, 215160641Syongari sizeof(struct stge_softc) 216160641Syongari}; 217160641Syongari 218160641Syongaristatic devclass_t stge_devclass; 219160641Syongari 220160641SyongariDRIVER_MODULE(stge, pci, stge_driver, stge_devclass, 0, 0); 221160641SyongariDRIVER_MODULE(miibus, stge, miibus_driver, miibus_devclass, 0, 0); 222160641Syongari 223160641Syongaristatic struct resource_spec stge_res_spec_io[] = { 224160641Syongari { SYS_RES_IOPORT, PCIR_BAR(0), RF_ACTIVE }, 225160641Syongari { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 226160641Syongari { -1, 0, 0 } 227160641Syongari}; 228160641Syongari 229160641Syongaristatic struct resource_spec stge_res_spec_mem[] = { 230160641Syongari { SYS_RES_MEMORY, PCIR_BAR(1), RF_ACTIVE }, 231160641Syongari { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 232160641Syongari { -1, 0, 0 } 233160641Syongari}; 234160641Syongari 235160641Syongari#define MII_SET(x) \ 236160641Syongari CSR_WRITE_1(sc, STGE_PhyCtrl, CSR_READ_1(sc, STGE_PhyCtrl) | (x)) 237160641Syongari#define MII_CLR(x) \ 238160641Syongari CSR_WRITE_1(sc, STGE_PhyCtrl, CSR_READ_1(sc, STGE_PhyCtrl) & ~(x)) 239160641Syongari 240160641Syongari/* 241160641Syongari * Sync the PHYs by setting data bit and strobing the clock 32 times. 242160641Syongari */ 243160641Syongaristatic void 244160641Syongaristge_mii_sync(struct stge_softc *sc) 245160641Syongari{ 246160641Syongari int i; 247160641Syongari 248160641Syongari MII_SET(PC_MgmtDir | PC_MgmtData); 249160641Syongari 250160641Syongari for (i = 0; i < 32; i++) { 251160641Syongari MII_SET(PC_MgmtClk); 252160641Syongari DELAY(1); 253160641Syongari MII_CLR(PC_MgmtClk); 254160641Syongari DELAY(1); 255160641Syongari } 256160641Syongari} 257160641Syongari 258160641Syongari/* 259160641Syongari * Clock a series of bits through the MII. 260160641Syongari */ 261160641Syongaristatic void 262160641Syongaristge_mii_send(struct stge_softc *sc, uint32_t bits, int cnt) 263160641Syongari{ 264160641Syongari int i; 265160641Syongari 266160641Syongari MII_CLR(PC_MgmtClk); 267160641Syongari 268160641Syongari for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 269160641Syongari if (bits & i) 270160641Syongari MII_SET(PC_MgmtData); 271160641Syongari else 272160641Syongari MII_CLR(PC_MgmtData); 273160641Syongari DELAY(1); 274160641Syongari MII_CLR(PC_MgmtClk); 275160641Syongari DELAY(1); 276160641Syongari MII_SET(PC_MgmtClk); 277160641Syongari } 278160641Syongari} 279160641Syongari 280160641Syongari/* 281160641Syongari * Read an PHY register through the MII. 282160641Syongari */ 283160641Syongaristatic int 284160641Syongaristge_mii_readreg(struct stge_softc *sc, struct stge_mii_frame *frame) 285160641Syongari{ 286160641Syongari int i, ack; 287160641Syongari 288160641Syongari /* 289160641Syongari * Set up frame for RX. 290160641Syongari */ 291160641Syongari frame->mii_stdelim = STGE_MII_STARTDELIM; 292160641Syongari frame->mii_opcode = STGE_MII_READOP; 293160641Syongari frame->mii_turnaround = 0; 294160641Syongari frame->mii_data = 0; 295160641Syongari 296160641Syongari CSR_WRITE_1(sc, STGE_PhyCtrl, 0 | sc->sc_PhyCtrl); 297160641Syongari /* 298160641Syongari * Turn on data xmit. 299160641Syongari */ 300160641Syongari MII_SET(PC_MgmtDir); 301160641Syongari 302160641Syongari stge_mii_sync(sc); 303160641Syongari 304160641Syongari /* 305160641Syongari * Send command/address info. 306160641Syongari */ 307160641Syongari stge_mii_send(sc, frame->mii_stdelim, 2); 308160641Syongari stge_mii_send(sc, frame->mii_opcode, 2); 309160641Syongari stge_mii_send(sc, frame->mii_phyaddr, 5); 310160641Syongari stge_mii_send(sc, frame->mii_regaddr, 5); 311160641Syongari 312160641Syongari /* Turn off xmit. */ 313160641Syongari MII_CLR(PC_MgmtDir); 314160641Syongari 315160641Syongari /* Idle bit */ 316160641Syongari MII_CLR((PC_MgmtClk | PC_MgmtData)); 317160641Syongari DELAY(1); 318160641Syongari MII_SET(PC_MgmtClk); 319160641Syongari DELAY(1); 320160641Syongari 321160641Syongari /* Check for ack */ 322160641Syongari MII_CLR(PC_MgmtClk); 323160641Syongari DELAY(1); 324160641Syongari ack = CSR_READ_1(sc, STGE_PhyCtrl) & PC_MgmtData; 325160641Syongari MII_SET(PC_MgmtClk); 326160641Syongari DELAY(1); 327160641Syongari 328160641Syongari /* 329160641Syongari * Now try reading data bits. If the ack failed, we still 330160641Syongari * need to clock through 16 cycles to keep the PHY(s) in sync. 331160641Syongari */ 332160641Syongari if (ack) { 333160641Syongari for(i = 0; i < 16; i++) { 334160641Syongari MII_CLR(PC_MgmtClk); 335160641Syongari DELAY(1); 336160641Syongari MII_SET(PC_MgmtClk); 337160641Syongari DELAY(1); 338160641Syongari } 339160641Syongari goto fail; 340160641Syongari } 341160641Syongari 342160641Syongari for (i = 0x8000; i; i >>= 1) { 343160641Syongari MII_CLR(PC_MgmtClk); 344160641Syongari DELAY(1); 345160641Syongari if (!ack) { 346160641Syongari if (CSR_READ_1(sc, STGE_PhyCtrl) & PC_MgmtData) 347160641Syongari frame->mii_data |= i; 348160641Syongari DELAY(1); 349160641Syongari } 350160641Syongari MII_SET(PC_MgmtClk); 351160641Syongari DELAY(1); 352160641Syongari } 353160641Syongari 354160641Syongarifail: 355160641Syongari MII_CLR(PC_MgmtClk); 356160641Syongari DELAY(1); 357160641Syongari MII_SET(PC_MgmtClk); 358160641Syongari DELAY(1); 359160641Syongari 360160641Syongari if (ack) 361160641Syongari return(1); 362160641Syongari return(0); 363160641Syongari} 364160641Syongari 365160641Syongari/* 366160641Syongari * Write to a PHY register through the MII. 367160641Syongari */ 368160641Syongaristatic int 369160641Syongaristge_mii_writereg(struct stge_softc *sc, struct stge_mii_frame *frame) 370160641Syongari{ 371160641Syongari 372160641Syongari /* 373160641Syongari * Set up frame for TX. 374160641Syongari */ 375160641Syongari frame->mii_stdelim = STGE_MII_STARTDELIM; 376160641Syongari frame->mii_opcode = STGE_MII_WRITEOP; 377160641Syongari frame->mii_turnaround = STGE_MII_TURNAROUND; 378160641Syongari 379160641Syongari /* 380160641Syongari * Turn on data output. 381160641Syongari */ 382160641Syongari MII_SET(PC_MgmtDir); 383160641Syongari 384160641Syongari stge_mii_sync(sc); 385160641Syongari 386160641Syongari stge_mii_send(sc, frame->mii_stdelim, 2); 387160641Syongari stge_mii_send(sc, frame->mii_opcode, 2); 388160641Syongari stge_mii_send(sc, frame->mii_phyaddr, 5); 389160641Syongari stge_mii_send(sc, frame->mii_regaddr, 5); 390160641Syongari stge_mii_send(sc, frame->mii_turnaround, 2); 391160641Syongari stge_mii_send(sc, frame->mii_data, 16); 392160641Syongari 393160641Syongari /* Idle bit. */ 394160641Syongari MII_SET(PC_MgmtClk); 395160641Syongari DELAY(1); 396160641Syongari MII_CLR(PC_MgmtClk); 397160641Syongari DELAY(1); 398160641Syongari 399160641Syongari /* 400160641Syongari * Turn off xmit. 401160641Syongari */ 402160641Syongari MII_CLR(PC_MgmtDir); 403160641Syongari 404160641Syongari return(0); 405160641Syongari} 406160641Syongari 407160641Syongari/* 408160641Syongari * sc_miibus_readreg: [mii interface function] 409160641Syongari * 410160641Syongari * Read a PHY register on the MII of the TC9021. 411160641Syongari */ 412160641Syongaristatic int 413160641Syongaristge_miibus_readreg(device_t dev, int phy, int reg) 414160641Syongari{ 415160641Syongari struct stge_softc *sc; 416160641Syongari struct stge_mii_frame frame; 417160641Syongari int error; 418160641Syongari 419160641Syongari sc = device_get_softc(dev); 420160641Syongari 421160641Syongari if (reg == STGE_PhyCtrl) { 422160641Syongari /* XXX allow ip1000phy read STGE_PhyCtrl register. */ 423160641Syongari STGE_MII_LOCK(sc); 424160641Syongari error = CSR_READ_1(sc, STGE_PhyCtrl); 425160641Syongari STGE_MII_UNLOCK(sc); 426160641Syongari return (error); 427160641Syongari } 428160641Syongari bzero(&frame, sizeof(frame)); 429160641Syongari frame.mii_phyaddr = phy; 430160641Syongari frame.mii_regaddr = reg; 431160641Syongari 432160641Syongari STGE_MII_LOCK(sc); 433160641Syongari error = stge_mii_readreg(sc, &frame); 434160641Syongari STGE_MII_UNLOCK(sc); 435160641Syongari 436160641Syongari if (error != 0) { 437160641Syongari /* Don't show errors for PHY probe request */ 438160641Syongari if (reg != 1) 439160641Syongari device_printf(sc->sc_dev, "phy read fail\n"); 440160641Syongari return (0); 441160641Syongari } 442160641Syongari return (frame.mii_data); 443160641Syongari} 444160641Syongari 445160641Syongari/* 446160641Syongari * stge_miibus_writereg: [mii interface function] 447160641Syongari * 448160641Syongari * Write a PHY register on the MII of the TC9021. 449160641Syongari */ 450160641Syongaristatic int 451160641Syongaristge_miibus_writereg(device_t dev, int phy, int reg, int val) 452160641Syongari{ 453160641Syongari struct stge_softc *sc; 454160641Syongari struct stge_mii_frame frame; 455160641Syongari int error; 456160641Syongari 457160641Syongari sc = device_get_softc(dev); 458160641Syongari 459160641Syongari bzero(&frame, sizeof(frame)); 460160641Syongari frame.mii_phyaddr = phy; 461160641Syongari frame.mii_regaddr = reg; 462160641Syongari frame.mii_data = val; 463160641Syongari 464160641Syongari STGE_MII_LOCK(sc); 465160641Syongari error = stge_mii_writereg(sc, &frame); 466160641Syongari STGE_MII_UNLOCK(sc); 467160641Syongari 468160641Syongari if (error != 0) 469160641Syongari device_printf(sc->sc_dev, "phy write fail\n"); 470160641Syongari return (0); 471160641Syongari} 472160641Syongari 473160641Syongari/* 474160641Syongari * stge_miibus_statchg: [mii interface function] 475160641Syongari * 476160641Syongari * Callback from MII layer when media changes. 477160641Syongari */ 478160641Syongaristatic void 479160641Syongaristge_miibus_statchg(device_t dev) 480160641Syongari{ 481160641Syongari struct stge_softc *sc; 482160641Syongari struct mii_data *mii; 483160641Syongari 484160641Syongari sc = device_get_softc(dev); 485160641Syongari mii = device_get_softc(sc->sc_miibus); 486160641Syongari 487160641Syongari STGE_MII_LOCK(sc); 488160641Syongari if (IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE) { 489160641Syongari STGE_MII_UNLOCK(sc); 490160641Syongari return; 491160641Syongari } 492160641Syongari 493160641Syongari sc->sc_MACCtrl = 0; 494160641Syongari if (((mii->mii_media_active & IFM_GMASK) & IFM_FDX) != 0) 495160641Syongari sc->sc_MACCtrl |= MC_DuplexSelect; 496160641Syongari if (((mii->mii_media_active & IFM_GMASK) & IFM_FLAG0) != 0) 497160641Syongari sc->sc_MACCtrl |= MC_RxFlowControlEnable; 498160641Syongari if (((mii->mii_media_active & IFM_GMASK) & IFM_FLAG1) != 0) 499160641Syongari sc->sc_MACCtrl |= MC_TxFlowControlEnable; 500160641Syongari /* 501160641Syongari * We can't access STGE_MACCtrl register in this context due to 502160641Syongari * the races between MII layer and driver which accesses this 503160641Syongari * register to program MAC. In order to solve the race, we defer 504160641Syongari * STGE_MACCtrl programming until we know we are out of MII. 505160641Syongari */ 506160641Syongari taskqueue_enqueue(taskqueue_swi, &sc->sc_link_task); 507160641Syongari STGE_MII_UNLOCK(sc); 508160641Syongari} 509160641Syongari 510160641Syongari/* 511160641Syongari * stge_mediastatus: [ifmedia interface function] 512160641Syongari * 513160641Syongari * Get the current interface media status. 514160641Syongari */ 515160641Syongaristatic void 516160641Syongaristge_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 517160641Syongari{ 518160641Syongari struct stge_softc *sc; 519160641Syongari struct mii_data *mii; 520160641Syongari 521160641Syongari sc = ifp->if_softc; 522160641Syongari mii = device_get_softc(sc->sc_miibus); 523160641Syongari 524160641Syongari mii_pollstat(mii); 525160641Syongari ifmr->ifm_status = mii->mii_media_status; 526160641Syongari ifmr->ifm_active = mii->mii_media_active; 527160641Syongari} 528160641Syongari 529160641Syongari/* 530160641Syongari * stge_mediachange: [ifmedia interface function] 531160641Syongari * 532160641Syongari * Set hardware to newly-selected media. 533160641Syongari */ 534160641Syongaristatic int 535160641Syongaristge_mediachange(struct ifnet *ifp) 536160641Syongari{ 537160641Syongari struct stge_softc *sc; 538160641Syongari struct mii_data *mii; 539160641Syongari 540160641Syongari sc = ifp->if_softc; 541160641Syongari mii = device_get_softc(sc->sc_miibus); 542160641Syongari mii_mediachg(mii); 543160641Syongari 544160641Syongari return (0); 545160641Syongari} 546160641Syongari 547160641Syongaristatic int 548160641Syongaristge_eeprom_wait(struct stge_softc *sc) 549160641Syongari{ 550160641Syongari int i; 551160641Syongari 552160641Syongari for (i = 0; i < STGE_TIMEOUT; i++) { 553160641Syongari DELAY(1000); 554160641Syongari if ((CSR_READ_2(sc, STGE_EepromCtrl) & EC_EepromBusy) == 0) 555160641Syongari return (0); 556160641Syongari } 557160641Syongari return (1); 558160641Syongari} 559160641Syongari 560160641Syongari/* 561160641Syongari * stge_read_eeprom: 562160641Syongari * 563160641Syongari * Read data from the serial EEPROM. 564160641Syongari */ 565160641Syongaristatic void 566160641Syongaristge_read_eeprom(struct stge_softc *sc, int offset, uint16_t *data) 567160641Syongari{ 568160641Syongari 569160641Syongari if (stge_eeprom_wait(sc)) 570160641Syongari device_printf(sc->sc_dev, "EEPROM failed to come ready\n"); 571160641Syongari 572160641Syongari CSR_WRITE_2(sc, STGE_EepromCtrl, 573160641Syongari EC_EepromAddress(offset) | EC_EepromOpcode(EC_OP_RR)); 574160641Syongari if (stge_eeprom_wait(sc)) 575160641Syongari device_printf(sc->sc_dev, "EEPROM read timed out\n"); 576160641Syongari *data = CSR_READ_2(sc, STGE_EepromData); 577160641Syongari} 578160641Syongari 579160641Syongari 580160641Syongaristatic int 581160641Syongaristge_probe(device_t dev) 582160641Syongari{ 583160641Syongari struct stge_product *sp; 584160641Syongari int i; 585160641Syongari uint16_t vendor, devid; 586160641Syongari 587160641Syongari vendor = pci_get_vendor(dev); 588160641Syongari devid = pci_get_device(dev); 589160641Syongari sp = stge_products; 590160641Syongari for (i = 0; i < sizeof(stge_products)/sizeof(stge_products[0]); 591160641Syongari i++, sp++) { 592160641Syongari if (vendor == sp->stge_vendorid && 593160641Syongari devid == sp->stge_deviceid) { 594160641Syongari device_set_desc(dev, sp->stge_name); 595160641Syongari return (BUS_PROBE_DEFAULT); 596160641Syongari } 597160641Syongari } 598160641Syongari 599160641Syongari return (ENXIO); 600160641Syongari} 601160641Syongari 602160641Syongaristatic int 603160641Syongaristge_attach(device_t dev) 604160641Syongari{ 605160641Syongari struct stge_softc *sc; 606160641Syongari struct ifnet *ifp; 607160641Syongari uint8_t enaddr[ETHER_ADDR_LEN]; 608160641Syongari int error, i; 609160641Syongari uint16_t cmd; 610160641Syongari uint32_t val; 611160641Syongari 612160641Syongari error = 0; 613160641Syongari sc = device_get_softc(dev); 614160641Syongari sc->sc_dev = dev; 615160641Syongari 616160641Syongari mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 617160641Syongari MTX_DEF); 618160641Syongari mtx_init(&sc->sc_mii_mtx, "stge_mii_mutex", NULL, MTX_DEF); 619160641Syongari callout_init_mtx(&sc->sc_tick_ch, &sc->sc_mtx, 0); 620160641Syongari TASK_INIT(&sc->sc_link_task, 0, stge_link_task, sc); 621160641Syongari 622160641Syongari /* 623160641Syongari * Map the device. 624160641Syongari */ 625160641Syongari pci_enable_busmaster(dev); 626160641Syongari cmd = pci_read_config(dev, PCIR_COMMAND, 2); 627160641Syongari val = pci_read_config(dev, PCIR_BAR(1), 4); 628160641Syongari if ((val & 0x01) != 0) 629160641Syongari sc->sc_spec = stge_res_spec_mem; 630160641Syongari else { 631160641Syongari val = pci_read_config(dev, PCIR_BAR(0), 4); 632160641Syongari if ((val & 0x01) == 0) { 633160641Syongari device_printf(sc->sc_dev, "couldn't locate IO BAR\n"); 634160641Syongari error = ENXIO; 635160641Syongari goto fail; 636160641Syongari } 637160641Syongari sc->sc_spec = stge_res_spec_io; 638160641Syongari } 639160641Syongari error = bus_alloc_resources(dev, sc->sc_spec, sc->sc_res); 640160641Syongari if (error != 0) { 641160641Syongari device_printf(dev, "couldn't allocate %s resources\n", 642160641Syongari sc->sc_spec == stge_res_spec_mem ? "memory" : "I/O"); 643160641Syongari goto fail; 644160641Syongari } 645160641Syongari sc->sc_rev = pci_get_revid(dev); 646160641Syongari 647160641Syongari SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 648160641Syongari SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 649160641Syongari "rxint_nframe", CTLTYPE_INT|CTLFLAG_RW, &sc->sc_rxint_nframe, 0, 650160641Syongari sysctl_hw_stge_rxint_nframe, "I", "stge rx interrupt nframe"); 651160641Syongari 652160641Syongari SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 653160641Syongari SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 654160641Syongari "rxint_dmawait", CTLTYPE_INT|CTLFLAG_RW, &sc->sc_rxint_dmawait, 0, 655160641Syongari sysctl_hw_stge_rxint_dmawait, "I", "stge rx interrupt dmawait"); 656160641Syongari 657160641Syongari /* Pull in device tunables. */ 658160641Syongari sc->sc_rxint_nframe = STGE_RXINT_NFRAME_DEFAULT; 659160641Syongari error = resource_int_value(device_get_name(dev), device_get_unit(dev), 660160641Syongari "rxint_nframe", &sc->sc_rxint_nframe); 661160641Syongari if (error == 0) { 662160641Syongari if (sc->sc_rxint_nframe < STGE_RXINT_NFRAME_MIN || 663160641Syongari sc->sc_rxint_nframe > STGE_RXINT_NFRAME_MAX) { 664160641Syongari device_printf(dev, "rxint_nframe value out of range; " 665160641Syongari "using default: %d\n", STGE_RXINT_NFRAME_DEFAULT); 666160641Syongari sc->sc_rxint_nframe = STGE_RXINT_NFRAME_DEFAULT; 667160641Syongari } 668160641Syongari } 669160641Syongari 670160641Syongari sc->sc_rxint_dmawait = STGE_RXINT_DMAWAIT_DEFAULT; 671160641Syongari error = resource_int_value(device_get_name(dev), device_get_unit(dev), 672160641Syongari "rxint_dmawait", &sc->sc_rxint_dmawait); 673160641Syongari if (error == 0) { 674160641Syongari if (sc->sc_rxint_dmawait < STGE_RXINT_DMAWAIT_MIN || 675160641Syongari sc->sc_rxint_dmawait > STGE_RXINT_DMAWAIT_MAX) { 676160641Syongari device_printf(dev, "rxint_dmawait value out of range; " 677160641Syongari "using default: %d\n", STGE_RXINT_DMAWAIT_DEFAULT); 678160641Syongari sc->sc_rxint_dmawait = STGE_RXINT_DMAWAIT_DEFAULT; 679160641Syongari } 680160641Syongari } 681160641Syongari 682160641Syongari if ((error = stge_dma_alloc(sc) != 0)) 683160641Syongari goto fail; 684160641Syongari 685160641Syongari /* 686160641Syongari * Determine if we're copper or fiber. It affects how we 687160641Syongari * reset the card. 688160641Syongari */ 689160641Syongari if (CSR_READ_4(sc, STGE_AsicCtrl) & AC_PhyMedia) 690160641Syongari sc->sc_usefiber = 1; 691160641Syongari else 692160641Syongari sc->sc_usefiber = 0; 693160641Syongari 694160641Syongari /* Load LED configuration from EEPROM. */ 695160641Syongari stge_read_eeprom(sc, STGE_EEPROM_LEDMode, &sc->sc_led); 696160641Syongari 697160641Syongari /* 698160641Syongari * Reset the chip to a known state. 699160641Syongari */ 700160641Syongari STGE_LOCK(sc); 701160641Syongari stge_reset(sc, STGE_RESET_FULL); 702160641Syongari STGE_UNLOCK(sc); 703160641Syongari 704160641Syongari /* 705160641Syongari * Reading the station address from the EEPROM doesn't seem 706160641Syongari * to work, at least on my sample boards. Instead, since 707160641Syongari * the reset sequence does AutoInit, read it from the station 708160641Syongari * address registers. For Sundance 1023 you can only read it 709160641Syongari * from EEPROM. 710160641Syongari */ 711160641Syongari if (pci_get_device(dev) != DEVICEID_SUNDANCETI_ST1023) { 712160641Syongari uint16_t v; 713160641Syongari 714160641Syongari v = CSR_READ_2(sc, STGE_StationAddress0); 715160641Syongari enaddr[0] = v & 0xff; 716160641Syongari enaddr[1] = v >> 8; 717160641Syongari v = CSR_READ_2(sc, STGE_StationAddress1); 718160641Syongari enaddr[2] = v & 0xff; 719160641Syongari enaddr[3] = v >> 8; 720160641Syongari v = CSR_READ_2(sc, STGE_StationAddress2); 721160641Syongari enaddr[4] = v & 0xff; 722160641Syongari enaddr[5] = v >> 8; 723160641Syongari sc->sc_stge1023 = 0; 724160641Syongari } else { 725160641Syongari uint16_t myaddr[ETHER_ADDR_LEN / 2]; 726160641Syongari for (i = 0; i <ETHER_ADDR_LEN / 2; i++) { 727160641Syongari stge_read_eeprom(sc, STGE_EEPROM_StationAddress0 + i, 728160641Syongari &myaddr[i]); 729160641Syongari myaddr[i] = le16toh(myaddr[i]); 730160641Syongari } 731160641Syongari bcopy(myaddr, enaddr, sizeof(enaddr)); 732160641Syongari sc->sc_stge1023 = 1; 733160641Syongari } 734160641Syongari 735160641Syongari ifp = sc->sc_ifp = if_alloc(IFT_ETHER); 736160641Syongari if (ifp == NULL) { 737160641Syongari device_printf(sc->sc_dev, "failed to if_alloc()\n"); 738160641Syongari error = ENXIO; 739160641Syongari goto fail; 740160641Syongari } 741160641Syongari 742160641Syongari ifp->if_softc = sc; 743160641Syongari if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 744160641Syongari ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 745160641Syongari ifp->if_ioctl = stge_ioctl; 746160641Syongari ifp->if_start = stge_start; 747160641Syongari ifp->if_watchdog = stge_watchdog; 748160641Syongari ifp->if_init = stge_init; 749160641Syongari ifp->if_mtu = ETHERMTU; 750160641Syongari ifp->if_snd.ifq_drv_maxlen = STGE_TX_RING_CNT - 1; 751160641Syongari IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 752160641Syongari IFQ_SET_READY(&ifp->if_snd); 753160641Syongari /* Revision B3 and earlier chips have checksum bug. */ 754160641Syongari if (sc->sc_rev >= 0x0c) { 755160641Syongari ifp->if_hwassist = STGE_CSUM_FEATURES; 756160641Syongari ifp->if_capabilities = IFCAP_HWCSUM; 757160641Syongari } else { 758160641Syongari ifp->if_hwassist = 0; 759160641Syongari ifp->if_capabilities = 0; 760160641Syongari } 761160641Syongari ifp->if_capenable = ifp->if_capabilities; 762160641Syongari 763160641Syongari /* 764160641Syongari * Read some important bits from the PhyCtrl register. 765160641Syongari */ 766160641Syongari sc->sc_PhyCtrl = CSR_READ_1(sc, STGE_PhyCtrl) & 767160641Syongari (PC_PhyDuplexPolarity | PC_PhyLnkPolarity); 768160641Syongari 769160641Syongari /* Set up MII bus. */ 770160641Syongari if ((error = mii_phy_probe(sc->sc_dev, &sc->sc_miibus, stge_mediachange, 771160641Syongari stge_mediastatus)) != 0) { 772160641Syongari device_printf(sc->sc_dev, "no PHY found!\n"); 773160641Syongari goto fail; 774160641Syongari } 775160641Syongari 776160641Syongari ether_ifattach(ifp, enaddr); 777160641Syongari 778160641Syongari /* VLAN capability setup */ 779160641Syongari ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 780160641Syongari if (sc->sc_rev >= 0x0c) 781160641Syongari ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 782160641Syongari ifp->if_capenable = ifp->if_capabilities; 783160641Syongari#ifdef DEVICE_POLLING 784160641Syongari ifp->if_capabilities |= IFCAP_POLLING; 785160641Syongari#endif 786160641Syongari /* 787160641Syongari * Tell the upper layer(s) we support long frames. 788160641Syongari * Must appear after the call to ether_ifattach() because 789160641Syongari * ether_ifattach() sets ifi_hdrlen to the default value. 790160641Syongari */ 791160641Syongari ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 792160641Syongari 793160641Syongari /* 794160641Syongari * The manual recommends disabling early transmit, so we 795160641Syongari * do. It's disabled anyway, if using IP checksumming, 796160641Syongari * since the entire packet must be in the FIFO in order 797160641Syongari * for the chip to perform the checksum. 798160641Syongari */ 799160641Syongari sc->sc_txthresh = 0x0fff; 800160641Syongari 801160641Syongari /* 802160641Syongari * Disable MWI if the PCI layer tells us to. 803160641Syongari */ 804160641Syongari sc->sc_DMACtrl = 0; 805160641Syongari if ((cmd & PCIM_CMD_MWRICEN) == 0) 806160641Syongari sc->sc_DMACtrl |= DMAC_MWIDisable; 807160641Syongari 808160641Syongari /* 809160641Syongari * Hookup IRQ 810160641Syongari */ 811160641Syongari error = bus_setup_intr(dev, sc->sc_res[1], INTR_TYPE_NET | INTR_MPSAFE, 812160641Syongari stge_intr, sc, &sc->sc_ih); 813160641Syongari if (error != 0) { 814160641Syongari ether_ifdetach(ifp); 815160641Syongari device_printf(sc->sc_dev, "couldn't set up IRQ\n"); 816160641Syongari sc->sc_ifp = NULL; 817160641Syongari goto fail; 818160641Syongari } 819160641Syongari 820160641Syongarifail: 821160641Syongari if (error != 0) 822160641Syongari stge_detach(dev); 823160641Syongari 824160641Syongari return (error); 825160641Syongari} 826160641Syongari 827160641Syongaristatic int 828160641Syongaristge_detach(device_t dev) 829160641Syongari{ 830160641Syongari struct stge_softc *sc; 831160641Syongari struct ifnet *ifp; 832160641Syongari 833160641Syongari sc = device_get_softc(dev); 834160641Syongari 835160641Syongari ifp = sc->sc_ifp; 836160641Syongari#ifdef DEVICE_POLLING 837160641Syongari if (ifp && ifp->if_capenable & IFCAP_POLLING) 838160641Syongari ether_poll_deregister(ifp); 839160641Syongari#endif 840160641Syongari if (device_is_attached(dev)) { 841160641Syongari STGE_LOCK(sc); 842160641Syongari /* XXX */ 843160641Syongari sc->sc_detach = 1; 844160641Syongari stge_stop(sc); 845160641Syongari STGE_UNLOCK(sc); 846160641Syongari callout_drain(&sc->sc_tick_ch); 847160641Syongari taskqueue_drain(taskqueue_swi, &sc->sc_link_task); 848160641Syongari ether_ifdetach(ifp); 849160641Syongari } 850160641Syongari 851160641Syongari if (sc->sc_miibus != NULL) { 852160641Syongari device_delete_child(dev, sc->sc_miibus); 853160641Syongari sc->sc_miibus = NULL; 854160641Syongari } 855160641Syongari bus_generic_detach(dev); 856160641Syongari stge_dma_free(sc); 857160641Syongari 858160641Syongari if (ifp != NULL) { 859160641Syongari if_free(ifp); 860160641Syongari sc->sc_ifp = NULL; 861160641Syongari } 862160641Syongari 863160641Syongari if (sc->sc_ih) { 864160641Syongari bus_teardown_intr(dev, sc->sc_res[1], sc->sc_ih); 865160641Syongari sc->sc_ih = NULL; 866160641Syongari } 867160641Syongari bus_release_resources(dev, sc->sc_spec, sc->sc_res); 868160641Syongari 869160641Syongari mtx_destroy(&sc->sc_mii_mtx); 870160641Syongari mtx_destroy(&sc->sc_mtx); 871160641Syongari 872160641Syongari return (0); 873160641Syongari} 874160641Syongari 875160641Syongaristruct stge_dmamap_arg { 876160641Syongari bus_addr_t stge_busaddr; 877160641Syongari}; 878160641Syongari 879160641Syongaristatic void 880160641Syongaristge_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 881160641Syongari{ 882160641Syongari struct stge_dmamap_arg *ctx; 883160641Syongari 884160641Syongari if (error != 0) 885160641Syongari return; 886160641Syongari 887160641Syongari ctx = (struct stge_dmamap_arg *)arg; 888160641Syongari ctx->stge_busaddr = segs[0].ds_addr; 889160641Syongari} 890160641Syongari 891160641Syongaristatic int 892160641Syongaristge_dma_alloc(struct stge_softc *sc) 893160641Syongari{ 894160641Syongari struct stge_dmamap_arg ctx; 895160641Syongari struct stge_txdesc *txd; 896160641Syongari struct stge_rxdesc *rxd; 897160641Syongari int error, i; 898160641Syongari 899160641Syongari /* create parent tag. */ 900160641Syongari error = bus_dma_tag_create(NULL, /* parent */ 901160641Syongari 1, 0, /* algnmnt, boundary */ 902160641Syongari STGE_DMA_MAXADDR, /* lowaddr */ 903160641Syongari BUS_SPACE_MAXADDR, /* highaddr */ 904160641Syongari NULL, NULL, /* filter, filterarg */ 905160641Syongari BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 906160641Syongari 0, /* nsegments */ 907160641Syongari BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 908160641Syongari 0, /* flags */ 909160641Syongari NULL, NULL, /* lockfunc, lockarg */ 910160641Syongari &sc->sc_cdata.stge_parent_tag); 911160641Syongari if (error != 0) { 912160641Syongari device_printf(sc->sc_dev, "failed to create parent DMA tag\n"); 913160641Syongari goto fail; 914160641Syongari } 915160641Syongari /* create tag for Tx ring. */ 916160641Syongari error = bus_dma_tag_create(sc->sc_cdata.stge_parent_tag,/* parent */ 917160641Syongari STGE_RING_ALIGN, 0, /* algnmnt, boundary */ 918160641Syongari BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 919160641Syongari BUS_SPACE_MAXADDR, /* highaddr */ 920160641Syongari NULL, NULL, /* filter, filterarg */ 921160641Syongari STGE_TX_RING_SZ, /* maxsize */ 922160641Syongari 1, /* nsegments */ 923160641Syongari STGE_TX_RING_SZ, /* maxsegsize */ 924160641Syongari 0, /* flags */ 925160641Syongari NULL, NULL, /* lockfunc, lockarg */ 926160641Syongari &sc->sc_cdata.stge_tx_ring_tag); 927160641Syongari if (error != 0) { 928160641Syongari device_printf(sc->sc_dev, 929160641Syongari "failed to allocate Tx ring DMA tag\n"); 930160641Syongari goto fail; 931160641Syongari } 932160641Syongari 933160641Syongari /* create tag for Rx ring. */ 934160641Syongari error = bus_dma_tag_create(sc->sc_cdata.stge_parent_tag,/* parent */ 935160641Syongari STGE_RING_ALIGN, 0, /* algnmnt, boundary */ 936160641Syongari BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 937160641Syongari BUS_SPACE_MAXADDR, /* highaddr */ 938160641Syongari NULL, NULL, /* filter, filterarg */ 939160641Syongari STGE_RX_RING_SZ, /* maxsize */ 940160641Syongari 1, /* nsegments */ 941160641Syongari STGE_RX_RING_SZ, /* maxsegsize */ 942160641Syongari 0, /* flags */ 943160641Syongari NULL, NULL, /* lockfunc, lockarg */ 944160641Syongari &sc->sc_cdata.stge_rx_ring_tag); 945160641Syongari if (error != 0) { 946160641Syongari device_printf(sc->sc_dev, 947160641Syongari "failed to allocate Rx ring DMA tag\n"); 948160641Syongari goto fail; 949160641Syongari } 950160641Syongari 951160641Syongari /* create tag for Tx buffers. */ 952160641Syongari error = bus_dma_tag_create(sc->sc_cdata.stge_parent_tag,/* parent */ 953160641Syongari 1, 0, /* algnmnt, boundary */ 954160641Syongari BUS_SPACE_MAXADDR, /* lowaddr */ 955160641Syongari BUS_SPACE_MAXADDR, /* highaddr */ 956160641Syongari NULL, NULL, /* filter, filterarg */ 957160641Syongari MCLBYTES * STGE_MAXTXSEGS, /* maxsize */ 958160641Syongari STGE_MAXTXSEGS, /* nsegments */ 959160641Syongari MCLBYTES, /* maxsegsize */ 960160641Syongari 0, /* flags */ 961160641Syongari NULL, NULL, /* lockfunc, lockarg */ 962160641Syongari &sc->sc_cdata.stge_tx_tag); 963160641Syongari if (error != 0) { 964160641Syongari device_printf(sc->sc_dev, "failed to allocate Tx DMA tag\n"); 965160641Syongari goto fail; 966160641Syongari } 967160641Syongari 968160641Syongari /* create tag for Rx buffers. */ 969160641Syongari error = bus_dma_tag_create(sc->sc_cdata.stge_parent_tag,/* parent */ 970160641Syongari 1, 0, /* algnmnt, boundary */ 971160641Syongari BUS_SPACE_MAXADDR, /* lowaddr */ 972160641Syongari BUS_SPACE_MAXADDR, /* highaddr */ 973160641Syongari NULL, NULL, /* filter, filterarg */ 974160641Syongari MCLBYTES, /* maxsize */ 975160641Syongari 1, /* nsegments */ 976160641Syongari MCLBYTES, /* maxsegsize */ 977160641Syongari 0, /* flags */ 978160641Syongari NULL, NULL, /* lockfunc, lockarg */ 979160641Syongari &sc->sc_cdata.stge_rx_tag); 980160641Syongari if (error != 0) { 981160641Syongari device_printf(sc->sc_dev, "failed to allocate Rx DMA tag\n"); 982160641Syongari goto fail; 983160641Syongari } 984160641Syongari 985160641Syongari /* allocate DMA'able memory and load the DMA map for Tx ring. */ 986160641Syongari error = bus_dmamem_alloc(sc->sc_cdata.stge_tx_ring_tag, 987160641Syongari (void **)&sc->sc_rdata.stge_tx_ring, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 988160641Syongari &sc->sc_cdata.stge_tx_ring_map); 989160641Syongari if (error != 0) { 990160641Syongari device_printf(sc->sc_dev, 991160641Syongari "failed to allocate DMA'able memory for Tx ring\n"); 992160641Syongari goto fail; 993160641Syongari } 994160641Syongari 995160641Syongari ctx.stge_busaddr = 0; 996160641Syongari error = bus_dmamap_load(sc->sc_cdata.stge_tx_ring_tag, 997160641Syongari sc->sc_cdata.stge_tx_ring_map, sc->sc_rdata.stge_tx_ring, 998160641Syongari STGE_TX_RING_SZ, stge_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 999160641Syongari if (error != 0 || ctx.stge_busaddr == 0) { 1000160641Syongari device_printf(sc->sc_dev, 1001160641Syongari "failed to load DMA'able memory for Tx ring\n"); 1002160641Syongari goto fail; 1003160641Syongari } 1004160641Syongari sc->sc_rdata.stge_tx_ring_paddr = ctx.stge_busaddr; 1005160641Syongari 1006160641Syongari /* allocate DMA'able memory and load the DMA map for Rx ring. */ 1007160641Syongari error = bus_dmamem_alloc(sc->sc_cdata.stge_rx_ring_tag, 1008160641Syongari (void **)&sc->sc_rdata.stge_rx_ring, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1009160641Syongari &sc->sc_cdata.stge_rx_ring_map); 1010160641Syongari if (error != 0) { 1011160641Syongari device_printf(sc->sc_dev, 1012160641Syongari "failed to allocate DMA'able memory for Rx ring\n"); 1013160641Syongari goto fail; 1014160641Syongari } 1015160641Syongari 1016160641Syongari ctx.stge_busaddr = 0; 1017160641Syongari error = bus_dmamap_load(sc->sc_cdata.stge_rx_ring_tag, 1018160641Syongari sc->sc_cdata.stge_rx_ring_map, sc->sc_rdata.stge_rx_ring, 1019160641Syongari STGE_RX_RING_SZ, stge_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 1020160641Syongari if (error != 0 || ctx.stge_busaddr == 0) { 1021160641Syongari device_printf(sc->sc_dev, 1022160641Syongari "failed to load DMA'able memory for Rx ring\n"); 1023160641Syongari goto fail; 1024160641Syongari } 1025160641Syongari sc->sc_rdata.stge_rx_ring_paddr = ctx.stge_busaddr; 1026160641Syongari 1027160641Syongari /* create DMA maps for Tx buffers. */ 1028160641Syongari for (i = 0; i < STGE_TX_RING_CNT; i++) { 1029160641Syongari txd = &sc->sc_cdata.stge_txdesc[i]; 1030160641Syongari txd->tx_m = NULL; 1031160641Syongari txd->tx_dmamap = 0; 1032160641Syongari error = bus_dmamap_create(sc->sc_cdata.stge_tx_tag, 0, 1033160641Syongari &txd->tx_dmamap); 1034160641Syongari if (error != 0) { 1035160641Syongari device_printf(sc->sc_dev, 1036160641Syongari "failed to create Tx dmamap\n"); 1037160641Syongari goto fail; 1038160641Syongari } 1039160641Syongari } 1040160641Syongari /* create DMA maps for Rx buffers. */ 1041160641Syongari if ((error = bus_dmamap_create(sc->sc_cdata.stge_rx_tag, 0, 1042160641Syongari &sc->sc_cdata.stge_rx_sparemap)) != 0) { 1043160641Syongari device_printf(sc->sc_dev, "failed to create spare Rx dmamap\n"); 1044160641Syongari goto fail; 1045160641Syongari } 1046160641Syongari for (i = 0; i < STGE_RX_RING_CNT; i++) { 1047160641Syongari rxd = &sc->sc_cdata.stge_rxdesc[i]; 1048160641Syongari rxd->rx_m = NULL; 1049160641Syongari rxd->rx_dmamap = 0; 1050160641Syongari error = bus_dmamap_create(sc->sc_cdata.stge_rx_tag, 0, 1051160641Syongari &rxd->rx_dmamap); 1052160641Syongari if (error != 0) { 1053160641Syongari device_printf(sc->sc_dev, 1054160641Syongari "failed to create Rx dmamap\n"); 1055160641Syongari goto fail; 1056160641Syongari } 1057160641Syongari } 1058160641Syongari 1059160641Syongarifail: 1060160641Syongari return (error); 1061160641Syongari} 1062160641Syongari 1063160641Syongaristatic void 1064160641Syongaristge_dma_free(struct stge_softc *sc) 1065160641Syongari{ 1066160641Syongari struct stge_txdesc *txd; 1067160641Syongari struct stge_rxdesc *rxd; 1068160641Syongari int i; 1069160641Syongari 1070160641Syongari /* Tx ring */ 1071160641Syongari if (sc->sc_cdata.stge_tx_ring_tag) { 1072160641Syongari if (sc->sc_cdata.stge_tx_ring_map) 1073160641Syongari bus_dmamap_unload(sc->sc_cdata.stge_tx_ring_tag, 1074160641Syongari sc->sc_cdata.stge_tx_ring_map); 1075160641Syongari if (sc->sc_cdata.stge_tx_ring_map && 1076160641Syongari sc->sc_rdata.stge_tx_ring) 1077160641Syongari bus_dmamem_free(sc->sc_cdata.stge_tx_ring_tag, 1078160641Syongari sc->sc_rdata.stge_tx_ring, 1079160641Syongari sc->sc_cdata.stge_tx_ring_map); 1080160641Syongari sc->sc_rdata.stge_tx_ring = NULL; 1081160641Syongari sc->sc_cdata.stge_tx_ring_map = 0; 1082160641Syongari bus_dma_tag_destroy(sc->sc_cdata.stge_tx_ring_tag); 1083160641Syongari sc->sc_cdata.stge_tx_ring_tag = NULL; 1084160641Syongari } 1085160641Syongari /* Rx ring */ 1086160641Syongari if (sc->sc_cdata.stge_rx_ring_tag) { 1087160641Syongari if (sc->sc_cdata.stge_rx_ring_map) 1088160641Syongari bus_dmamap_unload(sc->sc_cdata.stge_rx_ring_tag, 1089160641Syongari sc->sc_cdata.stge_rx_ring_map); 1090160641Syongari if (sc->sc_cdata.stge_rx_ring_map && 1091160641Syongari sc->sc_rdata.stge_rx_ring) 1092160641Syongari bus_dmamem_free(sc->sc_cdata.stge_rx_ring_tag, 1093160641Syongari sc->sc_rdata.stge_rx_ring, 1094160641Syongari sc->sc_cdata.stge_rx_ring_map); 1095160641Syongari sc->sc_rdata.stge_rx_ring = NULL; 1096160641Syongari sc->sc_cdata.stge_rx_ring_map = 0; 1097160641Syongari bus_dma_tag_destroy(sc->sc_cdata.stge_rx_ring_tag); 1098160641Syongari sc->sc_cdata.stge_rx_ring_tag = NULL; 1099160641Syongari } 1100160641Syongari /* Tx buffers */ 1101160641Syongari if (sc->sc_cdata.stge_tx_tag) { 1102160641Syongari for (i = 0; i < STGE_TX_RING_CNT; i++) { 1103160641Syongari txd = &sc->sc_cdata.stge_txdesc[i]; 1104160641Syongari if (txd->tx_dmamap) { 1105160641Syongari bus_dmamap_destroy(sc->sc_cdata.stge_tx_tag, 1106160641Syongari txd->tx_dmamap); 1107160641Syongari txd->tx_dmamap = 0; 1108160641Syongari } 1109160641Syongari } 1110160641Syongari bus_dma_tag_destroy(sc->sc_cdata.stge_tx_tag); 1111160641Syongari sc->sc_cdata.stge_tx_tag = NULL; 1112160641Syongari } 1113160641Syongari /* Rx buffers */ 1114160641Syongari if (sc->sc_cdata.stge_rx_tag) { 1115160641Syongari for (i = 0; i < STGE_RX_RING_CNT; i++) { 1116160641Syongari rxd = &sc->sc_cdata.stge_rxdesc[i]; 1117160641Syongari if (rxd->rx_dmamap) { 1118160641Syongari bus_dmamap_destroy(sc->sc_cdata.stge_rx_tag, 1119160641Syongari rxd->rx_dmamap); 1120160641Syongari rxd->rx_dmamap = 0; 1121160641Syongari } 1122160641Syongari } 1123160641Syongari if (sc->sc_cdata.stge_rx_sparemap) { 1124160641Syongari bus_dmamap_destroy(sc->sc_cdata.stge_rx_tag, 1125160641Syongari sc->sc_cdata.stge_rx_sparemap); 1126160641Syongari sc->sc_cdata.stge_rx_sparemap = 0; 1127160641Syongari } 1128160641Syongari bus_dma_tag_destroy(sc->sc_cdata.stge_rx_tag); 1129160641Syongari sc->sc_cdata.stge_rx_tag = NULL; 1130160641Syongari } 1131160641Syongari 1132160641Syongari if (sc->sc_cdata.stge_parent_tag) { 1133160641Syongari bus_dma_tag_destroy(sc->sc_cdata.stge_parent_tag); 1134160641Syongari sc->sc_cdata.stge_parent_tag = NULL; 1135160641Syongari } 1136160641Syongari} 1137160641Syongari 1138160641Syongari/* 1139160641Syongari * stge_shutdown: 1140160641Syongari * 1141160641Syongari * Make sure the interface is stopped at reboot time. 1142160641Syongari */ 1143160641Syongaristatic void 1144160641Syongaristge_shutdown(device_t dev) 1145160641Syongari{ 1146160641Syongari struct stge_softc *sc; 1147160641Syongari 1148160641Syongari sc = device_get_softc(dev); 1149160641Syongari 1150160641Syongari STGE_LOCK(sc); 1151160641Syongari stge_stop(sc); 1152160641Syongari STGE_UNLOCK(sc); 1153160641Syongari} 1154160641Syongari 1155160641Syongaristatic int 1156160641Syongaristge_suspend(device_t dev) 1157160641Syongari{ 1158160641Syongari struct stge_softc *sc; 1159160641Syongari 1160160641Syongari sc = device_get_softc(dev); 1161160641Syongari 1162160641Syongari STGE_LOCK(sc); 1163160641Syongari stge_stop(sc); 1164160641Syongari sc->sc_suspended = 1; 1165160641Syongari STGE_UNLOCK(sc); 1166160641Syongari 1167160641Syongari return (0); 1168160641Syongari} 1169160641Syongari 1170160641Syongaristatic int 1171160641Syongaristge_resume(device_t dev) 1172160641Syongari{ 1173160641Syongari struct stge_softc *sc; 1174160641Syongari struct ifnet *ifp; 1175160641Syongari 1176160641Syongari sc = device_get_softc(dev); 1177160641Syongari 1178160641Syongari STGE_LOCK(sc); 1179160641Syongari ifp = sc->sc_ifp; 1180160641Syongari if (ifp->if_flags & IFF_UP) 1181160641Syongari stge_init_locked(sc); 1182160641Syongari 1183160641Syongari sc->sc_suspended = 0; 1184160641Syongari STGE_UNLOCK(sc); 1185160641Syongari 1186160641Syongari return (0); 1187160641Syongari} 1188160641Syongari 1189160641Syongaristatic void 1190160641Syongaristge_dma_wait(struct stge_softc *sc) 1191160641Syongari{ 1192160641Syongari int i; 1193160641Syongari 1194160641Syongari for (i = 0; i < STGE_TIMEOUT; i++) { 1195160641Syongari DELAY(2); 1196160641Syongari if ((CSR_READ_4(sc, STGE_DMACtrl) & DMAC_TxDMAInProg) == 0) 1197160641Syongari break; 1198160641Syongari } 1199160641Syongari 1200160641Syongari if (i == STGE_TIMEOUT) 1201160641Syongari device_printf(sc->sc_dev, "DMA wait timed out\n"); 1202160641Syongari} 1203160641Syongari 1204160641Syongaristatic int 1205160641Syongaristge_encap(struct stge_softc *sc, struct mbuf **m_head) 1206160641Syongari{ 1207160641Syongari struct stge_txdesc *txd; 1208160641Syongari struct stge_tfd *tfd; 1209161235Syongari struct mbuf *m; 1210160641Syongari struct m_tag *mtag; 1211160641Syongari bus_dma_segment_t txsegs[STGE_MAXTXSEGS]; 1212160641Syongari int error, i, nsegs, si; 1213160641Syongari uint64_t csum_flags, tfc; 1214160641Syongari 1215160641Syongari STGE_LOCK_ASSERT(sc); 1216160641Syongari 1217160641Syongari if ((txd = STAILQ_FIRST(&sc->sc_cdata.stge_txfreeq)) == NULL) 1218160641Syongari return (ENOBUFS); 1219160641Syongari 1220160641Syongari error = bus_dmamap_load_mbuf_sg(sc->sc_cdata.stge_tx_tag, 1221161235Syongari txd->tx_dmamap, *m_head, txsegs, &nsegs, 0); 1222160641Syongari if (error == EFBIG) { 1223161235Syongari m = m_defrag(*m_head, M_DONTWAIT); 1224161235Syongari if (m == NULL) { 1225161235Syongari m_freem(*m_head); 1226161235Syongari *m_head = NULL; 1227160641Syongari return (ENOMEM); 1228160641Syongari } 1229161235Syongari *m_head = m; 1230160641Syongari error = bus_dmamap_load_mbuf_sg(sc->sc_cdata.stge_tx_tag, 1231161235Syongari txd->tx_dmamap, *m_head, txsegs, &nsegs, 0); 1232160641Syongari if (error != 0) { 1233161235Syongari m_freem(*m_head); 1234161235Syongari *m_head = NULL; 1235160641Syongari return (error); 1236160641Syongari } 1237160641Syongari } else if (error != 0) 1238160641Syongari return (error); 1239160641Syongari if (nsegs == 0) { 1240161235Syongari m_freem(*m_head); 1241161235Syongari *m_head = NULL; 1242160641Syongari return (EIO); 1243160641Syongari } 1244160641Syongari 1245161235Syongari m = *m_head; 1246160641Syongari csum_flags = 0; 1247160641Syongari if ((m->m_pkthdr.csum_flags & STGE_CSUM_FEATURES) != 0) { 1248160641Syongari if (m->m_pkthdr.csum_flags & CSUM_IP) 1249160641Syongari csum_flags |= TFD_IPChecksumEnable; 1250160641Syongari if (m->m_pkthdr.csum_flags & CSUM_TCP) 1251160641Syongari csum_flags |= TFD_TCPChecksumEnable; 1252160641Syongari else if (m->m_pkthdr.csum_flags & CSUM_UDP) 1253160641Syongari csum_flags |= TFD_UDPChecksumEnable; 1254160641Syongari } 1255160641Syongari 1256160641Syongari si = sc->sc_cdata.stge_tx_prod; 1257160641Syongari tfd = &sc->sc_rdata.stge_tx_ring[si]; 1258160641Syongari for (i = 0; i < nsegs; i++) 1259160641Syongari tfd->tfd_frags[i].frag_word0 = 1260160641Syongari htole64(FRAG_ADDR(txsegs[i].ds_addr) | 1261160641Syongari FRAG_LEN(txsegs[i].ds_len)); 1262160641Syongari sc->sc_cdata.stge_tx_cnt++; 1263160641Syongari 1264160641Syongari tfc = TFD_FrameId(si) | TFD_WordAlign(TFD_WordAlign_disable) | 1265160641Syongari TFD_FragCount(nsegs) | csum_flags; 1266160641Syongari if (sc->sc_cdata.stge_tx_cnt >= STGE_TX_HIWAT) 1267160641Syongari tfc |= TFD_TxDMAIndicate; 1268160641Syongari 1269160641Syongari /* Update producer index. */ 1270160641Syongari sc->sc_cdata.stge_tx_prod = (si + 1) % STGE_TX_RING_CNT; 1271160641Syongari 1272160641Syongari /* Check if we have a VLAN tag to insert. */ 1273160641Syongari mtag = VLAN_OUTPUT_TAG(sc->sc_ifp, m); 1274160641Syongari if (mtag != NULL) 1275160641Syongari tfc |= TFD_VLANTagInsert | TFD_VID(VLAN_TAG_VALUE(mtag)); 1276160641Syongari tfd->tfd_control = htole64(tfc); 1277160641Syongari 1278160641Syongari /* Update Tx Queue. */ 1279160641Syongari STAILQ_REMOVE_HEAD(&sc->sc_cdata.stge_txfreeq, tx_q); 1280160641Syongari STAILQ_INSERT_TAIL(&sc->sc_cdata.stge_txbusyq, txd, tx_q); 1281160641Syongari txd->tx_m = m; 1282160641Syongari 1283160641Syongari /* Sync descriptors. */ 1284160641Syongari bus_dmamap_sync(sc->sc_cdata.stge_tx_tag, txd->tx_dmamap, 1285160641Syongari BUS_DMASYNC_PREWRITE); 1286160641Syongari bus_dmamap_sync(sc->sc_cdata.stge_tx_ring_tag, 1287160641Syongari sc->sc_cdata.stge_tx_ring_map, 1288160641Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1289160641Syongari 1290160641Syongari return (0); 1291160641Syongari} 1292160641Syongari 1293160641Syongari/* 1294160641Syongari * stge_start: [ifnet interface function] 1295160641Syongari * 1296160641Syongari * Start packet transmission on the interface. 1297160641Syongari */ 1298160641Syongaristatic void 1299160641Syongaristge_start(struct ifnet *ifp) 1300160641Syongari{ 1301160641Syongari struct stge_softc *sc; 1302160641Syongari 1303160641Syongari sc = ifp->if_softc; 1304160641Syongari STGE_LOCK(sc); 1305160641Syongari stge_start_locked(ifp); 1306160641Syongari STGE_UNLOCK(sc); 1307160641Syongari} 1308160641Syongari 1309160641Syongaristatic void 1310160641Syongaristge_start_locked(struct ifnet *ifp) 1311160641Syongari{ 1312160641Syongari struct stge_softc *sc; 1313160641Syongari struct mbuf *m_head; 1314160641Syongari int enq; 1315160641Syongari 1316160641Syongari sc = ifp->if_softc; 1317160641Syongari 1318160641Syongari STGE_LOCK_ASSERT(sc); 1319160641Syongari 1320160641Syongari if ((ifp->if_drv_flags & (IFF_DRV_RUNNING|IFF_DRV_OACTIVE)) != 1321160641Syongari IFF_DRV_RUNNING) 1322160641Syongari return; 1323160641Syongari 1324160641Syongari for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) { 1325160641Syongari if (sc->sc_cdata.stge_tx_cnt >= STGE_TX_HIWAT) { 1326160641Syongari ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1327160641Syongari break; 1328160641Syongari } 1329160641Syongari 1330160641Syongari IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1331160641Syongari if (m_head == NULL) 1332160641Syongari break; 1333160641Syongari /* 1334160641Syongari * Pack the data into the transmit ring. If we 1335160641Syongari * don't have room, set the OACTIVE flag and wait 1336160641Syongari * for the NIC to drain the ring. 1337160641Syongari */ 1338160641Syongari if (stge_encap(sc, &m_head)) { 1339160641Syongari if (m_head == NULL) 1340160641Syongari break; 1341160641Syongari IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1342160641Syongari ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1343160641Syongari break; 1344160641Syongari } 1345160641Syongari 1346160641Syongari enq++; 1347160641Syongari /* 1348160641Syongari * If there's a BPF listener, bounce a copy of this frame 1349160641Syongari * to him. 1350160641Syongari */ 1351160641Syongari BPF_MTAP(ifp, m_head); 1352160641Syongari } 1353160641Syongari 1354160641Syongari if (enq > 0) { 1355160641Syongari /* Transmit */ 1356160641Syongari CSR_WRITE_4(sc, STGE_DMACtrl, DMAC_TxDMAPollNow); 1357160641Syongari 1358160641Syongari /* Set a timeout in case the chip goes out to lunch. */ 1359160641Syongari ifp->if_timer = 5; 1360160641Syongari } 1361160641Syongari} 1362160641Syongari 1363160641Syongari/* 1364160641Syongari * stge_watchdog: [ifnet interface function] 1365160641Syongari * 1366160641Syongari * Watchdog timer handler. 1367160641Syongari */ 1368160641Syongaristatic void 1369160641Syongaristge_watchdog(struct ifnet *ifp) 1370160641Syongari{ 1371160641Syongari struct stge_softc *sc; 1372160641Syongari 1373160641Syongari sc = ifp->if_softc; 1374160641Syongari 1375160641Syongari STGE_LOCK(sc); 1376160641Syongari if_printf(sc->sc_ifp, "device timeout\n"); 1377160641Syongari ifp->if_oerrors++; 1378160641Syongari stge_init_locked(sc); 1379160641Syongari STGE_UNLOCK(sc); 1380160641Syongari} 1381160641Syongari 1382160641Syongari/* 1383160641Syongari * stge_ioctl: [ifnet interface function] 1384160641Syongari * 1385160641Syongari * Handle control requests from the operator. 1386160641Syongari */ 1387160641Syongaristatic int 1388160641Syongaristge_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1389160641Syongari{ 1390160641Syongari struct stge_softc *sc; 1391160641Syongari struct ifreq *ifr; 1392160641Syongari struct mii_data *mii; 1393160641Syongari int error, mask; 1394160641Syongari 1395160641Syongari sc = ifp->if_softc; 1396160641Syongari ifr = (struct ifreq *)data; 1397160641Syongari error = 0; 1398160641Syongari switch (cmd) { 1399160641Syongari case SIOCSIFMTU: 1400160641Syongari if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > STGE_JUMBO_MTU) 1401160641Syongari error = EINVAL; 1402160641Syongari else if (ifp->if_mtu != ifr->ifr_mtu) { 1403160641Syongari ifp->if_mtu = ifr->ifr_mtu; 1404160641Syongari STGE_LOCK(sc); 1405160641Syongari stge_init_locked(sc); 1406160641Syongari STGE_UNLOCK(sc); 1407160641Syongari } 1408160641Syongari break; 1409160641Syongari case SIOCSIFFLAGS: 1410160641Syongari STGE_LOCK(sc); 1411160641Syongari if ((ifp->if_flags & IFF_UP) != 0) { 1412160641Syongari if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1413160641Syongari if (((ifp->if_flags ^ sc->sc_if_flags) 1414160641Syongari & IFF_PROMISC) != 0) 1415160641Syongari stge_set_filter(sc); 1416160641Syongari } else { 1417160641Syongari if (sc->sc_detach == 0) 1418160641Syongari stge_init_locked(sc); 1419160641Syongari } 1420160641Syongari } else { 1421160641Syongari if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1422160641Syongari stge_stop(sc); 1423160641Syongari } 1424160641Syongari sc->sc_if_flags = ifp->if_flags; 1425160641Syongari STGE_UNLOCK(sc); 1426160641Syongari break; 1427160641Syongari case SIOCADDMULTI: 1428160641Syongari case SIOCDELMULTI: 1429160641Syongari STGE_LOCK(sc); 1430160641Syongari if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1431160641Syongari stge_set_multi(sc); 1432160641Syongari STGE_UNLOCK(sc); 1433160641Syongari break; 1434160641Syongari case SIOCSIFMEDIA: 1435160641Syongari case SIOCGIFMEDIA: 1436160641Syongari mii = device_get_softc(sc->sc_miibus); 1437160641Syongari error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1438160641Syongari break; 1439160641Syongari case SIOCSIFCAP: 1440160641Syongari mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1441160641Syongari#ifdef DEVICE_POLLING 1442160641Syongari if ((mask & IFCAP_POLLING) != 0) { 1443160641Syongari if ((ifr->ifr_reqcap & IFCAP_POLLING) != 0) { 1444160641Syongari error = ether_poll_register(stge_poll, ifp); 1445160641Syongari if (error != 0) 1446160641Syongari break; 1447160641Syongari STGE_LOCK(sc); 1448160641Syongari CSR_WRITE_2(sc, STGE_IntEnable, 0); 1449160641Syongari ifp->if_capenable |= IFCAP_POLLING; 1450160641Syongari STGE_UNLOCK(sc); 1451160641Syongari } else { 1452160641Syongari error = ether_poll_deregister(ifp); 1453160641Syongari if (error != 0) 1454160641Syongari break; 1455160641Syongari STGE_LOCK(sc); 1456160641Syongari CSR_WRITE_2(sc, STGE_IntEnable, 1457160641Syongari sc->sc_IntEnable); 1458160641Syongari ifp->if_capenable &= ~IFCAP_POLLING; 1459160641Syongari STGE_UNLOCK(sc); 1460160641Syongari } 1461160641Syongari } 1462160641Syongari#endif 1463160641Syongari if ((mask & IFCAP_HWCSUM) != 0) { 1464160641Syongari ifp->if_capenable ^= IFCAP_HWCSUM; 1465160641Syongari if ((IFCAP_HWCSUM & ifp->if_capenable) != 0 && 1466160641Syongari (IFCAP_HWCSUM & ifp->if_capabilities) != 0) 1467160641Syongari ifp->if_hwassist = STGE_CSUM_FEATURES; 1468160641Syongari else 1469160641Syongari ifp->if_hwassist = 0; 1470160641Syongari } 1471160641Syongari if ((mask & IFCAP_VLAN_HWTAGGING) != 0) { 1472160641Syongari ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1473160641Syongari if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1474160641Syongari STGE_LOCK(sc); 1475160641Syongari stge_vlan_setup(sc); 1476160641Syongari STGE_UNLOCK(sc); 1477160641Syongari } 1478160641Syongari } 1479160641Syongari VLAN_CAPABILITIES(ifp); 1480160641Syongari break; 1481160641Syongari default: 1482160641Syongari error = ether_ioctl(ifp, cmd, data); 1483160641Syongari break; 1484160641Syongari } 1485160641Syongari 1486160641Syongari return (error); 1487160641Syongari} 1488160641Syongari 1489160641Syongaristatic void 1490160641Syongaristge_link_task(void *arg, int pending) 1491160641Syongari{ 1492160641Syongari struct stge_softc *sc; 1493160641Syongari uint32_t v, ac; 1494160641Syongari int i; 1495160641Syongari 1496160641Syongari sc = (struct stge_softc *)arg; 1497160641Syongari STGE_LOCK(sc); 1498160641Syongari /* 1499160641Syongari * Update STGE_MACCtrl register depending on link status. 1500160641Syongari * (duplex, flow control etc) 1501160641Syongari */ 1502160641Syongari v = ac = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 1503160641Syongari v &= ~(MC_DuplexSelect|MC_RxFlowControlEnable|MC_TxFlowControlEnable); 1504160641Syongari v |= sc->sc_MACCtrl; 1505160641Syongari CSR_WRITE_4(sc, STGE_MACCtrl, v); 1506160641Syongari if (((ac ^ sc->sc_MACCtrl) & MC_DuplexSelect) != 0) { 1507160641Syongari /* Duplex setting changed, reset Tx/Rx functions. */ 1508160641Syongari ac = CSR_READ_4(sc, STGE_AsicCtrl); 1509160641Syongari ac |= AC_TxReset | AC_RxReset; 1510160641Syongari CSR_WRITE_4(sc, STGE_AsicCtrl, ac); 1511160641Syongari for (i = 0; i < STGE_TIMEOUT; i++) { 1512160641Syongari DELAY(100); 1513160641Syongari if ((CSR_READ_4(sc, STGE_AsicCtrl) & AC_ResetBusy) == 0) 1514160641Syongari break; 1515160641Syongari } 1516160641Syongari if (i == STGE_TIMEOUT) 1517160641Syongari device_printf(sc->sc_dev, "reset failed to complete\n"); 1518160641Syongari } 1519160641Syongari STGE_UNLOCK(sc); 1520160641Syongari} 1521160641Syongari 1522160641Syongaristatic __inline int 1523160641Syongaristge_tx_error(struct stge_softc *sc) 1524160641Syongari{ 1525160641Syongari uint32_t txstat; 1526160641Syongari int error; 1527160641Syongari 1528160641Syongari for (error = 0;;) { 1529160641Syongari txstat = CSR_READ_4(sc, STGE_TxStatus); 1530160641Syongari if ((txstat & TS_TxComplete) == 0) 1531160641Syongari break; 1532160641Syongari /* Tx underrun */ 1533160641Syongari if ((txstat & TS_TxUnderrun) != 0) { 1534160641Syongari /* 1535160641Syongari * XXX 1536160641Syongari * There should be a more better way to recover 1537160641Syongari * from Tx underrun instead of a full reset. 1538160641Syongari */ 1539160641Syongari if (sc->sc_nerr++ < STGE_MAXERR) 1540160641Syongari device_printf(sc->sc_dev, "Tx underrun, " 1541160641Syongari "resetting...\n"); 1542160641Syongari if (sc->sc_nerr == STGE_MAXERR) 1543160641Syongari device_printf(sc->sc_dev, "too many errors; " 1544160641Syongari "not reporting any more\n"); 1545160641Syongari error = -1; 1546160641Syongari break; 1547160641Syongari } 1548160641Syongari /* Maximum/Late collisions, Re-enable Tx MAC. */ 1549160641Syongari if ((txstat & (TS_MaxCollisions|TS_LateCollision)) != 0) 1550160641Syongari CSR_WRITE_4(sc, STGE_MACCtrl, 1551160641Syongari (CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK) | 1552160641Syongari MC_TxEnable); 1553160641Syongari } 1554160641Syongari 1555160641Syongari return (error); 1556160641Syongari} 1557160641Syongari 1558160641Syongari/* 1559160641Syongari * stge_intr: 1560160641Syongari * 1561160641Syongari * Interrupt service routine. 1562160641Syongari */ 1563160641Syongaristatic void 1564160641Syongaristge_intr(void *arg) 1565160641Syongari{ 1566160641Syongari struct stge_softc *sc; 1567160641Syongari struct ifnet *ifp; 1568160641Syongari int reinit; 1569160641Syongari uint16_t status; 1570160641Syongari 1571160641Syongari sc = (struct stge_softc *)arg; 1572160641Syongari ifp = sc->sc_ifp; 1573160641Syongari 1574160641Syongari STGE_LOCK(sc); 1575160641Syongari 1576160641Syongari#ifdef DEVICE_POLLING 1577160641Syongari if ((ifp->if_capenable & IFCAP_POLLING) != 0) 1578160641Syongari goto done_locked; 1579160641Syongari#endif 1580160641Syongari status = CSR_READ_2(sc, STGE_IntStatus); 1581160641Syongari if (sc->sc_suspended || (status & IS_InterruptStatus) == 0) 1582160641Syongari goto done_locked; 1583160641Syongari 1584160641Syongari /* Disable interrupts. */ 1585160641Syongari for (reinit = 0;;) { 1586160641Syongari status = CSR_READ_2(sc, STGE_IntStatusAck); 1587160641Syongari status &= sc->sc_IntEnable; 1588160641Syongari if (status == 0) 1589160641Syongari break; 1590160641Syongari /* Host interface errors. */ 1591160641Syongari if ((status & IS_HostError) != 0) { 1592160641Syongari device_printf(sc->sc_dev, 1593160641Syongari "Host interface error, resetting...\n"); 1594160641Syongari reinit = 1; 1595160641Syongari goto force_init; 1596160641Syongari } 1597160641Syongari 1598160641Syongari /* Receive interrupts. */ 1599160641Syongari if ((status & IS_RxDMAComplete) != 0) { 1600160641Syongari stge_rxeof(sc); 1601160641Syongari if ((status & IS_RFDListEnd) != 0) 1602160641Syongari CSR_WRITE_4(sc, STGE_DMACtrl, 1603160641Syongari DMAC_RxDMAPollNow); 1604160641Syongari } 1605160641Syongari 1606160641Syongari /* Transmit interrupts. */ 1607160641Syongari if ((status & (IS_TxDMAComplete | IS_TxComplete)) != 0) 1608160641Syongari stge_txeof(sc); 1609160641Syongari 1610160641Syongari /* Transmission errors.*/ 1611160641Syongari if ((status & IS_TxComplete) != 0) { 1612160641Syongari if ((reinit = stge_tx_error(sc)) != 0) 1613160641Syongari break; 1614160641Syongari } 1615160641Syongari } 1616160641Syongari 1617160641Syongariforce_init: 1618160641Syongari if (reinit != 0) 1619160641Syongari stge_init_locked(sc); 1620160641Syongari 1621160641Syongari /* Re-enable interrupts. */ 1622160641Syongari CSR_WRITE_2(sc, STGE_IntEnable, sc->sc_IntEnable); 1623160641Syongari 1624160641Syongari /* Try to get more packets going. */ 1625160641Syongari if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1626160641Syongari stge_start_locked(ifp); 1627160641Syongari 1628160641Syongaridone_locked: 1629160641Syongari STGE_UNLOCK(sc); 1630160641Syongari} 1631160641Syongari 1632160641Syongari/* 1633160641Syongari * stge_txeof: 1634160641Syongari * 1635160641Syongari * Helper; handle transmit interrupts. 1636160641Syongari */ 1637160641Syongaristatic void 1638160641Syongaristge_txeof(struct stge_softc *sc) 1639160641Syongari{ 1640160641Syongari struct ifnet *ifp; 1641160641Syongari struct stge_txdesc *txd; 1642160641Syongari uint64_t control; 1643160641Syongari int cons; 1644160641Syongari 1645160641Syongari STGE_LOCK_ASSERT(sc); 1646160641Syongari 1647160641Syongari ifp = sc->sc_ifp; 1648160641Syongari 1649160641Syongari txd = STAILQ_FIRST(&sc->sc_cdata.stge_txbusyq); 1650160641Syongari if (txd == NULL) 1651160641Syongari return; 1652160641Syongari bus_dmamap_sync(sc->sc_cdata.stge_tx_ring_tag, 1653160641Syongari sc->sc_cdata.stge_tx_ring_map, BUS_DMASYNC_POSTREAD); 1654160641Syongari 1655160641Syongari /* 1656160641Syongari * Go through our Tx list and free mbufs for those 1657160641Syongari * frames which have been transmitted. 1658160641Syongari */ 1659160641Syongari for (cons = sc->sc_cdata.stge_tx_cons;; 1660160641Syongari cons = (cons + 1) % STGE_TX_RING_CNT) { 1661160641Syongari if (sc->sc_cdata.stge_tx_cnt <= 0) 1662160641Syongari break; 1663160641Syongari control = le64toh(sc->sc_rdata.stge_tx_ring[cons].tfd_control); 1664160641Syongari if ((control & TFD_TFDDone) == 0) 1665160641Syongari break; 1666160641Syongari sc->sc_cdata.stge_tx_cnt--; 1667160641Syongari ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1668160641Syongari 1669160641Syongari bus_dmamap_sync(sc->sc_cdata.stge_tx_tag, txd->tx_dmamap, 1670160641Syongari BUS_DMASYNC_POSTWRITE); 1671160641Syongari bus_dmamap_unload(sc->sc_cdata.stge_tx_tag, txd->tx_dmamap); 1672160641Syongari 1673160641Syongari /* Output counter is updated with statistics register */ 1674160641Syongari m_freem(txd->tx_m); 1675160641Syongari txd->tx_m = NULL; 1676160641Syongari STAILQ_REMOVE_HEAD(&sc->sc_cdata.stge_txbusyq, tx_q); 1677160641Syongari STAILQ_INSERT_TAIL(&sc->sc_cdata.stge_txfreeq, txd, tx_q); 1678160641Syongari txd = STAILQ_FIRST(&sc->sc_cdata.stge_txbusyq); 1679160641Syongari } 1680160641Syongari sc->sc_cdata.stge_tx_cons = cons; 1681160641Syongari if (sc->sc_cdata.stge_tx_cnt == 0) 1682160641Syongari ifp->if_timer = 0; 1683160641Syongari 1684160641Syongari bus_dmamap_sync(sc->sc_cdata.stge_tx_ring_tag, 1685160641Syongari sc->sc_cdata.stge_tx_ring_map, 1686160641Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1687160641Syongari} 1688160641Syongari 1689160641Syongaristatic __inline void 1690160641Syongaristge_discard_rxbuf(struct stge_softc *sc, int idx) 1691160641Syongari{ 1692160641Syongari struct stge_rfd *rfd; 1693160641Syongari 1694160641Syongari rfd = &sc->sc_rdata.stge_rx_ring[idx]; 1695160641Syongari rfd->rfd_status = 0; 1696160641Syongari} 1697160641Syongari 1698160641Syongari#ifndef __NO_STRICT_ALIGNMENT 1699160641Syongari/* 1700160641Syongari * It seems that TC9021's DMA engine has alignment restrictions in 1701160641Syongari * DMA scatter operations. The first DMA segment has no address 1702160641Syongari * alignment restrictins but the rest should be aligned on 4(?) bytes 1703160641Syongari * boundary. Otherwise it would corrupt random memory. Since we don't 1704160641Syongari * know which one is used for the first segment in advance we simply 1705160641Syongari * don't align at all. 1706160641Syongari * To avoid copying over an entire frame to align, we allocate a new 1707160641Syongari * mbuf and copy ethernet header to the new mbuf. The new mbuf is 1708160641Syongari * prepended into the existing mbuf chain. 1709160641Syongari */ 1710160641Syongaristatic __inline struct mbuf * 1711160641Syongaristge_fixup_rx(struct stge_softc *sc, struct mbuf *m) 1712160641Syongari{ 1713160641Syongari struct mbuf *n; 1714160641Syongari 1715160641Syongari n = NULL; 1716160641Syongari if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 1717160641Syongari bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 1718160641Syongari m->m_data += ETHER_HDR_LEN; 1719160641Syongari n = m; 1720160641Syongari } else { 1721160641Syongari MGETHDR(n, M_DONTWAIT, MT_DATA); 1722160641Syongari if (n != NULL) { 1723160641Syongari bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 1724160641Syongari m->m_data += ETHER_HDR_LEN; 1725160641Syongari m->m_len -= ETHER_HDR_LEN; 1726160641Syongari n->m_len = ETHER_HDR_LEN; 1727160641Syongari M_MOVE_PKTHDR(n, m); 1728160641Syongari n->m_next = m; 1729160641Syongari } else 1730160641Syongari m_freem(m); 1731160641Syongari } 1732160641Syongari 1733160641Syongari return (n); 1734160641Syongari} 1735160641Syongari#endif 1736160641Syongari 1737160641Syongari/* 1738160641Syongari * stge_rxeof: 1739160641Syongari * 1740160641Syongari * Helper; handle receive interrupts. 1741160641Syongari */ 1742160641Syongaristatic void 1743160641Syongaristge_rxeof(struct stge_softc *sc) 1744160641Syongari{ 1745160641Syongari struct ifnet *ifp; 1746160641Syongari struct stge_rxdesc *rxd; 1747160641Syongari struct mbuf *mp, *m; 1748160641Syongari uint64_t status64; 1749160641Syongari uint32_t status; 1750160641Syongari int cons, prog; 1751160641Syongari 1752160641Syongari STGE_LOCK_ASSERT(sc); 1753160641Syongari 1754160641Syongari ifp = sc->sc_ifp; 1755160641Syongari 1756160641Syongari bus_dmamap_sync(sc->sc_cdata.stge_rx_ring_tag, 1757160641Syongari sc->sc_cdata.stge_rx_ring_map, BUS_DMASYNC_POSTREAD); 1758160641Syongari 1759160641Syongari prog = 0; 1760160641Syongari for (cons = sc->sc_cdata.stge_rx_cons; prog < STGE_RX_RING_CNT; 1761160641Syongari prog++, cons = (cons + 1) % STGE_RX_RING_CNT) { 1762160641Syongari status64 = le64toh(sc->sc_rdata.stge_rx_ring[cons].rfd_status); 1763160641Syongari status = RFD_RxStatus(status64); 1764160641Syongari if ((status & RFD_RFDDone) == 0) 1765160641Syongari break; 1766160641Syongari#ifdef DEVICE_POLLING 1767160641Syongari if (ifp->if_capenable & IFCAP_POLLING) { 1768160641Syongari if (sc->sc_cdata.stge_rxcycles <= 0) 1769160641Syongari break; 1770160641Syongari sc->sc_cdata.stge_rxcycles--; 1771160641Syongari } 1772160641Syongari#endif 1773160641Syongari prog++; 1774160641Syongari rxd = &sc->sc_cdata.stge_rxdesc[cons]; 1775160641Syongari mp = rxd->rx_m; 1776160641Syongari 1777160641Syongari /* 1778160641Syongari * If the packet had an error, drop it. Note we count 1779160641Syongari * the error later in the periodic stats update. 1780160641Syongari */ 1781160641Syongari if ((status & RFD_FrameEnd) != 0 && (status & 1782160641Syongari (RFD_RxFIFOOverrun | RFD_RxRuntFrame | 1783160641Syongari RFD_RxAlignmentError | RFD_RxFCSError | 1784160641Syongari RFD_RxLengthError)) != 0) { 1785160641Syongari stge_discard_rxbuf(sc, cons); 1786160641Syongari if (sc->sc_cdata.stge_rxhead != NULL) { 1787160641Syongari m_freem(sc->sc_cdata.stge_rxhead); 1788160641Syongari STGE_RXCHAIN_RESET(sc); 1789160641Syongari } 1790160641Syongari continue; 1791160641Syongari } 1792160641Syongari /* 1793160641Syongari * Add a new receive buffer to the ring. 1794160641Syongari */ 1795160641Syongari if (stge_newbuf(sc, cons) != 0) { 1796160641Syongari ifp->if_iqdrops++; 1797160641Syongari stge_discard_rxbuf(sc, cons); 1798160641Syongari if (sc->sc_cdata.stge_rxhead != NULL) { 1799160641Syongari m_freem(sc->sc_cdata.stge_rxhead); 1800160641Syongari STGE_RXCHAIN_RESET(sc); 1801160641Syongari } 1802160641Syongari continue; 1803160641Syongari } 1804160641Syongari 1805160641Syongari if ((status & RFD_FrameEnd) != 0) 1806160641Syongari mp->m_len = RFD_RxDMAFrameLen(status) - 1807160641Syongari sc->sc_cdata.stge_rxlen; 1808160641Syongari sc->sc_cdata.stge_rxlen += mp->m_len; 1809160641Syongari 1810160641Syongari /* Chain mbufs. */ 1811160641Syongari if (sc->sc_cdata.stge_rxhead == NULL) { 1812160641Syongari sc->sc_cdata.stge_rxhead = mp; 1813160641Syongari sc->sc_cdata.stge_rxtail = mp; 1814160641Syongari } else { 1815160641Syongari mp->m_flags &= ~M_PKTHDR; 1816160641Syongari sc->sc_cdata.stge_rxtail->m_next = mp; 1817160641Syongari sc->sc_cdata.stge_rxtail = mp; 1818160641Syongari } 1819160641Syongari 1820160641Syongari if ((status & RFD_FrameEnd) != 0) { 1821160641Syongari m = sc->sc_cdata.stge_rxhead; 1822160641Syongari m->m_pkthdr.rcvif = ifp; 1823160641Syongari m->m_pkthdr.len = sc->sc_cdata.stge_rxlen; 1824160641Syongari 1825160641Syongari if (m->m_pkthdr.len > sc->sc_if_framesize) { 1826160641Syongari m_freem(m); 1827160641Syongari STGE_RXCHAIN_RESET(sc); 1828160641Syongari continue; 1829160641Syongari } 1830160641Syongari /* 1831160641Syongari * Set the incoming checksum information for 1832160641Syongari * the packet. 1833160641Syongari */ 1834160641Syongari if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) { 1835160641Syongari if ((status & RFD_IPDetected) != 0) { 1836160641Syongari m->m_pkthdr.csum_flags |= 1837160641Syongari CSUM_IP_CHECKED; 1838160641Syongari if ((status & RFD_IPError) == 0) 1839160641Syongari m->m_pkthdr.csum_flags |= 1840160641Syongari CSUM_IP_VALID; 1841160641Syongari } 1842160641Syongari if (((status & RFD_TCPDetected) != 0 && 1843160641Syongari (status & RFD_TCPError) == 0) || 1844160641Syongari ((status & RFD_UDPDetected) != 0 && 1845160641Syongari (status & RFD_UDPError) == 0)) { 1846160641Syongari m->m_pkthdr.csum_flags |= 1847160641Syongari (CSUM_DATA_VALID | CSUM_PSEUDO_HDR); 1848160641Syongari m->m_pkthdr.csum_data = 0xffff; 1849160641Syongari } 1850160641Syongari } 1851160641Syongari 1852160641Syongari#ifndef __NO_STRICT_ALIGNMENT 1853160641Syongari if (sc->sc_if_framesize > (MCLBYTES - ETHER_ALIGN)) { 1854160641Syongari if ((m = stge_fixup_rx(sc, m)) == NULL) { 1855160641Syongari STGE_RXCHAIN_RESET(sc); 1856160641Syongari continue; 1857160641Syongari } 1858160641Syongari } 1859160641Syongari#endif 1860160641Syongari /* Check for VLAN tagged packets. */ 1861160641Syongari if ((status & RFD_VLANDetected) != 0 && 1862160641Syongari (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 1863160641Syongari VLAN_INPUT_TAG(ifp, m, RFD_TCI(status64)); 1864160641Syongari 1865160641Syongari STGE_UNLOCK(sc); 1866160641Syongari /* Pass it on. */ 1867160641Syongari (*ifp->if_input)(ifp, m); 1868160641Syongari STGE_LOCK(sc); 1869160641Syongari 1870160641Syongari STGE_RXCHAIN_RESET(sc); 1871160641Syongari } 1872160641Syongari } 1873160641Syongari 1874160641Syongari if (prog > 0) { 1875160641Syongari /* Update the consumer index. */ 1876160641Syongari sc->sc_cdata.stge_rx_cons = cons; 1877160641Syongari bus_dmamap_sync(sc->sc_cdata.stge_rx_ring_tag, 1878160641Syongari sc->sc_cdata.stge_rx_ring_map, 1879160641Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1880160641Syongari } 1881160641Syongari} 1882160641Syongari 1883160641Syongari#ifdef DEVICE_POLLING 1884160641Syongaristatic void 1885160641Syongaristge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1886160641Syongari{ 1887160641Syongari struct stge_softc *sc; 1888160641Syongari uint16_t status; 1889160641Syongari 1890160641Syongari sc = ifp->if_softc; 1891160641Syongari STGE_LOCK(sc); 1892160641Syongari if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1893160641Syongari STGE_UNLOCK(sc); 1894160641Syongari return; 1895160641Syongari } 1896160641Syongari 1897160641Syongari sc->sc_cdata.stge_rxcycles = count; 1898160641Syongari stge_rxeof(sc); 1899160641Syongari stge_txeof(sc); 1900160641Syongari 1901160641Syongari if (cmd == POLL_AND_CHECK_STATUS) { 1902160641Syongari status = CSR_READ_2(sc, STGE_IntStatus); 1903160641Syongari status &= sc->sc_IntEnable; 1904160641Syongari if (status != 0) { 1905160641Syongari if ((status & IS_HostError) != 0) { 1906160641Syongari device_printf(sc->sc_dev, 1907160641Syongari "Host interface error, resetting...\n"); 1908160641Syongari stge_init_locked(sc); 1909160641Syongari } 1910160641Syongari if ((status & IS_TxComplete) != 0) { 1911160641Syongari if (stge_tx_error(sc) != 0) 1912160641Syongari stge_init_locked(sc); 1913160641Syongari } 1914160641Syongari } 1915160641Syongari 1916160641Syongari } 1917160641Syongari 1918160641Syongari if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1919160641Syongari stge_start_locked(ifp); 1920160641Syongari 1921160641Syongari STGE_UNLOCK(sc); 1922160641Syongari} 1923160641Syongari#endif /* DEVICE_POLLING */ 1924160641Syongari 1925160641Syongari/* 1926160641Syongari * stge_tick: 1927160641Syongari * 1928160641Syongari * One second timer, used to tick the MII. 1929160641Syongari */ 1930160641Syongaristatic void 1931160641Syongaristge_tick(void *arg) 1932160641Syongari{ 1933160641Syongari struct stge_softc *sc; 1934160641Syongari struct mii_data *mii; 1935160641Syongari 1936160641Syongari sc = (struct stge_softc *)arg; 1937160641Syongari 1938160641Syongari STGE_LOCK_ASSERT(sc); 1939160641Syongari 1940160641Syongari mii = device_get_softc(sc->sc_miibus); 1941160641Syongari mii_tick(mii); 1942160641Syongari 1943160641Syongari /* Update statistics counters. */ 1944160641Syongari stge_stats_update(sc); 1945160641Syongari 1946160641Syongari /* 1947160641Syongari * Relcaim any pending Tx descriptors to release mbufs in a 1948160641Syongari * timely manner as we don't generate Tx completion interrupts 1949160641Syongari * for every frame. This limits the delay to a maximum of one 1950160641Syongari * second. 1951160641Syongari */ 1952160641Syongari if (sc->sc_cdata.stge_tx_cnt != 0) 1953160641Syongari stge_txeof(sc); 1954160641Syongari 1955160641Syongari callout_reset(&sc->sc_tick_ch, hz, stge_tick, sc); 1956160641Syongari} 1957160641Syongari 1958160641Syongari/* 1959160641Syongari * stge_stats_update: 1960160641Syongari * 1961160641Syongari * Read the TC9021 statistics counters. 1962160641Syongari */ 1963160641Syongaristatic void 1964160641Syongaristge_stats_update(struct stge_softc *sc) 1965160641Syongari{ 1966160641Syongari struct ifnet *ifp; 1967160641Syongari 1968160641Syongari STGE_LOCK_ASSERT(sc); 1969160641Syongari 1970160641Syongari ifp = sc->sc_ifp; 1971160641Syongari 1972160641Syongari CSR_READ_4(sc,STGE_OctetRcvOk); 1973160641Syongari 1974160641Syongari ifp->if_ipackets += CSR_READ_4(sc, STGE_FramesRcvdOk); 1975160641Syongari 1976160641Syongari ifp->if_ierrors += CSR_READ_2(sc, STGE_FramesLostRxErrors); 1977160641Syongari 1978160641Syongari CSR_READ_4(sc, STGE_OctetXmtdOk); 1979160641Syongari 1980160641Syongari ifp->if_opackets += CSR_READ_4(sc, STGE_FramesXmtdOk); 1981160641Syongari 1982160641Syongari ifp->if_collisions += 1983160641Syongari CSR_READ_4(sc, STGE_LateCollisions) + 1984160641Syongari CSR_READ_4(sc, STGE_MultiColFrames) + 1985160641Syongari CSR_READ_4(sc, STGE_SingleColFrames); 1986160641Syongari 1987160641Syongari ifp->if_oerrors += 1988160641Syongari CSR_READ_2(sc, STGE_FramesAbortXSColls) + 1989160641Syongari CSR_READ_2(sc, STGE_FramesWEXDeferal); 1990160641Syongari} 1991160641Syongari 1992160641Syongari/* 1993160641Syongari * stge_reset: 1994160641Syongari * 1995160641Syongari * Perform a soft reset on the TC9021. 1996160641Syongari */ 1997160641Syongaristatic void 1998160641Syongaristge_reset(struct stge_softc *sc, uint32_t how) 1999160641Syongari{ 2000160641Syongari uint32_t ac; 2001160641Syongari uint8_t v; 2002160641Syongari int i, dv; 2003160641Syongari 2004160641Syongari STGE_LOCK_ASSERT(sc); 2005160641Syongari 2006160641Syongari dv = 5000; 2007160641Syongari ac = CSR_READ_4(sc, STGE_AsicCtrl); 2008160641Syongari switch (how) { 2009160641Syongari case STGE_RESET_TX: 2010160641Syongari ac |= AC_TxReset | AC_FIFO; 2011160641Syongari dv = 100; 2012160641Syongari break; 2013160641Syongari case STGE_RESET_RX: 2014160641Syongari ac |= AC_RxReset | AC_FIFO; 2015160641Syongari dv = 100; 2016160641Syongari break; 2017160641Syongari case STGE_RESET_FULL: 2018160641Syongari default: 2019160641Syongari /* 2020160641Syongari * Only assert RstOut if we're fiber. We need GMII clocks 2021160641Syongari * to be present in order for the reset to complete on fiber 2022160641Syongari * cards. 2023160641Syongari */ 2024160641Syongari ac |= AC_GlobalReset | AC_RxReset | AC_TxReset | 2025160641Syongari AC_DMA | AC_FIFO | AC_Network | AC_Host | AC_AutoInit | 2026160641Syongari (sc->sc_usefiber ? AC_RstOut : 0); 2027160641Syongari break; 2028160641Syongari } 2029160641Syongari 2030160641Syongari CSR_WRITE_4(sc, STGE_AsicCtrl, ac); 2031160641Syongari 2032160641Syongari /* Account for reset problem at 10Mbps. */ 2033160641Syongari DELAY(dv); 2034160641Syongari 2035160641Syongari for (i = 0; i < STGE_TIMEOUT; i++) { 2036160641Syongari if ((CSR_READ_4(sc, STGE_AsicCtrl) & AC_ResetBusy) == 0) 2037160641Syongari break; 2038160641Syongari DELAY(dv); 2039160641Syongari } 2040160641Syongari 2041160641Syongari if (i == STGE_TIMEOUT) 2042160641Syongari device_printf(sc->sc_dev, "reset failed to complete\n"); 2043160641Syongari 2044160641Syongari /* Set LED, from Linux IPG driver. */ 2045160641Syongari ac = CSR_READ_4(sc, STGE_AsicCtrl); 2046160641Syongari ac &= ~(AC_LEDMode | AC_LEDSpeed | AC_LEDModeBit1); 2047160641Syongari if ((sc->sc_led & 0x01) != 0) 2048160641Syongari ac |= AC_LEDMode; 2049160641Syongari if ((sc->sc_led & 0x03) != 0) 2050160641Syongari ac |= AC_LEDModeBit1; 2051160641Syongari if ((sc->sc_led & 0x08) != 0) 2052160641Syongari ac |= AC_LEDSpeed; 2053160641Syongari CSR_WRITE_4(sc, STGE_AsicCtrl, ac); 2054160641Syongari 2055160641Syongari /* Set PHY, from Linux IPG driver */ 2056160641Syongari v = CSR_READ_1(sc, STGE_PhySet); 2057160641Syongari v &= ~(PS_MemLenb9b | PS_MemLen | PS_NonCompdet); 2058160641Syongari v |= ((sc->sc_led & 0x70) >> 4); 2059160641Syongari CSR_WRITE_1(sc, STGE_PhySet, v); 2060160641Syongari} 2061160641Syongari 2062160641Syongari/* 2063160641Syongari * stge_init: [ ifnet interface function ] 2064160641Syongari * 2065160641Syongari * Initialize the interface. 2066160641Syongari */ 2067160641Syongaristatic void 2068160641Syongaristge_init(void *xsc) 2069160641Syongari{ 2070160641Syongari struct stge_softc *sc; 2071160641Syongari 2072160641Syongari sc = (struct stge_softc *)xsc; 2073160641Syongari STGE_LOCK(sc); 2074160641Syongari stge_init_locked(sc); 2075160641Syongari STGE_UNLOCK(sc); 2076160641Syongari} 2077160641Syongari 2078160641Syongaristatic void 2079160641Syongaristge_init_locked(struct stge_softc *sc) 2080160641Syongari{ 2081160641Syongari struct ifnet *ifp; 2082160641Syongari struct mii_data *mii; 2083160641Syongari uint16_t eaddr[3]; 2084160641Syongari uint32_t v; 2085160641Syongari int error; 2086160641Syongari 2087160641Syongari STGE_LOCK_ASSERT(sc); 2088160641Syongari 2089160641Syongari ifp = sc->sc_ifp; 2090160641Syongari mii = device_get_softc(sc->sc_miibus); 2091160641Syongari 2092160641Syongari /* 2093160641Syongari * Cancel any pending I/O. 2094160641Syongari */ 2095160641Syongari stge_stop(sc); 2096160641Syongari 2097160641Syongari /* Init descriptors. */ 2098160641Syongari error = stge_init_rx_ring(sc); 2099160641Syongari if (error != 0) { 2100160641Syongari device_printf(sc->sc_dev, 2101160641Syongari "initialization failed: no memory for rx buffers\n"); 2102160641Syongari stge_stop(sc); 2103160641Syongari goto out; 2104160641Syongari } 2105160641Syongari stge_init_tx_ring(sc); 2106160641Syongari 2107160641Syongari /* Set the station address. */ 2108160641Syongari bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 2109160641Syongari CSR_WRITE_2(sc, STGE_StationAddress0, htole16(eaddr[0])); 2110160641Syongari CSR_WRITE_2(sc, STGE_StationAddress1, htole16(eaddr[1])); 2111160641Syongari CSR_WRITE_2(sc, STGE_StationAddress2, htole16(eaddr[2])); 2112160641Syongari 2113160641Syongari /* 2114160641Syongari * Set the statistics masks. Disable all the RMON stats, 2115160641Syongari * and disable selected stats in the non-RMON stats registers. 2116160641Syongari */ 2117160641Syongari CSR_WRITE_4(sc, STGE_RMONStatisticsMask, 0xffffffff); 2118160641Syongari CSR_WRITE_4(sc, STGE_StatisticsMask, 2119160641Syongari (1U << 1) | (1U << 2) | (1U << 3) | (1U << 4) | (1U << 5) | 2120160641Syongari (1U << 6) | (1U << 7) | (1U << 8) | (1U << 9) | (1U << 10) | 2121160641Syongari (1U << 13) | (1U << 14) | (1U << 15) | (1U << 19) | (1U << 20) | 2122160641Syongari (1U << 21)); 2123160641Syongari 2124160641Syongari /* Set up the receive filter. */ 2125160641Syongari stge_set_filter(sc); 2126160641Syongari /* Program multicast filter. */ 2127160641Syongari stge_set_multi(sc); 2128160641Syongari 2129160641Syongari /* 2130160641Syongari * Give the transmit and receive ring to the chip. 2131160641Syongari */ 2132160641Syongari CSR_WRITE_4(sc, STGE_TFDListPtrHi, 2133160641Syongari STGE_ADDR_HI(STGE_TX_RING_ADDR(sc, 0))); 2134160641Syongari CSR_WRITE_4(sc, STGE_TFDListPtrLo, 2135160641Syongari STGE_ADDR_LO(STGE_TX_RING_ADDR(sc, 0))); 2136160641Syongari 2137160641Syongari CSR_WRITE_4(sc, STGE_RFDListPtrHi, 2138160641Syongari STGE_ADDR_HI(STGE_RX_RING_ADDR(sc, 0))); 2139160641Syongari CSR_WRITE_4(sc, STGE_RFDListPtrLo, 2140160641Syongari STGE_ADDR_LO(STGE_RX_RING_ADDR(sc, 0))); 2141160641Syongari 2142160641Syongari /* 2143160641Syongari * Initialize the Tx auto-poll period. It's OK to make this number 2144160641Syongari * large (255 is the max, but we use 127) -- we explicitly kick the 2145160641Syongari * transmit engine when there's actually a packet. 2146160641Syongari */ 2147160641Syongari CSR_WRITE_1(sc, STGE_TxDMAPollPeriod, 127); 2148160641Syongari 2149160641Syongari /* ..and the Rx auto-poll period. */ 2150160641Syongari CSR_WRITE_1(sc, STGE_RxDMAPollPeriod, 1); 2151160641Syongari 2152160641Syongari /* Initialize the Tx start threshold. */ 2153160641Syongari CSR_WRITE_2(sc, STGE_TxStartThresh, sc->sc_txthresh); 2154160641Syongari 2155160641Syongari /* Rx DMA thresholds, from Linux */ 2156160641Syongari CSR_WRITE_1(sc, STGE_RxDMABurstThresh, 0x30); 2157160641Syongari CSR_WRITE_1(sc, STGE_RxDMAUrgentThresh, 0x30); 2158160641Syongari 2159160641Syongari /* Rx early threhold, from Linux */ 2160160641Syongari CSR_WRITE_2(sc, STGE_RxEarlyThresh, 0x7ff); 2161160641Syongari 2162160641Syongari /* Tx DMA thresholds, from Linux */ 2163160641Syongari CSR_WRITE_1(sc, STGE_TxDMABurstThresh, 0x30); 2164160641Syongari CSR_WRITE_1(sc, STGE_TxDMAUrgentThresh, 0x04); 2165160641Syongari 2166160641Syongari /* 2167160641Syongari * Initialize the Rx DMA interrupt control register. We 2168160641Syongari * request an interrupt after every incoming packet, but 2169160641Syongari * defer it for sc_rxint_dmawait us. When the number of 2170160641Syongari * interrupts pending reaches STGE_RXINT_NFRAME, we stop 2171160641Syongari * deferring the interrupt, and signal it immediately. 2172160641Syongari */ 2173160641Syongari CSR_WRITE_4(sc, STGE_RxDMAIntCtrl, 2174160641Syongari RDIC_RxFrameCount(sc->sc_rxint_nframe) | 2175160641Syongari RDIC_RxDMAWaitTime(STGE_RXINT_USECS2TICK(sc->sc_rxint_dmawait))); 2176160641Syongari 2177160641Syongari /* 2178160641Syongari * Initialize the interrupt mask. 2179160641Syongari */ 2180160641Syongari sc->sc_IntEnable = IS_HostError | IS_TxComplete | 2181160641Syongari IS_TxDMAComplete | IS_RxDMAComplete | IS_RFDListEnd; 2182160641Syongari#ifdef DEVICE_POLLING 2183160641Syongari /* Disable interrupts if we are polling. */ 2184160641Syongari if ((ifp->if_capenable & IFCAP_POLLING) != 0) 2185160641Syongari CSR_WRITE_2(sc, STGE_IntEnable, 0); 2186160641Syongari else 2187160641Syongari#endif 2188160641Syongari CSR_WRITE_2(sc, STGE_IntEnable, sc->sc_IntEnable); 2189160641Syongari 2190160641Syongari /* 2191160641Syongari * Configure the DMA engine. 2192160641Syongari * XXX Should auto-tune TxBurstLimit. 2193160641Syongari */ 2194160641Syongari CSR_WRITE_4(sc, STGE_DMACtrl, sc->sc_DMACtrl | DMAC_TxBurstLimit(3)); 2195160641Syongari 2196160641Syongari /* 2197160641Syongari * Send a PAUSE frame when we reach 29,696 bytes in the Rx 2198160641Syongari * FIFO, and send an un-PAUSE frame when we reach 3056 bytes 2199160641Syongari * in the Rx FIFO. 2200160641Syongari */ 2201160641Syongari CSR_WRITE_2(sc, STGE_FlowOnTresh, 29696 / 16); 2202160641Syongari CSR_WRITE_2(sc, STGE_FlowOffThresh, 3056 / 16); 2203160641Syongari 2204160641Syongari /* 2205160641Syongari * Set the maximum frame size. 2206160641Syongari */ 2207160641Syongari sc->sc_if_framesize = ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 2208160641Syongari CSR_WRITE_2(sc, STGE_MaxFrameSize, sc->sc_if_framesize); 2209160641Syongari 2210160641Syongari /* 2211160641Syongari * Initialize MacCtrl -- do it before setting the media, 2212160641Syongari * as setting the media will actually program the register. 2213160641Syongari * 2214160641Syongari * Note: We have to poke the IFS value before poking 2215160641Syongari * anything else. 2216160641Syongari */ 2217160641Syongari /* Tx/Rx MAC should be disabled before programming IFS.*/ 2218160641Syongari CSR_WRITE_4(sc, STGE_MACCtrl, MC_IFSSelect(MC_IFS96bit)); 2219160641Syongari 2220160641Syongari stge_vlan_setup(sc); 2221160641Syongari 2222160641Syongari if (sc->sc_rev >= 6) { /* >= B.2 */ 2223160641Syongari /* Multi-frag frame bug work-around. */ 2224160641Syongari CSR_WRITE_2(sc, STGE_DebugCtrl, 2225160641Syongari CSR_READ_2(sc, STGE_DebugCtrl) | 0x0200); 2226160641Syongari 2227160641Syongari /* Tx Poll Now bug work-around. */ 2228160641Syongari CSR_WRITE_2(sc, STGE_DebugCtrl, 2229160641Syongari CSR_READ_2(sc, STGE_DebugCtrl) | 0x0010); 2230160641Syongari /* Tx Poll Now bug work-around. */ 2231160641Syongari CSR_WRITE_2(sc, STGE_DebugCtrl, 2232160641Syongari CSR_READ_2(sc, STGE_DebugCtrl) | 0x0020); 2233160641Syongari } 2234160641Syongari 2235160641Syongari v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 2236160641Syongari v |= MC_StatisticsEnable | MC_TxEnable | MC_RxEnable; 2237160641Syongari CSR_WRITE_4(sc, STGE_MACCtrl, v); 2238160641Syongari /* 2239160641Syongari * It seems that transmitting frames without checking the state of 2240160641Syongari * Rx/Tx MAC wedge the hardware. 2241160641Syongari */ 2242160641Syongari stge_start_tx(sc); 2243160641Syongari stge_start_rx(sc); 2244160641Syongari 2245160641Syongari /* 2246160641Syongari * Set the current media. 2247160641Syongari */ 2248160641Syongari mii_mediachg(mii); 2249160641Syongari 2250160641Syongari /* 2251160641Syongari * Start the one second MII clock. 2252160641Syongari */ 2253160641Syongari callout_reset(&sc->sc_tick_ch, hz, stge_tick, sc); 2254160641Syongari 2255160641Syongari /* 2256160641Syongari * ...all done! 2257160641Syongari */ 2258160641Syongari ifp->if_drv_flags |= IFF_DRV_RUNNING; 2259160641Syongari ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2260160641Syongari 2261160641Syongari out: 2262160641Syongari if (error != 0) 2263160641Syongari device_printf(sc->sc_dev, "interface not running\n"); 2264160641Syongari} 2265160641Syongari 2266160641Syongaristatic void 2267160641Syongaristge_vlan_setup(struct stge_softc *sc) 2268160641Syongari{ 2269160641Syongari struct ifnet *ifp; 2270160641Syongari uint32_t v; 2271160641Syongari 2272160641Syongari ifp = sc->sc_ifp; 2273160641Syongari /* 2274160641Syongari * The NIC always copy a VLAN tag regardless of STGE_MACCtrl 2275160641Syongari * MC_AutoVLANuntagging bit. 2276160641Syongari * MC_AutoVLANtagging bit selects which VLAN source to use 2277160641Syongari * between STGE_VLANTag and TFC. However TFC TFD_VLANTagInsert 2278160641Syongari * bit has priority over MC_AutoVLANtagging bit. So we always 2279160641Syongari * use TFC instead of STGE_VLANTag register. 2280160641Syongari */ 2281160641Syongari v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 2282160641Syongari if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 2283160641Syongari v |= MC_AutoVLANuntagging; 2284160641Syongari else 2285160641Syongari v &= ~MC_AutoVLANuntagging; 2286160641Syongari CSR_WRITE_4(sc, STGE_MACCtrl, v); 2287160641Syongari} 2288160641Syongari 2289160641Syongari/* 2290160641Syongari * Stop transmission on the interface. 2291160641Syongari */ 2292160641Syongaristatic void 2293160641Syongaristge_stop(struct stge_softc *sc) 2294160641Syongari{ 2295160641Syongari struct ifnet *ifp; 2296160641Syongari struct stge_txdesc *txd; 2297160641Syongari struct stge_rxdesc *rxd; 2298160641Syongari uint32_t v; 2299160641Syongari int i; 2300160641Syongari 2301160641Syongari STGE_LOCK_ASSERT(sc); 2302160641Syongari /* 2303160641Syongari * Stop the one second clock. 2304160641Syongari */ 2305160641Syongari callout_stop(&sc->sc_tick_ch); 2306160641Syongari 2307160641Syongari /* 2308160641Syongari * Reset the chip to a known state. 2309160641Syongari */ 2310160641Syongari stge_reset(sc, STGE_RESET_FULL); 2311160641Syongari 2312160641Syongari /* 2313160641Syongari * Disable interrupts. 2314160641Syongari */ 2315160641Syongari CSR_WRITE_2(sc, STGE_IntEnable, 0); 2316160641Syongari 2317160641Syongari /* 2318160641Syongari * Stop receiver, transmitter, and stats update. 2319160641Syongari */ 2320160641Syongari stge_stop_rx(sc); 2321160641Syongari stge_stop_tx(sc); 2322160641Syongari v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 2323160641Syongari v |= MC_StatisticsDisable; 2324160641Syongari CSR_WRITE_4(sc, STGE_MACCtrl, v); 2325160641Syongari 2326160641Syongari /* 2327160641Syongari * Stop the transmit and receive DMA. 2328160641Syongari */ 2329160641Syongari stge_dma_wait(sc); 2330160641Syongari CSR_WRITE_4(sc, STGE_TFDListPtrHi, 0); 2331160641Syongari CSR_WRITE_4(sc, STGE_TFDListPtrLo, 0); 2332160641Syongari CSR_WRITE_4(sc, STGE_RFDListPtrHi, 0); 2333160641Syongari CSR_WRITE_4(sc, STGE_RFDListPtrLo, 0); 2334160641Syongari 2335160641Syongari /* 2336160641Syongari * Free RX and TX mbufs still in the queues. 2337160641Syongari */ 2338160641Syongari for (i = 0; i < STGE_RX_RING_CNT; i++) { 2339160641Syongari rxd = &sc->sc_cdata.stge_rxdesc[i]; 2340160641Syongari if (rxd->rx_m != NULL) { 2341160641Syongari bus_dmamap_sync(sc->sc_cdata.stge_rx_tag, 2342160641Syongari rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 2343160641Syongari bus_dmamap_unload(sc->sc_cdata.stge_rx_tag, 2344160641Syongari rxd->rx_dmamap); 2345160641Syongari m_freem(rxd->rx_m); 2346160641Syongari rxd->rx_m = NULL; 2347160641Syongari } 2348160641Syongari } 2349160641Syongari for (i = 0; i < STGE_TX_RING_CNT; i++) { 2350160641Syongari txd = &sc->sc_cdata.stge_txdesc[i]; 2351160641Syongari if (txd->tx_m != NULL) { 2352160641Syongari bus_dmamap_sync(sc->sc_cdata.stge_tx_tag, 2353160641Syongari txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2354160641Syongari bus_dmamap_unload(sc->sc_cdata.stge_tx_tag, 2355160641Syongari txd->tx_dmamap); 2356160641Syongari m_freem(txd->tx_m); 2357160641Syongari txd->tx_m = NULL; 2358160641Syongari } 2359160641Syongari } 2360160641Syongari 2361160641Syongari /* 2362160641Syongari * Mark the interface down and cancel the watchdog timer. 2363160641Syongari */ 2364160641Syongari ifp = sc->sc_ifp; 2365160641Syongari ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2366160641Syongari ifp->if_timer = 0; 2367160641Syongari} 2368160641Syongari 2369160641Syongaristatic void 2370160641Syongaristge_start_tx(struct stge_softc *sc) 2371160641Syongari{ 2372160641Syongari uint32_t v; 2373160641Syongari int i; 2374160641Syongari 2375160641Syongari v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 2376160641Syongari if ((v & MC_TxEnabled) != 0) 2377160641Syongari return; 2378160641Syongari v |= MC_TxEnable; 2379160641Syongari CSR_WRITE_4(sc, STGE_MACCtrl, v); 2380160641Syongari CSR_WRITE_1(sc, STGE_TxDMAPollPeriod, 127); 2381160641Syongari for (i = STGE_TIMEOUT; i > 0; i--) { 2382160641Syongari DELAY(10); 2383160641Syongari v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 2384160641Syongari if ((v & MC_TxEnabled) != 0) 2385160641Syongari break; 2386160641Syongari } 2387160641Syongari if (i == 0) 2388160641Syongari device_printf(sc->sc_dev, "Starting Tx MAC timed out\n"); 2389160641Syongari} 2390160641Syongari 2391160641Syongaristatic void 2392160641Syongaristge_start_rx(struct stge_softc *sc) 2393160641Syongari{ 2394160641Syongari uint32_t v; 2395160641Syongari int i; 2396160641Syongari 2397160641Syongari v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 2398160641Syongari if ((v & MC_RxEnabled) != 0) 2399160641Syongari return; 2400160641Syongari v |= MC_RxEnable; 2401160641Syongari CSR_WRITE_4(sc, STGE_MACCtrl, v); 2402160641Syongari CSR_WRITE_1(sc, STGE_RxDMAPollPeriod, 1); 2403160641Syongari for (i = STGE_TIMEOUT; i > 0; i--) { 2404160641Syongari DELAY(10); 2405160641Syongari v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 2406160641Syongari if ((v & MC_RxEnabled) != 0) 2407160641Syongari break; 2408160641Syongari } 2409160641Syongari if (i == 0) 2410160641Syongari device_printf(sc->sc_dev, "Starting Rx MAC timed out\n"); 2411160641Syongari} 2412160641Syongari 2413160641Syongaristatic void 2414160641Syongaristge_stop_tx(struct stge_softc *sc) 2415160641Syongari{ 2416160641Syongari uint32_t v; 2417160641Syongari int i; 2418160641Syongari 2419160641Syongari v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 2420160641Syongari if ((v & MC_TxEnabled) == 0) 2421160641Syongari return; 2422160641Syongari v |= MC_TxDisable; 2423160641Syongari CSR_WRITE_4(sc, STGE_MACCtrl, v); 2424160641Syongari for (i = STGE_TIMEOUT; i > 0; i--) { 2425160641Syongari DELAY(10); 2426160641Syongari v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 2427160641Syongari if ((v & MC_TxEnabled) == 0) 2428160641Syongari break; 2429160641Syongari } 2430160641Syongari if (i == 0) 2431160641Syongari device_printf(sc->sc_dev, "Stopping Tx MAC timed out\n"); 2432160641Syongari} 2433160641Syongari 2434160641Syongaristatic void 2435160641Syongaristge_stop_rx(struct stge_softc *sc) 2436160641Syongari{ 2437160641Syongari uint32_t v; 2438160641Syongari int i; 2439160641Syongari 2440160641Syongari v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 2441160641Syongari if ((v & MC_RxEnabled) == 0) 2442160641Syongari return; 2443160641Syongari v |= MC_RxDisable; 2444160641Syongari CSR_WRITE_4(sc, STGE_MACCtrl, v); 2445160641Syongari for (i = STGE_TIMEOUT; i > 0; i--) { 2446160641Syongari DELAY(10); 2447160641Syongari v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 2448160641Syongari if ((v & MC_RxEnabled) == 0) 2449160641Syongari break; 2450160641Syongari } 2451160641Syongari if (i == 0) 2452160641Syongari device_printf(sc->sc_dev, "Stopping Rx MAC timed out\n"); 2453160641Syongari} 2454160641Syongari 2455160641Syongaristatic void 2456160641Syongaristge_init_tx_ring(struct stge_softc *sc) 2457160641Syongari{ 2458160641Syongari struct stge_ring_data *rd; 2459160641Syongari struct stge_txdesc *txd; 2460160641Syongari bus_addr_t addr; 2461160641Syongari int i; 2462160641Syongari 2463160641Syongari STAILQ_INIT(&sc->sc_cdata.stge_txfreeq); 2464160641Syongari STAILQ_INIT(&sc->sc_cdata.stge_txbusyq); 2465160641Syongari 2466160641Syongari sc->sc_cdata.stge_tx_prod = 0; 2467160641Syongari sc->sc_cdata.stge_tx_cons = 0; 2468160641Syongari sc->sc_cdata.stge_tx_cnt = 0; 2469160641Syongari 2470160641Syongari rd = &sc->sc_rdata; 2471160641Syongari bzero(rd->stge_tx_ring, STGE_TX_RING_SZ); 2472160641Syongari for (i = 0; i < STGE_TX_RING_CNT; i++) { 2473160641Syongari if (i == (STGE_TX_RING_CNT - 1)) 2474160641Syongari addr = STGE_TX_RING_ADDR(sc, 0); 2475160641Syongari else 2476160641Syongari addr = STGE_TX_RING_ADDR(sc, i + 1); 2477160641Syongari rd->stge_tx_ring[i].tfd_next = htole64(addr); 2478160641Syongari rd->stge_tx_ring[i].tfd_control = htole64(TFD_TFDDone); 2479160641Syongari txd = &sc->sc_cdata.stge_txdesc[i]; 2480160641Syongari STAILQ_INSERT_TAIL(&sc->sc_cdata.stge_txfreeq, txd, tx_q); 2481160641Syongari } 2482160641Syongari 2483160641Syongari bus_dmamap_sync(sc->sc_cdata.stge_tx_ring_tag, 2484160641Syongari sc->sc_cdata.stge_tx_ring_map, 2485160641Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2486160641Syongari 2487160641Syongari} 2488160641Syongari 2489160641Syongaristatic int 2490160641Syongaristge_init_rx_ring(struct stge_softc *sc) 2491160641Syongari{ 2492160641Syongari struct stge_ring_data *rd; 2493160641Syongari bus_addr_t addr; 2494160641Syongari int i; 2495160641Syongari 2496160641Syongari sc->sc_cdata.stge_rx_cons = 0; 2497160641Syongari STGE_RXCHAIN_RESET(sc); 2498160641Syongari 2499160641Syongari rd = &sc->sc_rdata; 2500160641Syongari bzero(rd->stge_rx_ring, STGE_RX_RING_SZ); 2501160641Syongari for (i = 0; i < STGE_RX_RING_CNT; i++) { 2502160641Syongari if (stge_newbuf(sc, i) != 0) 2503160641Syongari return (ENOBUFS); 2504160641Syongari if (i == (STGE_RX_RING_CNT - 1)) 2505160641Syongari addr = STGE_RX_RING_ADDR(sc, 0); 2506160641Syongari else 2507160641Syongari addr = STGE_RX_RING_ADDR(sc, i + 1); 2508160641Syongari rd->stge_rx_ring[i].rfd_next = htole64(addr); 2509160641Syongari rd->stge_rx_ring[i].rfd_status = 0; 2510160641Syongari } 2511160641Syongari 2512160641Syongari bus_dmamap_sync(sc->sc_cdata.stge_rx_ring_tag, 2513160641Syongari sc->sc_cdata.stge_rx_ring_map, 2514160641Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2515160641Syongari 2516160641Syongari return (0); 2517160641Syongari} 2518160641Syongari 2519160641Syongari/* 2520160641Syongari * stge_newbuf: 2521160641Syongari * 2522160641Syongari * Add a receive buffer to the indicated descriptor. 2523160641Syongari */ 2524160641Syongaristatic int 2525160641Syongaristge_newbuf(struct stge_softc *sc, int idx) 2526160641Syongari{ 2527160641Syongari struct stge_rxdesc *rxd; 2528160641Syongari struct stge_rfd *rfd; 2529160641Syongari struct mbuf *m; 2530160641Syongari bus_dma_segment_t segs[1]; 2531160641Syongari bus_dmamap_t map; 2532160641Syongari int nsegs; 2533160641Syongari 2534160641Syongari m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2535160641Syongari if (m == NULL) 2536160641Syongari return (ENOBUFS); 2537160641Syongari m->m_len = m->m_pkthdr.len = MCLBYTES; 2538160641Syongari /* 2539160641Syongari * The hardware requires 4bytes aligned DMA address when JUMBO 2540160641Syongari * frame is used. 2541160641Syongari */ 2542160641Syongari if (sc->sc_if_framesize <= (MCLBYTES - ETHER_ALIGN)) 2543160641Syongari m_adj(m, ETHER_ALIGN); 2544160641Syongari 2545160641Syongari if (bus_dmamap_load_mbuf_sg(sc->sc_cdata.stge_rx_tag, 2546160641Syongari sc->sc_cdata.stge_rx_sparemap, m, segs, &nsegs, 0) != 0) { 2547160641Syongari m_freem(m); 2548160641Syongari return (ENOBUFS); 2549160641Syongari } 2550160641Syongari KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 2551160641Syongari 2552160641Syongari rxd = &sc->sc_cdata.stge_rxdesc[idx]; 2553160641Syongari if (rxd->rx_m != NULL) { 2554160641Syongari bus_dmamap_sync(sc->sc_cdata.stge_rx_tag, rxd->rx_dmamap, 2555160641Syongari BUS_DMASYNC_POSTREAD); 2556160641Syongari bus_dmamap_unload(sc->sc_cdata.stge_rx_tag, rxd->rx_dmamap); 2557160641Syongari } 2558160641Syongari map = rxd->rx_dmamap; 2559160641Syongari rxd->rx_dmamap = sc->sc_cdata.stge_rx_sparemap; 2560160641Syongari sc->sc_cdata.stge_rx_sparemap = map; 2561160641Syongari bus_dmamap_sync(sc->sc_cdata.stge_rx_tag, rxd->rx_dmamap, 2562160641Syongari BUS_DMASYNC_PREREAD); 2563160641Syongari rxd->rx_m = m; 2564160641Syongari 2565160641Syongari rfd = &sc->sc_rdata.stge_rx_ring[idx]; 2566160641Syongari rfd->rfd_frag.frag_word0 = 2567160641Syongari htole64(FRAG_ADDR(segs[0].ds_addr) | FRAG_LEN(segs[0].ds_len)); 2568160641Syongari rfd->rfd_status = 0; 2569160641Syongari 2570160641Syongari return (0); 2571160641Syongari} 2572160641Syongari 2573160641Syongari/* 2574160641Syongari * stge_set_filter: 2575160641Syongari * 2576160641Syongari * Set up the receive filter. 2577160641Syongari */ 2578160641Syongaristatic void 2579160641Syongaristge_set_filter(struct stge_softc *sc) 2580160641Syongari{ 2581160641Syongari struct ifnet *ifp; 2582160641Syongari uint16_t mode; 2583160641Syongari 2584160641Syongari STGE_LOCK_ASSERT(sc); 2585160641Syongari 2586160641Syongari ifp = sc->sc_ifp; 2587160641Syongari 2588160641Syongari mode = CSR_READ_2(sc, STGE_ReceiveMode); 2589160641Syongari mode |= RM_ReceiveUnicast; 2590160641Syongari if ((ifp->if_flags & IFF_BROADCAST) != 0) 2591160641Syongari mode |= RM_ReceiveBroadcast; 2592160641Syongari else 2593160641Syongari mode &= ~RM_ReceiveBroadcast; 2594160641Syongari if ((ifp->if_flags & IFF_PROMISC) != 0) 2595160641Syongari mode |= RM_ReceiveAllFrames; 2596160641Syongari else 2597160641Syongari mode &= ~RM_ReceiveAllFrames; 2598160641Syongari 2599160641Syongari CSR_WRITE_2(sc, STGE_ReceiveMode, mode); 2600160641Syongari} 2601160641Syongari 2602160641Syongaristatic void 2603160641Syongaristge_set_multi(struct stge_softc *sc) 2604160641Syongari{ 2605160641Syongari struct ifnet *ifp; 2606160641Syongari struct ifmultiaddr *ifma; 2607160641Syongari uint32_t crc; 2608160641Syongari uint32_t mchash[2]; 2609160641Syongari uint16_t mode; 2610160641Syongari int count; 2611160641Syongari 2612160641Syongari STGE_LOCK_ASSERT(sc); 2613160641Syongari 2614160641Syongari ifp = sc->sc_ifp; 2615160641Syongari 2616160641Syongari mode = CSR_READ_2(sc, STGE_ReceiveMode); 2617160641Syongari if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 2618160641Syongari if ((ifp->if_flags & IFF_PROMISC) != 0) 2619160641Syongari mode |= RM_ReceiveAllFrames; 2620160641Syongari else if ((ifp->if_flags & IFF_ALLMULTI) != 0) 2621160641Syongari mode |= RM_ReceiveMulticast; 2622160641Syongari CSR_WRITE_2(sc, STGE_ReceiveMode, mode); 2623160641Syongari return; 2624160641Syongari } 2625160641Syongari 2626160641Syongari /* clear existing filters. */ 2627160641Syongari CSR_WRITE_4(sc, STGE_HashTable0, 0); 2628160641Syongari CSR_WRITE_4(sc, STGE_HashTable1, 0); 2629160641Syongari 2630160641Syongari /* 2631160641Syongari * Set up the multicast address filter by passing all multicast 2632160641Syongari * addresses through a CRC generator, and then using the low-order 2633160641Syongari * 6 bits as an index into the 64 bit multicast hash table. The 2634160641Syongari * high order bits select the register, while the rest of the bits 2635160641Syongari * select the bit within the register. 2636160641Syongari */ 2637160641Syongari 2638160641Syongari bzero(mchash, sizeof(mchash)); 2639160641Syongari 2640160641Syongari count = 0; 2641160641Syongari IF_ADDR_LOCK(sc->sc_ifp); 2642160641Syongari TAILQ_FOREACH(ifma, &sc->sc_ifp->if_multiaddrs, ifma_link) { 2643160641Syongari if (ifma->ifma_addr->sa_family != AF_LINK) 2644160641Syongari continue; 2645160641Syongari crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) 2646160641Syongari ifma->ifma_addr), ETHER_ADDR_LEN); 2647160641Syongari 2648160641Syongari /* Just want the 6 least significant bits. */ 2649160641Syongari crc &= 0x3f; 2650160641Syongari 2651160641Syongari /* Set the corresponding bit in the hash table. */ 2652160641Syongari mchash[crc >> 5] |= 1 << (crc & 0x1f); 2653160641Syongari count++; 2654160641Syongari } 2655160641Syongari IF_ADDR_UNLOCK(ifp); 2656160641Syongari 2657160641Syongari mode &= ~(RM_ReceiveMulticast | RM_ReceiveAllFrames); 2658160641Syongari if (count > 0) 2659160641Syongari mode |= RM_ReceiveMulticastHash; 2660160641Syongari else 2661160641Syongari mode &= ~RM_ReceiveMulticastHash; 2662160641Syongari 2663160641Syongari CSR_WRITE_4(sc, STGE_HashTable0, mchash[0]); 2664160641Syongari CSR_WRITE_4(sc, STGE_HashTable1, mchash[1]); 2665160641Syongari CSR_WRITE_2(sc, STGE_ReceiveMode, mode); 2666160641Syongari} 2667160641Syongari 2668160641Syongaristatic int 2669160641Syongarisysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 2670160641Syongari{ 2671160641Syongari int error, value; 2672160641Syongari 2673160641Syongari if (!arg1) 2674160641Syongari return (EINVAL); 2675160641Syongari value = *(int *)arg1; 2676160641Syongari error = sysctl_handle_int(oidp, &value, 0, req); 2677160641Syongari if (error || !req->newptr) 2678160641Syongari return (error); 2679160641Syongari if (value < low || value > high) 2680160641Syongari return (EINVAL); 2681160641Syongari *(int *)arg1 = value; 2682160641Syongari 2683160641Syongari return (0); 2684160641Syongari} 2685160641Syongari 2686160641Syongaristatic int 2687160641Syongarisysctl_hw_stge_rxint_nframe(SYSCTL_HANDLER_ARGS) 2688160641Syongari{ 2689160641Syongari return (sysctl_int_range(oidp, arg1, arg2, req, 2690160641Syongari STGE_RXINT_NFRAME_MIN, STGE_RXINT_NFRAME_MAX)); 2691160641Syongari} 2692160641Syongari 2693160641Syongaristatic int 2694160641Syongarisysctl_hw_stge_rxint_dmawait(SYSCTL_HANDLER_ARGS) 2695160641Syongari{ 2696160641Syongari return (sysctl_int_range(oidp, arg1, arg2, req, 2697160641Syongari STGE_RXINT_DMAWAIT_MIN, STGE_RXINT_DMAWAIT_MAX)); 2698160641Syongari} 2699