1/*- 2 * Copyright (c) 2018 Microsemi Corporation. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27/* $FreeBSD: stable/11/sys/dev/smartpqi/smartpqi_defines.h 346376 2019-04-19 12:40:21Z kib $ */ 28 29#ifndef _PQI_DEFINES_H 30#define _PQI_DEFINES_H 31 32#define PQI_STATUS_FAILURE -1 33#define PQI_STATUS_TIMEOUT -2 34#define PQI_STATUS_QFULL -3 35#define PQI_STATUS_SUCCESS 0 36 37#define PQISRC_CMD_TIMEOUT_CNT 1200000 /* 500usec * 1200000 = 5 min */ 38 39/* #define SHARE_EVENT_QUEUE_FOR_IO 1 */ 40 41#define INVALID_ELEM 0xffff 42#ifndef MIN 43#define MIN(a,b) ((a) < (b) ? (a) : (b)) 44#endif 45 46#ifndef MAX 47#define MAX(a,b) ((a) > (b) ? (a) : (b)) 48#endif 49 50#define PQISRC_ROUNDUP(x, y) (((x) + (y) - 1) / (y) * (y)) 51#define PQISRC_DIV_ROUND_UP(x, y) (((x) + (y) - 1) / (y)) 52 53#define ALIGN_BOUNDARY(a, n) { \ 54 if (a % n) \ 55 a = a + (n - a % n); \ 56 } 57 58/* Busy wait timeout on a condition */ 59#define COND_BUSYWAIT(cond, timeout /* in millisecond */) { \ 60 if (!(cond)) { \ 61 while (timeout) { \ 62 OS_BUSYWAIT(1000); \ 63 if (cond) \ 64 break; \ 65 timeout--; \ 66 } \ 67 } \ 68 } 69 70/* Wait timeout on a condition*/ 71#define COND_WAIT(cond, timeout /* in millisecond */) { \ 72 if (!(cond)) { \ 73 while (timeout) { \ 74 OS_SLEEP(1000); \ 75 if (cond) \ 76 break; \ 77 timeout--; \ 78 } \ 79 } \ 80 } 81 82#define FILL_QUEUE_ARRAY_ADDR(q,virt,dma) { \ 83 q->array_virt_addr = virt; \ 84 q->array_dma_addr = dma; \ 85 } 86 87#define true 1 88#define false 0 89 90enum INTR_TYPE { 91 LOCK_INTR, 92 LOCK_SLEEP 93}; 94 95#define LOCKNAME_SIZE 32 96 97#define INTR_TYPE_FIXED 0x1 98#define INTR_TYPE_MSI 0x2 99#define INTR_TYPE_MSIX 0x4 100#define SIS_ENABLE_MSIX 0x40 101 102#define DMA_TO_VIRT(mem) ((mem)->virt_addr) 103#define DMA_PHYS_LOW(mem) (((mem)->dma_addr) & 0x00000000ffffffff) 104#define DMA_PHYS_HIGH(mem) ((((mem)->dma_addr) & 0xffffffff00000000) >> 32) 105 106 107typedef enum REQUEST_STATUS { 108 REQUEST_SUCCESS = 0, 109 REQUEST_PENDING = -1, 110 REQUEST_FAILED = -2, 111}REQUEST_STATUS_T; 112 113typedef enum IO_PATH { 114 AIO_PATH, 115 RAID_PATH 116}IO_PATH_T; 117 118typedef enum device_type 119{ 120 DISK_DEVICE, 121 TAPE_DEVICE, 122 ROM_DEVICE = 5, 123 MEDIUM_CHANGER_DEVICE = 8, 124 RAID_DEVICE = 0x0c, 125 ENCLOSURE_DEVICE, 126 ZBC_DEVICE = 0x14 127} device_type_t; 128 129typedef enum controller_state { 130 PQI_UP_RUNNING, 131 PQI_BUS_RESET, 132}controller_state_t; 133 134 135#define PQISRC_MAX_MSIX_SUPPORTED 64 136 137/* SIS Specific */ 138#define PQISRC_INIT_STRUCT_REVISION 9 139#define PQISRC_SECTOR_SIZE 512 140#define PQISRC_BLK_SIZE PQISRC_SECTOR_SIZE 141#define PQISRC_DEFAULT_DMA_ALIGN 4 142#define PQISRC_DMA_ALIGN_MASK (PQISRC_DEFAULT_DMA_ALIGN - 1) 143#define PQISRC_ERR_BUF_DMA_ALIGN 32 144#define PQISRC_ERR_BUF_ELEM_SIZE MAX(sizeof(raid_path_error_info_elem_t),sizeof(aio_path_error_info_elem_t)) 145#define PQISRC_INIT_STRUCT_DMA_ALIGN 16 146 147#define SIS_CMD_GET_ADAPTER_PROPERTIES 0x19 148#define SIS_CMD_GET_COMM_PREFERRED_SETTINGS 0x26 149#define SIS_CMD_GET_PQI_CAPABILITIES 0x3000 150#define SIS_CMD_INIT_BASE_STRUCT_ADDRESS 0x1b 151 152#define SIS_SUPPORT_EXT_OPT 0x00800000 153#define SIS_SUPPORT_PQI 0x00000004 154#define SIS_SUPPORT_PQI_RESET_QUIESCE 0x00000008 155 156#define SIS_PQI_RESET_QUIESCE 0x1000000 157 158#define SIS_STATUS_OK_TIMEOUT 120000 /* in milli sec, 5 sec */ 159 160#define SIS_CMD_COMPLETE_TIMEOUT 30000 /* in milli sec, 30 secs */ 161#define SIS_POLL_START_WAIT_TIME 20000 /* in micro sec, 20 milli sec */ 162#define SIS_DB_BIT_CLEAR_TIMEOUT_CNT 120000 /* 500usec * 120000 = 60 sec */ 163 164#define SIS_ENABLE_TIMEOUT 3000 165#define REENABLE_SIS 0x1 166#define TRIGGER_NMI_SIS 0x800000 167/*SIS Register status defines */ 168 169#define PQI_CTRL_KERNEL_UP_AND_RUNNING 0x80 170#define PQI_CTRL_KERNEL_PANIC 0x100 171 172#define SIS_CTL_TO_HOST_DB_DISABLE_ALL 0xFFFFFFFF 173#define SIS_CTL_TO_HOST_DB_CLEAR 0x00001000 174#define SIS_CMD_SUBMIT 0x00000200 /* Bit 9 */ 175#define SIS_CMD_COMPLETE 0x00001000 /* Bit 12 */ 176#define SIS_CMD_STATUS_SUCCESS 0x1 177 178/* PQI specific */ 179 180/* defines */ 181#define PQISRC_PQI_REG_OFFSET 0x4000 182#define PQISRC_MAX_OUTSTANDING_REQ 4096 183#define PQISRC_MAX_ADMIN_IB_QUEUE_ELEM_NUM 16 184#define PQISRC_MAX_ADMIN_OB_QUEUE_ELEM_NUM 16 185 186 187 188#define PQI_MIN_OP_IB_QUEUE_ID 1 189#define PQI_OP_EVENT_QUEUE_ID 1 190#define PQI_MIN_OP_OB_QUEUE_ID 2 191 192#define PQISRC_MAX_SUPPORTED_OP_IB_Q 128 193#define PQISRC_MAX_SUPPORTED_OP_RAID_IB_Q (PQISRC_MAX_SUPPORTED_OP_IB_Q / 2) 194#define PQISRC_MAX_SUPPORTED_OP_AIO_IB_Q (PQISRC_MAX_SUPPORTED_OP_RAID_IB_Q) 195#define PQISRC_MAX_OP_IB_QUEUE_ELEM_NUM (PQISRC_MAX_OUTSTANDING_REQ / PQISRC_MAX_SUPPORTED_OP_IB_Q) 196#define PQISRC_MAX_OP_OB_QUEUE_ELEM_NUM PQISRC_MAX_OUTSTANDING_REQ 197#define PQISRC_MIN_OP_OB_QUEUE_ELEM_NUM 2 198#define PQISRC_MAX_SUPPORTED_OP_OB_Q 64 199#define PQISRC_OP_MAX_IBQ_ELEM_SIZE 8 /* 8 * 16 = 128 bytes */ 200#define PQISRC_OP_MIN_IBQ_ELEM_SIZE 2 /* 2 * 16 = 32 bytes */ 201#define PQISRC_OP_OBQ_ELEM_SIZE 1 /* 16 bytes */ 202#define PQISRC_ADMIN_IBQ_ELEM_SIZE 2 /* 2 * 16 = 32 bytes */ 203#define PQISRC_INTR_COALSC_GRAN 0 204#define PQISRC_PROTO_BIT_MASK 0 205#define PQISRC_SGL_SUPPORTED_BIT_MASK 0 206 207#define PQISRC_NUM_EVENT_Q_ELEM 32 208#define PQISRC_EVENT_Q_ELEM_SIZE 32 209 210/* PQI Registers state status */ 211 212#define PQI_RESET_ACTION_RESET 0x1 213#define PQI_RESET_ACTION_COMPLETED 0x2 214#define PQI_RESET_TYPE_NO_RESET 0x0 215#define PQI_RESET_TYPE_SOFT_RESET 0x1 216#define PQI_RESET_TYPE_FIRM_RESET 0x2 217#define PQI_RESET_TYPE_HARD_RESET 0x3 218 219#define PQI_RESET_POLL_INTERVAL 100000 /*100 msec*/ 220 221enum pqisrc_ctrl_mode{ 222 CTRL_SIS_MODE = 0, 223 CTRL_PQI_MODE 224}; 225 226/* PQI device performing internal initialization (e.g., POST). */ 227#define PQI_DEV_STATE_POWER_ON_AND_RESET 0x0 228/* Upon entry to this state PQI device initialization begins. */ 229#define PQI_DEV_STATE_PQI_STATUS_AVAILABLE 0x1 230/* PQI device Standard registers are available to the driver. */ 231#define PQI_DEV_STATE_ALL_REGISTERS_READY 0x2 232/* PQI device is initialized and ready to process any PCI transactions. */ 233#define PQI_DEV_STATE_ADMIN_QUEUE_PAIR_READY 0x3 234/* The PQI Device Error register indicates the error. */ 235#define PQI_DEV_STATE_ERROR 0x4 236 237#define PQI_DEV_STATE_AT_INIT ( PQI_DEV_STATE_PQI_STATUS_AVAILABLE | \ 238 PQI_DEV_STATE_ALL_REGISTERS_READY | \ 239 PQI_DEV_STATE_ADMIN_QUEUE_PAIR_READY ) 240 241#define PQISRC_PQI_DEVICE_SIGNATURE "PQI DREG" 242#define PQI_ADMINQ_ELEM_ARRAY_ALIGN 64 243#define PQI_ADMINQ_CI_PI_ALIGN 64 244#define PQI_OPQ_ELEM_ARRAY_ALIGN 64 245#define PQI_OPQ_CI_PI_ALIGN 4 246#define PQI_ADDR_ALIGN_MASK_64 0x3F /* lsb 6 bits */ 247#define PQI_ADDR_ALIGN_MASK_4 0x3 /* lsb 2 bits */ 248 249#define PQISRC_PQIMODE_READY_TIMEOUT (30 * 1000 ) /* 30 secs */ 250#define PQISRC_MODE_READY_POLL_INTERVAL 1000 /* 1 msec */ 251 252#define PRINT_PQI_SIGNATURE(sign) { int i = 0; \ 253 char si[9]; \ 254 for(i=0;i<8;i++) \ 255 si[i] = *((char *)&(sign)+i); \ 256 si[i] = '\0'; \ 257 DBG_INFO("Signature is %s",si); \ 258 } 259#define PQI_CONF_TABLE_MAX_LEN ((uint16_t)~0) 260#define PQI_CONF_TABLE_SIGNATURE "CFGTABLE" 261 262/* PQI configuration table section IDs */ 263#define PQI_CONF_TABLE_SECTION_GENERAL_INFO 0 264#define PQI_CONF_TABLE_SECTION_FIRMWARE_FEATURES 1 265#define PQI_CONF_TABLE_SECTION_FIRMWARE_ERRATA 2 266#define PQI_CONF_TABLE_SECTION_DEBUG 3 267#define PQI_CONF_TABLE_SECTION_HEARTBEAT 4 268 269#define CTRLR_HEARTBEAT_CNT(softs) LE_64(PCI_MEM_GET64(softs, softs->heartbeat_counter_abs_addr, softs->heartbeat_counter_off)) 270#define PQI_NEW_HEARTBEAT_MECHANISM(softs) 1 271 272 /* pqi-2r00a table 36 */ 273#define PQI_ADMIN_QUEUE_MSIX_DISABLE (0x80000000) 274#define PQI_ADMIN_QUEUE_MSIX_ENABLE (0 << 31) 275 276#define PQI_ADMIN_QUEUE_CONF_FUNC_CREATE_Q_PAIR 0x01 277#define PQI_ADMIN_QUEUE_CONF_FUNC_DEL_Q_PAIR 0x02 278#define PQI_ADMIN_QUEUE_CONF_FUNC_STATUS_IDLE 0x00 279#define PQISRC_ADMIN_QUEUE_CREATE_TIMEOUT 1000 /* in miLLI sec, 1 sec, 100 ms is standard */ 280#define PQISRC_ADMIN_QUEUE_DELETE_TIMEOUT 100 /* 100 ms is standard */ 281#define PQISRC_ADMIN_CMD_RESP_TIMEOUT 3000 /* 3 sec */ 282#define PQISRC_RAIDPATH_CMD_TIMEOUT 30000 /* 30 sec */ 283 284#define REPORT_PQI_DEV_CAP_DATA_BUF_SIZE sizeof(pqi_dev_cap_t) 285#define REPORT_MANUFACTURER_INFO_DATA_BUF_SIZE 0x80 /* Data buffer size specified in bytes 0-1 of data buffer. 128 bytes. */ 286/* PQI IUs */ 287/* Admin IU request length not including header. */ 288#define PQI_STANDARD_IU_LENGTH 0x003C /* 60 bytes. */ 289#define PQI_IU_TYPE_GENERAL_ADMIN_REQUEST 0x60 290#define PQI_IU_TYPE_GENERAL_ADMIN_RESPONSE 0xe0 291 292/* PQI / Vendor specific IU */ 293#define PQI_FUNCTION_REPORT_DEV_CAP 0x00 294#define PQI_REQUEST_IU_TASK_MANAGEMENT 0x13 295#define PQI_IU_TYPE_RAID_PATH_IO_REQUEST 0x14 296#define PQI_IU_TYPE_AIO_PATH_IO_REQUEST 0x15 297#define PQI_REQUEST_IU_GENERAL_ADMIN 0x60 298#define PQI_REQUEST_IU_REPORT_VENDOR_EVENT_CONFIG 0x72 299#define PQI_REQUEST_IU_SET_VENDOR_EVENT_CONFIG 0x73 300#define PQI_RESPONSE_IU_GENERAL_MANAGEMENT 0x81 301#define PQI_RESPONSE_IU_TASK_MANAGEMENT 0x93 302#define PQI_RESPONSE_IU_GENERAL_ADMIN 0xe0 303 304#define PQI_RESPONSE_IU_RAID_PATH_IO_SUCCESS 0xf0 305#define PQI_RESPONSE_IU_AIO_PATH_IO_SUCCESS 0xf1 306#define PQI_RESPONSE_IU_RAID_PATH_IO_ERROR 0xf2 307#define PQI_RESPONSE_IU_AIO_PATH_IO_ERROR 0xf3 308#define PQI_RESPONSE_IU_AIO_PATH_IS_OFF 0xf4 309#define PQI_REQUEST_IU_ACKNOWLEDGE_VENDOR_EVENT 0xf6 310#define PQI_REQUEST_HEADER_LENGTH 4 311#define PQI_FUNCTION_CREATE_OPERATIONAL_IQ 0x10 312#define PQI_FUNCTION_CREATE_OPERATIONAL_OQ 0x11 313#define PQI_FUNCTION_DELETE_OPERATIONAL_IQ 0x12 314#define PQI_FUNCTION_DELETE_OPERATIONAL_OQ 0x13 315#define PQI_FUNCTION_CHANGE_OPERATIONAL_IQ_PROP 0x14 316#define PQI_CHANGE_OP_IQ_PROP_ASSIGN_AIO 1 317 318#define PQI_DEFAULT_IB_QUEUE 0 319/* Interface macros */ 320 321#define GET_FW_STATUS(softs) \ 322 (PCI_MEM_GET32(softs, &softs->ioa_reg->scratchpad3_fw_status, LEGACY_SIS_OMR)) 323 324#define SIS_IS_KERNEL_PANIC(softs) \ 325 (GET_FW_STATUS(softs) & PQI_CTRL_KERNEL_PANIC) 326 327#define SIS_IS_KERNEL_UP(softs) \ 328 (GET_FW_STATUS(softs) & PQI_CTRL_KERNEL_UP_AND_RUNNING) 329 330#define PQI_GET_CTRL_MODE(softs) \ 331 (PCI_MEM_GET32(softs, &softs->ioa_reg->scratchpad0, LEGACY_SIS_SCR0)) 332 333#define PQI_SAVE_CTRL_MODE(softs, mode) \ 334 PCI_MEM_PUT32(softs, &softs->ioa_reg->scratchpad0, LEGACY_SIS_SCR0, mode) 335 336#define PQISRC_MAX_TARGETID 1024 337#define PQISRC_MAX_TARGETLUN 64 338 339/* Vendor specific IU Type for Event config Cmds */ 340#define PQI_REQUEST_IU_REPORT_EVENT_CONFIG 0x72 341#define PQI_REQUEST_IU_SET_EVENT_CONFIG 0x73 342#define PQI_REQUEST_IU_ACKNOWLEDGE_VENDOR_EVENT 0xf6 343#define PQI_RESPONSE_IU_GENERAL_MANAGEMENT 0x81 344#define PQI_MANAGEMENT_CMD_RESP_TIMEOUT 3000 345#define PQISRC_EVENT_ACK_RESP_TIMEOUT 1000 346 347 348/* Supported Event types by controller */ 349#define PQI_NUM_SUPPORTED_EVENTS 7 350 351#define PQI_EVENT_TYPE_HOTPLUG 0x1 352#define PQI_EVENT_TYPE_HARDWARE 0x2 353#define PQI_EVENT_TYPE_PHYSICAL_DEVICE 0x4 354#define PQI_EVENT_TYPE_LOGICAL_DEVICE 0x5 355#define PQI_EVENT_TYPE_AIO_STATE_CHANGE 0xfd 356#define PQI_EVENT_TYPE_AIO_CONFIG_CHANGE 0xfe 357#define PQI_EVENT_TYPE_HEARTBEAT 0xff 358 359/* for indexing into the pending_events[] field of struct pqisrc_softstate */ 360#define PQI_EVENT_HEARTBEAT 0 361#define PQI_EVENT_HOTPLUG 1 362#define PQI_EVENT_HARDWARE 2 363#define PQI_EVENT_PHYSICAL_DEVICE 3 364#define PQI_EVENT_LOGICAL_DEVICE 4 365#define PQI_EVENT_AIO_STATE_CHANGE 5 366#define PQI_EVENT_AIO_CONFIG_CHANGE 6 367 368#define PQI_MAX_HEARTBEAT_REQUESTS 5 369 370 371/* Device flags */ 372#define PQISRC_DFLAG_VALID (1 << 0) 373#define PQISRC_DFLAG_CONFIGURING (1 << 1) 374 375#define MAX_EMBEDDED_SG_IN_FIRST_IU 4 376#define MAX_EMBEDDED_SG_IN_IU 8 377#define SG_FLAG_LAST 0x40000000 378#define SG_FLAG_CHAIN 0x80000000 379 380#define IN_PQI_RESET(softs) (softs->ctlr_state & PQI_BUS_RESET) 381#define DEV_GONE(dev) (!dev || (dev->invalid == true)) 382#define IS_AIO_PATH(dev) (dev->aio_enabled) 383#define IS_RAID_PATH(dev) (!dev->aio_enabled) 384 385/* SOP data direction flags */ 386#define SOP_DATA_DIR_NONE 0x00 387#define SOP_DATA_DIR_FROM_DEVICE 0x01 388#define SOP_DATA_DIR_TO_DEVICE 0x02 389#define SOP_DATA_DIR_BIDIRECTIONAL 0x03 390#define SOP_PARTIAL_DATA_BUFFER 0x04 391 392#define PQISRC_DMA_VALID (1 << 0) 393#define PQISRC_CMD_NO_INTR (1 << 1) 394 395#define SOP_TASK_ATTRIBUTE_SIMPLE 0 396#define SOP_TASK_ATTRIBUTE_HEAD_OF_QUEUE 1 397#define SOP_TASK_ATTRIBUTE_ORDERED 2 398#define SOP_TASK_ATTRIBUTE_ACA 4 399 400#define SOP_TASK_MANAGEMENT_FUNCTION_COMPLETE 0x0 401#define SOP_TASK_MANAGEMENT_FUNCTION_REJECTED 0x4 402#define SOP_TASK_MANAGEMENT_FUNCTION_FAILED 0x5 403#define SOP_TASK_MANAGEMENT_FUNCTION_SUCCEEDED 0x8 404#define SOP_TASK_MANAGEMENT_FUNCTION_ABORT_TASK 0x01 405#define SOP_TASK_MANAGEMENT_FUNCTION_ABORT_TASK_SET 0x02 406#define SOP_TASK_MANAGEMENT_LUN_RESET 0x8 407 408 409/* Additional CDB bytes */ 410#define PQI_ADDITIONAL_CDB_BYTES_0 0 /* 16 byte CDB */ 411#define PQI_ADDITIONAL_CDB_BYTES_4 1 /* 20 byte CDB */ 412#define PQI_ADDITIONAL_CDB_BYTES_8 2 /* 24 byte CDB */ 413#define PQI_ADDITIONAL_CDB_BYTES_12 3 /* 28 byte CDB */ 414#define PQI_ADDITIONAL_CDB_BYTES_16 4 /* 32 byte CDB */ 415 416#define PQI_PROTOCOL_SOP 0x0 417 418#define PQI_AIO_STATUS_GOOD 0x0 419#define PQI_AIO_STATUS_CHECK_CONDITION 0x2 420#define PQI_AIO_STATUS_CONDITION_MET 0x4 421#define PQI_AIO_STATUS_DEVICE_BUSY 0x8 422#define PQI_AIO_STATUS_INT_GOOD 0x10 423#define PQI_AIO_STATUS_INT_COND_MET 0x14 424#define PQI_AIO_STATUS_RESERV_CONFLICT 0x18 425#define PQI_AIO_STATUS_CMD_TERMINATED 0x22 426#define PQI_AIO_STATUS_QUEUE_FULL 0x28 427#define PQI_AIO_STATUS_TASK_ABORTED 0x40 428#define PQI_AIO_STATUS_UNDERRUN 0x51 429#define PQI_AIO_STATUS_OVERRUN 0x75 430/* Status when Target Failure */ 431#define PQI_AIO_STATUS_IO_ERROR 0x1 432#define PQI_AIO_STATUS_IO_ABORTED 0x2 433#define PQI_AIO_STATUS_IO_NO_DEVICE 0x3 434#define PQI_AIO_STATUS_INVALID_DEVICE 0x4 435#define PQI_AIO_STATUS_AIO_PATH_DISABLED 0xe 436 437/* Service Response */ 438#define PQI_AIO_SERV_RESPONSE_COMPLETE 0 439#define PQI_AIO_SERV_RESPONSE_FAILURE 1 440#define PQI_AIO_SERV_RESPONSE_TMF_COMPLETE 2 441#define PQI_AIO_SERV_RESPONSE_TMF_SUCCEEDED 3 442#define PQI_AIO_SERV_RESPONSE_TMF_REJECTED 4 443#define PQI_AIO_SERV_RESPONSE_TMF_INCORRECT_LUN 5 444 445#define PQI_TMF_WAIT_DELAY 10000000 /* 10 seconds */ 446 447#define PQI_RAID_STATUS_GOOD PQI_AIO_STATUS_GOOD 448#define PQI_RAID_STATUS_CHECK_CONDITION PQI_AIO_STATUS_CHECK_CONDITION 449#define PQI_RAID_STATUS_CONDITION_MET PQI_AIO_STATUS_CONDITION_MET 450#define PQI_RAID_STATUS_DEVICE_BUSY PQI_AIO_STATUS_DEVICE_BUSY 451#define PQI_RAID_STATUS_INT_GOOD PQI_AIO_STATUS_INT_GOOD 452#define PQI_RAID_STATUS_INT_COND_MET PQI_AIO_STATUS_INT_COND_MET 453#define PQI_RAID_STATUS_RESERV_CONFLICT PQI_AIO_STATUS_RESERV_CONFLICT 454#define PQI_RAID_STATUS_CMD_TERMINATED PQI_AIO_STATUS_CMD_TERMINATED 455#define PQI_RAID_STATUS_QUEUE_FULL PQI_AIO_STATUS_QUEUE_FULL 456#define PQI_RAID_STATUS_TASK_ABORTED PQI_AIO_STATUS_TASK_ABORTED 457#define PQI_RAID_STATUS_UNDERRUN PQI_AIO_STATUS_UNDERRUN 458#define PQI_RAID_STATUS_OVERRUN PQI_AIO_STATUS_OVERRUN 459 460/* VPD inquiry pages */ 461#define SCSI_VPD_SUPPORTED_PAGES 0x0 /* standard page */ 462#define SCSI_VPD_DEVICE_ID 0x83 /* standard page */ 463#define SA_VPD_PHYS_DEVICE_ID 0xc0 /* vendor-specific page */ 464#define SA_VPD_LV_DEVICE_GEOMETRY 0xc1 /* vendor-specific page */ 465#define SA_VPD_LV_IOACCEL_STATUS 0xc2 /* vendor-specific page */ 466#define SA_VPD_LV_STATUS 0xc3 /* vendor-specific page */ 467 468#define VPD_PAGE (1 << 8) 469 470 471/* logical volume states */ 472#define SA_LV_OK 0x0 473#define SA_LV_NOT_AVAILABLE 0xb 474#define SA_LV_UNDERGOING_ERASE 0xf 475#define SA_LV_UNDERGOING_RPI 0x12 476#define SA_LV_PENDING_RPI 0x13 477#define SA_LV_ENCRYPTED_NO_KEY 0x14 478#define SA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER 0x15 479#define SA_LV_UNDERGOING_ENCRYPTION 0x16 480#define SA_LV_UNDERGOING_ENCRYPTION_REKEYING 0x17 481#define SA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER 0x18 482#define SA_LV_PENDING_ENCRYPTION 0x19 483#define SA_LV_PENDING_ENCRYPTION_REKEYING 0x1a 484#define SA_LV_STATUS_VPD_UNSUPPORTED 0xff 485 486/* 487 * assume worst case: SATA queue depth of 31 minus 4 internal firmware commands 488 */ 489#define PQI_PHYSICAL_DISK_DEFAULT_MAX_QUEUE_DEPTH 27 490 491/* 0 = no limit */ 492#define PQI_LOGICAL_DISK_DEFAULT_MAX_QUEUE_DEPTH 0 493 494 495 496#define RAID_CTLR_LUNID "\0\0\0\0\0\0\0\0" 497 498#define SA_CACHE_FLUSH 0x1 499#define SA_INQUIRY 0x12 500#define SA_REPORT_LOG 0xc2 /* Report Logical LUNs */ 501#define SA_REPORT_PHYS 0xc3 /* Report Physical LUNs */ 502#define SA_CISS_READ 0xc0 503#define SA_GET_RAID_MAP 0xc8 504 505#define SA_REPORT_LOG_EXTENDED 0x1 506#define SA_REPORT_PHYS_EXTENDED 0x2 507 508#define SA_CACHE_FLUSH_BUF_LEN 4 509 510#define REPORT_LUN_DEV_FLAG_AIO_ENABLED 0x8 511#define PQI_MAX_TRANSFER_SIZE (4 * 1024U * 1024U) 512#define RAID_MAP_MAX_ENTRIES 1024 513#define RAID_MAP_ENCRYPTION_ENABLED 0x1 514#define PQI_PHYSICAL_DISK_DEFAULT_MAX_QUEUE_DEPTH 27 515 516#define ASC_LUN_NOT_READY 0x4 517#define ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS 0x4 518#define ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ 0x2 519 520 521#define OBDR_SIG_OFFSET 43 522#define OBDR_TAPE_SIG "$DR-10" 523#define OBDR_SIG_LEN (sizeof(OBDR_TAPE_SIG) - 1) 524#define OBDR_TAPE_INQ_SIZE (OBDR_SIG_OFFSET + OBDR_SIG_LEN) 525 526 527#define IOACCEL_STATUS_BYTE 4 528#define OFFLOAD_CONFIGURED_BIT 0x1 529#define OFFLOAD_ENABLED_BIT 0x2 530 531#define PQI_RAID_DATA_IN_OUT_GOOD 0x0 532#define PQI_RAID_DATA_IN_OUT_UNDERFLOW 0x1 533#define PQI_RAID_DATA_IN_OUT_UNSOLICITED_ABORT 0xf3 534#define PQI_RAID_DATA_IN_OUT_ABORTED 0xf4 535 536#define PQI_PHYSICAL_DEVICE_BUS 0 537#define PQI_RAID_VOLUME_BUS 1 538#define PQI_HBA_BUS 2 539#define PQI_EXTERNAL_RAID_VOLUME_BUS 3 540#define PQI_MAX_BUS PQI_EXTERNAL_RAID_VOLUME_BUS 541 542#define TEST_UNIT_READY 0x00 543#define SCSI_VPD_HEADER_LENGTH 64 544 545 546#define PQI_MAX_MULTILUN 256 547#define PQI_MAX_LOGICALS 64 548#define PQI_MAX_PHYSICALS 1024 549#define PQI_MAX_DEVICES (PQI_MAX_LOGICALS + PQI_MAX_PHYSICALS + 1) /* 1 for controller device entry */ 550 551 552#define PQI_CTLR_INDEX (PQI_MAX_DEVICES - 1) 553#define PQI_PD_INDEX(t) (t + PQI_MAX_LOGICALS) 554 555#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) 556#define MAX_TARGET_DEVICES 1024 557 558#define PQI_NO_MEM 2 559 560typedef enum pqisrc_device_status { 561 DEVICE_NOT_FOUND, 562 DEVICE_CHANGED, 563 DEVICE_UNCHANGED, 564} device_status_t; 565 566#define SA_RAID_0 0 567#define SA_RAID_4 1 568#define SA_RAID_1 2 /* also used for RAID 10 */ 569#define SA_RAID_5 3 /* also used for RAID 50 */ 570#define SA_RAID_51 4 571#define SA_RAID_6 5 /* also used for RAID 60 */ 572#define SA_RAID_ADM 6 /* also used for RAID 1+0 ADM */ 573#define SA_RAID_MAX SA_RAID_ADM 574#define SA_RAID_UNKNOWN 0xff 575 576/* BMIC commands */ 577#define BMIC_IDENTIFY_CONTROLLER 0x11 578#define BMIC_IDENTIFY_PHYSICAL_DEVICE 0x15 579#define BMIC_READ 0x26 580#define BMIC_WRITE 0x27 581#define BMIC_SENSE_CONTROLLER_PARAMETERS 0x64 582#define BMIC_SENSE_SUBSYSTEM_INFORMATION 0x66 583#define BMIC_CACHE_FLUSH 0xc2 584#define BMIC_FLASH_FIRMWARE 0xf7 585#define BMIC_WRITE_HOST_WELLNESS 0xa5 586 587 588#define MASKED_DEVICE(lunid) ((lunid)[3] & 0xC0) 589#define BMIC_GET_LEVEL_2_BUS(lunid) ((lunid)[7] & 0x3F) 590#define BMIC_GET_LEVEL_TWO_TARGET(lunid) ((lunid)[6]) 591#define BMIC_GET_DRIVE_NUMBER(lunid) \ 592 (((BMIC_GET_LEVEL_2_BUS((lunid)) - 1) << 8) + \ 593 BMIC_GET_LEVEL_TWO_TARGET((lunid))) 594#define NON_DISK_PHYS_DEV(rle) \ 595 (((reportlun_ext_entry_t *)(rle))->device_flags & 0x1) 596 597#define NO_TIMEOUT ((unsigned long) -1) 598 599#define BMIC_DEVICE_TYPE_SATA 0x1 600 601/* No of IO slots required for internal requests */ 602#define PQI_RESERVED_IO_SLOTS_SYNC_REQUESTS 3 603#define PQI_RESERVED_IO_SLOTS_TMF 1 604#define PQI_RESERVED_IO_SLOTS_CNT (PQI_NUM_SUPPORTED_EVENTS + \ 605 PQI_RESERVED_IO_SLOTS_TMF + \ 606 PQI_RESERVED_IO_SLOTS_SYNC_REQUESTS) 607 608static inline uint16_t GET_LE16(const uint8_t *p) 609{ 610 return p[0] | p[1] << 8; 611} 612 613static inline uint32_t GET_LE32(const uint8_t *p) 614{ 615 return p[0] | p[1] << 8 | p[2] << 16 | p[3] << 24; 616} 617 618static inline uint64_t GET_LE64(const uint8_t *p) 619{ 620 return (((uint64_t)GET_LE32(p + 4) << 32) | 621 GET_LE32(p)); 622} 623 624static inline uint16_t GET_BE16(const uint8_t *p) 625{ 626 return p[0] << 8 | p[1]; 627} 628 629static inline uint32_t GET_BE32(const uint8_t *p) 630{ 631 return p[0] << 24 | p[1] << 16 | p[2] << 8 | p[3]; 632} 633 634static inline uint64_t GET_BE64(const uint8_t *p) 635{ 636 return (((uint64_t)GET_BE32(p) << 32) | 637 GET_BE32(p + 4)); 638} 639 640static inline void PUT_BE16(uint16_t val, uint8_t *p) 641{ 642 *p++ = val >> 8; 643 *p++ = val; 644} 645 646static inline void PUT_BE32(uint32_t val, uint8_t *p) 647{ 648 PUT_BE16(val >> 16, p); 649 PUT_BE16(val, p + 2); 650} 651 652static inline void PUT_BE64(uint64_t val, uint8_t *p) 653{ 654 PUT_BE32(val >> 32, p); 655 PUT_BE32(val, p + 4); 656} 657 658 659#define OS_FREEBSD 660#define SIS_POLL_WAIT 661 662#define OS_ATTRIBUTE_PACKED __attribute__((__packed__)) 663#define OS_ATTRIBUTE_ALIGNED(n) __attribute__((aligned(n))) 664 665 666/* Management Interface */ 667#define CCISS_IOC_MAGIC 'C' 668#define SMARTPQI_IOCTL_BASE 'M' 669#define CCISS_GETDRIVVER _IOWR(SMARTPQI_IOCTL_BASE, 0, driver_info) 670#define CCISS_GETPCIINFO _IOWR(SMARTPQI_IOCTL_BASE, 1, pqi_pci_info_t) 671#define SMARTPQI_PASS_THRU _IOWR(SMARTPQI_IOCTL_BASE, 2, IOCTL_Command_struct) 672#define CCISS_PASSTHRU _IOWR('C', 210, IOCTL_Command_struct) 673#define CCISS_REGNEWD _IO(CCISS_IOC_MAGIC, 14) 674 675/*IOCTL pci_info structure */ 676typedef struct pqi_pci_info 677{ 678 unsigned char bus; 679 unsigned char dev_fn; 680 unsigned short domain; 681 uint32_t board_id; 682 uint32_t chip_id; 683}pqi_pci_info_t; 684 685typedef struct _driver_info 686{ 687 unsigned char major_version; 688 unsigned char minor_version; 689 unsigned char release_version; 690 unsigned long build_revision; 691 unsigned long max_targets; 692 unsigned long max_io; 693 unsigned long max_transfer_length; 694}driver_info, *pdriver_info; 695 696typedef uint8_t *passthru_buf_type_t; 697 698 699#define PQISRC_DRIVER_MAJOR 1 700#define PQISRC_DRIVER_MINOR 0 701#define PQISRC_DRIVER_RELEASE 1 702# define PQISRC_DRIVER_REVISION 239 703 704#define STR(s) # s 705#define PQISRC_VERSION(a, b, c, d) STR(a.b.c-d) 706#define PQISRC_DRIVER_VERSION PQISRC_VERSION(PQISRC_DRIVER_MAJOR, \ 707 PQISRC_DRIVER_MINOR, \ 708 PQISRC_DRIVER_RELEASE, \ 709 PQISRC_DRIVER_REVISION) 710 711/* End Management interface */ 712 713#ifdef ASSERT 714#undef ASSERT 715#endif 716 717#define ASSERT(cond) {\ 718 if (!(cond)) { \ 719 printf("Assertion failed at file %s line %d\n",__FILE__,__LINE__); \ 720 } \ 721 } 722 723 724#define PQI_MAX_MSIX 64 /* vectors */ 725#define PQI_MSI_CTX_SIZE sizeof(pqi_intr_ctx)+1 726#define IS_POLLING_REQUIRED(softs) if (cold) {\ 727 pqisrc_process_event_intr_src(softs, 0);\ 728 pqisrc_process_response_queue(softs, 1);\ 729 } 730 731#define OS_GET_TASK_ATTR(rcb) os_get_task_attr(rcb) 732#define OS_FW_HEARTBEAT_TIMER_INTERVAL (5) 733 734typedef struct PCI_ACC_HANDLE { 735 bus_space_tag_t pqi_btag; 736 bus_space_handle_t pqi_bhandle; 737} PCI_ACC_HANDLE_T; 738 739/* 740 * Legacy SIS Register definitions for the Adaptec PMC SRC/SRCv/smartraid adapters. 741 */ 742/* accessible via BAR0 */ 743#define LEGACY_SIS_IOAR 0x18 /* IOA->host interrupt register */ 744#define LEGACY_SIS_IDBR 0x20 /* inbound doorbell register */ 745#define LEGACY_SIS_IISR 0x24 /* inbound interrupt status register */ 746#define LEGACY_SIS_OIMR 0x34 /* outbound interrupt mask register */ 747#define LEGACY_SIS_ODBR_R 0x9c /* outbound doorbell register read */ 748#define LEGACY_SIS_ODBR_C 0xa0 /* outbound doorbell register clear */ 749 750#define LEGACY_SIS_SCR0 0xb0 /* scratchpad 0 */ 751#define LEGACY_SIS_OMR 0xbc /* outbound message register */ 752#define LEGACY_SIS_IQUE64_L 0xc0 /* inbound queue address 64-bit (low) */ 753#define LEGACY_SIS_IQUE64_H 0xc4 /* inbound queue address 64-bit (high)*/ 754#define LEGACY_SIS_ODBR_MSI 0xc8 /* MSI register for sync./AIF */ 755#define LEGACY_SIS_IQN_L 0xd0 /* inbound queue native mode (low) */ 756#define LEGACY_SIS_IQN_H 0xd4 /* inbound queue native mode (high)*/ 757#define LEGACY_SIS_MAILBOX 0x7fc60 /* mailbox (20 bytes) */ 758#define LEGACY_SIS_SRCV_MAILBOX 0x1000 /* mailbox (20 bytes) */ 759 760#define LEGACY_SIS_ODR_SHIFT 12 /* outbound doorbell shift */ 761#define LEGACY_SIS_IDR_SHIFT 9 /* inbound doorbell shift */ 762 763 764/* 765 * PQI Register definitions for the smartraid adapters 766 */ 767/* accessible via BAR0 */ 768#define PQI_SIGNATURE 0x4000 769#define PQI_ADMINQ_CONFIG 0x4008 770#define PQI_ADMINQ_CAP 0x4010 771#define PQI_LEGACY_INTR_STATUS 0x4018 772#define PQI_LEGACY_INTR_MASK_SET 0x401C 773#define PQI_LEGACY_INTR_MASK_CLR 0x4020 774#define PQI_DEV_STATUS 0x4040 775#define PQI_ADMIN_IBQ_PI_OFFSET 0x4048 776#define PQI_ADMIN_OBQ_CI_OFFSET 0x4050 777#define PQI_ADMIN_IBQ_ELEM_ARRAY_ADDR 0x4058 778#define PQI_ADMIN_OBQ_ELEM_ARRAY_ADDR 0x4060 779#define PQI_ADMIN_IBQ_CI_ADDR 0x4068 780#define PQI_ADMIN_OBQ_PI_ADDR 0x4070 781#define PQI_ADMINQ_PARAM 0x4078 782#define PQI_DEV_ERR 0x4080 783#define PQI_DEV_ERR_DETAILS 0x4088 784#define PQI_DEV_RESET 0x4090 785#define PQI_POWER_ACTION 0x4094 786 787/* Busy wait micro seconds */ 788#define OS_BUSYWAIT(x) DELAY(x) 789#define OS_SLEEP(timeout) \ 790 DELAY(timeout); 791 792#define OS_HOST_WELLNESS_TIMEOUT (24 * 3600) 793 794 795#define LE_16(x) htole16(x) 796#define LE_32(x) htole32(x) 797#define LE_64(x) htole64(x) 798#define BE_16(x) htobe16(x) 799#define BE_32(x) htobe32(x) 800#define BE_64(x) htobe64(x) 801 802#define PQI_HWIF_SRCV 0 803#define PQI_HWIF_UNKNOWN -1 804 805 806#define SMART_STATE_SUSPEND (1<<0) 807#define SMART_STATE_UNUSED0 (1<<1) 808#define SMART_STATE_INTERRUPTS_ON (1<<2) 809#define SMART_STATE_AIF_SLEEPER (1<<3) 810#define SMART_STATE_RESET (1<<4) 811 812#define PQI_FLAG_BUSY (1<<0) 813#define PQI_MSI_ENABLED (1<<1) 814#define PQI_SIM_REGISTERED (1<<2) 815#define PQI_MTX_INIT (1<<3) 816 817 818#define PQI_CMD_MAPPED (1<<2) 819 820/* Interrupt context to get oq_id */ 821typedef struct pqi_intr_ctx { 822 int oq_id; 823 device_t pqi_dev; 824}pqi_intr_ctx_t; 825 826typedef uint8_t os_dev_info_t; 827 828typedef struct OS_SPECIFIC { 829 device_t pqi_dev; 830 struct resource *pqi_regs_res0; /* reg. if. window */ 831 int pqi_regs_rid0; /* resource ID */ 832 bus_dma_tag_t pqi_parent_dmat; /* parent DMA tag */ 833 bus_dma_tag_t pqi_buffer_dmat; 834 835 /* controller hardware interface */ 836 int pqi_hwif; 837 struct resource *pqi_irq[PQI_MAX_MSIX]; /* interrupt */ 838 int pqi_irq_rid[PQI_MAX_MSIX]; 839 void *intrcookie[PQI_MAX_MSIX]; 840 bool intr_registered[PQI_MAX_MSIX]; 841 bool msi_enabled; /* MSI/MSI-X enabled */ 842 pqi_intr_ctx_t *msi_ctx; 843 int oq_id; 844 int pqi_state; 845 uint32_t pqi_flags; 846 struct mtx cam_lock; 847 struct mtx map_lock; 848 int mtx_init; 849 int sim_registered; 850 struct cam_devq *devq; 851 struct cam_sim *sim; 852 struct cam_path *path; 853 struct task event_task; 854 struct cdev *cdev; 855 struct callout_handle wellness_periodic; /* periodic event handling */ 856 struct callout_handle heartbeat_timeout_id; /* heart beat event handling */ 857 eventhandler_tag eh; 858} OS_SPECIFIC_T; 859 860typedef bus_addr_t dma_addr_t; 861 862/* Atomic */ 863typedef volatile uint64_t OS_ATOMIC64_T; 864#define OS_ATOMIC64_SET(_softs, target, val) atomic_set_long(&(_softs)->target, val) 865#define OS_ATOMIC64_READ(_softs, target) atomic_load_acq_64(&(_softs)->target) 866#define OS_ATOMIC64_INC(_softs, target) atomic_add_64(&(_softs)->target, 1) 867 868/* Register access macros */ 869#define PCI_MEM_GET32( _softs, _absaddr, _offset ) \ 870 bus_space_read_4(_softs->pci_mem_handle.pqi_btag, \ 871 _softs->pci_mem_handle.pqi_bhandle, _offset) 872 873#define PCI_MEM_GET64( _softs, _absaddr, _offset ) \ 874 bus_space_read_8(_softs->pci_mem_handle.pqi_btag, \ 875 _softs->pci_mem_handle.pqi_bhandle, _offset) 876 877#define PCI_MEM_PUT32( _softs, _absaddr, _offset, _val ) \ 878 bus_space_write_4(_softs->pci_mem_handle.pqi_btag, \ 879 _softs->pci_mem_handle.pqi_bhandle, _offset, _val) 880 881#define PCI_MEM_PUT64( _softs, _absaddr, _offset, _val ) \ 882 bus_space_write_8(_softs->pci_mem_handle.pqi_btag, \ 883 _softs->pci_mem_handle.pqi_bhandle, _offset, _val) 884 885#define PCI_MEM_GET_BUF(_softs, _absaddr, _offset, buf, size) \ 886 bus_space_read_region_1(_softs->pci_mem_handle.pqi_btag,\ 887 _softs->pci_mem_handle.pqi_bhandle, _offset, buf, size) 888 889/* Lock */ 890typedef struct mtx OS_LOCK_T; 891typedef struct sema OS_SEMA_LOCK_T; 892 893#define OS_ACQUIRE_SPINLOCK(_lock) mtx_lock_spin(_lock) 894#define OS_RELEASE_SPINLOCK(_lock) mtx_unlock_spin(_lock) 895 896#define PQI_LOCK(_lock) OS_ACQUIRE_SPINLOCK(_lock) 897#define PQI_UNLOCK(_lock) OS_RELEASE_SPINLOCK(_lock) 898 899#define OS_INIT_PQILOCK(_softs,_lock,_lockname) os_init_spinlock(_softs,_lock,_lockname) 900#define OS_UNINIT_PQILOCK(_lock) os_uninit_spinlock(_lock) 901 902#define OS_GET_CDBP(rcb) ((rcb->cm_ccb->ccb_h.flags & CAM_CDB_POINTER) ? rcb->cm_ccb->csio.cdb_io.cdb_ptr : rcb->cm_ccb->csio.cdb_io.cdb_bytes) 903#define GET_SCSI_BUFFLEN(rcb) (rcb->cm_ccb->csio.dxfer_len) 904 905#define OS_GET_IO_QINDEX(softs,rcb) curcpu % softs->num_op_obq 906#define OS_GET_IO_RESP_QID(softs,rcb) (softs->op_ob_q[(OS_GET_IO_QINDEX(softs,rcb))].q_id) 907#define OS_GET_IO_REQ_QINDEX(softs,rcb) OS_GET_IO_QINDEX(softs,rcb) 908#define OS_GET_TMF_RESP_QID OS_GET_IO_RESP_QID 909#define OS_GET_TMF_REQ_QINDEX OS_GET_IO_REQ_QINDEX 910/* sg elements addr, len, flags */ 911#define OS_GET_IO_SG_COUNT(rcb) rcb->nseg 912#define OS_GET_IO_SG_ADDR(rcb,i) rcb->sgt[i].addr 913#define OS_GET_IO_SG_LEN(rcb,i) rcb->sgt[i].len 914 915/* scsi commands used in pqilib for RAID bypass*/ 916#define SCMD_READ_6 READ_6 917#define SCMD_WRITE_6 WRITE_6 918#define SCMD_READ_10 READ_10 919#define SCMD_WRITE_10 WRITE_10 920#define SCMD_READ_12 READ_12 921#define SCMD_WRITE_12 WRITE_12 922#define SCMD_READ_16 READ_16 923#define SCMD_WRITE_16 WRITE_16 924 925/* Debug facility */ 926 927#define PQISRC_LOG_LEVEL 0x30 928 929static int logging_level = PQISRC_LOG_LEVEL; 930 931#define PQISRC_FLAGS_MASK 0x0000ffff 932#define PQISRC_FLAGS_INIT 0x00000001 933#define PQISRC_FLAGS_INFO 0x00000002 934#define PQISRC_FLAGS_FUNC 0x00000004 935#define PQISRC_FLAGS_TRACEIO 0x00000008 936#define PQISRC_FLAGS_WARN 0x00000010 937#define PQISRC_FLAGS_ERROR 0x00000020 938 939 940#define DBG_INIT(fmt,args...) \ 941 do { \ 942 if (logging_level & PQISRC_FLAGS_INIT) { \ 943 printf("[INIT]:[ %s ] [ %d ]"fmt,__func__,__LINE__,##args); \ 944 } \ 945 }while(0); 946 947#define DBG_INFO(fmt,args...) \ 948 do { \ 949 if (logging_level & PQISRC_FLAGS_INFO) { \ 950 printf("[INFO]:[ %s ] [ %d ]"fmt,__func__,__LINE__,##args); \ 951 } \ 952 }while(0); 953 954#define DBG_FUNC(fmt,args...) \ 955 do { \ 956 if (logging_level & PQISRC_FLAGS_FUNC) { \ 957 printf("[FUNC]:[ %s ] [ %d ]"fmt,__func__,__LINE__,##args); \ 958 } \ 959 }while(0); 960 961#define DBG_TRACEIO(fmt,args...) \ 962 do { \ 963 if (logging_level & PQISRC_FLAGS_TRACEIO) { \ 964 printf("[TRACEIO]:[ %s ] [ %d ]"fmt,__func__,__LINE__,##args); \ 965 } \ 966 }while(0); 967 968#define DBG_WARN(fmt,args...) \ 969 do { \ 970 if (logging_level & PQISRC_FLAGS_WARN) { \ 971 printf("[WARN]:[%u:%u.%u][CPU %d][%s][%d]:"fmt,softs->bus_id,softs->device_id,softs->func_id,curcpu,__func__,__LINE__,##args);\ 972 } \ 973 }while(0); 974 975#define DBG_ERR(fmt,args...) \ 976 do { \ 977 if (logging_level & PQISRC_FLAGS_ERROR) { \ 978 printf("[ERROR]::[%u:%u.%u][CPU %d][%s][%d]:"fmt,softs->bus_id,softs->device_id,softs->func_id,curcpu,__func__,__LINE__,##args); \ 979 } \ 980 }while(0); 981#define DBG_IO(fmt,args...) \ 982 do { \ 983 if (logging_level & PQISRC_FLAGS_TRACEIO) { \ 984 printf("[IO]:[ %s ] [ %d ]"fmt,__func__,__LINE__,##args); \ 985 } \ 986 }while(0); 987 988#define DBG_ERR_BTL(device,fmt,args...) \ 989 do { \ 990 if (logging_level & PQISRC_FLAGS_ERROR) { \ 991 printf("[ERROR]::[%u:%u.%u][%u,%u,%u][CPU %d][%s][%d]:"fmt, softs->bus_id, softs->device_id, softs->func_id, device->bus, device->target, device->lun,curcpu,__func__,__LINE__,##args); \ 992 } \ 993 }while(0); 994 995#define DBG_WARN_BTL(device,fmt,args...) \ 996 do { \ 997 if (logging_level & PQISRC_FLAGS_WARN) { \ 998 printf("[WARN]:[%u:%u.%u][%u,%u,%u][CPU %d][%s][%d]:"fmt, softs->bus_id, softs->device_id, softs->func_id, device->bus, device->target, device->lun,curcpu,__func__,__LINE__,##args);\ 999 } \ 1000 }while(0); 1001 1002#endif // _PQI_DEFINES_H 1003