if_sk.c revision 158096
1/* $OpenBSD: if_sk.c,v 2.33 2003/08/12 05:23:06 nate Exp $ */ 2 3/*- 4 * Copyright (c) 1997, 1998, 1999, 2000 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34/*- 35 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 36 * 37 * Permission to use, copy, modify, and distribute this software for any 38 * purpose with or without fee is hereby granted, provided that the above 39 * copyright notice and this permission notice appear in all copies. 40 * 41 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 42 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 43 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 44 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 45 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 46 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 47 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 48 */ 49 50#include <sys/cdefs.h> 51__FBSDID("$FreeBSD: head/sys/dev/sk/if_sk.c 158096 2006-04-28 03:17:37Z sobomax $"); 52 53/* 54 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 55 * the SK-984x series adapters, both single port and dual port. 56 * References: 57 * The XaQti XMAC II datasheet, 58 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 59 * The SysKonnect GEnesis manual, http://www.syskonnect.com 60 * 61 * Note: XaQti has been aquired by Vitesse, and Vitesse does not have the 62 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 63 * convenience to others until Vitesse corrects this problem: 64 * 65 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 66 * 67 * Written by Bill Paul <wpaul@ee.columbia.edu> 68 * Department of Electrical Engineering 69 * Columbia University, New York City 70 */ 71/* 72 * The SysKonnect gigabit ethernet adapters consist of two main 73 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 74 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 75 * components and a PHY while the GEnesis controller provides a PCI 76 * interface with DMA support. Each card may have between 512K and 77 * 2MB of SRAM on board depending on the configuration. 78 * 79 * The SysKonnect GEnesis controller can have either one or two XMAC 80 * chips connected to it, allowing single or dual port NIC configurations. 81 * SysKonnect has the distinction of being the only vendor on the market 82 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 83 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 84 * XMAC registers. This driver takes advantage of these features to allow 85 * both XMACs to operate as independent interfaces. 86 */ 87 88#include <sys/param.h> 89#include <sys/systm.h> 90#include <sys/bus.h> 91#include <sys/endian.h> 92#include <sys/mbuf.h> 93#include <sys/malloc.h> 94#include <sys/kernel.h> 95#include <sys/module.h> 96#include <sys/socket.h> 97#include <sys/sockio.h> 98#include <sys/queue.h> 99#include <sys/sysctl.h> 100 101#include <net/bpf.h> 102#include <net/ethernet.h> 103#include <net/if.h> 104#include <net/if_arp.h> 105#include <net/if_dl.h> 106#include <net/if_media.h> 107#include <net/if_types.h> 108#include <net/if_vlan_var.h> 109 110#include <netinet/in.h> 111#include <netinet/in_systm.h> 112#include <netinet/ip.h> 113 114#include <machine/bus.h> 115#include <machine/in_cksum.h> 116#include <machine/resource.h> 117#include <sys/rman.h> 118 119#include <dev/mii/mii.h> 120#include <dev/mii/miivar.h> 121#include <dev/mii/brgphyreg.h> 122 123#include <dev/pci/pcireg.h> 124#include <dev/pci/pcivar.h> 125 126#if 0 127#define SK_USEIOSPACE 128#endif 129 130#include <dev/sk/if_skreg.h> 131#include <dev/sk/xmaciireg.h> 132#include <dev/sk/yukonreg.h> 133 134MODULE_DEPEND(sk, pci, 1, 1, 1); 135MODULE_DEPEND(sk, ether, 1, 1, 1); 136MODULE_DEPEND(sk, miibus, 1, 1, 1); 137 138/* "device miibus" required. See GENERIC if you get errors here. */ 139#include "miibus_if.h" 140 141#ifndef lint 142static const char rcsid[] = 143 "$FreeBSD: head/sys/dev/sk/if_sk.c 158096 2006-04-28 03:17:37Z sobomax $"; 144#endif 145 146static struct sk_type sk_devs[] = { 147 { 148 VENDORID_SK, 149 DEVICEID_SK_V1, 150 "SysKonnect Gigabit Ethernet (V1.0)" 151 }, 152 { 153 VENDORID_SK, 154 DEVICEID_SK_V2, 155 "SysKonnect Gigabit Ethernet (V2.0)" 156 }, 157 { 158 VENDORID_MARVELL, 159 DEVICEID_SK_V2, 160 "Marvell Gigabit Ethernet" 161 }, 162 { 163 VENDORID_MARVELL, 164 DEVICEID_MRVL_4360, 165 "Marvell 88E8052 Gigabit Ethernet Controller" 166 }, 167 { 168 VENDORID_MARVELL, 169 DEVICEID_MRVL_4361, 170 "Marvell 88E8050 Gigabit Ethernet Controller" 171 }, 172 { 173 VENDORID_MARVELL, 174 DEVICEID_MRVL_4362, 175 "Marvell 88E8053 Gigabit Ethernet Controller" 176 }, 177 { 178 VENDORID_MARVELL, 179 DEVICEID_BELKIN_5005, 180 "Belkin F5D5005 Gigabit Ethernet" 181 }, 182 { 183 VENDORID_3COM, 184 DEVICEID_3COM_3C940, 185 "3Com 3C940 Gigabit Ethernet" 186 }, 187 { 188 VENDORID_LINKSYS, 189 DEVICEID_LINKSYS_EG1032, 190 "Linksys EG1032 Gigabit Ethernet" 191 }, 192 { 193 VENDORID_DLINK, 194 DEVICEID_DLINK_DGE530T, 195 "D-Link DGE-530T Gigabit Ethernet" 196 }, 197 { 0, 0, NULL } 198}; 199 200static int skc_probe(device_t); 201static int skc_attach(device_t); 202static int skc_detach(device_t); 203static void skc_shutdown(device_t); 204static int skc_suspend(device_t); 205static int skc_resume(device_t); 206static int sk_detach(device_t); 207static int sk_probe(device_t); 208static int sk_attach(device_t); 209static void sk_tick(void *); 210static void sk_yukon_tick(void *); 211static void sk_intr(void *); 212static void sk_intr_xmac(struct sk_if_softc *); 213static void sk_intr_bcom(struct sk_if_softc *); 214static void sk_intr_yukon(struct sk_if_softc *); 215static __inline void sk_rxcksum(struct ifnet *, struct mbuf *, u_int32_t); 216static __inline int sk_rxvalid(struct sk_softc *, u_int32_t, u_int32_t); 217static void sk_rxeof(struct sk_if_softc *); 218static void sk_jumbo_rxeof(struct sk_if_softc *); 219static void sk_txeof(struct sk_if_softc *); 220static void sk_txcksum(struct ifnet *, struct mbuf *, struct sk_tx_desc *); 221static int sk_encap(struct sk_if_softc *, struct mbuf **); 222static void sk_start(struct ifnet *); 223static void sk_start_locked(struct ifnet *); 224static int sk_ioctl(struct ifnet *, u_long, caddr_t); 225static void sk_init(void *); 226static void sk_init_locked(struct sk_if_softc *); 227static void sk_init_xmac(struct sk_if_softc *); 228static void sk_init_yukon(struct sk_if_softc *); 229static void sk_stop(struct sk_if_softc *); 230static void sk_watchdog(struct ifnet *); 231static int sk_ifmedia_upd(struct ifnet *); 232static void sk_ifmedia_sts(struct ifnet *, struct ifmediareq *); 233static void sk_reset(struct sk_softc *); 234static __inline void sk_discard_rxbuf(struct sk_if_softc *, int); 235static __inline void sk_discard_jumbo_rxbuf(struct sk_if_softc *, int); 236static int sk_newbuf(struct sk_if_softc *, int); 237static int sk_jumbo_newbuf(struct sk_if_softc *, int); 238static void sk_dmamap_cb(void *, bus_dma_segment_t *, int, int); 239static int sk_dma_alloc(struct sk_if_softc *); 240static void sk_dma_free(struct sk_if_softc *); 241static void *sk_jalloc(struct sk_if_softc *); 242static void sk_jfree(void *, void *); 243static int sk_init_rx_ring(struct sk_if_softc *); 244static int sk_init_jumbo_rx_ring(struct sk_if_softc *); 245static void sk_init_tx_ring(struct sk_if_softc *); 246static u_int32_t sk_win_read_4(struct sk_softc *, int); 247static u_int16_t sk_win_read_2(struct sk_softc *, int); 248static u_int8_t sk_win_read_1(struct sk_softc *, int); 249static void sk_win_write_4(struct sk_softc *, int, u_int32_t); 250static void sk_win_write_2(struct sk_softc *, int, u_int32_t); 251static void sk_win_write_1(struct sk_softc *, int, u_int32_t); 252static u_int8_t sk_vpd_readbyte(struct sk_softc *, int); 253static void sk_vpd_read_res(struct sk_softc *, struct vpd_res *, int); 254static void sk_vpd_read(struct sk_softc *); 255 256static int sk_miibus_readreg(device_t, int, int); 257static int sk_miibus_writereg(device_t, int, int, int); 258static void sk_miibus_statchg(device_t); 259 260static int sk_xmac_miibus_readreg(struct sk_if_softc *, int, int); 261static int sk_xmac_miibus_writereg(struct sk_if_softc *, int, int, 262 int); 263static void sk_xmac_miibus_statchg(struct sk_if_softc *); 264 265static int sk_marv_miibus_readreg(struct sk_if_softc *, int, int); 266static int sk_marv_miibus_writereg(struct sk_if_softc *, int, int, 267 int); 268static void sk_marv_miibus_statchg(struct sk_if_softc *); 269 270static uint32_t sk_xmchash(const uint8_t *); 271static uint32_t sk_gmchash(const uint8_t *); 272static void sk_setfilt(struct sk_if_softc *, u_int16_t *, int); 273static void sk_setmulti(struct sk_if_softc *); 274static void sk_setpromisc(struct sk_if_softc *); 275 276static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high); 277static int sysctl_hw_sk_int_mod(SYSCTL_HANDLER_ARGS); 278 279#ifdef SK_USEIOSPACE 280#define SK_RES SYS_RES_IOPORT 281#define SK_RID SK_PCI_LOIO 282#else 283#define SK_RES SYS_RES_MEMORY 284#define SK_RID SK_PCI_LOMEM 285#endif 286 287/* 288 * It seems that SK-NET GENESIS supports very simple checksum offload 289 * capability for Tx and I believe it can generate 0 checksum value for 290 * UDP packets in Tx as the hardware can't differenciate UDP packets from 291 * TCP packets. 0 chcecksum value for UDP packet is an invalid one as it 292 * means sender didn't perforam checksum computation. For the safety I 293 * disabled UDP checksum offload capability at the moment. Alternatively 294 * we can intrduce a LINK0/LINK1 flag as hme(4) did in its Tx checksum 295 * offload routine. 296 */ 297#define SK_CSUM_FEATURES (CSUM_TCP) 298 299/* 300 * Note that we have newbus methods for both the GEnesis controller 301 * itself and the XMAC(s). The XMACs are children of the GEnesis, and 302 * the miibus code is a child of the XMACs. We need to do it this way 303 * so that the miibus drivers can access the PHY registers on the 304 * right PHY. It's not quite what I had in mind, but it's the only 305 * design that achieves the desired effect. 306 */ 307static device_method_t skc_methods[] = { 308 /* Device interface */ 309 DEVMETHOD(device_probe, skc_probe), 310 DEVMETHOD(device_attach, skc_attach), 311 DEVMETHOD(device_detach, skc_detach), 312 DEVMETHOD(device_suspend, skc_suspend), 313 DEVMETHOD(device_resume, skc_resume), 314 DEVMETHOD(device_shutdown, skc_shutdown), 315 316 /* bus interface */ 317 DEVMETHOD(bus_print_child, bus_generic_print_child), 318 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 319 320 { 0, 0 } 321}; 322 323static driver_t skc_driver = { 324 "skc", 325 skc_methods, 326 sizeof(struct sk_softc) 327}; 328 329static devclass_t skc_devclass; 330 331static device_method_t sk_methods[] = { 332 /* Device interface */ 333 DEVMETHOD(device_probe, sk_probe), 334 DEVMETHOD(device_attach, sk_attach), 335 DEVMETHOD(device_detach, sk_detach), 336 DEVMETHOD(device_shutdown, bus_generic_shutdown), 337 338 /* bus interface */ 339 DEVMETHOD(bus_print_child, bus_generic_print_child), 340 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 341 342 /* MII interface */ 343 DEVMETHOD(miibus_readreg, sk_miibus_readreg), 344 DEVMETHOD(miibus_writereg, sk_miibus_writereg), 345 DEVMETHOD(miibus_statchg, sk_miibus_statchg), 346 347 { 0, 0 } 348}; 349 350static driver_t sk_driver = { 351 "sk", 352 sk_methods, 353 sizeof(struct sk_if_softc) 354}; 355 356static devclass_t sk_devclass; 357 358DRIVER_MODULE(skc, pci, skc_driver, skc_devclass, 0, 0); 359DRIVER_MODULE(sk, skc, sk_driver, sk_devclass, 0, 0); 360DRIVER_MODULE(miibus, sk, miibus_driver, miibus_devclass, 0, 0); 361 362#define SK_SETBIT(sc, reg, x) \ 363 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 364 365#define SK_CLRBIT(sc, reg, x) \ 366 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 367 368#define SK_WIN_SETBIT_4(sc, reg, x) \ 369 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) | x) 370 371#define SK_WIN_CLRBIT_4(sc, reg, x) \ 372 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) & ~x) 373 374#define SK_WIN_SETBIT_2(sc, reg, x) \ 375 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) | x) 376 377#define SK_WIN_CLRBIT_2(sc, reg, x) \ 378 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) & ~x) 379 380static u_int32_t 381sk_win_read_4(sc, reg) 382 struct sk_softc *sc; 383 int reg; 384{ 385#ifdef SK_USEIOSPACE 386 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 387 return(CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg))); 388#else 389 return(CSR_READ_4(sc, reg)); 390#endif 391} 392 393static u_int16_t 394sk_win_read_2(sc, reg) 395 struct sk_softc *sc; 396 int reg; 397{ 398#ifdef SK_USEIOSPACE 399 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 400 return(CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg))); 401#else 402 return(CSR_READ_2(sc, reg)); 403#endif 404} 405 406static u_int8_t 407sk_win_read_1(sc, reg) 408 struct sk_softc *sc; 409 int reg; 410{ 411#ifdef SK_USEIOSPACE 412 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 413 return(CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg))); 414#else 415 return(CSR_READ_1(sc, reg)); 416#endif 417} 418 419static void 420sk_win_write_4(sc, reg, val) 421 struct sk_softc *sc; 422 int reg; 423 u_int32_t val; 424{ 425#ifdef SK_USEIOSPACE 426 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 427 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), val); 428#else 429 CSR_WRITE_4(sc, reg, val); 430#endif 431 return; 432} 433 434static void 435sk_win_write_2(sc, reg, val) 436 struct sk_softc *sc; 437 int reg; 438 u_int32_t val; 439{ 440#ifdef SK_USEIOSPACE 441 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 442 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), val); 443#else 444 CSR_WRITE_2(sc, reg, val); 445#endif 446 return; 447} 448 449static void 450sk_win_write_1(sc, reg, val) 451 struct sk_softc *sc; 452 int reg; 453 u_int32_t val; 454{ 455#ifdef SK_USEIOSPACE 456 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 457 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), val); 458#else 459 CSR_WRITE_1(sc, reg, val); 460#endif 461 return; 462} 463 464/* 465 * The VPD EEPROM contains Vital Product Data, as suggested in 466 * the PCI 2.1 specification. The VPD data is separared into areas 467 * denoted by resource IDs. The SysKonnect VPD contains an ID string 468 * resource (the name of the adapter), a read-only area resource 469 * containing various key/data fields and a read/write area which 470 * can be used to store asset management information or log messages. 471 * We read the ID string and read-only into buffers attached to 472 * the controller softc structure for later use. At the moment, 473 * we only use the ID string during skc_attach(). 474 */ 475static u_int8_t 476sk_vpd_readbyte(sc, addr) 477 struct sk_softc *sc; 478 int addr; 479{ 480 int i; 481 482 sk_win_write_2(sc, SK_PCI_REG(SK_PCI_VPD_ADDR), addr); 483 for (i = 0; i < SK_TIMEOUT; i++) { 484 /* ASUS LOM takes a very long time to read VPD. */ 485 DELAY(100); 486 if (sk_win_read_2(sc, 487 SK_PCI_REG(SK_PCI_VPD_ADDR)) & SK_VPD_FLAG) 488 break; 489 } 490 491 if (i == SK_TIMEOUT) 492 return(0); 493 494 return(sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_DATA))); 495} 496 497static void 498sk_vpd_read_res(sc, res, addr) 499 struct sk_softc *sc; 500 struct vpd_res *res; 501 int addr; 502{ 503 int i; 504 u_int8_t *ptr; 505 506 ptr = (u_int8_t *)res; 507 for (i = 0; i < sizeof(struct vpd_res); i++) 508 ptr[i] = sk_vpd_readbyte(sc, i + addr); 509 510 return; 511} 512 513static void 514sk_vpd_read(sc) 515 struct sk_softc *sc; 516{ 517 int pos = 0, i; 518 struct vpd_res res; 519 520 /* Check VPD capability */ 521 if (sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_CAPID)) != PCIY_VPD) 522 return; 523 if (sc->sk_vpd_prodname != NULL) 524 free(sc->sk_vpd_prodname, M_DEVBUF); 525 if (sc->sk_vpd_readonly != NULL) 526 free(sc->sk_vpd_readonly, M_DEVBUF); 527 sc->sk_vpd_prodname = NULL; 528 sc->sk_vpd_readonly = NULL; 529 sc->sk_vpd_readonly_len = 0; 530 531 sk_vpd_read_res(sc, &res, pos); 532 533 /* 534 * Bail out quietly if the eeprom appears to be missing or empty. 535 */ 536 if (res.vr_id == 0xff && res.vr_len == 0xff && res.vr_pad == 0xff) 537 return; 538 539 if (res.vr_id != VPD_RES_ID) { 540 device_printf(sc->sk_dev, "bad VPD resource id: expected %x " 541 "got %x\n", VPD_RES_ID, res.vr_id); 542 return; 543 } 544 545 pos += sizeof(res); 546 sc->sk_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 547 if (sc->sk_vpd_prodname != NULL) { 548 for (i = 0; i < res.vr_len; i++) 549 sc->sk_vpd_prodname[i] = sk_vpd_readbyte(sc, i + pos); 550 sc->sk_vpd_prodname[i] = '\0'; 551 } 552 pos += res.vr_len; 553 554 sk_vpd_read_res(sc, &res, pos); 555 556 if (res.vr_id != VPD_RES_READ) { 557 device_printf(sc->sk_dev, "bad VPD resource id: expected %x " 558 "got %x\n", VPD_RES_READ, res.vr_id); 559 return; 560 } 561 562 pos += sizeof(res); 563 sc->sk_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 564 for (i = 0; i < res.vr_len; i++) 565 sc->sk_vpd_readonly[i] = sk_vpd_readbyte(sc, i + pos); 566 sc->sk_vpd_readonly_len = res.vr_len; 567 568 return; 569} 570 571static int 572sk_miibus_readreg(dev, phy, reg) 573 device_t dev; 574 int phy, reg; 575{ 576 struct sk_if_softc *sc_if; 577 int v; 578 579 sc_if = device_get_softc(dev); 580 581 SK_IF_MII_LOCK(sc_if); 582 switch(sc_if->sk_softc->sk_type) { 583 case SK_GENESIS: 584 v = sk_xmac_miibus_readreg(sc_if, phy, reg); 585 break; 586 case SK_YUKON: 587 case SK_YUKON_LITE: 588 case SK_YUKON_LP: 589 case SK_YUKON_EC: 590 v = sk_marv_miibus_readreg(sc_if, phy, reg); 591 break; 592 default: 593 v = 0; 594 break; 595 } 596 SK_IF_MII_UNLOCK(sc_if); 597 598 return (v); 599} 600 601static int 602sk_miibus_writereg(dev, phy, reg, val) 603 device_t dev; 604 int phy, reg, val; 605{ 606 struct sk_if_softc *sc_if; 607 int v; 608 609 sc_if = device_get_softc(dev); 610 611 SK_IF_MII_LOCK(sc_if); 612 switch(sc_if->sk_softc->sk_type) { 613 case SK_GENESIS: 614 v = sk_xmac_miibus_writereg(sc_if, phy, reg, val); 615 break; 616 case SK_YUKON: 617 case SK_YUKON_LITE: 618 case SK_YUKON_LP: 619 case SK_YUKON_EC: 620 v = sk_marv_miibus_writereg(sc_if, phy, reg, val); 621 break; 622 default: 623 v = 0; 624 break; 625 } 626 SK_IF_MII_UNLOCK(sc_if); 627 628 return (v); 629} 630 631static void 632sk_miibus_statchg(dev) 633 device_t dev; 634{ 635 struct sk_if_softc *sc_if; 636 637 sc_if = device_get_softc(dev); 638 639 SK_IF_MII_LOCK(sc_if); 640 switch(sc_if->sk_softc->sk_type) { 641 case SK_GENESIS: 642 sk_xmac_miibus_statchg(sc_if); 643 break; 644 case SK_YUKON: 645 case SK_YUKON_LITE: 646 case SK_YUKON_LP: 647 case SK_YUKON_EC: 648 sk_marv_miibus_statchg(sc_if); 649 break; 650 } 651 SK_IF_MII_UNLOCK(sc_if); 652 653 return; 654} 655 656static int 657sk_xmac_miibus_readreg(sc_if, phy, reg) 658 struct sk_if_softc *sc_if; 659 int phy, reg; 660{ 661 int i; 662 663 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0) 664 return(0); 665 666 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 667 SK_XM_READ_2(sc_if, XM_PHY_DATA); 668 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 669 for (i = 0; i < SK_TIMEOUT; i++) { 670 DELAY(1); 671 if (SK_XM_READ_2(sc_if, XM_MMUCMD) & 672 XM_MMUCMD_PHYDATARDY) 673 break; 674 } 675 676 if (i == SK_TIMEOUT) { 677 if_printf(sc_if->sk_ifp, "phy failed to come ready\n"); 678 return(0); 679 } 680 } 681 DELAY(1); 682 i = SK_XM_READ_2(sc_if, XM_PHY_DATA); 683 684 return(i); 685} 686 687static int 688sk_xmac_miibus_writereg(sc_if, phy, reg, val) 689 struct sk_if_softc *sc_if; 690 int phy, reg, val; 691{ 692 int i; 693 694 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 695 for (i = 0; i < SK_TIMEOUT; i++) { 696 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 697 break; 698 } 699 700 if (i == SK_TIMEOUT) { 701 if_printf(sc_if->sk_ifp, "phy failed to come ready\n"); 702 return (ETIMEDOUT); 703 } 704 705 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val); 706 for (i = 0; i < SK_TIMEOUT; i++) { 707 DELAY(1); 708 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 709 break; 710 } 711 if (i == SK_TIMEOUT) 712 if_printf(sc_if->sk_ifp, "phy write timed out\n"); 713 714 return(0); 715} 716 717static void 718sk_xmac_miibus_statchg(sc_if) 719 struct sk_if_softc *sc_if; 720{ 721 struct mii_data *mii; 722 723 mii = device_get_softc(sc_if->sk_miibus); 724 725 /* 726 * If this is a GMII PHY, manually set the XMAC's 727 * duplex mode accordingly. 728 */ 729 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 730 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 731 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 732 } else { 733 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 734 } 735 } 736} 737 738static int 739sk_marv_miibus_readreg(sc_if, phy, reg) 740 struct sk_if_softc *sc_if; 741 int phy, reg; 742{ 743 u_int16_t val; 744 int i; 745 746 if (phy != 0 || 747 (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER && 748 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) { 749 return(0); 750 } 751 752 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 753 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 754 755 for (i = 0; i < SK_TIMEOUT; i++) { 756 DELAY(1); 757 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 758 if (val & YU_SMICR_READ_VALID) 759 break; 760 } 761 762 if (i == SK_TIMEOUT) { 763 if_printf(sc_if->sk_ifp, "phy failed to come ready\n"); 764 return(0); 765 } 766 767 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 768 769 return(val); 770} 771 772static int 773sk_marv_miibus_writereg(sc_if, phy, reg, val) 774 struct sk_if_softc *sc_if; 775 int phy, reg, val; 776{ 777 int i; 778 779 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 780 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 781 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 782 783 for (i = 0; i < SK_TIMEOUT; i++) { 784 DELAY(1); 785 if (SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY) 786 break; 787 } 788 if (i == SK_TIMEOUT) { 789 if_printf(sc_if->sk_ifp, "phy write timeout\n"); 790 return (0); 791 } 792 793 return(0); 794} 795 796static void 797sk_marv_miibus_statchg(sc_if) 798 struct sk_if_softc *sc_if; 799{ 800 return; 801} 802 803#define HASH_BITS 6 804 805static u_int32_t 806sk_xmchash(addr) 807 const uint8_t *addr; 808{ 809 uint32_t crc; 810 811 /* Compute CRC for the address value. */ 812 crc = ether_crc32_le(addr, ETHER_ADDR_LEN); 813 814 return (~crc & ((1 << HASH_BITS) - 1)); 815} 816 817/* gmchash is just a big endian crc */ 818static u_int32_t 819sk_gmchash(addr) 820 const uint8_t *addr; 821{ 822 uint32_t crc; 823 824 /* Compute CRC for the address value. */ 825 crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 826 827 return (crc & ((1 << HASH_BITS) - 1)); 828} 829 830static void 831sk_setfilt(sc_if, addr, slot) 832 struct sk_if_softc *sc_if; 833 u_int16_t *addr; 834 int slot; 835{ 836 int base; 837 838 base = XM_RXFILT_ENTRY(slot); 839 840 SK_XM_WRITE_2(sc_if, base, addr[0]); 841 SK_XM_WRITE_2(sc_if, base + 2, addr[1]); 842 SK_XM_WRITE_2(sc_if, base + 4, addr[2]); 843 844 return; 845} 846 847static void 848sk_setmulti(sc_if) 849 struct sk_if_softc *sc_if; 850{ 851 struct sk_softc *sc = sc_if->sk_softc; 852 struct ifnet *ifp = sc_if->sk_ifp; 853 u_int32_t hashes[2] = { 0, 0 }; 854 int h = 0, i; 855 struct ifmultiaddr *ifma; 856 u_int16_t dummy[] = { 0, 0, 0 }; 857 u_int16_t maddr[(ETHER_ADDR_LEN+1)/2]; 858 859 SK_IF_LOCK_ASSERT(sc_if); 860 861 /* First, zot all the existing filters. */ 862 switch(sc->sk_type) { 863 case SK_GENESIS: 864 for (i = 1; i < XM_RXFILT_MAX; i++) 865 sk_setfilt(sc_if, dummy, i); 866 867 SK_XM_WRITE_4(sc_if, XM_MAR0, 0); 868 SK_XM_WRITE_4(sc_if, XM_MAR2, 0); 869 break; 870 case SK_YUKON: 871 case SK_YUKON_LITE: 872 case SK_YUKON_LP: 873 case SK_YUKON_EC: 874 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 875 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 876 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 877 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 878 break; 879 } 880 881 /* Now program new ones. */ 882 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 883 hashes[0] = 0xFFFFFFFF; 884 hashes[1] = 0xFFFFFFFF; 885 } else { 886 i = 1; 887 IF_ADDR_LOCK(ifp); 888 TAILQ_FOREACH_REVERSE(ifma, &ifp->if_multiaddrs, ifmultihead, ifma_link) { 889 if (ifma->ifma_addr->sa_family != AF_LINK) 890 continue; 891 /* 892 * Program the first XM_RXFILT_MAX multicast groups 893 * into the perfect filter. For all others, 894 * use the hash table. 895 */ 896 if (sc->sk_type == SK_GENESIS && i < XM_RXFILT_MAX) { 897 bcopy(LLADDR( 898 (struct sockaddr_dl *)ifma->ifma_addr), 899 maddr, ETHER_ADDR_LEN); 900 sk_setfilt(sc_if, maddr, i); 901 i++; 902 continue; 903 } 904 905 switch(sc->sk_type) { 906 case SK_GENESIS: 907 bcopy(LLADDR( 908 (struct sockaddr_dl *)ifma->ifma_addr), 909 maddr, ETHER_ADDR_LEN); 910 h = sk_xmchash((const uint8_t *)maddr); 911 break; 912 case SK_YUKON: 913 case SK_YUKON_LITE: 914 case SK_YUKON_LP: 915 case SK_YUKON_EC: 916 bcopy(LLADDR( 917 (struct sockaddr_dl *)ifma->ifma_addr), 918 maddr, ETHER_ADDR_LEN); 919 h = sk_gmchash((const uint8_t *)maddr); 920 break; 921 } 922 if (h < 32) 923 hashes[0] |= (1 << h); 924 else 925 hashes[1] |= (1 << (h - 32)); 926 } 927 IF_ADDR_UNLOCK(ifp); 928 } 929 930 switch(sc->sk_type) { 931 case SK_GENESIS: 932 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH| 933 XM_MODE_RX_USE_PERFECT); 934 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]); 935 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]); 936 break; 937 case SK_YUKON: 938 case SK_YUKON_LITE: 939 case SK_YUKON_LP: 940 case SK_YUKON_EC: 941 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 942 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 943 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 944 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 945 break; 946 } 947 948 return; 949} 950 951static void 952sk_setpromisc(sc_if) 953 struct sk_if_softc *sc_if; 954{ 955 struct sk_softc *sc = sc_if->sk_softc; 956 struct ifnet *ifp = sc_if->sk_ifp; 957 958 SK_IF_LOCK_ASSERT(sc_if); 959 960 switch(sc->sk_type) { 961 case SK_GENESIS: 962 if (ifp->if_flags & IFF_PROMISC) { 963 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 964 } else { 965 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 966 } 967 break; 968 case SK_YUKON: 969 case SK_YUKON_LITE: 970 case SK_YUKON_LP: 971 case SK_YUKON_EC: 972 if (ifp->if_flags & IFF_PROMISC) { 973 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 974 YU_RCR_UFLEN | YU_RCR_MUFLEN); 975 } else { 976 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 977 YU_RCR_UFLEN | YU_RCR_MUFLEN); 978 } 979 break; 980 } 981 982 return; 983} 984 985static int 986sk_init_rx_ring(sc_if) 987 struct sk_if_softc *sc_if; 988{ 989 struct sk_ring_data *rd; 990 bus_addr_t addr; 991 u_int32_t csum_start; 992 int i; 993 994 sc_if->sk_cdata.sk_rx_cons = 0; 995 996 csum_start = (ETHER_HDR_LEN + sizeof(struct ip)) << 16 | 997 ETHER_HDR_LEN; 998 rd = &sc_if->sk_rdata; 999 bzero(rd->sk_rx_ring, sizeof(struct sk_rx_desc) * SK_RX_RING_CNT); 1000 for (i = 0; i < SK_RX_RING_CNT; i++) { 1001 if (sk_newbuf(sc_if, i) != 0) 1002 return (ENOBUFS); 1003 if (i == (SK_RX_RING_CNT - 1)) 1004 addr = SK_RX_RING_ADDR(sc_if, 0); 1005 else 1006 addr = SK_RX_RING_ADDR(sc_if, i + 1); 1007 rd->sk_rx_ring[i].sk_next = htole32(SK_ADDR_LO(addr)); 1008 rd->sk_rx_ring[i].sk_csum_start = htole32(csum_start); 1009 } 1010 1011 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_ring_tag, 1012 sc_if->sk_cdata.sk_rx_ring_map, 1013 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1014 1015 return(0); 1016} 1017 1018static int 1019sk_init_jumbo_rx_ring(sc_if) 1020 struct sk_if_softc *sc_if; 1021{ 1022 struct sk_ring_data *rd; 1023 bus_addr_t addr; 1024 u_int32_t csum_start; 1025 int i; 1026 1027 sc_if->sk_cdata.sk_jumbo_rx_cons = 0; 1028 1029 csum_start = ((ETHER_HDR_LEN + sizeof(struct ip)) << 16) | 1030 ETHER_HDR_LEN; 1031 rd = &sc_if->sk_rdata; 1032 bzero(rd->sk_jumbo_rx_ring, 1033 sizeof(struct sk_rx_desc) * SK_JUMBO_RX_RING_CNT); 1034 for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) { 1035 if (sk_jumbo_newbuf(sc_if, i) != 0) 1036 return (ENOBUFS); 1037 if (i == (SK_JUMBO_RX_RING_CNT - 1)) 1038 addr = SK_JUMBO_RX_RING_ADDR(sc_if, 0); 1039 else 1040 addr = SK_JUMBO_RX_RING_ADDR(sc_if, i + 1); 1041 rd->sk_jumbo_rx_ring[i].sk_next = htole32(SK_ADDR_LO(addr)); 1042 rd->sk_jumbo_rx_ring[i].sk_csum_start = htole32(csum_start); 1043 } 1044 1045 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_ring_tag, 1046 sc_if->sk_cdata.sk_jumbo_rx_ring_map, 1047 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1048 1049 return (0); 1050} 1051 1052static void 1053sk_init_tx_ring(sc_if) 1054 struct sk_if_softc *sc_if; 1055{ 1056 struct sk_ring_data *rd; 1057 struct sk_txdesc *txd; 1058 bus_addr_t addr; 1059 int i; 1060 1061 STAILQ_INIT(&sc_if->sk_cdata.sk_txfreeq); 1062 STAILQ_INIT(&sc_if->sk_cdata.sk_txbusyq); 1063 1064 sc_if->sk_cdata.sk_tx_prod = 0; 1065 sc_if->sk_cdata.sk_tx_cons = 0; 1066 sc_if->sk_cdata.sk_tx_cnt = 0; 1067 1068 rd = &sc_if->sk_rdata; 1069 bzero(rd->sk_tx_ring, sizeof(struct sk_tx_desc) * SK_TX_RING_CNT); 1070 for (i = 0; i < SK_TX_RING_CNT; i++) { 1071 if (i == (SK_TX_RING_CNT - 1)) 1072 addr = SK_TX_RING_ADDR(sc_if, 0); 1073 else 1074 addr = SK_TX_RING_ADDR(sc_if, i + 1); 1075 rd->sk_tx_ring[i].sk_next = htole32(SK_ADDR_LO(addr)); 1076 txd = &sc_if->sk_cdata.sk_txdesc[i]; 1077 STAILQ_INSERT_TAIL(&sc_if->sk_cdata.sk_txfreeq, txd, tx_q); 1078 } 1079 1080 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag, 1081 sc_if->sk_cdata.sk_tx_ring_map, 1082 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1083} 1084 1085static __inline void 1086sk_discard_rxbuf(sc_if, idx) 1087 struct sk_if_softc *sc_if; 1088 int idx; 1089{ 1090 struct sk_rx_desc *r; 1091 struct sk_rxdesc *rxd; 1092 struct mbuf *m; 1093 1094 1095 r = &sc_if->sk_rdata.sk_rx_ring[idx]; 1096 rxd = &sc_if->sk_cdata.sk_rxdesc[idx]; 1097 m = rxd->rx_m; 1098 r->sk_ctl = htole32(m->m_len | SK_RXSTAT | SK_OPCODE_CSUM); 1099} 1100 1101static __inline void 1102sk_discard_jumbo_rxbuf(sc_if, idx) 1103 struct sk_if_softc *sc_if; 1104 int idx; 1105{ 1106 struct sk_rx_desc *r; 1107 struct sk_rxdesc *rxd; 1108 struct mbuf *m; 1109 1110 r = &sc_if->sk_rdata.sk_jumbo_rx_ring[idx]; 1111 rxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[idx]; 1112 m = rxd->rx_m; 1113 r->sk_ctl = htole32(m->m_len | SK_RXSTAT | SK_OPCODE_CSUM); 1114} 1115 1116static int 1117sk_newbuf(sc_if, idx) 1118 struct sk_if_softc *sc_if; 1119 int idx; 1120{ 1121 struct sk_rx_desc *r; 1122 struct sk_rxdesc *rxd; 1123 struct mbuf *m; 1124 bus_dma_segment_t segs[1]; 1125 bus_dmamap_t map; 1126 int nsegs; 1127 1128 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1129 if (m == NULL) 1130 return (ENOBUFS); 1131 m->m_len = m->m_pkthdr.len = MCLBYTES; 1132 m_adj(m, ETHER_ALIGN); 1133 1134 if (bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_rx_tag, 1135 sc_if->sk_cdata.sk_rx_sparemap, m, segs, &nsegs, 0) != 0) { 1136 m_freem(m); 1137 return (ENOBUFS); 1138 } 1139 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1140 1141 rxd = &sc_if->sk_cdata.sk_rxdesc[idx]; 1142 if (rxd->rx_m != NULL) { 1143 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_tag, rxd->rx_dmamap, 1144 BUS_DMASYNC_POSTREAD); 1145 bus_dmamap_unload(sc_if->sk_cdata.sk_rx_tag, rxd->rx_dmamap); 1146 } 1147 map = rxd->rx_dmamap; 1148 rxd->rx_dmamap = sc_if->sk_cdata.sk_rx_sparemap; 1149 sc_if->sk_cdata.sk_rx_sparemap = map; 1150 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_tag, rxd->rx_dmamap, 1151 BUS_DMASYNC_PREREAD); 1152 rxd->rx_m = m; 1153 r = &sc_if->sk_rdata.sk_rx_ring[idx]; 1154 r->sk_data_lo = htole32(SK_ADDR_LO(segs[0].ds_addr)); 1155 r->sk_data_hi = htole32(SK_ADDR_HI(segs[0].ds_addr)); 1156 r->sk_ctl = htole32(segs[0].ds_len | SK_RXSTAT | SK_OPCODE_CSUM); 1157 1158 return (0); 1159} 1160 1161static int 1162sk_jumbo_newbuf(sc_if, idx) 1163 struct sk_if_softc *sc_if; 1164 int idx; 1165{ 1166 struct sk_rx_desc *r; 1167 struct sk_rxdesc *rxd; 1168 struct mbuf *m; 1169 bus_dma_segment_t segs[1]; 1170 bus_dmamap_t map; 1171 int nsegs; 1172 void *buf; 1173 1174 MGETHDR(m, M_DONTWAIT, MT_DATA); 1175 if (m == NULL) 1176 return (ENOBUFS); 1177 buf = sk_jalloc(sc_if); 1178 if (buf == NULL) { 1179 m_freem(m); 1180 return (ENOBUFS); 1181 } 1182 /* Attach the buffer to the mbuf */ 1183 MEXTADD(m, buf, SK_JLEN, sk_jfree, (struct sk_if_softc *)sc_if, 0, 1184 EXT_NET_DRV); 1185 if ((m->m_flags & M_EXT) == 0) { 1186 m_freem(m); 1187 return (ENOBUFS); 1188 } 1189 m->m_pkthdr.len = m->m_len = SK_JLEN; 1190 /* 1191 * Adjust alignment so packet payload begins on a 1192 * longword boundary. Mandatory for Alpha, useful on 1193 * x86 too. 1194 */ 1195 m_adj(m, ETHER_ALIGN); 1196 1197 if (bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_jumbo_rx_tag, 1198 sc_if->sk_cdata.sk_jumbo_rx_sparemap, m, segs, &nsegs, 0) != 0) { 1199 m_freem(m); 1200 return (ENOBUFS); 1201 } 1202 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1203 1204 rxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[idx]; 1205 if (rxd->rx_m != NULL) { 1206 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_tag, rxd->rx_dmamap, 1207 BUS_DMASYNC_POSTREAD); 1208 bus_dmamap_unload(sc_if->sk_cdata.sk_jumbo_rx_tag, 1209 rxd->rx_dmamap); 1210 } 1211 map = rxd->rx_dmamap; 1212 rxd->rx_dmamap = sc_if->sk_cdata.sk_jumbo_rx_sparemap; 1213 sc_if->sk_cdata.sk_jumbo_rx_sparemap = map; 1214 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_tag, rxd->rx_dmamap, 1215 BUS_DMASYNC_PREREAD); 1216 rxd->rx_m = m; 1217 r = &sc_if->sk_rdata.sk_jumbo_rx_ring[idx]; 1218 r->sk_data_lo = htole32(SK_ADDR_LO(segs[0].ds_addr)); 1219 r->sk_data_hi = htole32(SK_ADDR_HI(segs[0].ds_addr)); 1220 r->sk_ctl = htole32(segs[0].ds_len | SK_RXSTAT | SK_OPCODE_CSUM); 1221 1222 return (0); 1223} 1224 1225/* 1226 * Set media options. 1227 */ 1228static int 1229sk_ifmedia_upd(ifp) 1230 struct ifnet *ifp; 1231{ 1232 struct sk_if_softc *sc_if = ifp->if_softc; 1233 struct mii_data *mii; 1234 1235 mii = device_get_softc(sc_if->sk_miibus); 1236 sk_init(sc_if); 1237 mii_mediachg(mii); 1238 1239 return(0); 1240} 1241 1242/* 1243 * Report current media status. 1244 */ 1245static void 1246sk_ifmedia_sts(ifp, ifmr) 1247 struct ifnet *ifp; 1248 struct ifmediareq *ifmr; 1249{ 1250 struct sk_if_softc *sc_if; 1251 struct mii_data *mii; 1252 1253 sc_if = ifp->if_softc; 1254 mii = device_get_softc(sc_if->sk_miibus); 1255 1256 mii_pollstat(mii); 1257 ifmr->ifm_active = mii->mii_media_active; 1258 ifmr->ifm_status = mii->mii_media_status; 1259 1260 return; 1261} 1262 1263static int 1264sk_ioctl(ifp, command, data) 1265 struct ifnet *ifp; 1266 u_long command; 1267 caddr_t data; 1268{ 1269 struct sk_if_softc *sc_if = ifp->if_softc; 1270 struct ifreq *ifr = (struct ifreq *) data; 1271 int error, mask; 1272 struct mii_data *mii; 1273 1274 error = 0; 1275 switch(command) { 1276 case SIOCSIFMTU: 1277 SK_IF_LOCK(sc_if); 1278 if (ifr->ifr_mtu > SK_JUMBO_MTU) 1279 error = EINVAL; 1280 else { 1281 ifp->if_mtu = ifr->ifr_mtu; 1282 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1283 sk_init_locked(sc_if); 1284 } 1285 SK_IF_UNLOCK(sc_if); 1286 break; 1287 case SIOCSIFFLAGS: 1288 SK_IF_LOCK(sc_if); 1289 if (ifp->if_flags & IFF_UP) { 1290 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1291 if ((ifp->if_flags ^ sc_if->sk_if_flags) 1292 & IFF_PROMISC) { 1293 sk_setpromisc(sc_if); 1294 sk_setmulti(sc_if); 1295 } 1296 } else 1297 sk_init_locked(sc_if); 1298 } else { 1299 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1300 sk_stop(sc_if); 1301 } 1302 sc_if->sk_if_flags = ifp->if_flags; 1303 SK_IF_UNLOCK(sc_if); 1304 break; 1305 case SIOCADDMULTI: 1306 case SIOCDELMULTI: 1307 SK_IF_LOCK(sc_if); 1308 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1309 sk_setmulti(sc_if); 1310 SK_IF_UNLOCK(sc_if); 1311 break; 1312 case SIOCGIFMEDIA: 1313 case SIOCSIFMEDIA: 1314 mii = device_get_softc(sc_if->sk_miibus); 1315 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1316 break; 1317 case SIOCSIFCAP: 1318 SK_IF_LOCK(sc_if); 1319 if (sc_if->sk_softc->sk_type == SK_GENESIS) { 1320 SK_IF_UNLOCK(sc_if); 1321 break; 1322 } 1323 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1324 if (mask & IFCAP_HWCSUM) { 1325 ifp->if_capenable ^= IFCAP_HWCSUM; 1326 if (IFCAP_HWCSUM & ifp->if_capenable && 1327 IFCAP_HWCSUM & ifp->if_capabilities) 1328 ifp->if_hwassist = SK_CSUM_FEATURES; 1329 else 1330 ifp->if_hwassist = 0; 1331 } 1332 SK_IF_UNLOCK(sc_if); 1333 break; 1334 default: 1335 error = ether_ioctl(ifp, command, data); 1336 break; 1337 } 1338 1339 return (error); 1340} 1341 1342/* 1343 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device 1344 * IDs against our list and return a device name if we find a match. 1345 */ 1346static int 1347skc_probe(dev) 1348 device_t dev; 1349{ 1350 struct sk_type *t = sk_devs; 1351 1352 while(t->sk_name != NULL) { 1353 if ((pci_get_vendor(dev) == t->sk_vid) && 1354 (pci_get_device(dev) == t->sk_did)) { 1355 /* 1356 * Only attach to rev. 2 of the Linksys EG1032 adapter. 1357 * Rev. 3 is supported by re(4). 1358 */ 1359 if ((t->sk_vid == VENDORID_LINKSYS) && 1360 (t->sk_did == DEVICEID_LINKSYS_EG1032) && 1361 (pci_get_subdevice(dev) != 1362 SUBDEVICEID_LINKSYS_EG1032_REV2)) { 1363 t++; 1364 continue; 1365 } 1366 device_set_desc(dev, t->sk_name); 1367 return (BUS_PROBE_DEFAULT); 1368 } 1369 t++; 1370 } 1371 1372 return(ENXIO); 1373} 1374 1375/* 1376 * Force the GEnesis into reset, then bring it out of reset. 1377 */ 1378static void 1379sk_reset(sc) 1380 struct sk_softc *sc; 1381{ 1382 1383 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET); 1384 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET); 1385 if (SK_YUKON_FAMILY(sc->sk_type)) 1386 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 1387 1388 DELAY(1000); 1389 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET); 1390 DELAY(2); 1391 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 1392 if (SK_YUKON_FAMILY(sc->sk_type)) 1393 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 1394 1395 if (sc->sk_type == SK_GENESIS) { 1396 /* Configure packet arbiter */ 1397 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET); 1398 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT); 1399 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT); 1400 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT); 1401 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT); 1402 } 1403 1404 /* Enable RAM interface */ 1405 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 1406 1407 /* 1408 * Configure interrupt moderation. The moderation timer 1409 * defers interrupts specified in the interrupt moderation 1410 * timer mask based on the timeout specified in the interrupt 1411 * moderation timer init register. Each bit in the timer 1412 * register represents one tick, so to specify a timeout in 1413 * microseconds, we have to multiply by the correct number of 1414 * ticks-per-microsecond. 1415 */ 1416 switch (sc->sk_type) { 1417 case SK_GENESIS: 1418 sc->sk_int_ticks = SK_IMTIMER_TICKS_GENESIS; 1419 break; 1420 case SK_YUKON_EC: 1421 sc->sk_int_ticks = SK_IMTIMER_TICKS_YUKON_EC; 1422 break; 1423 default: 1424 sc->sk_int_ticks = SK_IMTIMER_TICKS_YUKON; 1425 break; 1426 } 1427 if (bootverbose) 1428 device_printf(sc->sk_dev, "interrupt moderation is %d us\n", 1429 sc->sk_int_mod); 1430 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod, 1431 sc->sk_int_ticks)); 1432 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 1433 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 1434 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 1435 1436 return; 1437} 1438 1439static int 1440sk_probe(dev) 1441 device_t dev; 1442{ 1443 struct sk_softc *sc; 1444 1445 sc = device_get_softc(device_get_parent(dev)); 1446 1447 /* 1448 * Not much to do here. We always know there will be 1449 * at least one XMAC present, and if there are two, 1450 * skc_attach() will create a second device instance 1451 * for us. 1452 */ 1453 switch (sc->sk_type) { 1454 case SK_GENESIS: 1455 device_set_desc(dev, "XaQti Corp. XMAC II"); 1456 break; 1457 case SK_YUKON: 1458 case SK_YUKON_LITE: 1459 case SK_YUKON_LP: 1460 case SK_YUKON_EC: 1461 device_set_desc(dev, "Marvell Semiconductor, Inc. Yukon"); 1462 break; 1463 } 1464 1465 return (BUS_PROBE_DEFAULT); 1466} 1467 1468/* 1469 * Each XMAC chip is attached as a separate logical IP interface. 1470 * Single port cards will have only one logical interface of course. 1471 */ 1472static int 1473sk_attach(dev) 1474 device_t dev; 1475{ 1476 struct sk_softc *sc; 1477 struct sk_if_softc *sc_if; 1478 struct ifnet *ifp; 1479 int i, port, error; 1480 u_char eaddr[6]; 1481 1482 if (dev == NULL) 1483 return(EINVAL); 1484 1485 error = 0; 1486 sc_if = device_get_softc(dev); 1487 sc = device_get_softc(device_get_parent(dev)); 1488 port = *(int *)device_get_ivars(dev); 1489 1490 sc_if->sk_if_dev = dev; 1491 sc_if->sk_port = port; 1492 sc_if->sk_softc = sc; 1493 sc->sk_if[port] = sc_if; 1494 if (port == SK_PORT_A) 1495 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0; 1496 if (port == SK_PORT_B) 1497 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1; 1498 1499 callout_init_mtx(&sc_if->sk_tick_ch, &sc_if->sk_softc->sk_mtx, 0); 1500 1501 if (sk_dma_alloc(sc_if) != 0) { 1502 error = ENOMEM; 1503 goto fail; 1504 } 1505 1506 ifp = sc_if->sk_ifp = if_alloc(IFT_ETHER); 1507 if (ifp == NULL) { 1508 device_printf(sc_if->sk_if_dev, "can not if_alloc()\n"); 1509 error = ENOSPC; 1510 goto fail; 1511 } 1512 ifp->if_softc = sc_if; 1513 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1514 ifp->if_mtu = ETHERMTU; 1515 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1516 /* 1517 * SK_GENESIS has a bug in checksum offload - From linux. 1518 */ 1519 if (sc_if->sk_softc->sk_type != SK_GENESIS) { 1520 ifp->if_capabilities = IFCAP_HWCSUM; 1521 ifp->if_hwassist = SK_CSUM_FEATURES; 1522 } else { 1523 ifp->if_capabilities = 0; 1524 ifp->if_hwassist = 0; 1525 } 1526 ifp->if_capenable = ifp->if_capabilities; 1527 ifp->if_ioctl = sk_ioctl; 1528 ifp->if_start = sk_start; 1529 ifp->if_watchdog = sk_watchdog; 1530 ifp->if_init = sk_init; 1531 IFQ_SET_MAXLEN(&ifp->if_snd, SK_TX_RING_CNT - 1); 1532 ifp->if_snd.ifq_drv_maxlen = SK_TX_RING_CNT - 1; 1533 IFQ_SET_READY(&ifp->if_snd); 1534 1535 /* 1536 * Get station address for this interface. Note that 1537 * dual port cards actually come with three station 1538 * addresses: one for each port, plus an extra. The 1539 * extra one is used by the SysKonnect driver software 1540 * as a 'virtual' station address for when both ports 1541 * are operating in failover mode. Currently we don't 1542 * use this extra address. 1543 */ 1544 SK_IF_LOCK(sc_if); 1545 for (i = 0; i < ETHER_ADDR_LEN; i++) 1546 eaddr[i] = 1547 sk_win_read_1(sc, SK_MAC0_0 + (port * 8) + i); 1548 1549 /* 1550 * Set up RAM buffer addresses. The NIC will have a certain 1551 * amount of SRAM on it, somewhere between 512K and 2MB. We 1552 * need to divide this up a) between the transmitter and 1553 * receiver and b) between the two XMACs, if this is a 1554 * dual port NIC. Our algotithm is to divide up the memory 1555 * evenly so that everyone gets a fair share. 1556 * 1557 * Just to be contrary, Yukon2 appears to have separate memory 1558 * for each MAC. 1559 */ 1560 if (SK_IS_YUKON2(sc) || 1561 sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) { 1562 u_int32_t chunk, val; 1563 1564 chunk = sc->sk_ramsize / 2; 1565 val = sc->sk_rboff / sizeof(u_int64_t); 1566 sc_if->sk_rx_ramstart = val; 1567 val += (chunk / sizeof(u_int64_t)); 1568 sc_if->sk_rx_ramend = val - 1; 1569 sc_if->sk_tx_ramstart = val; 1570 val += (chunk / sizeof(u_int64_t)); 1571 sc_if->sk_tx_ramend = val - 1; 1572 } else { 1573 u_int32_t chunk, val; 1574 1575 chunk = sc->sk_ramsize / 4; 1576 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) / 1577 sizeof(u_int64_t); 1578 sc_if->sk_rx_ramstart = val; 1579 val += (chunk / sizeof(u_int64_t)); 1580 sc_if->sk_rx_ramend = val - 1; 1581 sc_if->sk_tx_ramstart = val; 1582 val += (chunk / sizeof(u_int64_t)); 1583 sc_if->sk_tx_ramend = val - 1; 1584 } 1585 1586 /* Read and save PHY type and set PHY address */ 1587 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 1588 if (!SK_YUKON_FAMILY(sc->sk_type)) { 1589 switch(sc_if->sk_phytype) { 1590 case SK_PHYTYPE_XMAC: 1591 sc_if->sk_phyaddr = SK_PHYADDR_XMAC; 1592 break; 1593 case SK_PHYTYPE_BCOM: 1594 sc_if->sk_phyaddr = SK_PHYADDR_BCOM; 1595 break; 1596 default: 1597 device_printf(sc->sk_dev, "unsupported PHY type: %d\n", 1598 sc_if->sk_phytype); 1599 error = ENODEV; 1600 SK_IF_UNLOCK(sc_if); 1601 goto fail; 1602 } 1603 } else { 1604 if (sc_if->sk_phytype < SK_PHYTYPE_MARV_COPPER && 1605 sc->sk_pmd == IFM_1000_T) { 1606 /* not initialized, punt */ 1607 sc_if->sk_phytype = SK_PHYTYPE_MARV_COPPER; 1608 } 1609 1610 sc_if->sk_phyaddr = SK_PHYADDR_MARV; 1611 1612 if (sc->sk_pmd != IFM_1000_T && sc->sk_pmd != IFM_1000_CX) 1613 sc_if->sk_phytype = SK_PHYTYPE_MARV_FIBER; 1614 } 1615 1616 /* 1617 * Call MI attach routine. Can't hold locks when calling into ether_*. 1618 */ 1619 SK_IF_UNLOCK(sc_if); 1620 ether_ifattach(ifp, eaddr); 1621 SK_IF_LOCK(sc_if); 1622 1623 /* 1624 * The hardware should be ready for VLAN_MTU by default: 1625 * XMAC II has 0x8100 in VLAN Tag Level 1 register initially; 1626 * YU_SMR_MFL_VLAN is set by this driver in Yukon. 1627 * 1628 */ 1629 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1630 ifp->if_capenable |= IFCAP_VLAN_MTU; 1631 /* 1632 * Tell the upper layer(s) we support long frames. 1633 * Must appear after the call to ether_ifattach() because 1634 * ether_ifattach() sets ifi_hdrlen to the default value. 1635 */ 1636 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1637 1638 /* 1639 * Do miibus setup. 1640 */ 1641 switch (sc->sk_type) { 1642 case SK_GENESIS: 1643 sk_init_xmac(sc_if); 1644 break; 1645 case SK_YUKON: 1646 case SK_YUKON_LITE: 1647 case SK_YUKON_LP: 1648 case SK_YUKON_EC: 1649 sk_init_yukon(sc_if); 1650 break; 1651 } 1652 1653 SK_IF_UNLOCK(sc_if); 1654 if (mii_phy_probe(dev, &sc_if->sk_miibus, 1655 sk_ifmedia_upd, sk_ifmedia_sts)) { 1656 device_printf(sc_if->sk_if_dev, "no PHY found!\n"); 1657 ether_ifdetach(ifp); 1658 error = ENXIO; 1659 goto fail; 1660 } 1661 1662fail: 1663 if (error) { 1664 /* Access should be ok even though lock has been dropped */ 1665 sc->sk_if[port] = NULL; 1666 sk_detach(dev); 1667 } 1668 1669 return(error); 1670} 1671 1672/* 1673 * Attach the interface. Allocate softc structures, do ifmedia 1674 * setup and ethernet/BPF attach. 1675 */ 1676static int 1677skc_attach(dev) 1678 device_t dev; 1679{ 1680 struct sk_softc *sc; 1681 int error = 0, rid, *port, sk_macs; 1682 uint8_t skrs; 1683 char *pname, *revstr; 1684 1685 sc = device_get_softc(dev); 1686 sc->sk_dev = dev; 1687 1688 mtx_init(&sc->sk_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1689 MTX_DEF); 1690 mtx_init(&sc->sk_mii_mtx, "sk_mii_mutex", NULL, MTX_DEF); 1691 /* 1692 * Map control/status registers. 1693 */ 1694 pci_enable_busmaster(dev); 1695 1696 rid = SK_RID; 1697 sc->sk_res = bus_alloc_resource_any(dev, SK_RES, &rid, RF_ACTIVE); 1698 1699 if (sc->sk_res == NULL) { 1700 device_printf(dev, "couldn't map ports/memory\n"); 1701 error = ENXIO; 1702 goto fail; 1703 } 1704 1705 sc->sk_btag = rman_get_bustag(sc->sk_res); 1706 sc->sk_bhandle = rman_get_bushandle(sc->sk_res); 1707 1708 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1709 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4) & 0xf; 1710 1711 /* Bail out if chip is not recognized. */ 1712 if (sc->sk_type != SK_GENESIS && !SK_YUKON_FAMILY(sc->sk_type)) { 1713 device_printf(dev, "unknown device: chipver=%02x, rev=%x\n", 1714 sc->sk_type, sc->sk_rev); 1715 error = ENXIO; 1716 goto fail; 1717 } 1718 1719 /* Allocate interrupt */ 1720 rid = 0; 1721 sc->sk_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1722 RF_SHAREABLE | RF_ACTIVE); 1723 1724 if (sc->sk_irq == NULL) { 1725 device_printf(dev, "couldn't map interrupt\n"); 1726 error = ENXIO; 1727 goto fail; 1728 } 1729 1730 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 1731 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 1732 OID_AUTO, "int_mod", CTLTYPE_INT|CTLFLAG_RW, 1733 &sc->sk_int_mod, 0, sysctl_hw_sk_int_mod, "I", 1734 "SK interrupt moderation"); 1735 1736 /* Pull in device tunables. */ 1737 sc->sk_int_mod = SK_IM_DEFAULT; 1738 error = resource_int_value(device_get_name(dev), device_get_unit(dev), 1739 "int_mod", &sc->sk_int_mod); 1740 if (error == 0) { 1741 if (sc->sk_int_mod < SK_IM_MIN || 1742 sc->sk_int_mod > SK_IM_MAX) { 1743 device_printf(dev, "int_mod value out of range; " 1744 "using default: %d\n", SK_IM_DEFAULT); 1745 sc->sk_int_mod = SK_IM_DEFAULT; 1746 } 1747 } 1748 1749 /* Reset the adapter. */ 1750 sk_reset(sc); 1751 1752 /* Read and save vital product data from EEPROM. */ 1753 sk_vpd_read(sc); 1754 1755 skrs = sk_win_read_1(sc, SK_EPROM0); 1756 if (sc->sk_type == SK_GENESIS) { 1757 /* Read and save RAM size and RAMbuffer offset */ 1758 switch(skrs) { 1759 case SK_RAMSIZE_512K_64: 1760 sc->sk_ramsize = 0x80000; 1761 sc->sk_rboff = SK_RBOFF_0; 1762 break; 1763 case SK_RAMSIZE_1024K_64: 1764 sc->sk_ramsize = 0x100000; 1765 sc->sk_rboff = SK_RBOFF_80000; 1766 break; 1767 case SK_RAMSIZE_1024K_128: 1768 sc->sk_ramsize = 0x100000; 1769 sc->sk_rboff = SK_RBOFF_0; 1770 break; 1771 case SK_RAMSIZE_2048K_128: 1772 sc->sk_ramsize = 0x200000; 1773 sc->sk_rboff = SK_RBOFF_0; 1774 break; 1775 default: 1776 device_printf(dev, "unknown ram size: %d\n", skrs); 1777 error = ENXIO; 1778 goto fail; 1779 } 1780 } else { /* SK_YUKON_FAMILY */ 1781 if (skrs == 0x00) 1782 sc->sk_ramsize = 0x20000; 1783 else 1784 sc->sk_ramsize = skrs * (1<<12); 1785 sc->sk_rboff = SK_RBOFF_0; 1786 } 1787 1788 /* Read and save physical media type */ 1789 switch(sk_win_read_1(sc, SK_PMDTYPE)) { 1790 case SK_PMD_1000BASESX: 1791 sc->sk_pmd = IFM_1000_SX; 1792 break; 1793 case SK_PMD_1000BASELX: 1794 sc->sk_pmd = IFM_1000_LX; 1795 break; 1796 case SK_PMD_1000BASECX: 1797 sc->sk_pmd = IFM_1000_CX; 1798 break; 1799 case SK_PMD_1000BASETX: 1800 sc->sk_pmd = IFM_1000_T; 1801 break; 1802 default: 1803 if (SK_YUKON_FAMILY(sc->sk_type) && (sk_win_read_1(sc, SK_EPROM1) 1804 & 0xF) < SK_PHYTYPE_MARV_COPPER) { 1805 /* not initialized, punt */ 1806 sc->sk_pmd = IFM_1000_T; 1807 break; 1808 } 1809 device_printf(dev, "unknown media type: 0x%x\n", 1810 sk_win_read_1(sc, SK_PMDTYPE)); 1811 error = ENXIO; 1812 goto fail; 1813 } 1814 1815 /* Determine whether to name it with VPD PN or just make it up. 1816 * Marvell Yukon VPD PN seems to freqently be bogus. */ 1817 switch (pci_get_device(dev)) { 1818 case DEVICEID_SK_V1: 1819 case DEVICEID_BELKIN_5005: 1820 case DEVICEID_3COM_3C940: 1821 case DEVICEID_LINKSYS_EG1032: 1822 case DEVICEID_DLINK_DGE530T: 1823 /* Stay with VPD PN. */ 1824 pname = sc->sk_vpd_prodname; 1825 break; 1826 case DEVICEID_SK_V2: 1827 case DEVICEID_MRVL_4360: 1828 case DEVICEID_MRVL_4361: 1829 case DEVICEID_MRVL_4362: 1830 /* YUKON VPD PN might bear no resemblance to reality. */ 1831 switch (sc->sk_type) { 1832 case SK_GENESIS: 1833 /* Stay with VPD PN. */ 1834 pname = sc->sk_vpd_prodname; 1835 break; 1836 case SK_YUKON: 1837 pname = "Marvell Yukon Gigabit Ethernet"; 1838 break; 1839 case SK_YUKON_LITE: 1840 pname = "Marvell Yukon Lite Gigabit Ethernet"; 1841 break; 1842 case SK_YUKON_LP: 1843 pname = "Marvell Yukon LP Gigabit Ethernet"; 1844 break; 1845 case SK_YUKON_EC: 1846 pname = "Marvell Yukon-2 EC Gigabit Ethernet"; 1847 break; 1848 default: 1849 pname = "Marvell Yukon (Unknown) Gigabit Ethernet"; 1850 break; 1851 } 1852 1853 /* Yukon Lite Rev. A0 needs special test. */ 1854 if (sc->sk_type == SK_YUKON || sc->sk_type == SK_YUKON_LP) { 1855 u_int32_t far; 1856 u_int8_t testbyte; 1857 1858 /* Save flash address register before testing. */ 1859 far = sk_win_read_4(sc, SK_EP_ADDR); 1860 1861 sk_win_write_1(sc, SK_EP_ADDR+0x03, 0xff); 1862 testbyte = sk_win_read_1(sc, SK_EP_ADDR+0x03); 1863 1864 if (testbyte != 0x00) { 1865 /* Yukon Lite Rev. A0 detected. */ 1866 sc->sk_type = SK_YUKON_LITE; 1867 sc->sk_rev = SK_YUKON_LITE_REV_A0; 1868 /* Restore flash address register. */ 1869 sk_win_write_4(sc, SK_EP_ADDR, far); 1870 } 1871 } 1872 break; 1873 default: 1874 device_printf(dev, "unknown device: vendor=%04x, device=%04x, " 1875 "chipver=%02x, rev=%x\n", 1876 pci_get_vendor(dev), pci_get_device(dev), 1877 sc->sk_type, sc->sk_rev); 1878 error = ENXIO; 1879 goto fail; 1880 } 1881 1882 if (sc->sk_type == SK_YUKON_LITE) { 1883 switch (sc->sk_rev) { 1884 case SK_YUKON_LITE_REV_A0: 1885 revstr = "A0"; 1886 break; 1887 case SK_YUKON_LITE_REV_A1: 1888 revstr = "A1"; 1889 break; 1890 case SK_YUKON_LITE_REV_A3: 1891 revstr = "A3"; 1892 break; 1893 default: 1894 revstr = ""; 1895 break; 1896 } 1897 } else if (sc->sk_type == SK_YUKON_EC) { 1898 switch (sc->sk_rev) { 1899 case SK_YUKON_EC_REV_A1: 1900 revstr = "A1"; 1901 break; 1902 case SK_YUKON_EC_REV_A2: 1903 revstr = "A2"; 1904 break; 1905 case SK_YUKON_EC_REV_A3: 1906 revstr = "A3"; 1907 break; 1908 default: 1909 revstr = ""; 1910 break; 1911 } 1912 } else { 1913 revstr = ""; 1914 } 1915 1916 /* Announce the product name and more VPD data if there. */ 1917 device_printf(dev, "%s rev. %s(0x%x)\n", 1918 pname != NULL ? pname : "<unknown>", revstr, sc->sk_rev); 1919 1920 if (bootverbose) { 1921 if (sc->sk_vpd_readonly != NULL && 1922 sc->sk_vpd_readonly_len != 0) { 1923 char buf[256]; 1924 char *dp = sc->sk_vpd_readonly; 1925 uint16_t l, len = sc->sk_vpd_readonly_len; 1926 1927 while (len >= 3) { 1928 if ((*dp == 'P' && *(dp+1) == 'N') || 1929 (*dp == 'E' && *(dp+1) == 'C') || 1930 (*dp == 'M' && *(dp+1) == 'N') || 1931 (*dp == 'S' && *(dp+1) == 'N')) { 1932 l = 0; 1933 while (l < *(dp+2)) { 1934 buf[l] = *(dp+3+l); 1935 ++l; 1936 } 1937 buf[l] = '\0'; 1938 device_printf(dev, "%c%c: %s\n", 1939 *dp, *(dp+1), buf); 1940 len -= (3 + l); 1941 dp += (3 + l); 1942 } else { 1943 len -= (3 + *(dp+2)); 1944 dp += (3 + *(dp+2)); 1945 } 1946 } 1947 } 1948 device_printf(dev, "chip ver = 0x%02x\n", sc->sk_type); 1949 device_printf(dev, "chip rev = 0x%02x\n", sc->sk_rev); 1950 device_printf(dev, "SK_EPROM0 = 0x%02x\n", skrs); 1951 device_printf(dev, "SRAM size = 0x%06x\n", sc->sk_ramsize); 1952 } 1953 1954 sc->sk_devs[SK_PORT_A] = device_add_child(dev, "sk", -1); 1955 if (sc->sk_devs[SK_PORT_A] == NULL) { 1956 device_printf(dev, "failed to add child for PORT_A\n"); 1957 error = ENXIO; 1958 goto fail; 1959 } 1960 port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT); 1961 if (port == NULL) { 1962 device_printf(dev, "failed to allocate memory for " 1963 "ivars of PORT_A\n"); 1964 error = ENXIO; 1965 goto fail; 1966 } 1967 *port = SK_PORT_A; 1968 device_set_ivars(sc->sk_devs[SK_PORT_A], port); 1969 1970 sk_macs = 1; 1971 1972 if (SK_IS_YUKON2(sc)) { 1973 u_int8_t hw; 1974 1975 hw = sk_win_read_1(sc, SK_Y2_HWRES); 1976 if ((hw & SK_Y2_HWRES_LINK_MASK) == SK_Y2_HWRES_LINK_DUAL) { 1977 if ((sk_win_read_1(sc, SK_Y2_CLKGATE) & 1978 SK_Y2_CLKGATE_LINK2_INACTIVE) == 0) 1979 sk_macs++; 1980 } 1981 } else { 1982 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) 1983 sk_macs++; 1984 } 1985 1986 if (sk_macs > 1) { 1987 sc->sk_devs[SK_PORT_B] = device_add_child(dev, "sk", -1); 1988 if (sc->sk_devs[SK_PORT_B] == NULL) { 1989 device_printf(dev, "failed to add child for PORT_B\n"); 1990 error = ENXIO; 1991 goto fail; 1992 } 1993 port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT); 1994 if (port == NULL) { 1995 device_printf(dev, "failed to allocate memory for " 1996 "ivars of PORT_B\n"); 1997 error = ENXIO; 1998 goto fail; 1999 } 2000 *port = SK_PORT_B; 2001 device_set_ivars(sc->sk_devs[SK_PORT_B], port); 2002 } 2003 2004 /* Turn on the 'driver is loaded' LED. */ 2005 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 2006 2007 error = bus_generic_attach(dev); 2008 if (error) { 2009 device_printf(dev, "failed to attach port(s)\n"); 2010 goto fail; 2011 } 2012 2013 /* Hook interrupt last to avoid having to lock softc */ 2014 error = bus_setup_intr(dev, sc->sk_irq, INTR_TYPE_NET|INTR_MPSAFE, 2015 sk_intr, sc, &sc->sk_intrhand); 2016 2017 if (error) { 2018 device_printf(dev, "couldn't set up irq\n"); 2019 goto fail; 2020 } 2021 2022fail: 2023 if (error) 2024 skc_detach(dev); 2025 2026 return(error); 2027} 2028 2029/* 2030 * Shutdown hardware and free up resources. This can be called any 2031 * time after the mutex has been initialized. It is called in both 2032 * the error case in attach and the normal detach case so it needs 2033 * to be careful about only freeing resources that have actually been 2034 * allocated. 2035 */ 2036static int 2037sk_detach(dev) 2038 device_t dev; 2039{ 2040 struct sk_if_softc *sc_if; 2041 struct ifnet *ifp; 2042 2043 sc_if = device_get_softc(dev); 2044 KASSERT(mtx_initialized(&sc_if->sk_softc->sk_mtx), 2045 ("sk mutex not initialized in sk_detach")); 2046 SK_IF_LOCK(sc_if); 2047 2048 ifp = sc_if->sk_ifp; 2049 /* These should only be active if attach_xmac succeeded */ 2050 if (device_is_attached(dev)) { 2051 sk_stop(sc_if); 2052 /* Can't hold locks while calling detach */ 2053 SK_IF_UNLOCK(sc_if); 2054 callout_drain(&sc_if->sk_tick_ch); 2055 ether_ifdetach(ifp); 2056 SK_IF_LOCK(sc_if); 2057 } 2058 if (ifp) 2059 if_free(ifp); 2060 /* 2061 * We're generally called from skc_detach() which is using 2062 * device_delete_child() to get to here. It's already trashed 2063 * miibus for us, so don't do it here or we'll panic. 2064 */ 2065 /* 2066 if (sc_if->sk_miibus != NULL) 2067 device_delete_child(dev, sc_if->sk_miibus); 2068 */ 2069 bus_generic_detach(dev); 2070 sk_dma_free(sc_if); 2071 SK_IF_UNLOCK(sc_if); 2072 2073 return(0); 2074} 2075 2076static int 2077skc_detach(dev) 2078 device_t dev; 2079{ 2080 struct sk_softc *sc; 2081 2082 sc = device_get_softc(dev); 2083 KASSERT(mtx_initialized(&sc->sk_mtx), ("sk mutex not initialized")); 2084 2085 if (device_is_alive(dev)) { 2086 if (sc->sk_devs[SK_PORT_A] != NULL) { 2087 free(device_get_ivars(sc->sk_devs[SK_PORT_A]), M_DEVBUF); 2088 device_delete_child(dev, sc->sk_devs[SK_PORT_A]); 2089 } 2090 if (sc->sk_devs[SK_PORT_B] != NULL) { 2091 free(device_get_ivars(sc->sk_devs[SK_PORT_B]), M_DEVBUF); 2092 device_delete_child(dev, sc->sk_devs[SK_PORT_B]); 2093 } 2094 bus_generic_detach(dev); 2095 } 2096 2097 if (sc->sk_vpd_prodname != NULL) 2098 free(sc->sk_vpd_prodname, M_DEVBUF); 2099 if (sc->sk_vpd_readonly != NULL) 2100 free(sc->sk_vpd_readonly, M_DEVBUF); 2101 2102 if (sc->sk_intrhand) 2103 bus_teardown_intr(dev, sc->sk_irq, sc->sk_intrhand); 2104 if (sc->sk_irq) 2105 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq); 2106 if (sc->sk_res) 2107 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res); 2108 2109 mtx_destroy(&sc->sk_mii_mtx); 2110 mtx_destroy(&sc->sk_mtx); 2111 2112 return(0); 2113} 2114 2115struct sk_dmamap_arg { 2116 bus_addr_t sk_busaddr; 2117}; 2118 2119static void 2120sk_dmamap_cb(arg, segs, nseg, error) 2121 void *arg; 2122 bus_dma_segment_t *segs; 2123 int nseg; 2124 int error; 2125{ 2126 struct sk_dmamap_arg *ctx; 2127 2128 if (error != 0) 2129 return; 2130 2131 ctx = arg; 2132 ctx->sk_busaddr = segs[0].ds_addr; 2133} 2134 2135/* 2136 * Allocate jumbo buffer storage. The SysKonnect adapters support 2137 * "jumbograms" (9K frames), although SysKonnect doesn't currently 2138 * use them in their drivers. In order for us to use them, we need 2139 * large 9K receive buffers, however standard mbuf clusters are only 2140 * 2048 bytes in size. Consequently, we need to allocate and manage 2141 * our own jumbo buffer pool. Fortunately, this does not require an 2142 * excessive amount of additional code. 2143 */ 2144static int 2145sk_dma_alloc(sc_if) 2146 struct sk_if_softc *sc_if; 2147{ 2148 struct sk_dmamap_arg ctx; 2149 struct sk_txdesc *txd; 2150 struct sk_rxdesc *rxd; 2151 struct sk_rxdesc *jrxd; 2152 u_int8_t *ptr; 2153 struct sk_jpool_entry *entry; 2154 int error, i; 2155 2156 mtx_init(&sc_if->sk_jlist_mtx, "sk_jlist_mtx", NULL, MTX_DEF); 2157 SLIST_INIT(&sc_if->sk_jfree_listhead); 2158 SLIST_INIT(&sc_if->sk_jinuse_listhead); 2159 2160 /* create parent tag */ 2161 /* 2162 * XXX 2163 * This driver should use BUS_SPACE_MAXADDR for lowaddr argument 2164 * in bus_dma_tag_create(9) as the NIC would support DAC mode. 2165 * However bz@ reported that it does not work on amd64 with > 4GB 2166 * RAM. Until we have more clues of the breakage, disable DAC mode 2167 * by limiting DMA address to be in 32bit address space. 2168 */ 2169 error = bus_dma_tag_create(NULL, /* parent */ 2170 1, 0, /* algnmnt, boundary */ 2171 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 2172 BUS_SPACE_MAXADDR, /* highaddr */ 2173 NULL, NULL, /* filter, filterarg */ 2174 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 2175 0, /* nsegments */ 2176 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 2177 0, /* flags */ 2178 NULL, NULL, /* lockfunc, lockarg */ 2179 &sc_if->sk_cdata.sk_parent_tag); 2180 if (error != 0) { 2181 device_printf(sc_if->sk_if_dev, 2182 "failed to create parent DMA tag\n"); 2183 goto fail; 2184 } 2185 /* create tag for Tx ring */ 2186 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */ 2187 SK_RING_ALIGN, 0, /* algnmnt, boundary */ 2188 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 2189 BUS_SPACE_MAXADDR, /* highaddr */ 2190 NULL, NULL, /* filter, filterarg */ 2191 SK_TX_RING_SZ, /* maxsize */ 2192 1, /* nsegments */ 2193 SK_TX_RING_SZ, /* maxsegsize */ 2194 0, /* flags */ 2195 NULL, NULL, /* lockfunc, lockarg */ 2196 &sc_if->sk_cdata.sk_tx_ring_tag); 2197 if (error != 0) { 2198 device_printf(sc_if->sk_if_dev, 2199 "failed to allocate Tx ring DMA tag\n"); 2200 goto fail; 2201 } 2202 2203 /* create tag for Rx ring */ 2204 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */ 2205 SK_RING_ALIGN, 0, /* algnmnt, boundary */ 2206 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 2207 BUS_SPACE_MAXADDR, /* highaddr */ 2208 NULL, NULL, /* filter, filterarg */ 2209 SK_RX_RING_SZ, /* maxsize */ 2210 1, /* nsegments */ 2211 SK_RX_RING_SZ, /* maxsegsize */ 2212 0, /* flags */ 2213 NULL, NULL, /* lockfunc, lockarg */ 2214 &sc_if->sk_cdata.sk_rx_ring_tag); 2215 if (error != 0) { 2216 device_printf(sc_if->sk_if_dev, 2217 "failed to allocate Rx ring DMA tag\n"); 2218 goto fail; 2219 } 2220 2221 /* create tag for jumbo Rx ring */ 2222 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */ 2223 SK_RING_ALIGN, 0, /* algnmnt, boundary */ 2224 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 2225 BUS_SPACE_MAXADDR, /* highaddr */ 2226 NULL, NULL, /* filter, filterarg */ 2227 SK_JUMBO_RX_RING_SZ, /* maxsize */ 2228 1, /* nsegments */ 2229 SK_JUMBO_RX_RING_SZ, /* maxsegsize */ 2230 0, /* flags */ 2231 NULL, NULL, /* lockfunc, lockarg */ 2232 &sc_if->sk_cdata.sk_jumbo_rx_ring_tag); 2233 if (error != 0) { 2234 device_printf(sc_if->sk_if_dev, 2235 "failed to allocate jumbo Rx ring DMA tag\n"); 2236 goto fail; 2237 } 2238 2239 /* create tag for jumbo buffer blocks */ 2240 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */ 2241 PAGE_SIZE, 0, /* algnmnt, boundary */ 2242 BUS_SPACE_MAXADDR, /* lowaddr */ 2243 BUS_SPACE_MAXADDR, /* highaddr */ 2244 NULL, NULL, /* filter, filterarg */ 2245 SK_JMEM, /* maxsize */ 2246 1, /* nsegments */ 2247 SK_JMEM, /* maxsegsize */ 2248 0, /* flags */ 2249 NULL, NULL, /* lockfunc, lockarg */ 2250 &sc_if->sk_cdata.sk_jumbo_tag); 2251 if (error != 0) { 2252 device_printf(sc_if->sk_if_dev, 2253 "failed to allocate jumbo Rx buffer block DMA tag\n"); 2254 goto fail; 2255 } 2256 2257 /* create tag for Tx buffers */ 2258 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */ 2259 1, 0, /* algnmnt, boundary */ 2260 BUS_SPACE_MAXADDR, /* lowaddr */ 2261 BUS_SPACE_MAXADDR, /* highaddr */ 2262 NULL, NULL, /* filter, filterarg */ 2263 MCLBYTES * SK_MAXTXSEGS, /* maxsize */ 2264 SK_MAXTXSEGS, /* nsegments */ 2265 MCLBYTES, /* maxsegsize */ 2266 0, /* flags */ 2267 NULL, NULL, /* lockfunc, lockarg */ 2268 &sc_if->sk_cdata.sk_tx_tag); 2269 if (error != 0) { 2270 device_printf(sc_if->sk_if_dev, 2271 "failed to allocate Tx DMA tag\n"); 2272 goto fail; 2273 } 2274 2275 /* create tag for Rx buffers */ 2276 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */ 2277 1, 0, /* algnmnt, boundary */ 2278 BUS_SPACE_MAXADDR, /* lowaddr */ 2279 BUS_SPACE_MAXADDR, /* highaddr */ 2280 NULL, NULL, /* filter, filterarg */ 2281 MCLBYTES, /* maxsize */ 2282 1, /* nsegments */ 2283 MCLBYTES, /* maxsegsize */ 2284 0, /* flags */ 2285 NULL, NULL, /* lockfunc, lockarg */ 2286 &sc_if->sk_cdata.sk_rx_tag); 2287 if (error != 0) { 2288 device_printf(sc_if->sk_if_dev, 2289 "failed to allocate Rx DMA tag\n"); 2290 goto fail; 2291 } 2292 2293 /* create tag for jumbo Rx buffers */ 2294 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */ 2295 PAGE_SIZE, 0, /* algnmnt, boundary */ 2296 BUS_SPACE_MAXADDR, /* lowaddr */ 2297 BUS_SPACE_MAXADDR, /* highaddr */ 2298 NULL, NULL, /* filter, filterarg */ 2299 MCLBYTES * SK_MAXRXSEGS, /* maxsize */ 2300 SK_MAXRXSEGS, /* nsegments */ 2301 SK_JLEN, /* maxsegsize */ 2302 0, /* flags */ 2303 NULL, NULL, /* lockfunc, lockarg */ 2304 &sc_if->sk_cdata.sk_jumbo_rx_tag); 2305 if (error != 0) { 2306 device_printf(sc_if->sk_if_dev, 2307 "failed to allocate jumbo Rx DMA tag\n"); 2308 goto fail; 2309 } 2310 2311 /* allocate DMA'able memory and load the DMA map for Tx ring */ 2312 error = bus_dmamem_alloc(sc_if->sk_cdata.sk_tx_ring_tag, 2313 (void **)&sc_if->sk_rdata.sk_tx_ring, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 2314 &sc_if->sk_cdata.sk_tx_ring_map); 2315 if (error != 0) { 2316 device_printf(sc_if->sk_if_dev, 2317 "failed to allocate DMA'able memory for Tx ring\n"); 2318 goto fail; 2319 } 2320 2321 ctx.sk_busaddr = 0; 2322 error = bus_dmamap_load(sc_if->sk_cdata.sk_tx_ring_tag, 2323 sc_if->sk_cdata.sk_tx_ring_map, sc_if->sk_rdata.sk_tx_ring, 2324 SK_TX_RING_SZ, sk_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 2325 if (error != 0) { 2326 device_printf(sc_if->sk_if_dev, 2327 "failed to load DMA'able memory for Tx ring\n"); 2328 goto fail; 2329 } 2330 sc_if->sk_rdata.sk_tx_ring_paddr = ctx.sk_busaddr; 2331 2332 /* allocate DMA'able memory and load the DMA map for Rx ring */ 2333 error = bus_dmamem_alloc(sc_if->sk_cdata.sk_rx_ring_tag, 2334 (void **)&sc_if->sk_rdata.sk_rx_ring, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 2335 &sc_if->sk_cdata.sk_rx_ring_map); 2336 if (error != 0) { 2337 device_printf(sc_if->sk_if_dev, 2338 "failed to allocate DMA'able memory for Rx ring\n"); 2339 goto fail; 2340 } 2341 2342 ctx.sk_busaddr = 0; 2343 error = bus_dmamap_load(sc_if->sk_cdata.sk_rx_ring_tag, 2344 sc_if->sk_cdata.sk_rx_ring_map, sc_if->sk_rdata.sk_rx_ring, 2345 SK_RX_RING_SZ, sk_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 2346 if (error != 0) { 2347 device_printf(sc_if->sk_if_dev, 2348 "failed to load DMA'able memory for Rx ring\n"); 2349 goto fail; 2350 } 2351 sc_if->sk_rdata.sk_rx_ring_paddr = ctx.sk_busaddr; 2352 2353 /* allocate DMA'able memory and load the DMA map for jumbo Rx ring */ 2354 error = bus_dmamem_alloc(sc_if->sk_cdata.sk_jumbo_rx_ring_tag, 2355 (void **)&sc_if->sk_rdata.sk_jumbo_rx_ring, 2356 BUS_DMA_NOWAIT|BUS_DMA_ZERO, &sc_if->sk_cdata.sk_jumbo_rx_ring_map); 2357 if (error != 0) { 2358 device_printf(sc_if->sk_if_dev, 2359 "failed to allocate DMA'able memory for jumbo Rx ring\n"); 2360 goto fail; 2361 } 2362 2363 ctx.sk_busaddr = 0; 2364 error = bus_dmamap_load(sc_if->sk_cdata.sk_jumbo_rx_ring_tag, 2365 sc_if->sk_cdata.sk_jumbo_rx_ring_map, 2366 sc_if->sk_rdata.sk_jumbo_rx_ring, SK_JUMBO_RX_RING_SZ, sk_dmamap_cb, 2367 &ctx, BUS_DMA_NOWAIT); 2368 if (error != 0) { 2369 device_printf(sc_if->sk_if_dev, 2370 "failed to load DMA'able memory for jumbo Rx ring\n"); 2371 goto fail; 2372 } 2373 sc_if->sk_rdata.sk_jumbo_rx_ring_paddr = ctx.sk_busaddr; 2374 2375 /* create DMA maps for Tx buffers */ 2376 for (i = 0; i < SK_TX_RING_CNT; i++) { 2377 txd = &sc_if->sk_cdata.sk_txdesc[i]; 2378 txd->tx_m = NULL; 2379 txd->tx_dmamap = 0; 2380 error = bus_dmamap_create(sc_if->sk_cdata.sk_tx_tag, 0, 2381 &txd->tx_dmamap); 2382 if (error != 0) { 2383 device_printf(sc_if->sk_if_dev, 2384 "failed to create Tx dmamap\n"); 2385 goto fail; 2386 } 2387 } 2388 /* create DMA maps for Rx buffers */ 2389 if ((error = bus_dmamap_create(sc_if->sk_cdata.sk_rx_tag, 0, 2390 &sc_if->sk_cdata.sk_rx_sparemap)) != 0) { 2391 device_printf(sc_if->sk_if_dev, 2392 "failed to create spare Rx dmamap\n"); 2393 goto fail; 2394 } 2395 for (i = 0; i < SK_RX_RING_CNT; i++) { 2396 rxd = &sc_if->sk_cdata.sk_rxdesc[i]; 2397 rxd->rx_m = NULL; 2398 rxd->rx_dmamap = 0; 2399 error = bus_dmamap_create(sc_if->sk_cdata.sk_rx_tag, 0, 2400 &rxd->rx_dmamap); 2401 if (error != 0) { 2402 device_printf(sc_if->sk_if_dev, 2403 "failed to create Rx dmamap\n"); 2404 goto fail; 2405 } 2406 } 2407 /* create DMA maps for jumbo Rx buffers */ 2408 if ((error = bus_dmamap_create(sc_if->sk_cdata.sk_jumbo_rx_tag, 0, 2409 &sc_if->sk_cdata.sk_jumbo_rx_sparemap)) != 0) { 2410 device_printf(sc_if->sk_if_dev, 2411 "failed to create spare jumbo Rx dmamap\n"); 2412 goto fail; 2413 } 2414 for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) { 2415 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[i]; 2416 jrxd->rx_m = NULL; 2417 jrxd->rx_dmamap = 0; 2418 error = bus_dmamap_create(sc_if->sk_cdata.sk_jumbo_rx_tag, 0, 2419 &jrxd->rx_dmamap); 2420 if (error != 0) { 2421 device_printf(sc_if->sk_if_dev, 2422 "failed to create jumbo Rx dmamap\n"); 2423 goto fail; 2424 } 2425 } 2426 2427 /* allocate DMA'able memory and load the DMA map for jumbo buf */ 2428 error = bus_dmamem_alloc(sc_if->sk_cdata.sk_jumbo_tag, 2429 (void **)&sc_if->sk_rdata.sk_jumbo_buf, 2430 BUS_DMA_NOWAIT|BUS_DMA_ZERO, &sc_if->sk_cdata.sk_jumbo_map); 2431 if (error != 0) { 2432 device_printf(sc_if->sk_if_dev, 2433 "failed to allocate DMA'able memory for jumbo buf\n"); 2434 goto fail; 2435 } 2436 2437 ctx.sk_busaddr = 0; 2438 error = bus_dmamap_load(sc_if->sk_cdata.sk_jumbo_tag, 2439 sc_if->sk_cdata.sk_jumbo_map, 2440 sc_if->sk_rdata.sk_jumbo_buf, SK_JMEM, sk_dmamap_cb, 2441 &ctx, BUS_DMA_NOWAIT); 2442 if (error != 0) { 2443 device_printf(sc_if->sk_if_dev, 2444 "failed to load DMA'able memory for jumbobuf\n"); 2445 goto fail; 2446 } 2447 sc_if->sk_rdata.sk_jumbo_buf_paddr = ctx.sk_busaddr; 2448 2449 /* 2450 * Now divide it up into 9K pieces and save the addresses 2451 * in an array. 2452 */ 2453 ptr = sc_if->sk_rdata.sk_jumbo_buf; 2454 for (i = 0; i < SK_JSLOTS; i++) { 2455 sc_if->sk_cdata.sk_jslots[i] = ptr; 2456 ptr += SK_JLEN; 2457 entry = malloc(sizeof(struct sk_jpool_entry), 2458 M_DEVBUF, M_NOWAIT); 2459 if (entry == NULL) { 2460 device_printf(sc_if->sk_if_dev, 2461 "no memory for jumbo buffers!\n"); 2462 error = ENOMEM; 2463 goto fail; 2464 } 2465 entry->slot = i; 2466 SLIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, entry, 2467 jpool_entries); 2468 } 2469 2470fail: 2471 return (error); 2472} 2473 2474static void 2475sk_dma_free(sc_if) 2476 struct sk_if_softc *sc_if; 2477{ 2478 struct sk_txdesc *txd; 2479 struct sk_rxdesc *rxd; 2480 struct sk_rxdesc *jrxd; 2481 struct sk_jpool_entry *entry; 2482 int i; 2483 2484 SK_JLIST_LOCK(sc_if); 2485 while ((entry = SLIST_FIRST(&sc_if->sk_jinuse_listhead))) { 2486 device_printf(sc_if->sk_if_dev, 2487 "asked to free buffer that is in use!\n"); 2488 SLIST_REMOVE_HEAD(&sc_if->sk_jinuse_listhead, jpool_entries); 2489 SLIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, entry, 2490 jpool_entries); 2491 } 2492 2493 while (!SLIST_EMPTY(&sc_if->sk_jfree_listhead)) { 2494 entry = SLIST_FIRST(&sc_if->sk_jfree_listhead); 2495 SLIST_REMOVE_HEAD(&sc_if->sk_jfree_listhead, jpool_entries); 2496 free(entry, M_DEVBUF); 2497 } 2498 SK_JLIST_UNLOCK(sc_if); 2499 2500 /* destroy jumbo buffer block */ 2501 if (sc_if->sk_cdata.sk_jumbo_map) 2502 bus_dmamap_unload(sc_if->sk_cdata.sk_jumbo_tag, 2503 sc_if->sk_cdata.sk_jumbo_map); 2504 2505 if (sc_if->sk_rdata.sk_jumbo_buf) { 2506 bus_dmamem_free(sc_if->sk_cdata.sk_jumbo_tag, 2507 sc_if->sk_rdata.sk_jumbo_buf, 2508 sc_if->sk_cdata.sk_jumbo_map); 2509 sc_if->sk_rdata.sk_jumbo_buf = NULL; 2510 sc_if->sk_cdata.sk_jumbo_map = 0; 2511 } 2512 2513 /* Tx ring */ 2514 if (sc_if->sk_cdata.sk_tx_ring_tag) { 2515 if (sc_if->sk_cdata.sk_tx_ring_map) 2516 bus_dmamap_unload(sc_if->sk_cdata.sk_tx_ring_tag, 2517 sc_if->sk_cdata.sk_tx_ring_map); 2518 if (sc_if->sk_cdata.sk_tx_ring_map && 2519 sc_if->sk_rdata.sk_tx_ring) 2520 bus_dmamem_free(sc_if->sk_cdata.sk_tx_ring_tag, 2521 sc_if->sk_rdata.sk_tx_ring, 2522 sc_if->sk_cdata.sk_tx_ring_map); 2523 sc_if->sk_rdata.sk_tx_ring = NULL; 2524 sc_if->sk_cdata.sk_tx_ring_map = 0; 2525 bus_dma_tag_destroy(sc_if->sk_cdata.sk_tx_ring_tag); 2526 sc_if->sk_cdata.sk_tx_ring_tag = NULL; 2527 } 2528 /* Rx ring */ 2529 if (sc_if->sk_cdata.sk_rx_ring_tag) { 2530 if (sc_if->sk_cdata.sk_rx_ring_map) 2531 bus_dmamap_unload(sc_if->sk_cdata.sk_rx_ring_tag, 2532 sc_if->sk_cdata.sk_rx_ring_map); 2533 if (sc_if->sk_cdata.sk_rx_ring_map && 2534 sc_if->sk_rdata.sk_rx_ring) 2535 bus_dmamem_free(sc_if->sk_cdata.sk_rx_ring_tag, 2536 sc_if->sk_rdata.sk_rx_ring, 2537 sc_if->sk_cdata.sk_rx_ring_map); 2538 sc_if->sk_rdata.sk_rx_ring = NULL; 2539 sc_if->sk_cdata.sk_rx_ring_map = 0; 2540 bus_dma_tag_destroy(sc_if->sk_cdata.sk_rx_ring_tag); 2541 sc_if->sk_cdata.sk_rx_ring_tag = NULL; 2542 } 2543 /* jumbo Rx ring */ 2544 if (sc_if->sk_cdata.sk_jumbo_rx_ring_tag) { 2545 if (sc_if->sk_cdata.sk_jumbo_rx_ring_map) 2546 bus_dmamap_unload(sc_if->sk_cdata.sk_jumbo_rx_ring_tag, 2547 sc_if->sk_cdata.sk_jumbo_rx_ring_map); 2548 if (sc_if->sk_cdata.sk_jumbo_rx_ring_map && 2549 sc_if->sk_rdata.sk_jumbo_rx_ring) 2550 bus_dmamem_free(sc_if->sk_cdata.sk_jumbo_rx_ring_tag, 2551 sc_if->sk_rdata.sk_jumbo_rx_ring, 2552 sc_if->sk_cdata.sk_jumbo_rx_ring_map); 2553 sc_if->sk_rdata.sk_jumbo_rx_ring = NULL; 2554 sc_if->sk_cdata.sk_jumbo_rx_ring_map = 0; 2555 bus_dma_tag_destroy(sc_if->sk_cdata.sk_jumbo_rx_ring_tag); 2556 sc_if->sk_cdata.sk_jumbo_rx_ring_tag = NULL; 2557 } 2558 /* Tx buffers */ 2559 if (sc_if->sk_cdata.sk_tx_tag) { 2560 for (i = 0; i < SK_TX_RING_CNT; i++) { 2561 txd = &sc_if->sk_cdata.sk_txdesc[i]; 2562 if (txd->tx_dmamap) { 2563 bus_dmamap_destroy(sc_if->sk_cdata.sk_tx_tag, 2564 txd->tx_dmamap); 2565 txd->tx_dmamap = 0; 2566 } 2567 } 2568 bus_dma_tag_destroy(sc_if->sk_cdata.sk_tx_tag); 2569 sc_if->sk_cdata.sk_tx_tag = NULL; 2570 } 2571 /* Rx buffers */ 2572 if (sc_if->sk_cdata.sk_rx_tag) { 2573 for (i = 0; i < SK_RX_RING_CNT; i++) { 2574 rxd = &sc_if->sk_cdata.sk_rxdesc[i]; 2575 if (rxd->rx_dmamap) { 2576 bus_dmamap_destroy(sc_if->sk_cdata.sk_rx_tag, 2577 rxd->rx_dmamap); 2578 rxd->rx_dmamap = 0; 2579 } 2580 } 2581 if (sc_if->sk_cdata.sk_rx_sparemap) { 2582 bus_dmamap_destroy(sc_if->sk_cdata.sk_rx_tag, 2583 sc_if->sk_cdata.sk_rx_sparemap); 2584 sc_if->sk_cdata.sk_rx_sparemap = 0; 2585 } 2586 bus_dma_tag_destroy(sc_if->sk_cdata.sk_rx_tag); 2587 sc_if->sk_cdata.sk_rx_tag = NULL; 2588 } 2589 /* jumbo Rx buffers */ 2590 if (sc_if->sk_cdata.sk_jumbo_rx_tag) { 2591 for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) { 2592 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[i]; 2593 if (jrxd->rx_dmamap) { 2594 bus_dmamap_destroy( 2595 sc_if->sk_cdata.sk_jumbo_rx_tag, 2596 jrxd->rx_dmamap); 2597 jrxd->rx_dmamap = 0; 2598 } 2599 } 2600 if (sc_if->sk_cdata.sk_jumbo_rx_sparemap) { 2601 bus_dmamap_destroy(sc_if->sk_cdata.sk_jumbo_rx_tag, 2602 sc_if->sk_cdata.sk_jumbo_rx_sparemap); 2603 sc_if->sk_cdata.sk_jumbo_rx_sparemap = 0; 2604 } 2605 bus_dma_tag_destroy(sc_if->sk_cdata.sk_jumbo_rx_tag); 2606 sc_if->sk_cdata.sk_jumbo_rx_tag = NULL; 2607 } 2608 2609 if (sc_if->sk_cdata.sk_parent_tag) { 2610 bus_dma_tag_destroy(sc_if->sk_cdata.sk_parent_tag); 2611 sc_if->sk_cdata.sk_parent_tag = NULL; 2612 } 2613 mtx_destroy(&sc_if->sk_jlist_mtx); 2614} 2615 2616/* 2617 * Allocate a jumbo buffer. 2618 */ 2619static void * 2620sk_jalloc(sc_if) 2621 struct sk_if_softc *sc_if; 2622{ 2623 struct sk_jpool_entry *entry; 2624 2625 SK_JLIST_LOCK(sc_if); 2626 2627 entry = SLIST_FIRST(&sc_if->sk_jfree_listhead); 2628 2629 if (entry == NULL) { 2630 SK_JLIST_UNLOCK(sc_if); 2631 return (NULL); 2632 } 2633 2634 SLIST_REMOVE_HEAD(&sc_if->sk_jfree_listhead, jpool_entries); 2635 SLIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 2636 2637 SK_JLIST_UNLOCK(sc_if); 2638 2639 return (sc_if->sk_cdata.sk_jslots[entry->slot]); 2640} 2641 2642/* 2643 * Release a jumbo buffer. 2644 */ 2645static void 2646sk_jfree(buf, args) 2647 void *buf; 2648 void *args; 2649{ 2650 struct sk_if_softc *sc_if; 2651 struct sk_jpool_entry *entry; 2652 int i; 2653 2654 /* Extract the softc struct pointer. */ 2655 sc_if = (struct sk_if_softc *)args; 2656 KASSERT(sc_if != NULL, ("%s: can't find softc pointer!", __func__)); 2657 2658 SK_JLIST_LOCK(sc_if); 2659 /* calculate the slot this buffer belongs to */ 2660 i = ((vm_offset_t)buf 2661 - (vm_offset_t)sc_if->sk_rdata.sk_jumbo_buf) / SK_JLEN; 2662 KASSERT(i >= 0 && i < SK_JSLOTS, 2663 ("%s: asked to free buffer that we don't manage!", __func__)); 2664 2665 entry = SLIST_FIRST(&sc_if->sk_jinuse_listhead); 2666 KASSERT(entry != NULL, ("%s: buffer not in use!", __func__)); 2667 entry->slot = i; 2668 SLIST_REMOVE_HEAD(&sc_if->sk_jinuse_listhead, jpool_entries); 2669 SLIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, entry, jpool_entries); 2670 if (SLIST_EMPTY(&sc_if->sk_jinuse_listhead)) 2671 wakeup(sc_if); 2672 2673 SK_JLIST_UNLOCK(sc_if); 2674} 2675 2676static void 2677sk_txcksum(ifp, m, f) 2678 struct ifnet *ifp; 2679 struct mbuf *m; 2680 struct sk_tx_desc *f; 2681{ 2682 struct ip *ip; 2683 u_int16_t offset; 2684 u_int8_t *p; 2685 2686 offset = sizeof(struct ip) + ETHER_HDR_LEN; 2687 for(; m && m->m_len == 0; m = m->m_next) 2688 ; 2689 if (m == NULL || m->m_len < ETHER_HDR_LEN) { 2690 if_printf(ifp, "%s: m_len < ETHER_HDR_LEN\n", __func__); 2691 /* checksum may be corrupted */ 2692 goto sendit; 2693 } 2694 if (m->m_len < ETHER_HDR_LEN + sizeof(u_int32_t)) { 2695 if (m->m_len != ETHER_HDR_LEN) { 2696 if_printf(ifp, "%s: m_len != ETHER_HDR_LEN\n", 2697 __func__); 2698 /* checksum may be corrupted */ 2699 goto sendit; 2700 } 2701 for(m = m->m_next; m && m->m_len == 0; m = m->m_next) 2702 ; 2703 if (m == NULL) { 2704 offset = sizeof(struct ip) + ETHER_HDR_LEN; 2705 /* checksum may be corrupted */ 2706 goto sendit; 2707 } 2708 ip = mtod(m, struct ip *); 2709 } else { 2710 p = mtod(m, u_int8_t *); 2711 p += ETHER_HDR_LEN; 2712 ip = (struct ip *)p; 2713 } 2714 offset = (ip->ip_hl << 2) + ETHER_HDR_LEN; 2715 2716sendit: 2717 f->sk_csum_startval = 0; 2718 f->sk_csum_start = htole32(((offset + m->m_pkthdr.csum_data) & 0xffff) | 2719 (offset << 16)); 2720} 2721 2722static int 2723sk_encap(sc_if, m_head) 2724 struct sk_if_softc *sc_if; 2725 struct mbuf **m_head; 2726{ 2727 struct sk_txdesc *txd; 2728 struct sk_tx_desc *f = NULL; 2729 struct mbuf *m, *n; 2730 bus_dma_segment_t txsegs[SK_MAXTXSEGS]; 2731 u_int32_t cflags, frag, si, sk_ctl; 2732 int error, i, nseg; 2733 2734 SK_IF_LOCK_ASSERT(sc_if); 2735 2736 if ((txd = STAILQ_FIRST(&sc_if->sk_cdata.sk_txfreeq)) == NULL) 2737 return (ENOBUFS); 2738 2739 m = *m_head; 2740 error = bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_tx_tag, 2741 txd->tx_dmamap, m, txsegs, &nseg, 0); 2742 if (error == EFBIG) { 2743 n = m_defrag(m, M_DONTWAIT); 2744 if (n == NULL) { 2745 m_freem(m); 2746 m = NULL; 2747 return (ENOMEM); 2748 } 2749 m = n; 2750 error = bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_tx_tag, 2751 txd->tx_dmamap, m, txsegs, &nseg, 0); 2752 if (error != 0) { 2753 m_freem(m); 2754 m = NULL; 2755 return (error); 2756 } 2757 } else if (error != 0) 2758 return (error); 2759 if (nseg == 0) { 2760 m_freem(m); 2761 m = NULL; 2762 return (EIO); 2763 } 2764 if (sc_if->sk_cdata.sk_tx_cnt + nseg >= SK_TX_RING_CNT) { 2765 bus_dmamap_unload(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap); 2766 return (ENOBUFS); 2767 } 2768 2769 if ((m->m_pkthdr.csum_flags & sc_if->sk_ifp->if_hwassist) != 0) 2770 cflags = SK_OPCODE_CSUM; 2771 else 2772 cflags = SK_OPCODE_DEFAULT; 2773 si = frag = sc_if->sk_cdata.sk_tx_prod; 2774 for (i = 0; i < nseg; i++) { 2775 f = &sc_if->sk_rdata.sk_tx_ring[frag]; 2776 f->sk_data_lo = htole32(SK_ADDR_LO(txsegs[i].ds_addr)); 2777 f->sk_data_hi = htole32(SK_ADDR_HI(txsegs[i].ds_addr)); 2778 sk_ctl = txsegs[i].ds_len | cflags; 2779 if (i == 0) { 2780 if (cflags == SK_OPCODE_CSUM) 2781 sk_txcksum(sc_if->sk_ifp, m, f); 2782 sk_ctl |= SK_TXCTL_FIRSTFRAG; 2783 } else 2784 sk_ctl |= SK_TXCTL_OWN; 2785 f->sk_ctl = htole32(sk_ctl); 2786 sc_if->sk_cdata.sk_tx_cnt++; 2787 SK_INC(frag, SK_TX_RING_CNT); 2788 } 2789 sc_if->sk_cdata.sk_tx_prod = frag; 2790 2791 /* set EOF on the last desciptor */ 2792 frag = (frag + SK_TX_RING_CNT - 1) % SK_TX_RING_CNT; 2793 f = &sc_if->sk_rdata.sk_tx_ring[frag]; 2794 f->sk_ctl |= htole32(SK_TXCTL_LASTFRAG | SK_TXCTL_EOF_INTR); 2795 2796 /* turn the first descriptor ownership to NIC */ 2797 f = &sc_if->sk_rdata.sk_tx_ring[si]; 2798 f->sk_ctl |= htole32(SK_TXCTL_OWN); 2799 2800 STAILQ_REMOVE_HEAD(&sc_if->sk_cdata.sk_txfreeq, tx_q); 2801 STAILQ_INSERT_TAIL(&sc_if->sk_cdata.sk_txbusyq, txd, tx_q); 2802 txd->tx_m = m; 2803 2804 /* sync descriptors */ 2805 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap, 2806 BUS_DMASYNC_PREWRITE); 2807 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag, 2808 sc_if->sk_cdata.sk_tx_ring_map, 2809 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2810 2811 return (0); 2812} 2813 2814static void 2815sk_start(ifp) 2816 struct ifnet *ifp; 2817{ 2818 struct sk_if_softc *sc_if; 2819 2820 sc_if = ifp->if_softc; 2821 2822 SK_IF_LOCK(sc_if); 2823 sk_start_locked(ifp); 2824 SK_IF_UNLOCK(sc_if); 2825 2826 return; 2827} 2828 2829static void 2830sk_start_locked(ifp) 2831 struct ifnet *ifp; 2832{ 2833 struct sk_softc *sc; 2834 struct sk_if_softc *sc_if; 2835 struct mbuf *m_head; 2836 int enq; 2837 2838 sc_if = ifp->if_softc; 2839 sc = sc_if->sk_softc; 2840 2841 SK_IF_LOCK_ASSERT(sc_if); 2842 2843 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2844 sc_if->sk_cdata.sk_tx_cnt < SK_TX_RING_CNT - 1; ) { 2845 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2846 if (m_head == NULL) 2847 break; 2848 2849 /* 2850 * Pack the data into the transmit ring. If we 2851 * don't have room, set the OACTIVE flag and wait 2852 * for the NIC to drain the ring. 2853 */ 2854 if (sk_encap(sc_if, &m_head)) { 2855 if (m_head == NULL) 2856 break; 2857 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2858 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2859 break; 2860 } 2861 2862 enq++; 2863 /* 2864 * If there's a BPF listener, bounce a copy of this frame 2865 * to him. 2866 */ 2867 BPF_MTAP(ifp, m_head); 2868 } 2869 2870 if (enq > 0) { 2871 /* Transmit */ 2872 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 2873 2874 /* Set a timeout in case the chip goes out to lunch. */ 2875 ifp->if_timer = 5; 2876 } 2877} 2878 2879 2880static void 2881sk_watchdog(ifp) 2882 struct ifnet *ifp; 2883{ 2884 struct sk_if_softc *sc_if; 2885 2886 sc_if = ifp->if_softc; 2887 2888 SK_IF_LOCK(sc_if); 2889 if_printf(sc_if->sk_ifp, "watchdog timeout\n"); 2890 ifp->if_oerrors++; 2891 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2892 sk_init_locked(sc_if); 2893 SK_IF_UNLOCK(sc_if); 2894 2895 return; 2896} 2897 2898static void 2899skc_shutdown(dev) 2900 device_t dev; 2901{ 2902 struct sk_softc *sc; 2903 2904 sc = device_get_softc(dev); 2905 SK_LOCK(sc); 2906 2907 /* Turn off the 'driver is loaded' LED. */ 2908 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 2909 2910 /* 2911 * Reset the GEnesis controller. Doing this should also 2912 * assert the resets on the attached XMAC(s). 2913 */ 2914 sk_reset(sc); 2915 SK_UNLOCK(sc); 2916 2917 return; 2918} 2919 2920static int 2921skc_suspend(dev) 2922 device_t dev; 2923{ 2924 struct sk_softc *sc; 2925 struct sk_if_softc *sc_if0, *sc_if1; 2926 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2927 2928 sc = device_get_softc(dev); 2929 2930 SK_LOCK(sc); 2931 2932 sc_if0 = sc->sk_if[SK_PORT_A]; 2933 sc_if1 = sc->sk_if[SK_PORT_B]; 2934 if (sc_if0 != NULL) 2935 ifp0 = sc_if0->sk_ifp; 2936 if (sc_if1 != NULL) 2937 ifp1 = sc_if1->sk_ifp; 2938 if (ifp0 != NULL) 2939 sk_stop(sc_if0); 2940 if (ifp1 != NULL) 2941 sk_stop(sc_if1); 2942 sc->sk_suspended = 1; 2943 2944 SK_UNLOCK(sc); 2945 2946 return (0); 2947} 2948 2949static int 2950skc_resume(dev) 2951 device_t dev; 2952{ 2953 struct sk_softc *sc; 2954 struct sk_if_softc *sc_if0, *sc_if1; 2955 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2956 2957 sc = device_get_softc(dev); 2958 2959 SK_LOCK(sc); 2960 2961 sc_if0 = sc->sk_if[SK_PORT_A]; 2962 sc_if1 = sc->sk_if[SK_PORT_B]; 2963 if (sc_if0 != NULL) 2964 ifp0 = sc_if0->sk_ifp; 2965 if (sc_if1 != NULL) 2966 ifp1 = sc_if1->sk_ifp; 2967 if (ifp0 != NULL && ifp0->if_flags & IFF_UP) 2968 sk_init_locked(sc_if0); 2969 if (ifp1 != NULL && ifp1->if_flags & IFF_UP) 2970 sk_init_locked(sc_if1); 2971 sc->sk_suspended = 0; 2972 2973 SK_UNLOCK(sc); 2974 2975 return (0); 2976} 2977 2978/* 2979 * According to the data sheet from SK-NET GENESIS the hardware can compute 2980 * two Rx checksums at the same time(Each checksum start position is 2981 * programmed in Rx descriptors). However it seems that TCP/UDP checksum 2982 * does not work at least on my Yukon hardware. I tried every possible ways 2983 * to get correct checksum value but couldn't get correct one. So TCP/UDP 2984 * checksum offload was disabled at the moment and only IP checksum offload 2985 * was enabled. 2986 * As nomral IP header size is 20 bytes I can't expect it would give an 2987 * increase in throughput. However it seems it doesn't hurt performance in 2988 * my testing. If there is a more detailed information for checksum secret 2989 * of the hardware in question please contact yongari@FreeBSD.org to add 2990 * TCP/UDP checksum offload support. 2991 */ 2992static __inline void 2993sk_rxcksum(ifp, m, csum) 2994 struct ifnet *ifp; 2995 struct mbuf *m; 2996 u_int32_t csum; 2997{ 2998 struct ether_header *eh; 2999 struct ip *ip; 3000 int32_t hlen, len, pktlen; 3001 u_int16_t csum1, csum2, ipcsum; 3002 3003 pktlen = m->m_pkthdr.len; 3004 if (pktlen < sizeof(struct ether_header) + sizeof(struct ip)) 3005 return; 3006 eh = mtod(m, struct ether_header *); 3007 if (eh->ether_type != htons(ETHERTYPE_IP)) 3008 return; 3009 ip = (struct ip *)(eh + 1); 3010 if (ip->ip_v != IPVERSION) 3011 return; 3012 hlen = ip->ip_hl << 2; 3013 pktlen -= sizeof(struct ether_header); 3014 if (hlen < sizeof(struct ip)) 3015 return; 3016 if (ntohs(ip->ip_len) < hlen) 3017 return; 3018 if (ntohs(ip->ip_len) != pktlen) 3019 return; 3020 3021 csum1 = htons(csum & 0xffff); 3022 csum2 = htons((csum >> 16) & 0xffff); 3023 ipcsum = in_addword(csum1, ~csum2 & 0xffff); 3024 /* checksum fixup for IP options */ 3025 len = hlen - sizeof(struct ip); 3026 if (len > 0) { 3027 /* 3028 * If the second checksum value is correct we can compute IP 3029 * checksum with simple math. Unfortunately the second checksum 3030 * value is wrong so we can't verify the checksum from the 3031 * value(It seems there is some magic here to get correct 3032 * value). If the second checksum value is correct it also 3033 * means we can get TCP/UDP checksum) here. However, it still 3034 * needs pseudo header checksum calculation due to hardware 3035 * limitations. 3036 */ 3037 return; 3038 } 3039 m->m_pkthdr.csum_flags = CSUM_IP_CHECKED; 3040 if (ipcsum == 0xffff) 3041 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 3042} 3043 3044static __inline int 3045sk_rxvalid(sc, stat, len) 3046 struct sk_softc *sc; 3047 u_int32_t stat, len; 3048{ 3049 3050 if (sc->sk_type == SK_GENESIS) { 3051 if ((stat & XM_RXSTAT_ERRFRAME) == XM_RXSTAT_ERRFRAME || 3052 XM_RXSTAT_BYTES(stat) != len) 3053 return (0); 3054 } else { 3055 if ((stat & (YU_RXSTAT_CRCERR | YU_RXSTAT_LONGERR | 3056 YU_RXSTAT_MIIERR | YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | 3057 YU_RXSTAT_JABBER)) != 0 || 3058 (stat & YU_RXSTAT_RXOK) != YU_RXSTAT_RXOK || 3059 YU_RXSTAT_BYTES(stat) != len) 3060 return (0); 3061 } 3062 3063 return (1); 3064} 3065 3066static void 3067sk_rxeof(sc_if) 3068 struct sk_if_softc *sc_if; 3069{ 3070 struct sk_softc *sc; 3071 struct mbuf *m; 3072 struct ifnet *ifp; 3073 struct sk_rx_desc *cur_rx; 3074 struct sk_rxdesc *rxd; 3075 int cons, prog; 3076 u_int32_t csum, rxstat, sk_ctl; 3077 3078 sc = sc_if->sk_softc; 3079 ifp = sc_if->sk_ifp; 3080 3081 SK_IF_LOCK_ASSERT(sc_if); 3082 3083 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_ring_tag, 3084 sc_if->sk_cdata.sk_rx_ring_map, BUS_DMASYNC_POSTREAD); 3085 3086 prog = 0; 3087 for (cons = sc_if->sk_cdata.sk_rx_cons; prog < SK_RX_RING_CNT; 3088 prog++, SK_INC(cons, SK_RX_RING_CNT)) { 3089 cur_rx = &sc_if->sk_rdata.sk_rx_ring[cons]; 3090 sk_ctl = le32toh(cur_rx->sk_ctl); 3091 if ((sk_ctl & SK_RXCTL_OWN) != 0) 3092 break; 3093 rxd = &sc_if->sk_cdata.sk_rxdesc[cons]; 3094 rxstat = le32toh(cur_rx->sk_xmac_rxstat); 3095 3096 if ((sk_ctl & (SK_RXCTL_STATUS_VALID | SK_RXCTL_FIRSTFRAG | 3097 SK_RXCTL_LASTFRAG)) != (SK_RXCTL_STATUS_VALID | 3098 SK_RXCTL_FIRSTFRAG | SK_RXCTL_LASTFRAG) || 3099 SK_RXBYTES(sk_ctl) < SK_MIN_FRAMELEN || 3100 SK_RXBYTES(sk_ctl) > SK_MAX_FRAMELEN || 3101 sk_rxvalid(sc, rxstat, SK_RXBYTES(sk_ctl)) == 0) { 3102 ifp->if_ierrors++; 3103 sk_discard_rxbuf(sc_if, cons); 3104 continue; 3105 } 3106 3107 m = rxd->rx_m; 3108 csum = le32toh(cur_rx->sk_csum); 3109 if (sk_newbuf(sc_if, cons) != 0) { 3110 ifp->if_iqdrops++; 3111 /* reuse old buffer */ 3112 sk_discard_rxbuf(sc_if, cons); 3113 continue; 3114 } 3115 m->m_pkthdr.rcvif = ifp; 3116 m->m_pkthdr.len = m->m_len = SK_RXBYTES(sk_ctl); 3117 ifp->if_ipackets++; 3118 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 3119 sk_rxcksum(ifp, m, csum); 3120 SK_IF_UNLOCK(sc_if); 3121 (*ifp->if_input)(ifp, m); 3122 SK_IF_LOCK(sc_if); 3123 } 3124 3125 if (prog > 0) { 3126 sc_if->sk_cdata.sk_rx_cons = cons; 3127 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_ring_tag, 3128 sc_if->sk_cdata.sk_rx_ring_map, 3129 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3130 } 3131} 3132 3133static void 3134sk_jumbo_rxeof(sc_if) 3135 struct sk_if_softc *sc_if; 3136{ 3137 struct sk_softc *sc; 3138 struct mbuf *m; 3139 struct ifnet *ifp; 3140 struct sk_rx_desc *cur_rx; 3141 struct sk_rxdesc *jrxd; 3142 int cons, prog; 3143 u_int32_t csum, rxstat, sk_ctl; 3144 3145 sc = sc_if->sk_softc; 3146 ifp = sc_if->sk_ifp; 3147 3148 SK_IF_LOCK_ASSERT(sc_if); 3149 3150 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_ring_tag, 3151 sc_if->sk_cdata.sk_jumbo_rx_ring_map, BUS_DMASYNC_POSTREAD); 3152 3153 prog = 0; 3154 for (cons = sc_if->sk_cdata.sk_jumbo_rx_cons; 3155 prog < SK_JUMBO_RX_RING_CNT; 3156 prog++, SK_INC(cons, SK_JUMBO_RX_RING_CNT)) { 3157 cur_rx = &sc_if->sk_rdata.sk_jumbo_rx_ring[cons]; 3158 sk_ctl = le32toh(cur_rx->sk_ctl); 3159 if ((sk_ctl & SK_RXCTL_OWN) != 0) 3160 break; 3161 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[cons]; 3162 rxstat = le32toh(cur_rx->sk_xmac_rxstat); 3163 3164 if ((sk_ctl & (SK_RXCTL_STATUS_VALID | SK_RXCTL_FIRSTFRAG | 3165 SK_RXCTL_LASTFRAG)) != (SK_RXCTL_STATUS_VALID | 3166 SK_RXCTL_FIRSTFRAG | SK_RXCTL_LASTFRAG) || 3167 SK_RXBYTES(sk_ctl) < SK_MIN_FRAMELEN || 3168 SK_RXBYTES(sk_ctl) > SK_JUMBO_FRAMELEN || 3169 sk_rxvalid(sc, rxstat, SK_RXBYTES(sk_ctl)) == 0) { 3170 ifp->if_ierrors++; 3171 sk_discard_jumbo_rxbuf(sc_if, cons); 3172 continue; 3173 } 3174 3175 m = jrxd->rx_m; 3176 csum = le32toh(cur_rx->sk_csum); 3177 if (sk_jumbo_newbuf(sc_if, cons) != 0) { 3178 ifp->if_iqdrops++; 3179 /* reuse old buffer */ 3180 sk_discard_jumbo_rxbuf(sc_if, cons); 3181 continue; 3182 } 3183 m->m_pkthdr.rcvif = ifp; 3184 m->m_pkthdr.len = m->m_len = SK_RXBYTES(sk_ctl); 3185 ifp->if_ipackets++; 3186 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 3187 sk_rxcksum(ifp, m, csum); 3188 SK_IF_UNLOCK(sc_if); 3189 (*ifp->if_input)(ifp, m); 3190 SK_IF_LOCK(sc_if); 3191 } 3192 3193 if (prog > 0) { 3194 sc_if->sk_cdata.sk_jumbo_rx_cons = cons; 3195 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_ring_tag, 3196 sc_if->sk_cdata.sk_jumbo_rx_ring_map, 3197 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3198 } 3199} 3200 3201static void 3202sk_txeof(sc_if) 3203 struct sk_if_softc *sc_if; 3204{ 3205 struct sk_softc *sc; 3206 struct sk_txdesc *txd; 3207 struct sk_tx_desc *cur_tx; 3208 struct ifnet *ifp; 3209 u_int32_t idx, sk_ctl; 3210 3211 sc = sc_if->sk_softc; 3212 ifp = sc_if->sk_ifp; 3213 3214 txd = STAILQ_FIRST(&sc_if->sk_cdata.sk_txbusyq); 3215 if (txd == NULL) 3216 return; 3217 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag, 3218 sc_if->sk_cdata.sk_tx_ring_map, BUS_DMASYNC_POSTREAD); 3219 /* 3220 * Go through our tx ring and free mbufs for those 3221 * frames that have been sent. 3222 */ 3223 for (idx = sc_if->sk_cdata.sk_tx_cons;; SK_INC(idx, SK_TX_RING_CNT)) { 3224 if (sc_if->sk_cdata.sk_tx_cnt <= 0) 3225 break; 3226 cur_tx = &sc_if->sk_rdata.sk_tx_ring[idx]; 3227 sk_ctl = le32toh(cur_tx->sk_ctl); 3228 if (sk_ctl & SK_TXCTL_OWN) 3229 break; 3230 sc_if->sk_cdata.sk_tx_cnt--; 3231 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3232 if ((sk_ctl & SK_TXCTL_LASTFRAG) == 0) 3233 continue; 3234 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap, 3235 BUS_DMASYNC_POSTWRITE); 3236 bus_dmamap_unload(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap); 3237 3238 ifp->if_opackets++; 3239 m_freem(txd->tx_m); 3240 txd->tx_m = NULL; 3241 STAILQ_REMOVE_HEAD(&sc_if->sk_cdata.sk_txbusyq, tx_q); 3242 STAILQ_INSERT_TAIL(&sc_if->sk_cdata.sk_txfreeq, txd, tx_q); 3243 txd = STAILQ_FIRST(&sc_if->sk_cdata.sk_txbusyq); 3244 } 3245 sc_if->sk_cdata.sk_tx_cons = idx; 3246 ifp->if_timer = sc_if->sk_cdata.sk_tx_cnt > 0 ? 5 : 0; 3247 3248 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag, 3249 sc_if->sk_cdata.sk_tx_ring_map, 3250 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3251} 3252 3253static void 3254sk_tick(xsc_if) 3255 void *xsc_if; 3256{ 3257 struct sk_if_softc *sc_if; 3258 struct mii_data *mii; 3259 struct ifnet *ifp; 3260 int i; 3261 3262 sc_if = xsc_if; 3263 ifp = sc_if->sk_ifp; 3264 mii = device_get_softc(sc_if->sk_miibus); 3265 3266 if (!(ifp->if_flags & IFF_UP)) 3267 return; 3268 3269 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 3270 sk_intr_bcom(sc_if); 3271 return; 3272 } 3273 3274 /* 3275 * According to SysKonnect, the correct way to verify that 3276 * the link has come back up is to poll bit 0 of the GPIO 3277 * register three times. This pin has the signal from the 3278 * link_sync pin connected to it; if we read the same link 3279 * state 3 times in a row, we know the link is up. 3280 */ 3281 for (i = 0; i < 3; i++) { 3282 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET) 3283 break; 3284 } 3285 3286 if (i != 3) { 3287 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 3288 return; 3289 } 3290 3291 /* Turn the GP0 interrupt back on. */ 3292 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 3293 SK_XM_READ_2(sc_if, XM_ISR); 3294 mii_tick(mii); 3295 callout_stop(&sc_if->sk_tick_ch); 3296} 3297 3298static void 3299sk_yukon_tick(xsc_if) 3300 void *xsc_if; 3301{ 3302 struct sk_if_softc *sc_if; 3303 struct mii_data *mii; 3304 3305 sc_if = xsc_if; 3306 mii = device_get_softc(sc_if->sk_miibus); 3307 3308 mii_tick(mii); 3309 callout_reset(&sc_if->sk_tick_ch, hz, sk_yukon_tick, sc_if); 3310} 3311 3312static void 3313sk_intr_bcom(sc_if) 3314 struct sk_if_softc *sc_if; 3315{ 3316 struct mii_data *mii; 3317 struct ifnet *ifp; 3318 int status; 3319 mii = device_get_softc(sc_if->sk_miibus); 3320 ifp = sc_if->sk_ifp; 3321 3322 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 3323 3324 /* 3325 * Read the PHY interrupt register to make sure 3326 * we clear any pending interrupts. 3327 */ 3328 status = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, BRGPHY_MII_ISR); 3329 3330 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3331 sk_init_xmac(sc_if); 3332 return; 3333 } 3334 3335 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) { 3336 int lstat; 3337 lstat = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, 3338 BRGPHY_MII_AUXSTS); 3339 3340 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) { 3341 mii_mediachg(mii); 3342 /* Turn off the link LED. */ 3343 SK_IF_WRITE_1(sc_if, 0, 3344 SK_LINKLED1_CTL, SK_LINKLED_OFF); 3345 sc_if->sk_link = 0; 3346 } else if (status & BRGPHY_ISR_LNK_CHG) { 3347 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 3348 BRGPHY_MII_IMR, 0xFF00); 3349 mii_tick(mii); 3350 sc_if->sk_link = 1; 3351 /* Turn on the link LED. */ 3352 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 3353 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF| 3354 SK_LINKLED_BLINK_OFF); 3355 } else { 3356 mii_tick(mii); 3357 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 3358 } 3359 } 3360 3361 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 3362 3363 return; 3364} 3365 3366static void 3367sk_intr_xmac(sc_if) 3368 struct sk_if_softc *sc_if; 3369{ 3370 struct sk_softc *sc; 3371 u_int16_t status; 3372 3373 sc = sc_if->sk_softc; 3374 status = SK_XM_READ_2(sc_if, XM_ISR); 3375 3376 /* 3377 * Link has gone down. Start MII tick timeout to 3378 * watch for link resync. 3379 */ 3380 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) { 3381 if (status & XM_ISR_GP0_SET) { 3382 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 3383 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 3384 } 3385 3386 if (status & XM_ISR_AUTONEG_DONE) { 3387 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 3388 } 3389 } 3390 3391 if (status & XM_IMR_TX_UNDERRUN) 3392 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO); 3393 3394 if (status & XM_IMR_RX_OVERRUN) 3395 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO); 3396 3397 status = SK_XM_READ_2(sc_if, XM_ISR); 3398 3399 return; 3400} 3401 3402static void 3403sk_intr_yukon(sc_if) 3404 struct sk_if_softc *sc_if; 3405{ 3406 u_int8_t status; 3407 3408 status = SK_IF_READ_1(sc_if, 0, SK_GMAC_ISR); 3409 /* RX overrun */ 3410 if ((status & SK_GMAC_INT_RX_OVER) != 0) { 3411 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, 3412 SK_RFCTL_RX_FIFO_OVER); 3413 } 3414 /* TX underrun */ 3415 if ((status & SK_GMAC_INT_TX_UNDER) != 0) { 3416 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, 3417 SK_TFCTL_TX_FIFO_UNDER); 3418 } 3419} 3420 3421static void 3422sk_intr(xsc) 3423 void *xsc; 3424{ 3425 struct sk_softc *sc = xsc; 3426 struct sk_if_softc *sc_if0, *sc_if1; 3427 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 3428 u_int32_t status; 3429 3430 SK_LOCK(sc); 3431 3432 status = CSR_READ_4(sc, SK_ISSR); 3433 if (status == 0 || status == 0xffffffff || sc->sk_suspended) 3434 goto done_locked; 3435 3436 sc_if0 = sc->sk_if[SK_PORT_A]; 3437 sc_if1 = sc->sk_if[SK_PORT_B]; 3438 3439 if (sc_if0 != NULL) 3440 ifp0 = sc_if0->sk_ifp; 3441 if (sc_if1 != NULL) 3442 ifp1 = sc_if1->sk_ifp; 3443 3444 status &= sc->sk_intrmask; 3445 if ((status & sc->sk_intrmask) != 0) { 3446 /* Handle receive interrupts first. */ 3447 if (status & SK_ISR_RX1_EOF) { 3448 if (ifp0->if_mtu > SK_MAX_FRAMELEN) 3449 sk_jumbo_rxeof(sc_if0); 3450 else 3451 sk_rxeof(sc_if0); 3452 CSR_WRITE_4(sc, SK_BMU_RX_CSR0, 3453 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 3454 } 3455 if (status & SK_ISR_RX2_EOF) { 3456 if (ifp1->if_mtu > SK_MAX_FRAMELEN) 3457 sk_jumbo_rxeof(sc_if1); 3458 else 3459 sk_rxeof(sc_if1); 3460 CSR_WRITE_4(sc, SK_BMU_RX_CSR1, 3461 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 3462 } 3463 3464 /* Then transmit interrupts. */ 3465 if (status & SK_ISR_TX1_S_EOF) { 3466 sk_txeof(sc_if0); 3467 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, SK_TXBMU_CLR_IRQ_EOF); 3468 } 3469 if (status & SK_ISR_TX2_S_EOF) { 3470 sk_txeof(sc_if1); 3471 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, SK_TXBMU_CLR_IRQ_EOF); 3472 } 3473 3474 /* Then MAC interrupts. */ 3475 if (status & SK_ISR_MAC1 && 3476 ifp0->if_drv_flags & IFF_DRV_RUNNING) { 3477 if (sc->sk_type == SK_GENESIS) 3478 sk_intr_xmac(sc_if0); 3479 else 3480 sk_intr_yukon(sc_if0); 3481 } 3482 3483 if (status & SK_ISR_MAC2 && 3484 ifp1->if_drv_flags & IFF_DRV_RUNNING) { 3485 if (sc->sk_type == SK_GENESIS) 3486 sk_intr_xmac(sc_if1); 3487 else 3488 sk_intr_yukon(sc_if1); 3489 } 3490 3491 if (status & SK_ISR_EXTERNAL_REG) { 3492 if (ifp0 != NULL && 3493 sc_if0->sk_phytype == SK_PHYTYPE_BCOM) 3494 sk_intr_bcom(sc_if0); 3495 if (ifp1 != NULL && 3496 sc_if1->sk_phytype == SK_PHYTYPE_BCOM) 3497 sk_intr_bcom(sc_if1); 3498 } 3499 } 3500 3501 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 3502 3503 if (ifp0 != NULL && !IFQ_DRV_IS_EMPTY(&ifp0->if_snd)) 3504 sk_start_locked(ifp0); 3505 if (ifp1 != NULL && !IFQ_DRV_IS_EMPTY(&ifp1->if_snd)) 3506 sk_start_locked(ifp1); 3507 3508done_locked: 3509 SK_UNLOCK(sc); 3510} 3511 3512static void 3513sk_init_xmac(sc_if) 3514 struct sk_if_softc *sc_if; 3515{ 3516 struct sk_softc *sc; 3517 struct ifnet *ifp; 3518 u_int16_t eaddr[(ETHER_ADDR_LEN+1)/2]; 3519 struct sk_bcom_hack bhack[] = { 3520 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, 3521 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, 3522 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 3523 { 0, 0 } }; 3524 3525 SK_IF_LOCK_ASSERT(sc_if); 3526 3527 sc = sc_if->sk_softc; 3528 ifp = sc_if->sk_ifp; 3529 3530 /* Unreset the XMAC. */ 3531 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET); 3532 DELAY(1000); 3533 3534 /* Reset the XMAC's internal state. */ 3535 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 3536 3537 /* Save the XMAC II revision */ 3538 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID)); 3539 3540 /* 3541 * Perform additional initialization for external PHYs, 3542 * namely for the 1000baseTX cards that use the XMAC's 3543 * GMII mode. 3544 */ 3545 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 3546 int i = 0; 3547 u_int32_t val; 3548 3549 /* Take PHY out of reset. */ 3550 val = sk_win_read_4(sc, SK_GPIO); 3551 if (sc_if->sk_port == SK_PORT_A) 3552 val |= SK_GPIO_DIR0|SK_GPIO_DAT0; 3553 else 3554 val |= SK_GPIO_DIR2|SK_GPIO_DAT2; 3555 sk_win_write_4(sc, SK_GPIO, val); 3556 3557 /* Enable GMII mode on the XMAC. */ 3558 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE); 3559 3560 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 3561 BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET); 3562 DELAY(10000); 3563 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 3564 BRGPHY_MII_IMR, 0xFFF0); 3565 3566 /* 3567 * Early versions of the BCM5400 apparently have 3568 * a bug that requires them to have their reserved 3569 * registers initialized to some magic values. I don't 3570 * know what the numbers do, I'm just the messenger. 3571 */ 3572 if (sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, 0x03) 3573 == 0x6041) { 3574 while(bhack[i].reg) { 3575 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 3576 bhack[i].reg, bhack[i].val); 3577 i++; 3578 } 3579 } 3580 } 3581 3582 /* Set station address */ 3583 bcopy(IF_LLADDR(sc_if->sk_ifp), eaddr, ETHER_ADDR_LEN); 3584 SK_XM_WRITE_2(sc_if, XM_PAR0, eaddr[0]); 3585 SK_XM_WRITE_2(sc_if, XM_PAR1, eaddr[1]); 3586 SK_XM_WRITE_2(sc_if, XM_PAR2, eaddr[2]); 3587 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION); 3588 3589 if (ifp->if_flags & IFF_BROADCAST) { 3590 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 3591 } else { 3592 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 3593 } 3594 3595 /* We don't need the FCS appended to the packet. */ 3596 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS); 3597 3598 /* We want short frames padded to 60 bytes. */ 3599 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD); 3600 3601 /* 3602 * Enable the reception of all error frames. This is is 3603 * a necessary evil due to the design of the XMAC. The 3604 * XMAC's receive FIFO is only 8K in size, however jumbo 3605 * frames can be up to 9000 bytes in length. When bad 3606 * frame filtering is enabled, the XMAC's RX FIFO operates 3607 * in 'store and forward' mode. For this to work, the 3608 * entire frame has to fit into the FIFO, but that means 3609 * that jumbo frames larger than 8192 bytes will be 3610 * truncated. Disabling all bad frame filtering causes 3611 * the RX FIFO to operate in streaming mode, in which 3612 * case the XMAC will start transfering frames out of the 3613 * RX FIFO as soon as the FIFO threshold is reached. 3614 */ 3615 if (ifp->if_mtu > SK_MAX_FRAMELEN) { 3616 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES| 3617 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS| 3618 XM_MODE_RX_INRANGELEN); 3619 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 3620 } else 3621 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 3622 3623 /* 3624 * Bump up the transmit threshold. This helps hold off transmit 3625 * underruns when we're blasting traffic from both ports at once. 3626 */ 3627 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH); 3628 3629 /* Set promiscuous mode */ 3630 sk_setpromisc(sc_if); 3631 3632 /* Set multicast filter */ 3633 sk_setmulti(sc_if); 3634 3635 /* Clear and enable interrupts */ 3636 SK_XM_READ_2(sc_if, XM_ISR); 3637 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 3638 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS); 3639 else 3640 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 3641 3642 /* Configure MAC arbiter */ 3643 switch(sc_if->sk_xmac_rev) { 3644 case XM_XMAC_REV_B2: 3645 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2); 3646 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2); 3647 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2); 3648 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2); 3649 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2); 3650 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2); 3651 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2); 3652 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2); 3653 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 3654 break; 3655 case XM_XMAC_REV_C1: 3656 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1); 3657 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1); 3658 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1); 3659 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1); 3660 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1); 3661 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1); 3662 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1); 3663 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1); 3664 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 3665 break; 3666 default: 3667 break; 3668 } 3669 sk_win_write_2(sc, SK_MACARB_CTL, 3670 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF); 3671 3672 sc_if->sk_link = 1; 3673 3674 return; 3675} 3676 3677static void 3678sk_init_yukon(sc_if) 3679 struct sk_if_softc *sc_if; 3680{ 3681 u_int32_t phy, v; 3682 u_int16_t reg; 3683 struct sk_softc *sc; 3684 struct ifnet *ifp; 3685 int i; 3686 3687 SK_IF_LOCK_ASSERT(sc_if); 3688 3689 sc = sc_if->sk_softc; 3690 ifp = sc_if->sk_ifp; 3691 3692 if (sc->sk_type == SK_YUKON_LITE && 3693 sc->sk_rev >= SK_YUKON_LITE_REV_A3) { 3694 /* 3695 * Workaround code for COMA mode, set PHY reset. 3696 * Otherwise it will not correctly take chip out of 3697 * powerdown (coma) 3698 */ 3699 v = sk_win_read_4(sc, SK_GPIO); 3700 v |= SK_GPIO_DIR9 | SK_GPIO_DAT9; 3701 sk_win_write_4(sc, SK_GPIO, v); 3702 } 3703 3704 /* GMAC and GPHY Reset */ 3705 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 3706 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 3707 DELAY(1000); 3708 3709 if (sc->sk_type == SK_YUKON_LITE && 3710 sc->sk_rev >= SK_YUKON_LITE_REV_A3) { 3711 /* 3712 * Workaround code for COMA mode, clear PHY reset 3713 */ 3714 v = sk_win_read_4(sc, SK_GPIO); 3715 v |= SK_GPIO_DIR9; 3716 v &= ~SK_GPIO_DAT9; 3717 sk_win_write_4(sc, SK_GPIO, v); 3718 } 3719 3720 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP | 3721 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE; 3722 3723 switch(sc_if->sk_softc->sk_pmd) { 3724 case IFM_1000_SX: 3725 case IFM_1000_LX: 3726 phy |= SK_GPHY_FIBER; 3727 break; 3728 3729 case IFM_1000_CX: 3730 case IFM_1000_T: 3731 phy |= SK_GPHY_COPPER; 3732 break; 3733 } 3734 3735 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET); 3736 DELAY(1000); 3737 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR); 3738 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 3739 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 3740 3741 /* unused read of the interrupt source register */ 3742 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 3743 3744 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 3745 3746 /* MIB Counter Clear Mode set */ 3747 reg |= YU_PAR_MIB_CLR; 3748 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 3749 3750 /* MIB Counter Clear Mode clear */ 3751 reg &= ~YU_PAR_MIB_CLR; 3752 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 3753 3754 /* receive control reg */ 3755 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR); 3756 3757 /* transmit parameter register */ 3758 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 3759 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) ); 3760 3761 /* serial mode register */ 3762 reg = YU_SMR_DATA_BLIND(0x1c) | YU_SMR_MFL_VLAN | YU_SMR_IPG_DATA(0x1e); 3763 if (ifp->if_mtu > SK_MAX_FRAMELEN) 3764 reg |= YU_SMR_MFL_JUMBO; 3765 SK_YU_WRITE_2(sc_if, YUKON_SMR, reg); 3766 3767 /* Setup Yukon's address */ 3768 for (i = 0; i < 3; i++) { 3769 /* Write Source Address 1 (unicast filter) */ 3770 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 3771 IF_LLADDR(sc_if->sk_ifp)[i * 2] | 3772 IF_LLADDR(sc_if->sk_ifp)[i * 2 + 1] << 8); 3773 } 3774 3775 for (i = 0; i < 3; i++) { 3776 reg = sk_win_read_2(sc_if->sk_softc, 3777 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 3778 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 3779 } 3780 3781 /* Set promiscuous mode */ 3782 sk_setpromisc(sc_if); 3783 3784 /* Set multicast filter */ 3785 sk_setmulti(sc_if); 3786 3787 /* enable interrupt mask for counter overflows */ 3788 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 3789 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 3790 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 3791 3792 /* Configure RX MAC FIFO Flush Mask */ 3793 v = YU_RXSTAT_FOFL | YU_RXSTAT_CRCERR | YU_RXSTAT_MIIERR | 3794 YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | YU_RXSTAT_RUNT | 3795 YU_RXSTAT_JABBER; 3796 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_MASK, v); 3797 3798 /* Disable RX MAC FIFO Flush for YUKON-Lite Rev. A0 only */ 3799 if (sc->sk_type == SK_YUKON_LITE && sc->sk_rev == SK_YUKON_LITE_REV_A0) 3800 v = SK_TFCTL_OPERATION_ON; 3801 else 3802 v = SK_TFCTL_OPERATION_ON | SK_RFCTL_FIFO_FLUSH_ON; 3803 /* Configure RX MAC FIFO */ 3804 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 3805 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, v); 3806 3807 /* Increase flush threshould to 64 bytes */ 3808 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD, 3809 SK_RFCTL_FIFO_THRESHOLD + 1); 3810 3811 /* Configure TX MAC FIFO */ 3812 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 3813 SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 3814} 3815 3816/* 3817 * Note that to properly initialize any part of the GEnesis chip, 3818 * you first have to take it out of reset mode. 3819 */ 3820static void 3821sk_init(xsc) 3822 void *xsc; 3823{ 3824 struct sk_if_softc *sc_if = xsc; 3825 3826 SK_IF_LOCK(sc_if); 3827 sk_init_locked(sc_if); 3828 SK_IF_UNLOCK(sc_if); 3829 3830 return; 3831} 3832 3833static void 3834sk_init_locked(sc_if) 3835 struct sk_if_softc *sc_if; 3836{ 3837 struct sk_softc *sc; 3838 struct ifnet *ifp; 3839 struct mii_data *mii; 3840 u_int16_t reg; 3841 u_int32_t imr; 3842 int error; 3843 3844 SK_IF_LOCK_ASSERT(sc_if); 3845 3846 ifp = sc_if->sk_ifp; 3847 sc = sc_if->sk_softc; 3848 mii = device_get_softc(sc_if->sk_miibus); 3849 3850 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3851 return; 3852 3853 /* Cancel pending I/O and free all RX/TX buffers. */ 3854 sk_stop(sc_if); 3855 3856 if (sc->sk_type == SK_GENESIS) { 3857 /* Configure LINK_SYNC LED */ 3858 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON); 3859 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 3860 SK_LINKLED_LINKSYNC_ON); 3861 3862 /* Configure RX LED */ 3863 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, 3864 SK_RXLEDCTL_COUNTER_START); 3865 3866 /* Configure TX LED */ 3867 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, 3868 SK_TXLEDCTL_COUNTER_START); 3869 } 3870 3871 /* 3872 * Configure descriptor poll timer 3873 * 3874 * SK-NET GENESIS data sheet says that possibility of losing Start 3875 * transmit command due to CPU/cache related interim storage problems 3876 * under certain conditions. The document recommends a polling 3877 * mechanism to send a Start transmit command to initiate transfer 3878 * of ready descriptors regulary. To cope with this issue sk(4) now 3879 * enables descriptor poll timer to initiate descriptor processing 3880 * periodically as defined by SK_DPT_TIMER_MAX. However sk(4) still 3881 * issue SK_TXBMU_TX_START to Tx BMU to get fast execution of Tx 3882 * command instead of waiting for next descriptor polling time. 3883 * The same rule may apply to Rx side too but it seems that is not 3884 * needed at the moment. 3885 * Since sk(4) uses descriptor polling as a last resort there is no 3886 * need to set smaller polling time than maximum allowable one. 3887 */ 3888 SK_IF_WRITE_4(sc_if, 0, SK_DPT_INIT, SK_DPT_TIMER_MAX); 3889 3890 /* Configure I2C registers */ 3891 3892 /* Configure XMAC(s) */ 3893 switch (sc->sk_type) { 3894 case SK_GENESIS: 3895 sk_init_xmac(sc_if); 3896 break; 3897 case SK_YUKON: 3898 case SK_YUKON_LITE: 3899 case SK_YUKON_LP: 3900 case SK_YUKON_EC: 3901 sk_init_yukon(sc_if); 3902 break; 3903 } 3904 mii_mediachg(mii); 3905 3906 if (sc->sk_type == SK_GENESIS) { 3907 /* Configure MAC FIFOs */ 3908 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET); 3909 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END); 3910 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON); 3911 3912 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET); 3913 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END); 3914 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON); 3915 } 3916 3917 /* Configure transmit arbiter(s) */ 3918 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, 3919 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 3920 3921 /* Configure RAMbuffers */ 3922 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 3923 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 3924 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 3925 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 3926 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 3927 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 3928 3929 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET); 3930 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON); 3931 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart); 3932 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart); 3933 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart); 3934 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend); 3935 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON); 3936 3937 /* Configure BMUs */ 3938 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE); 3939 if (ifp->if_mtu > SK_MAX_FRAMELEN) { 3940 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 3941 SK_ADDR_LO(SK_JUMBO_RX_RING_ADDR(sc_if, 0))); 3942 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 3943 SK_ADDR_HI(SK_JUMBO_RX_RING_ADDR(sc_if, 0))); 3944 } else { 3945 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 3946 SK_ADDR_LO(SK_RX_RING_ADDR(sc_if, 0))); 3947 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 3948 SK_ADDR_HI(SK_RX_RING_ADDR(sc_if, 0))); 3949 } 3950 3951 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE); 3952 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO, 3953 SK_ADDR_LO(SK_TX_RING_ADDR(sc_if, 0))); 3954 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 3955 SK_ADDR_HI(SK_TX_RING_ADDR(sc_if, 0))); 3956 3957 /* Init descriptors */ 3958 if (ifp->if_mtu > SK_MAX_FRAMELEN) 3959 error = sk_init_jumbo_rx_ring(sc_if); 3960 else 3961 error = sk_init_rx_ring(sc_if); 3962 if (error != 0) { 3963 device_printf(sc_if->sk_if_dev, 3964 "initialization failed: no memory for rx buffers\n"); 3965 sk_stop(sc_if); 3966 return; 3967 } 3968 sk_init_tx_ring(sc_if); 3969 3970 /* Set interrupt moderation if changed via sysctl. */ 3971 imr = sk_win_read_4(sc, SK_IMTIMERINIT); 3972 if (imr != SK_IM_USECS(sc->sk_int_mod, sc->sk_int_ticks)) { 3973 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod, 3974 sc->sk_int_ticks)); 3975 if (bootverbose) 3976 device_printf(sc_if->sk_if_dev, 3977 "interrupt moderation is %d us.\n", 3978 sc->sk_int_mod); 3979 } 3980 3981 /* Configure interrupt handling */ 3982 CSR_READ_4(sc, SK_ISSR); 3983 if (sc_if->sk_port == SK_PORT_A) 3984 sc->sk_intrmask |= SK_INTRS1; 3985 else 3986 sc->sk_intrmask |= SK_INTRS2; 3987 3988 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG; 3989 3990 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 3991 3992 /* Start BMUs. */ 3993 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START); 3994 3995 switch(sc->sk_type) { 3996 case SK_GENESIS: 3997 /* Enable XMACs TX and RX state machines */ 3998 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE); 3999 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 4000 break; 4001 case SK_YUKON: 4002 case SK_YUKON_LITE: 4003 case SK_YUKON_LP: 4004 case SK_YUKON_EC: 4005 reg = SK_YU_READ_2(sc_if, YUKON_GPCR); 4006 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN; 4007#if 0 4008 /* XXX disable 100Mbps and full duplex mode? */ 4009 reg &= ~(YU_GPCR_SPEED | YU_GPCR_DPLX_DIS); 4010#endif 4011 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg); 4012 } 4013 4014 /* Activate descriptor polling timer */ 4015 SK_IF_WRITE_4(sc_if, 0, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_START); 4016 /* start transfer of Tx descriptors */ 4017 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 4018 4019 ifp->if_drv_flags |= IFF_DRV_RUNNING; 4020 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 4021 4022 switch (sc->sk_type) { 4023 case SK_YUKON: 4024 case SK_YUKON_LITE: 4025 case SK_YUKON_LP: 4026 case SK_YUKON_EC: 4027 callout_reset(&sc_if->sk_tick_ch, hz, sk_yukon_tick, sc_if); 4028 break; 4029 } 4030 4031 return; 4032} 4033 4034static void 4035sk_stop(sc_if) 4036 struct sk_if_softc *sc_if; 4037{ 4038 int i; 4039 struct sk_softc *sc; 4040 struct sk_txdesc *txd; 4041 struct sk_rxdesc *rxd; 4042 struct sk_rxdesc *jrxd; 4043 struct ifnet *ifp; 4044 u_int32_t val; 4045 4046 SK_IF_LOCK_ASSERT(sc_if); 4047 sc = sc_if->sk_softc; 4048 ifp = sc_if->sk_ifp; 4049 4050 callout_stop(&sc_if->sk_tick_ch); 4051 4052 /* stop Tx descriptor polling timer */ 4053 SK_IF_WRITE_4(sc_if, 0, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP); 4054 /* stop transfer of Tx descriptors */ 4055 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_STOP); 4056 for (i = 0; i < SK_TIMEOUT; i++) { 4057 val = CSR_READ_4(sc, sc_if->sk_tx_bmu); 4058 if ((val & SK_TXBMU_TX_STOP) == 0) 4059 break; 4060 DELAY(1); 4061 } 4062 if (i == SK_TIMEOUT) 4063 device_printf(sc_if->sk_if_dev, 4064 "can not stop transfer of Tx descriptor\n"); 4065 /* stop transfer of Rx descriptors */ 4066 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_STOP); 4067 for (i = 0; i < SK_TIMEOUT; i++) { 4068 val = SK_IF_READ_4(sc_if, 0, SK_RXQ1_BMU_CSR); 4069 if ((val & SK_RXBMU_RX_STOP) == 0) 4070 break; 4071 DELAY(1); 4072 } 4073 if (i == SK_TIMEOUT) 4074 device_printf(sc_if->sk_if_dev, 4075 "can not stop transfer of Rx descriptor\n"); 4076 4077 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 4078 /* Put PHY back into reset. */ 4079 val = sk_win_read_4(sc, SK_GPIO); 4080 if (sc_if->sk_port == SK_PORT_A) { 4081 val |= SK_GPIO_DIR0; 4082 val &= ~SK_GPIO_DAT0; 4083 } else { 4084 val |= SK_GPIO_DIR2; 4085 val &= ~SK_GPIO_DAT2; 4086 } 4087 sk_win_write_4(sc, SK_GPIO, val); 4088 } 4089 4090 /* Turn off various components of this interface. */ 4091 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 4092 switch (sc->sk_type) { 4093 case SK_GENESIS: 4094 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_RESET); 4095 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET); 4096 break; 4097 case SK_YUKON: 4098 case SK_YUKON_LITE: 4099 case SK_YUKON_LP: 4100 case SK_YUKON_EC: 4101 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 4102 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 4103 break; 4104 } 4105 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 4106 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 4107 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE); 4108 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 4109 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 4110 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 4111 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 4112 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 4113 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 4114 4115 /* Disable interrupts */ 4116 if (sc_if->sk_port == SK_PORT_A) 4117 sc->sk_intrmask &= ~SK_INTRS1; 4118 else 4119 sc->sk_intrmask &= ~SK_INTRS2; 4120 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 4121 4122 SK_XM_READ_2(sc_if, XM_ISR); 4123 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 4124 4125 /* Free RX and TX mbufs still in the queues. */ 4126 for (i = 0; i < SK_RX_RING_CNT; i++) { 4127 rxd = &sc_if->sk_cdata.sk_rxdesc[i]; 4128 if (rxd->rx_m != NULL) { 4129 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_tag, 4130 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 4131 bus_dmamap_unload(sc_if->sk_cdata.sk_rx_tag, 4132 rxd->rx_dmamap); 4133 m_freem(rxd->rx_m); 4134 rxd->rx_m = NULL; 4135 } 4136 } 4137 for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) { 4138 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[i]; 4139 if (jrxd->rx_m != NULL) { 4140 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_tag, 4141 jrxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 4142 bus_dmamap_unload(sc_if->sk_cdata.sk_jumbo_rx_tag, 4143 jrxd->rx_dmamap); 4144 m_freem(jrxd->rx_m); 4145 jrxd->rx_m = NULL; 4146 } 4147 } 4148 for (i = 0; i < SK_TX_RING_CNT; i++) { 4149 txd = &sc_if->sk_cdata.sk_txdesc[i]; 4150 if (txd->tx_m != NULL) { 4151 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_tag, 4152 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 4153 bus_dmamap_unload(sc_if->sk_cdata.sk_tx_tag, 4154 txd->tx_dmamap); 4155 m_freem(txd->tx_m); 4156 txd->tx_m = NULL; 4157 } 4158 } 4159 4160 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING|IFF_DRV_OACTIVE); 4161 4162 return; 4163} 4164 4165static int 4166sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 4167{ 4168 int error, value; 4169 4170 if (!arg1) 4171 return (EINVAL); 4172 value = *(int *)arg1; 4173 error = sysctl_handle_int(oidp, &value, 0, req); 4174 if (error || !req->newptr) 4175 return (error); 4176 if (value < low || value > high) 4177 return (EINVAL); 4178 *(int *)arg1 = value; 4179 return (0); 4180} 4181 4182static int 4183sysctl_hw_sk_int_mod(SYSCTL_HANDLER_ARGS) 4184{ 4185 return (sysctl_int_range(oidp, arg1, arg2, req, SK_IM_MIN, SK_IM_MAX)); 4186} 4187