if_sk.c revision 142398
1/* $OpenBSD: if_sk.c,v 2.33 2003/08/12 05:23:06 nate Exp $ */ 2 3/*- 4 * Copyright (c) 1997, 1998, 1999, 2000 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34/*- 35 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 36 * 37 * Permission to use, copy, modify, and distribute this software for any 38 * purpose with or without fee is hereby granted, provided that the above 39 * copyright notice and this permission notice appear in all copies. 40 * 41 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 42 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 43 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 44 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 45 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 46 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 47 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 48 */ 49 50#include <sys/cdefs.h> 51__FBSDID("$FreeBSD: head/sys/dev/sk/if_sk.c 142398 2005-02-24 21:32:56Z imp $"); 52 53/* 54 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 55 * the SK-984x series adapters, both single port and dual port. 56 * References: 57 * The XaQti XMAC II datasheet, 58 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 59 * The SysKonnect GEnesis manual, http://www.syskonnect.com 60 * 61 * Note: XaQti has been aquired by Vitesse, and Vitesse does not have the 62 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 63 * convenience to others until Vitesse corrects this problem: 64 * 65 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 66 * 67 * Written by Bill Paul <wpaul@ee.columbia.edu> 68 * Department of Electrical Engineering 69 * Columbia University, New York City 70 */ 71/* 72 * The SysKonnect gigabit ethernet adapters consist of two main 73 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 74 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 75 * components and a PHY while the GEnesis controller provides a PCI 76 * interface with DMA support. Each card may have between 512K and 77 * 2MB of SRAM on board depending on the configuration. 78 * 79 * The SysKonnect GEnesis controller can have either one or two XMAC 80 * chips connected to it, allowing single or dual port NIC configurations. 81 * SysKonnect has the distinction of being the only vendor on the market 82 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 83 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 84 * XMAC registers. This driver takes advantage of these features to allow 85 * both XMACs to operate as independent interfaces. 86 */ 87 88#include <sys/param.h> 89#include <sys/systm.h> 90#include <sys/sockio.h> 91#include <sys/mbuf.h> 92#include <sys/malloc.h> 93#include <sys/kernel.h> 94#include <sys/module.h> 95#include <sys/socket.h> 96#include <sys/queue.h> 97 98#include <net/if.h> 99#include <net/if_arp.h> 100#include <net/ethernet.h> 101#include <net/if_dl.h> 102#include <net/if_media.h> 103 104#include <net/bpf.h> 105 106#include <vm/vm.h> /* for vtophys */ 107#include <vm/pmap.h> /* for vtophys */ 108#include <machine/bus_pio.h> 109#include <machine/bus_memio.h> 110#include <machine/bus.h> 111#include <machine/resource.h> 112#include <sys/bus.h> 113#include <sys/rman.h> 114 115#include <dev/mii/mii.h> 116#include <dev/mii/miivar.h> 117#include <dev/mii/brgphyreg.h> 118 119#include <dev/pci/pcireg.h> 120#include <dev/pci/pcivar.h> 121 122#if 0 123#define SK_USEIOSPACE 124#endif 125 126#include <pci/if_skreg.h> 127#include <pci/xmaciireg.h> 128#include <pci/yukonreg.h> 129 130MODULE_DEPEND(sk, pci, 1, 1, 1); 131MODULE_DEPEND(sk, ether, 1, 1, 1); 132MODULE_DEPEND(sk, miibus, 1, 1, 1); 133 134/* "controller miibus0" required. See GENERIC if you get errors here. */ 135#include "miibus_if.h" 136 137#ifndef lint 138static const char rcsid[] = 139 "$FreeBSD: head/sys/dev/sk/if_sk.c 142398 2005-02-24 21:32:56Z imp $"; 140#endif 141 142static struct sk_type sk_devs[] = { 143 { 144 VENDORID_SK, 145 DEVICEID_SK_V1, 146 "SysKonnect Gigabit Ethernet (V1.0)" 147 }, 148 { 149 VENDORID_SK, 150 DEVICEID_SK_V2, 151 "SysKonnect Gigabit Ethernet (V2.0)" 152 }, 153 { 154 VENDORID_MARVELL, 155 DEVICEID_SK_V2, 156 "Marvell Gigabit Ethernet" 157 }, 158 { 159 VENDORID_MARVELL, 160 DEVICEID_BELKIN_5005, 161 "Belkin F5D5005 Gigabit Ethernet" 162 }, 163 { 164 VENDORID_3COM, 165 DEVICEID_3COM_3C940, 166 "3Com 3C940 Gigabit Ethernet" 167 }, 168 { 169 VENDORID_LINKSYS, 170 DEVICEID_LINKSYS_EG1032, 171 "Linksys EG1032 Gigabit Ethernet" 172 }, 173 { 174 VENDORID_DLINK, 175 DEVICEID_DLINK_DGE530T, 176 "D-Link DGE-530T Gigabit Ethernet" 177 }, 178 { 0, 0, NULL } 179}; 180 181static int skc_probe (device_t); 182static int skc_attach (device_t); 183static int skc_detach (device_t); 184static void skc_shutdown (device_t); 185static int sk_detach (device_t); 186static int sk_probe (device_t); 187static int sk_attach (device_t); 188static void sk_tick (void *); 189static void sk_intr (void *); 190static void sk_intr_xmac (struct sk_if_softc *); 191static void sk_intr_bcom (struct sk_if_softc *); 192static void sk_intr_yukon (struct sk_if_softc *); 193static void sk_rxeof (struct sk_if_softc *); 194static void sk_txeof (struct sk_if_softc *); 195static int sk_encap (struct sk_if_softc *, struct mbuf *, 196 u_int32_t *); 197static void sk_start (struct ifnet *); 198static int sk_ioctl (struct ifnet *, u_long, caddr_t); 199static void sk_init (void *); 200static void sk_init_xmac (struct sk_if_softc *); 201static void sk_init_yukon (struct sk_if_softc *); 202static void sk_stop (struct sk_if_softc *); 203static void sk_watchdog (struct ifnet *); 204static int sk_ifmedia_upd (struct ifnet *); 205static void sk_ifmedia_sts (struct ifnet *, struct ifmediareq *); 206static void sk_reset (struct sk_softc *); 207static int sk_newbuf (struct sk_if_softc *, 208 struct sk_chain *, struct mbuf *); 209static int sk_alloc_jumbo_mem (struct sk_if_softc *); 210static void *sk_jalloc (struct sk_if_softc *); 211static void sk_jfree (void *, void *); 212static int sk_init_rx_ring (struct sk_if_softc *); 213static void sk_init_tx_ring (struct sk_if_softc *); 214static u_int32_t sk_win_read_4 (struct sk_softc *, int); 215static u_int16_t sk_win_read_2 (struct sk_softc *, int); 216static u_int8_t sk_win_read_1 (struct sk_softc *, int); 217static void sk_win_write_4 (struct sk_softc *, int, u_int32_t); 218static void sk_win_write_2 (struct sk_softc *, int, u_int32_t); 219static void sk_win_write_1 (struct sk_softc *, int, u_int32_t); 220static u_int8_t sk_vpd_readbyte (struct sk_softc *, int); 221static void sk_vpd_read_res (struct sk_softc *, struct vpd_res *, int); 222static void sk_vpd_read (struct sk_softc *); 223 224static int sk_miibus_readreg (device_t, int, int); 225static int sk_miibus_writereg (device_t, int, int, int); 226static void sk_miibus_statchg (device_t); 227 228static int sk_xmac_miibus_readreg (struct sk_if_softc *, int, int); 229static int sk_xmac_miibus_writereg (struct sk_if_softc *, int, int, 230 int); 231static void sk_xmac_miibus_statchg (struct sk_if_softc *); 232 233static int sk_marv_miibus_readreg (struct sk_if_softc *, int, int); 234static int sk_marv_miibus_writereg (struct sk_if_softc *, int, int, 235 int); 236static void sk_marv_miibus_statchg (struct sk_if_softc *); 237 238static uint32_t sk_xmchash (const uint8_t *); 239static uint32_t sk_gmchash (const uint8_t *); 240static void sk_setfilt (struct sk_if_softc *, caddr_t, int); 241static void sk_setmulti (struct sk_if_softc *); 242static void sk_setpromisc (struct sk_if_softc *); 243 244#ifdef SK_USEIOSPACE 245#define SK_RES SYS_RES_IOPORT 246#define SK_RID SK_PCI_LOIO 247#else 248#define SK_RES SYS_RES_MEMORY 249#define SK_RID SK_PCI_LOMEM 250#endif 251 252/* 253 * Note that we have newbus methods for both the GEnesis controller 254 * itself and the XMAC(s). The XMACs are children of the GEnesis, and 255 * the miibus code is a child of the XMACs. We need to do it this way 256 * so that the miibus drivers can access the PHY registers on the 257 * right PHY. It's not quite what I had in mind, but it's the only 258 * design that achieves the desired effect. 259 */ 260static device_method_t skc_methods[] = { 261 /* Device interface */ 262 DEVMETHOD(device_probe, skc_probe), 263 DEVMETHOD(device_attach, skc_attach), 264 DEVMETHOD(device_detach, skc_detach), 265 DEVMETHOD(device_shutdown, skc_shutdown), 266 267 /* bus interface */ 268 DEVMETHOD(bus_print_child, bus_generic_print_child), 269 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 270 271 { 0, 0 } 272}; 273 274static driver_t skc_driver = { 275 "skc", 276 skc_methods, 277 sizeof(struct sk_softc) 278}; 279 280static devclass_t skc_devclass; 281 282static device_method_t sk_methods[] = { 283 /* Device interface */ 284 DEVMETHOD(device_probe, sk_probe), 285 DEVMETHOD(device_attach, sk_attach), 286 DEVMETHOD(device_detach, sk_detach), 287 DEVMETHOD(device_shutdown, bus_generic_shutdown), 288 289 /* bus interface */ 290 DEVMETHOD(bus_print_child, bus_generic_print_child), 291 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 292 293 /* MII interface */ 294 DEVMETHOD(miibus_readreg, sk_miibus_readreg), 295 DEVMETHOD(miibus_writereg, sk_miibus_writereg), 296 DEVMETHOD(miibus_statchg, sk_miibus_statchg), 297 298 { 0, 0 } 299}; 300 301static driver_t sk_driver = { 302 "sk", 303 sk_methods, 304 sizeof(struct sk_if_softc) 305}; 306 307static devclass_t sk_devclass; 308 309DRIVER_MODULE(sk, pci, skc_driver, skc_devclass, 0, 0); 310DRIVER_MODULE(sk, skc, sk_driver, sk_devclass, 0, 0); 311DRIVER_MODULE(miibus, sk, miibus_driver, miibus_devclass, 0, 0); 312 313#define SK_SETBIT(sc, reg, x) \ 314 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 315 316#define SK_CLRBIT(sc, reg, x) \ 317 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 318 319#define SK_WIN_SETBIT_4(sc, reg, x) \ 320 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) | x) 321 322#define SK_WIN_CLRBIT_4(sc, reg, x) \ 323 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) & ~x) 324 325#define SK_WIN_SETBIT_2(sc, reg, x) \ 326 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) | x) 327 328#define SK_WIN_CLRBIT_2(sc, reg, x) \ 329 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) & ~x) 330 331static u_int32_t 332sk_win_read_4(sc, reg) 333 struct sk_softc *sc; 334 int reg; 335{ 336#ifdef SK_USEIOSPACE 337 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 338 return(CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg))); 339#else 340 return(CSR_READ_4(sc, reg)); 341#endif 342} 343 344static u_int16_t 345sk_win_read_2(sc, reg) 346 struct sk_softc *sc; 347 int reg; 348{ 349#ifdef SK_USEIOSPACE 350 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 351 return(CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg))); 352#else 353 return(CSR_READ_2(sc, reg)); 354#endif 355} 356 357static u_int8_t 358sk_win_read_1(sc, reg) 359 struct sk_softc *sc; 360 int reg; 361{ 362#ifdef SK_USEIOSPACE 363 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 364 return(CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg))); 365#else 366 return(CSR_READ_1(sc, reg)); 367#endif 368} 369 370static void 371sk_win_write_4(sc, reg, val) 372 struct sk_softc *sc; 373 int reg; 374 u_int32_t val; 375{ 376#ifdef SK_USEIOSPACE 377 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 378 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), val); 379#else 380 CSR_WRITE_4(sc, reg, val); 381#endif 382 return; 383} 384 385static void 386sk_win_write_2(sc, reg, val) 387 struct sk_softc *sc; 388 int reg; 389 u_int32_t val; 390{ 391#ifdef SK_USEIOSPACE 392 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 393 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), val); 394#else 395 CSR_WRITE_2(sc, reg, val); 396#endif 397 return; 398} 399 400static void 401sk_win_write_1(sc, reg, val) 402 struct sk_softc *sc; 403 int reg; 404 u_int32_t val; 405{ 406#ifdef SK_USEIOSPACE 407 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 408 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), val); 409#else 410 CSR_WRITE_1(sc, reg, val); 411#endif 412 return; 413} 414 415/* 416 * The VPD EEPROM contains Vital Product Data, as suggested in 417 * the PCI 2.1 specification. The VPD data is separared into areas 418 * denoted by resource IDs. The SysKonnect VPD contains an ID string 419 * resource (the name of the adapter), a read-only area resource 420 * containing various key/data fields and a read/write area which 421 * can be used to store asset management information or log messages. 422 * We read the ID string and read-only into buffers attached to 423 * the controller softc structure for later use. At the moment, 424 * we only use the ID string during skc_attach(). 425 */ 426static u_int8_t 427sk_vpd_readbyte(sc, addr) 428 struct sk_softc *sc; 429 int addr; 430{ 431 int i; 432 433 sk_win_write_2(sc, SK_PCI_REG(SK_PCI_VPD_ADDR), addr); 434 for (i = 0; i < SK_TIMEOUT; i++) { 435 DELAY(1); 436 if (sk_win_read_2(sc, 437 SK_PCI_REG(SK_PCI_VPD_ADDR)) & SK_VPD_FLAG) 438 break; 439 } 440 441 if (i == SK_TIMEOUT) 442 return(0); 443 444 return(sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_DATA))); 445} 446 447static void 448sk_vpd_read_res(sc, res, addr) 449 struct sk_softc *sc; 450 struct vpd_res *res; 451 int addr; 452{ 453 int i; 454 u_int8_t *ptr; 455 456 ptr = (u_int8_t *)res; 457 for (i = 0; i < sizeof(struct vpd_res); i++) 458 ptr[i] = sk_vpd_readbyte(sc, i + addr); 459 460 return; 461} 462 463static void 464sk_vpd_read(sc) 465 struct sk_softc *sc; 466{ 467 int pos = 0, i; 468 struct vpd_res res; 469 470 if (sc->sk_vpd_prodname != NULL) 471 free(sc->sk_vpd_prodname, M_DEVBUF); 472 if (sc->sk_vpd_readonly != NULL) 473 free(sc->sk_vpd_readonly, M_DEVBUF); 474 sc->sk_vpd_prodname = NULL; 475 sc->sk_vpd_readonly = NULL; 476 sc->sk_vpd_readonly_len = 0; 477 478 sk_vpd_read_res(sc, &res, pos); 479 480 /* 481 * Bail out quietly if the eeprom appears to be missing or empty. 482 */ 483 if (res.vr_id == 0xff && res.vr_len == 0xff && res.vr_pad == 0xff) 484 return; 485 486 if (res.vr_id != VPD_RES_ID) { 487 printf("skc%d: bad VPD resource id: expected %x got %x\n", 488 sc->sk_unit, VPD_RES_ID, res.vr_id); 489 return; 490 } 491 492 pos += sizeof(res); 493 sc->sk_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 494 for (i = 0; i < res.vr_len; i++) 495 sc->sk_vpd_prodname[i] = sk_vpd_readbyte(sc, i + pos); 496 sc->sk_vpd_prodname[i] = '\0'; 497 pos += i; 498 499 sk_vpd_read_res(sc, &res, pos); 500 501 if (res.vr_id != VPD_RES_READ) { 502 printf("skc%d: bad VPD resource id: expected %x got %x\n", 503 sc->sk_unit, VPD_RES_READ, res.vr_id); 504 return; 505 } 506 507 pos += sizeof(res); 508 sc->sk_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 509 for (i = 0; i < res.vr_len; i++) 510 sc->sk_vpd_readonly[i] = sk_vpd_readbyte(sc, i + pos); 511 sc->sk_vpd_readonly_len = res.vr_len; 512 513 return; 514} 515 516static int 517sk_miibus_readreg(dev, phy, reg) 518 device_t dev; 519 int phy, reg; 520{ 521 struct sk_if_softc *sc_if; 522 523 sc_if = device_get_softc(dev); 524 525 switch(sc_if->sk_softc->sk_type) { 526 case SK_GENESIS: 527 return(sk_xmac_miibus_readreg(sc_if, phy, reg)); 528 case SK_YUKON: 529 return(sk_marv_miibus_readreg(sc_if, phy, reg)); 530 } 531 532 return(0); 533} 534 535static int 536sk_miibus_writereg(dev, phy, reg, val) 537 device_t dev; 538 int phy, reg, val; 539{ 540 struct sk_if_softc *sc_if; 541 542 sc_if = device_get_softc(dev); 543 544 switch(sc_if->sk_softc->sk_type) { 545 case SK_GENESIS: 546 return(sk_xmac_miibus_writereg(sc_if, phy, reg, val)); 547 case SK_YUKON: 548 return(sk_marv_miibus_writereg(sc_if, phy, reg, val)); 549 } 550 551 return(0); 552} 553 554static void 555sk_miibus_statchg(dev) 556 device_t dev; 557{ 558 struct sk_if_softc *sc_if; 559 560 sc_if = device_get_softc(dev); 561 562 switch(sc_if->sk_softc->sk_type) { 563 case SK_GENESIS: 564 sk_xmac_miibus_statchg(sc_if); 565 break; 566 case SK_YUKON: 567 sk_marv_miibus_statchg(sc_if); 568 break; 569 } 570 571 return; 572} 573 574static int 575sk_xmac_miibus_readreg(sc_if, phy, reg) 576 struct sk_if_softc *sc_if; 577 int phy, reg; 578{ 579 int i; 580 581 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0) 582 return(0); 583 584 SK_IF_LOCK(sc_if); 585 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 586 SK_XM_READ_2(sc_if, XM_PHY_DATA); 587 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 588 for (i = 0; i < SK_TIMEOUT; i++) { 589 DELAY(1); 590 if (SK_XM_READ_2(sc_if, XM_MMUCMD) & 591 XM_MMUCMD_PHYDATARDY) 592 break; 593 } 594 595 if (i == SK_TIMEOUT) { 596 printf("sk%d: phy failed to come ready\n", 597 sc_if->sk_unit); 598 SK_IF_UNLOCK(sc_if); 599 return(0); 600 } 601 } 602 DELAY(1); 603 i = SK_XM_READ_2(sc_if, XM_PHY_DATA); 604 SK_IF_UNLOCK(sc_if); 605 return(i); 606} 607 608static int 609sk_xmac_miibus_writereg(sc_if, phy, reg, val) 610 struct sk_if_softc *sc_if; 611 int phy, reg, val; 612{ 613 int i; 614 615 SK_IF_LOCK(sc_if); 616 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 617 for (i = 0; i < SK_TIMEOUT; i++) { 618 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 619 break; 620 } 621 622 if (i == SK_TIMEOUT) { 623 printf("sk%d: phy failed to come ready\n", sc_if->sk_unit); 624 SK_IF_UNLOCK(sc_if); 625 return(ETIMEDOUT); 626 } 627 628 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val); 629 for (i = 0; i < SK_TIMEOUT; i++) { 630 DELAY(1); 631 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 632 break; 633 } 634 SK_IF_UNLOCK(sc_if); 635 if (i == SK_TIMEOUT) 636 printf("sk%d: phy write timed out\n", sc_if->sk_unit); 637 638 return(0); 639} 640 641static void 642sk_xmac_miibus_statchg(sc_if) 643 struct sk_if_softc *sc_if; 644{ 645 struct mii_data *mii; 646 647 mii = device_get_softc(sc_if->sk_miibus); 648 649 SK_IF_LOCK(sc_if); 650 /* 651 * If this is a GMII PHY, manually set the XMAC's 652 * duplex mode accordingly. 653 */ 654 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 655 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 656 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 657 } else { 658 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 659 } 660 } 661 SK_IF_UNLOCK(sc_if); 662 663 return; 664} 665 666static int 667sk_marv_miibus_readreg(sc_if, phy, reg) 668 struct sk_if_softc *sc_if; 669 int phy, reg; 670{ 671 u_int16_t val; 672 int i; 673 674 if (phy != 0 || 675 (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER && 676 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) { 677 return(0); 678 } 679 680 SK_IF_LOCK(sc_if); 681 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 682 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 683 684 for (i = 0; i < SK_TIMEOUT; i++) { 685 DELAY(1); 686 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 687 if (val & YU_SMICR_READ_VALID) 688 break; 689 } 690 691 if (i == SK_TIMEOUT) { 692 printf("sk%d: phy failed to come ready\n", 693 sc_if->sk_unit); 694 SK_IF_UNLOCK(sc_if); 695 return(0); 696 } 697 698 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 699 SK_IF_UNLOCK(sc_if); 700 701 return(val); 702} 703 704static int 705sk_marv_miibus_writereg(sc_if, phy, reg, val) 706 struct sk_if_softc *sc_if; 707 int phy, reg, val; 708{ 709 int i; 710 711 SK_IF_LOCK(sc_if); 712 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 713 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 714 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 715 716 for (i = 0; i < SK_TIMEOUT; i++) { 717 DELAY(1); 718 if (SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY) 719 break; 720 } 721 SK_IF_UNLOCK(sc_if); 722 723 return(0); 724} 725 726static void 727sk_marv_miibus_statchg(sc_if) 728 struct sk_if_softc *sc_if; 729{ 730 return; 731} 732 733#define HASH_BITS 6 734 735static u_int32_t 736sk_xmchash(addr) 737 const uint8_t *addr; 738{ 739 uint32_t crc; 740 741 /* Compute CRC for the address value. */ 742 crc = ether_crc32_le(addr, ETHER_ADDR_LEN); 743 744 return (~crc & ((1 << HASH_BITS) - 1)); 745} 746 747/* gmchash is just a big endian crc */ 748static u_int32_t 749sk_gmchash(addr) 750 const uint8_t *addr; 751{ 752 uint32_t crc; 753 754 /* Compute CRC for the address value. */ 755 crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 756 757 return (crc & ((1 << HASH_BITS) - 1)); 758} 759 760static void 761sk_setfilt(sc_if, addr, slot) 762 struct sk_if_softc *sc_if; 763 caddr_t addr; 764 int slot; 765{ 766 int base; 767 768 base = XM_RXFILT_ENTRY(slot); 769 770 SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0])); 771 SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2])); 772 SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4])); 773 774 return; 775} 776 777static void 778sk_setmulti(sc_if) 779 struct sk_if_softc *sc_if; 780{ 781 struct sk_softc *sc = sc_if->sk_softc; 782 struct ifnet *ifp = &sc_if->arpcom.ac_if; 783 u_int32_t hashes[2] = { 0, 0 }; 784 int h = 0, i; 785 struct ifmultiaddr *ifma; 786 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 787 788 789 /* First, zot all the existing filters. */ 790 switch(sc->sk_type) { 791 case SK_GENESIS: 792 for (i = 1; i < XM_RXFILT_MAX; i++) 793 sk_setfilt(sc_if, (caddr_t)&dummy, i); 794 795 SK_XM_WRITE_4(sc_if, XM_MAR0, 0); 796 SK_XM_WRITE_4(sc_if, XM_MAR2, 0); 797 break; 798 case SK_YUKON: 799 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 800 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 801 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 802 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 803 break; 804 } 805 806 /* Now program new ones. */ 807 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 808 hashes[0] = 0xFFFFFFFF; 809 hashes[1] = 0xFFFFFFFF; 810 } else { 811 i = 1; 812 TAILQ_FOREACH_REVERSE(ifma, &ifp->if_multiaddrs, ifmultihead, ifma_link) { 813 if (ifma->ifma_addr->sa_family != AF_LINK) 814 continue; 815 /* 816 * Program the first XM_RXFILT_MAX multicast groups 817 * into the perfect filter. For all others, 818 * use the hash table. 819 */ 820 if (sc->sk_type == SK_GENESIS && i < XM_RXFILT_MAX) { 821 sk_setfilt(sc_if, 822 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i); 823 i++; 824 continue; 825 } 826 827 switch(sc->sk_type) { 828 case SK_GENESIS: 829 h = sk_xmchash( 830 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 831 break; 832 case SK_YUKON: 833 h = sk_gmchash( 834 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 835 break; 836 } 837 if (h < 32) 838 hashes[0] |= (1 << h); 839 else 840 hashes[1] |= (1 << (h - 32)); 841 } 842 } 843 844 switch(sc->sk_type) { 845 case SK_GENESIS: 846 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH| 847 XM_MODE_RX_USE_PERFECT); 848 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]); 849 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]); 850 break; 851 case SK_YUKON: 852 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 853 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 854 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 855 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 856 break; 857 } 858 859 return; 860} 861 862static void 863sk_setpromisc(sc_if) 864 struct sk_if_softc *sc_if; 865{ 866 struct sk_softc *sc = sc_if->sk_softc; 867 struct ifnet *ifp = &sc_if->arpcom.ac_if; 868 869 switch(sc->sk_type) { 870 case SK_GENESIS: 871 if (ifp->if_flags & IFF_PROMISC) { 872 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 873 } else { 874 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 875 } 876 break; 877 case SK_YUKON: 878 if (ifp->if_flags & IFF_PROMISC) { 879 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 880 YU_RCR_UFLEN | YU_RCR_MUFLEN); 881 } else { 882 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 883 YU_RCR_UFLEN | YU_RCR_MUFLEN); 884 } 885 break; 886 } 887 888 return; 889} 890 891static int 892sk_init_rx_ring(sc_if) 893 struct sk_if_softc *sc_if; 894{ 895 struct sk_chain_data *cd = &sc_if->sk_cdata; 896 struct sk_ring_data *rd = sc_if->sk_rdata; 897 int i; 898 899 bzero((char *)rd->sk_rx_ring, 900 sizeof(struct sk_rx_desc) * SK_RX_RING_CNT); 901 902 for (i = 0; i < SK_RX_RING_CNT; i++) { 903 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i]; 904 if (sk_newbuf(sc_if, &cd->sk_rx_chain[i], NULL) == ENOBUFS) 905 return(ENOBUFS); 906 if (i == (SK_RX_RING_CNT - 1)) { 907 cd->sk_rx_chain[i].sk_next = 908 &cd->sk_rx_chain[0]; 909 rd->sk_rx_ring[i].sk_next = 910 vtophys(&rd->sk_rx_ring[0]); 911 } else { 912 cd->sk_rx_chain[i].sk_next = 913 &cd->sk_rx_chain[i + 1]; 914 rd->sk_rx_ring[i].sk_next = 915 vtophys(&rd->sk_rx_ring[i + 1]); 916 } 917 } 918 919 sc_if->sk_cdata.sk_rx_prod = 0; 920 sc_if->sk_cdata.sk_rx_cons = 0; 921 922 return(0); 923} 924 925static void 926sk_init_tx_ring(sc_if) 927 struct sk_if_softc *sc_if; 928{ 929 struct sk_chain_data *cd = &sc_if->sk_cdata; 930 struct sk_ring_data *rd = sc_if->sk_rdata; 931 int i; 932 933 bzero((char *)sc_if->sk_rdata->sk_tx_ring, 934 sizeof(struct sk_tx_desc) * SK_TX_RING_CNT); 935 936 for (i = 0; i < SK_TX_RING_CNT; i++) { 937 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i]; 938 if (i == (SK_TX_RING_CNT - 1)) { 939 cd->sk_tx_chain[i].sk_next = 940 &cd->sk_tx_chain[0]; 941 rd->sk_tx_ring[i].sk_next = 942 vtophys(&rd->sk_tx_ring[0]); 943 } else { 944 cd->sk_tx_chain[i].sk_next = 945 &cd->sk_tx_chain[i + 1]; 946 rd->sk_tx_ring[i].sk_next = 947 vtophys(&rd->sk_tx_ring[i + 1]); 948 } 949 } 950 951 sc_if->sk_cdata.sk_tx_prod = 0; 952 sc_if->sk_cdata.sk_tx_cons = 0; 953 sc_if->sk_cdata.sk_tx_cnt = 0; 954 955 return; 956} 957 958static int 959sk_newbuf(sc_if, c, m) 960 struct sk_if_softc *sc_if; 961 struct sk_chain *c; 962 struct mbuf *m; 963{ 964 struct mbuf *m_new = NULL; 965 struct sk_rx_desc *r; 966 967 if (m == NULL) { 968 caddr_t *buf = NULL; 969 970 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 971 if (m_new == NULL) 972 return(ENOBUFS); 973 974 /* Allocate the jumbo buffer */ 975 buf = sk_jalloc(sc_if); 976 if (buf == NULL) { 977 m_freem(m_new); 978#ifdef SK_VERBOSE 979 printf("sk%d: jumbo allocation failed " 980 "-- packet dropped!\n", sc_if->sk_unit); 981#endif 982 return(ENOBUFS); 983 } 984 985 /* Attach the buffer to the mbuf */ 986 MEXTADD(m_new, buf, SK_JLEN, sk_jfree, 987 (struct sk_if_softc *)sc_if, 0, EXT_NET_DRV); 988 m_new->m_data = (void *)buf; 989 m_new->m_pkthdr.len = m_new->m_len = SK_JLEN; 990 } else { 991 /* 992 * We're re-using a previously allocated mbuf; 993 * be sure to re-init pointers and lengths to 994 * default values. 995 */ 996 m_new = m; 997 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 998 m_new->m_data = m_new->m_ext.ext_buf; 999 } 1000 1001 /* 1002 * Adjust alignment so packet payload begins on a 1003 * longword boundary. Mandatory for Alpha, useful on 1004 * x86 too. 1005 */ 1006 m_adj(m_new, ETHER_ALIGN); 1007 1008 r = c->sk_desc; 1009 c->sk_mbuf = m_new; 1010 r->sk_data_lo = vtophys(mtod(m_new, caddr_t)); 1011 r->sk_ctl = m_new->m_len | SK_RXSTAT; 1012 1013 return(0); 1014} 1015 1016/* 1017 * Allocate jumbo buffer storage. The SysKonnect adapters support 1018 * "jumbograms" (9K frames), although SysKonnect doesn't currently 1019 * use them in their drivers. In order for us to use them, we need 1020 * large 9K receive buffers, however standard mbuf clusters are only 1021 * 2048 bytes in size. Consequently, we need to allocate and manage 1022 * our own jumbo buffer pool. Fortunately, this does not require an 1023 * excessive amount of additional code. 1024 */ 1025static int 1026sk_alloc_jumbo_mem(sc_if) 1027 struct sk_if_softc *sc_if; 1028{ 1029 caddr_t ptr; 1030 register int i; 1031 struct sk_jpool_entry *entry; 1032 1033 /* Grab a big chunk o' storage. */ 1034 sc_if->sk_cdata.sk_jumbo_buf = contigmalloc(SK_JMEM, M_DEVBUF, 1035 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1036 1037 if (sc_if->sk_cdata.sk_jumbo_buf == NULL) { 1038 printf("sk%d: no memory for jumbo buffers!\n", sc_if->sk_unit); 1039 return(ENOBUFS); 1040 } 1041 1042 SLIST_INIT(&sc_if->sk_jfree_listhead); 1043 SLIST_INIT(&sc_if->sk_jinuse_listhead); 1044 1045 /* 1046 * Now divide it up into 9K pieces and save the addresses 1047 * in an array. 1048 */ 1049 ptr = sc_if->sk_cdata.sk_jumbo_buf; 1050 for (i = 0; i < SK_JSLOTS; i++) { 1051 sc_if->sk_cdata.sk_jslots[i] = ptr; 1052 ptr += SK_JLEN; 1053 entry = malloc(sizeof(struct sk_jpool_entry), 1054 M_DEVBUF, M_NOWAIT); 1055 if (entry == NULL) { 1056 free(sc_if->sk_cdata.sk_jumbo_buf, M_DEVBUF); 1057 sc_if->sk_cdata.sk_jumbo_buf = NULL; 1058 printf("sk%d: no memory for jumbo " 1059 "buffer queue!\n", sc_if->sk_unit); 1060 return(ENOBUFS); 1061 } 1062 entry->slot = i; 1063 SLIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 1064 entry, jpool_entries); 1065 } 1066 1067 return(0); 1068} 1069 1070/* 1071 * Allocate a jumbo buffer. 1072 */ 1073static void * 1074sk_jalloc(sc_if) 1075 struct sk_if_softc *sc_if; 1076{ 1077 struct sk_jpool_entry *entry; 1078 1079 SK_IF_LOCK_ASSERT(sc_if); 1080 1081 entry = SLIST_FIRST(&sc_if->sk_jfree_listhead); 1082 1083 if (entry == NULL) { 1084#ifdef SK_VERBOSE 1085 printf("sk%d: no free jumbo buffers\n", sc_if->sk_unit); 1086#endif 1087 return(NULL); 1088 } 1089 1090 SLIST_REMOVE_HEAD(&sc_if->sk_jfree_listhead, jpool_entries); 1091 SLIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 1092 return(sc_if->sk_cdata.sk_jslots[entry->slot]); 1093} 1094 1095/* 1096 * Release a jumbo buffer. 1097 */ 1098static void 1099sk_jfree(buf, args) 1100 void *buf; 1101 void *args; 1102{ 1103 struct sk_if_softc *sc_if; 1104 int i; 1105 struct sk_jpool_entry *entry; 1106 1107 /* Extract the softc struct pointer. */ 1108 sc_if = (struct sk_if_softc *)args; 1109 if (sc_if == NULL) 1110 panic("sk_jfree: didn't get softc pointer!"); 1111 1112 SK_IF_LOCK(sc_if); 1113 1114 /* calculate the slot this buffer belongs to */ 1115 i = ((vm_offset_t)buf 1116 - (vm_offset_t)sc_if->sk_cdata.sk_jumbo_buf) / SK_JLEN; 1117 1118 if ((i < 0) || (i >= SK_JSLOTS)) 1119 panic("sk_jfree: asked to free buffer that we don't manage!"); 1120 1121 entry = SLIST_FIRST(&sc_if->sk_jinuse_listhead); 1122 if (entry == NULL) 1123 panic("sk_jfree: buffer not in use!"); 1124 entry->slot = i; 1125 SLIST_REMOVE_HEAD(&sc_if->sk_jinuse_listhead, jpool_entries); 1126 SLIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, entry, jpool_entries); 1127 1128 SK_IF_UNLOCK(sc_if); 1129 return; 1130} 1131 1132/* 1133 * Set media options. 1134 */ 1135static int 1136sk_ifmedia_upd(ifp) 1137 struct ifnet *ifp; 1138{ 1139 struct sk_if_softc *sc_if = ifp->if_softc; 1140 struct mii_data *mii; 1141 1142 mii = device_get_softc(sc_if->sk_miibus); 1143 sk_init(sc_if); 1144 mii_mediachg(mii); 1145 1146 return(0); 1147} 1148 1149/* 1150 * Report current media status. 1151 */ 1152static void 1153sk_ifmedia_sts(ifp, ifmr) 1154 struct ifnet *ifp; 1155 struct ifmediareq *ifmr; 1156{ 1157 struct sk_if_softc *sc_if; 1158 struct mii_data *mii; 1159 1160 sc_if = ifp->if_softc; 1161 mii = device_get_softc(sc_if->sk_miibus); 1162 1163 mii_pollstat(mii); 1164 ifmr->ifm_active = mii->mii_media_active; 1165 ifmr->ifm_status = mii->mii_media_status; 1166 1167 return; 1168} 1169 1170static int 1171sk_ioctl(ifp, command, data) 1172 struct ifnet *ifp; 1173 u_long command; 1174 caddr_t data; 1175{ 1176 struct sk_if_softc *sc_if = ifp->if_softc; 1177 struct ifreq *ifr = (struct ifreq *) data; 1178 int error = 0; 1179 struct mii_data *mii; 1180 1181 SK_IF_LOCK(sc_if); 1182 1183 switch(command) { 1184 case SIOCSIFMTU: 1185 if (ifr->ifr_mtu > SK_JUMBO_MTU) 1186 error = EINVAL; 1187 else { 1188 ifp->if_mtu = ifr->ifr_mtu; 1189 sk_init(sc_if); 1190 } 1191 break; 1192 case SIOCSIFFLAGS: 1193 if (ifp->if_flags & IFF_UP) { 1194 if (ifp->if_flags & IFF_RUNNING) { 1195 if ((ifp->if_flags ^ sc_if->sk_if_flags) 1196 & IFF_PROMISC) { 1197 sk_setpromisc(sc_if); 1198 sk_setmulti(sc_if); 1199 } 1200 } else 1201 sk_init(sc_if); 1202 } else { 1203 if (ifp->if_flags & IFF_RUNNING) 1204 sk_stop(sc_if); 1205 } 1206 sc_if->sk_if_flags = ifp->if_flags; 1207 error = 0; 1208 break; 1209 case SIOCADDMULTI: 1210 case SIOCDELMULTI: 1211 sk_setmulti(sc_if); 1212 error = 0; 1213 break; 1214 case SIOCGIFMEDIA: 1215 case SIOCSIFMEDIA: 1216 mii = device_get_softc(sc_if->sk_miibus); 1217 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1218 break; 1219 default: 1220 error = ether_ioctl(ifp, command, data); 1221 break; 1222 } 1223 1224 SK_IF_UNLOCK(sc_if); 1225 1226 return(error); 1227} 1228 1229/* 1230 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device 1231 * IDs against our list and return a device name if we find a match. 1232 */ 1233static int 1234skc_probe(dev) 1235 device_t dev; 1236{ 1237 struct sk_softc *sc; 1238 struct sk_type *t = sk_devs; 1239 1240 sc = device_get_softc(dev); 1241 1242 while(t->sk_name != NULL) { 1243 if ((pci_get_vendor(dev) == t->sk_vid) && 1244 (pci_get_device(dev) == t->sk_did)) { 1245 device_set_desc(dev, t->sk_name); 1246 return (BUS_PROBE_DEFAULT); 1247 } 1248 t++; 1249 } 1250 1251 return(ENXIO); 1252} 1253 1254/* 1255 * Force the GEnesis into reset, then bring it out of reset. 1256 */ 1257static void 1258sk_reset(sc) 1259 struct sk_softc *sc; 1260{ 1261 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET); 1262 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET); 1263 if (sc->sk_type == SK_YUKON) 1264 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 1265 1266 DELAY(1000); 1267 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET); 1268 DELAY(2); 1269 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 1270 if (sc->sk_type == SK_YUKON) 1271 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 1272 1273 if (sc->sk_type == SK_GENESIS) { 1274 /* Configure packet arbiter */ 1275 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET); 1276 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT); 1277 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT); 1278 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT); 1279 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT); 1280 } 1281 1282 /* Enable RAM interface */ 1283 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 1284 1285 /* 1286 * Configure interrupt moderation. The moderation timer 1287 * defers interrupts specified in the interrupt moderation 1288 * timer mask based on the timeout specified in the interrupt 1289 * moderation timer init register. Each bit in the timer 1290 * register represents 18.825ns, so to specify a timeout in 1291 * microseconds, we have to multiply by 54. 1292 */ 1293 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(200)); 1294 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 1295 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 1296 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 1297 1298 return; 1299} 1300 1301static int 1302sk_probe(dev) 1303 device_t dev; 1304{ 1305 struct sk_softc *sc; 1306 1307 sc = device_get_softc(device_get_parent(dev)); 1308 1309 /* 1310 * Not much to do here. We always know there will be 1311 * at least one XMAC present, and if there are two, 1312 * skc_attach() will create a second device instance 1313 * for us. 1314 */ 1315 switch (sc->sk_type) { 1316 case SK_GENESIS: 1317 device_set_desc(dev, "XaQti Corp. XMAC II"); 1318 break; 1319 case SK_YUKON: 1320 device_set_desc(dev, "Marvell Semiconductor, Inc. Yukon"); 1321 break; 1322 } 1323 1324 return (BUS_PROBE_DEFAULT); 1325} 1326 1327/* 1328 * Each XMAC chip is attached as a separate logical IP interface. 1329 * Single port cards will have only one logical interface of course. 1330 */ 1331static int 1332sk_attach(dev) 1333 device_t dev; 1334{ 1335 struct sk_softc *sc; 1336 struct sk_if_softc *sc_if; 1337 struct ifnet *ifp; 1338 int i, port, error; 1339 1340 if (dev == NULL) 1341 return(EINVAL); 1342 1343 error = 0; 1344 sc_if = device_get_softc(dev); 1345 sc = device_get_softc(device_get_parent(dev)); 1346 port = *(int *)device_get_ivars(dev); 1347 free(device_get_ivars(dev), M_DEVBUF); 1348 device_set_ivars(dev, NULL); 1349 1350 sc_if->sk_dev = dev; 1351 sc_if->sk_unit = device_get_unit(dev); 1352 sc_if->sk_port = port; 1353 sc_if->sk_softc = sc; 1354 sc->sk_if[port] = sc_if; 1355 if (port == SK_PORT_A) 1356 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0; 1357 if (port == SK_PORT_B) 1358 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1; 1359 1360 /* Allocate the descriptor queues. */ 1361 sc_if->sk_rdata = contigmalloc(sizeof(struct sk_ring_data), M_DEVBUF, 1362 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1363 1364 if (sc_if->sk_rdata == NULL) { 1365 printf("sk%d: no memory for list buffers!\n", sc_if->sk_unit); 1366 error = ENOMEM; 1367 goto fail; 1368 } 1369 1370 bzero(sc_if->sk_rdata, sizeof(struct sk_ring_data)); 1371 1372 /* Try to allocate memory for jumbo buffers. */ 1373 if (sk_alloc_jumbo_mem(sc_if)) { 1374 printf("sk%d: jumbo buffer allocation failed\n", 1375 sc_if->sk_unit); 1376 error = ENOMEM; 1377 goto fail; 1378 } 1379 1380 ifp = &sc_if->arpcom.ac_if; 1381 ifp->if_softc = sc_if; 1382 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1383 ifp->if_mtu = ETHERMTU; 1384 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1385 ifp->if_ioctl = sk_ioctl; 1386 ifp->if_start = sk_start; 1387 ifp->if_watchdog = sk_watchdog; 1388 ifp->if_init = sk_init; 1389 ifp->if_baudrate = 1000000000; 1390 IFQ_SET_MAXLEN(&ifp->if_snd, SK_TX_RING_CNT - 1); 1391 ifp->if_snd.ifq_drv_maxlen = SK_TX_RING_CNT - 1; 1392 IFQ_SET_READY(&ifp->if_snd); 1393 1394 callout_handle_init(&sc_if->sk_tick_ch); 1395 1396 /* 1397 * Get station address for this interface. Note that 1398 * dual port cards actually come with three station 1399 * addresses: one for each port, plus an extra. The 1400 * extra one is used by the SysKonnect driver software 1401 * as a 'virtual' station address for when both ports 1402 * are operating in failover mode. Currently we don't 1403 * use this extra address. 1404 */ 1405 SK_LOCK(sc); 1406 for (i = 0; i < ETHER_ADDR_LEN; i++) 1407 sc_if->arpcom.ac_enaddr[i] = 1408 sk_win_read_1(sc, SK_MAC0_0 + (port * 8) + i); 1409 1410 /* 1411 * Set up RAM buffer addresses. The NIC will have a certain 1412 * amount of SRAM on it, somewhere between 512K and 2MB. We 1413 * need to divide this up a) between the transmitter and 1414 * receiver and b) between the two XMACs, if this is a 1415 * dual port NIC. Our algotithm is to divide up the memory 1416 * evenly so that everyone gets a fair share. 1417 */ 1418 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) { 1419 u_int32_t chunk, val; 1420 1421 chunk = sc->sk_ramsize / 2; 1422 val = sc->sk_rboff / sizeof(u_int64_t); 1423 sc_if->sk_rx_ramstart = val; 1424 val += (chunk / sizeof(u_int64_t)); 1425 sc_if->sk_rx_ramend = val - 1; 1426 sc_if->sk_tx_ramstart = val; 1427 val += (chunk / sizeof(u_int64_t)); 1428 sc_if->sk_tx_ramend = val - 1; 1429 } else { 1430 u_int32_t chunk, val; 1431 1432 chunk = sc->sk_ramsize / 4; 1433 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) / 1434 sizeof(u_int64_t); 1435 sc_if->sk_rx_ramstart = val; 1436 val += (chunk / sizeof(u_int64_t)); 1437 sc_if->sk_rx_ramend = val - 1; 1438 sc_if->sk_tx_ramstart = val; 1439 val += (chunk / sizeof(u_int64_t)); 1440 sc_if->sk_tx_ramend = val - 1; 1441 } 1442 1443 /* Read and save PHY type and set PHY address */ 1444 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 1445 switch(sc_if->sk_phytype) { 1446 case SK_PHYTYPE_XMAC: 1447 sc_if->sk_phyaddr = SK_PHYADDR_XMAC; 1448 break; 1449 case SK_PHYTYPE_BCOM: 1450 sc_if->sk_phyaddr = SK_PHYADDR_BCOM; 1451 break; 1452 case SK_PHYTYPE_MARV_COPPER: 1453 sc_if->sk_phyaddr = SK_PHYADDR_MARV; 1454 break; 1455 default: 1456 printf("skc%d: unsupported PHY type: %d\n", 1457 sc->sk_unit, sc_if->sk_phytype); 1458 error = ENODEV; 1459 SK_UNLOCK(sc); 1460 goto fail; 1461 } 1462 1463 1464 /* 1465 * Call MI attach routine. Can't hold locks when calling into ether_*. 1466 */ 1467 SK_UNLOCK(sc); 1468 ether_ifattach(ifp, sc_if->arpcom.ac_enaddr); 1469 SK_LOCK(sc); 1470 1471 /* 1472 * Do miibus setup. 1473 */ 1474 switch (sc->sk_type) { 1475 case SK_GENESIS: 1476 sk_init_xmac(sc_if); 1477 break; 1478 case SK_YUKON: 1479 sk_init_yukon(sc_if); 1480 break; 1481 } 1482 1483 SK_UNLOCK(sc); 1484 if (mii_phy_probe(dev, &sc_if->sk_miibus, 1485 sk_ifmedia_upd, sk_ifmedia_sts)) { 1486 printf("skc%d: no PHY found!\n", sc_if->sk_unit); 1487 ether_ifdetach(ifp); 1488 error = ENXIO; 1489 goto fail; 1490 } 1491 1492fail: 1493 if (error) { 1494 /* Access should be ok even though lock has been dropped */ 1495 sc->sk_if[port] = NULL; 1496 sk_detach(dev); 1497 } 1498 1499 return(error); 1500} 1501 1502/* 1503 * Attach the interface. Allocate softc structures, do ifmedia 1504 * setup and ethernet/BPF attach. 1505 */ 1506static int 1507skc_attach(dev) 1508 device_t dev; 1509{ 1510 struct sk_softc *sc; 1511 int unit, error = 0, rid, *port; 1512 uint8_t skrs; 1513 1514 sc = device_get_softc(dev); 1515 unit = device_get_unit(dev); 1516 1517 mtx_init(&sc->sk_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1518 MTX_DEF | MTX_RECURSE); 1519 /* 1520 * Map control/status registers. 1521 */ 1522 pci_enable_busmaster(dev); 1523 1524 rid = SK_RID; 1525 sc->sk_res = bus_alloc_resource_any(dev, SK_RES, &rid, RF_ACTIVE); 1526 1527 if (sc->sk_res == NULL) { 1528 printf("sk%d: couldn't map ports/memory\n", unit); 1529 error = ENXIO; 1530 goto fail; 1531 } 1532 1533 sc->sk_btag = rman_get_bustag(sc->sk_res); 1534 sc->sk_bhandle = rman_get_bushandle(sc->sk_res); 1535 1536 /* Allocate interrupt */ 1537 rid = 0; 1538 sc->sk_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1539 RF_SHAREABLE | RF_ACTIVE); 1540 1541 if (sc->sk_irq == NULL) { 1542 printf("skc%d: couldn't map interrupt\n", unit); 1543 error = ENXIO; 1544 goto fail; 1545 } 1546 1547 /* Set adapter type */ 1548 switch (pci_get_device(dev)) { 1549 case DEVICEID_SK_V1: 1550 sc->sk_type = SK_GENESIS; 1551 break; 1552 case DEVICEID_SK_V2: 1553 case DEVICEID_BELKIN_5005: 1554 case DEVICEID_3COM_3C940: 1555 case DEVICEID_LINKSYS_EG1032: 1556 case DEVICEID_DLINK_DGE530T: 1557 sc->sk_type = SK_YUKON; 1558 break; 1559 default: 1560 printf("skc%d: unknown device!\n", unit); 1561 error = ENXIO; 1562 goto fail; 1563 } 1564 1565 /* Reset the adapter. */ 1566 sk_reset(sc); 1567 1568 sc->sk_unit = unit; 1569 1570 /* Read and save vital product data from EEPROM. */ 1571 sk_vpd_read(sc); 1572 1573 skrs = sk_win_read_1(sc, SK_EPROM0); 1574 if (sc->sk_type == SK_GENESIS) { 1575 /* Read and save RAM size and RAMbuffer offset */ 1576 switch(skrs) { 1577 case SK_RAMSIZE_512K_64: 1578 sc->sk_ramsize = 0x80000; 1579 sc->sk_rboff = SK_RBOFF_0; 1580 break; 1581 case SK_RAMSIZE_1024K_64: 1582 sc->sk_ramsize = 0x100000; 1583 sc->sk_rboff = SK_RBOFF_80000; 1584 break; 1585 case SK_RAMSIZE_1024K_128: 1586 sc->sk_ramsize = 0x100000; 1587 sc->sk_rboff = SK_RBOFF_0; 1588 break; 1589 case SK_RAMSIZE_2048K_128: 1590 sc->sk_ramsize = 0x200000; 1591 sc->sk_rboff = SK_RBOFF_0; 1592 break; 1593 default: 1594 printf("skc%d: unknown ram size: %d\n", 1595 sc->sk_unit, sk_win_read_1(sc, SK_EPROM0)); 1596 error = ENXIO; 1597 goto fail; 1598 } 1599 } else { /* SK_YUKON */ 1600 if (skrs == 0x00) 1601 sc->sk_ramsize = 0x20000; 1602 else 1603 sc->sk_ramsize = skrs * (1<<12); 1604 sc->sk_rboff = SK_RBOFF_0; 1605 } 1606 1607 /* Read and save physical media type */ 1608 switch(sk_win_read_1(sc, SK_PMDTYPE)) { 1609 case SK_PMD_1000BASESX: 1610 sc->sk_pmd = IFM_1000_SX; 1611 break; 1612 case SK_PMD_1000BASELX: 1613 sc->sk_pmd = IFM_1000_LX; 1614 break; 1615 case SK_PMD_1000BASECX: 1616 sc->sk_pmd = IFM_1000_CX; 1617 break; 1618 case SK_PMD_1000BASETX: 1619 sc->sk_pmd = IFM_1000_T; 1620 break; 1621 default: 1622 printf("skc%d: unknown media type: 0x%x\n", 1623 sc->sk_unit, sk_win_read_1(sc, SK_PMDTYPE)); 1624 error = ENXIO; 1625 goto fail; 1626 } 1627 1628 /* Announce the product name and more VPD data if there. */ 1629 if (sc->sk_vpd_prodname != NULL) 1630 printf("skc%d: %s\n", sc->sk_unit, sc->sk_vpd_prodname); 1631 1632 if (bootverbose) { 1633 if (sc->sk_vpd_readonly != NULL && 1634 sc->sk_vpd_readonly_len != 0) { 1635 char buf[256]; 1636 char *dp = sc->sk_vpd_readonly; 1637 uint16_t l, len = sc->sk_vpd_readonly_len; 1638 1639 while (len >= 3) { 1640 if ((*dp == 'P' && *(dp+1) == 'N') || 1641 (*dp == 'E' && *(dp+1) == 'C') || 1642 (*dp == 'M' && *(dp+1) == 'N') || 1643 (*dp == 'S' && *(dp+1) == 'N')) { 1644 l = 0; 1645 while (l < *(dp+2)) { 1646 buf[l] = *(dp+3+l); 1647 ++l; 1648 } 1649 buf[l] = '\0'; 1650 device_printf(dev, "%c%c: %s\n", 1651 *dp, *(dp+1), buf); 1652 len -= (3 + l); 1653 dp += (3 + l); 1654 } else { 1655 len -= (3 + *(dp+2)); 1656 dp += (3 + *(dp+2)); 1657 } 1658 } 1659 } 1660 device_printf(dev, "type = %s\n", 1661 (sc->sk_type == SK_GENESIS) ? "GENESIS" : "YUKON"); 1662 device_printf(dev, "SK_EPROM0 = 0x%02x\n", skrs); 1663 device_printf(dev, "SRAM size = 0x%06x\n", sc->sk_ramsize); 1664 device_printf(dev, "chip ver 0x%02x\n", 1665 sk_win_read_1(sc, SK_CHIPVER)); 1666 device_printf(dev, "chip conf 0x%02x\n", 1667 sk_win_read_1(sc, SK_CONFIG)); 1668 } 1669 1670 sc->sk_devs[SK_PORT_A] = device_add_child(dev, "sk", -1); 1671 port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT); 1672 *port = SK_PORT_A; 1673 device_set_ivars(sc->sk_devs[SK_PORT_A], port); 1674 1675 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) { 1676 sc->sk_devs[SK_PORT_B] = device_add_child(dev, "sk", -1); 1677 port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT); 1678 *port = SK_PORT_B; 1679 device_set_ivars(sc->sk_devs[SK_PORT_B], port); 1680 } 1681 1682 /* Turn on the 'driver is loaded' LED. */ 1683 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1684 1685 bus_generic_attach(dev); 1686 1687 /* Hook interrupt last to avoid having to lock softc */ 1688 error = bus_setup_intr(dev, sc->sk_irq, INTR_TYPE_NET|INTR_MPSAFE, 1689 sk_intr, sc, &sc->sk_intrhand); 1690 1691 if (error) { 1692 printf("skc%d: couldn't set up irq\n", unit); 1693 goto fail; 1694 } 1695 1696fail: 1697 if (error) 1698 skc_detach(dev); 1699 1700 return(error); 1701} 1702 1703/* 1704 * Shutdown hardware and free up resources. This can be called any 1705 * time after the mutex has been initialized. It is called in both 1706 * the error case in attach and the normal detach case so it needs 1707 * to be careful about only freeing resources that have actually been 1708 * allocated. 1709 */ 1710static int 1711sk_detach(dev) 1712 device_t dev; 1713{ 1714 struct sk_if_softc *sc_if; 1715 struct ifnet *ifp; 1716 1717 sc_if = device_get_softc(dev); 1718 KASSERT(mtx_initialized(&sc_if->sk_softc->sk_mtx), 1719 ("sk mutex not initialized in sk_detach")); 1720 SK_IF_LOCK(sc_if); 1721 1722 ifp = &sc_if->arpcom.ac_if; 1723 /* These should only be active if attach_xmac succeeded */ 1724 if (device_is_attached(dev)) { 1725 sk_stop(sc_if); 1726 /* Can't hold locks while calling detach */ 1727 SK_IF_UNLOCK(sc_if); 1728 ether_ifdetach(ifp); 1729 SK_IF_LOCK(sc_if); 1730 } 1731 /* 1732 * We're generally called from skc_detach() which is using 1733 * device_delete_child() to get to here. It's already trashed 1734 * miibus for us, so don't do it here or we'll panic. 1735 */ 1736 /* 1737 if (sc_if->sk_miibus != NULL) 1738 device_delete_child(dev, sc_if->sk_miibus); 1739 */ 1740 bus_generic_detach(dev); 1741 if (sc_if->sk_cdata.sk_jumbo_buf != NULL) 1742 contigfree(sc_if->sk_cdata.sk_jumbo_buf, SK_JMEM, M_DEVBUF); 1743 if (sc_if->sk_rdata != NULL) { 1744 contigfree(sc_if->sk_rdata, sizeof(struct sk_ring_data), 1745 M_DEVBUF); 1746 } 1747 SK_IF_UNLOCK(sc_if); 1748 1749 return(0); 1750} 1751 1752static int 1753skc_detach(dev) 1754 device_t dev; 1755{ 1756 struct sk_softc *sc; 1757 1758 sc = device_get_softc(dev); 1759 KASSERT(mtx_initialized(&sc->sk_mtx), ("sk mutex not initialized")); 1760 1761 if (device_is_alive(dev)) { 1762 if (sc->sk_devs[SK_PORT_A] != NULL) 1763 device_delete_child(dev, sc->sk_devs[SK_PORT_A]); 1764 if (sc->sk_devs[SK_PORT_B] != NULL) 1765 device_delete_child(dev, sc->sk_devs[SK_PORT_B]); 1766 bus_generic_detach(dev); 1767 } 1768 1769 if (sc->sk_intrhand) 1770 bus_teardown_intr(dev, sc->sk_irq, sc->sk_intrhand); 1771 if (sc->sk_irq) 1772 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq); 1773 if (sc->sk_res) 1774 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res); 1775 1776 mtx_destroy(&sc->sk_mtx); 1777 1778 return(0); 1779} 1780 1781static int 1782sk_encap(sc_if, m_head, txidx) 1783 struct sk_if_softc *sc_if; 1784 struct mbuf *m_head; 1785 u_int32_t *txidx; 1786{ 1787 struct sk_tx_desc *f = NULL; 1788 struct mbuf *m; 1789 u_int32_t frag, cur, cnt = 0; 1790 1791 SK_IF_LOCK_ASSERT(sc_if); 1792 1793 m = m_head; 1794 cur = frag = *txidx; 1795 1796 /* 1797 * Start packing the mbufs in this chain into 1798 * the fragment pointers. Stop when we run out 1799 * of fragments or hit the end of the mbuf chain. 1800 */ 1801 for (m = m_head; m != NULL; m = m->m_next) { 1802 if (m->m_len != 0) { 1803 if ((SK_TX_RING_CNT - 1804 (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2) 1805 return(ENOBUFS); 1806 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1807 f->sk_data_lo = vtophys(mtod(m, vm_offset_t)); 1808 f->sk_ctl = m->m_len | SK_OPCODE_DEFAULT; 1809 if (cnt == 0) 1810 f->sk_ctl |= SK_TXCTL_FIRSTFRAG; 1811 else 1812 f->sk_ctl |= SK_TXCTL_OWN; 1813 cur = frag; 1814 SK_INC(frag, SK_TX_RING_CNT); 1815 cnt++; 1816 } 1817 } 1818 1819 if (m != NULL) 1820 return(ENOBUFS); 1821 1822 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= 1823 SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR; 1824 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1825 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |= SK_TXCTL_OWN; 1826 sc_if->sk_cdata.sk_tx_cnt += cnt; 1827 1828 *txidx = frag; 1829 1830 return(0); 1831} 1832 1833static void 1834sk_start(ifp) 1835 struct ifnet *ifp; 1836{ 1837 struct sk_softc *sc; 1838 struct sk_if_softc *sc_if; 1839 struct mbuf *m_head = NULL; 1840 u_int32_t idx; 1841 1842 sc_if = ifp->if_softc; 1843 sc = sc_if->sk_softc; 1844 1845 SK_IF_LOCK(sc_if); 1846 1847 idx = sc_if->sk_cdata.sk_tx_prod; 1848 1849 while(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1850 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1851 if (m_head == NULL) 1852 break; 1853 1854 /* 1855 * Pack the data into the transmit ring. If we 1856 * don't have room, set the OACTIVE flag and wait 1857 * for the NIC to drain the ring. 1858 */ 1859 if (sk_encap(sc_if, m_head, &idx)) { 1860 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1861 ifp->if_flags |= IFF_OACTIVE; 1862 break; 1863 } 1864 1865 /* 1866 * If there's a BPF listener, bounce a copy of this frame 1867 * to him. 1868 */ 1869 BPF_MTAP(ifp, m_head); 1870 } 1871 1872 /* Transmit */ 1873 if (idx != sc_if->sk_cdata.sk_tx_prod) { 1874 sc_if->sk_cdata.sk_tx_prod = idx; 1875 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 1876 1877 /* Set a timeout in case the chip goes out to lunch. */ 1878 ifp->if_timer = 5; 1879 } 1880 SK_IF_UNLOCK(sc_if); 1881 1882 return; 1883} 1884 1885 1886static void 1887sk_watchdog(ifp) 1888 struct ifnet *ifp; 1889{ 1890 struct sk_if_softc *sc_if; 1891 1892 sc_if = ifp->if_softc; 1893 1894 printf("sk%d: watchdog timeout\n", sc_if->sk_unit); 1895 sk_init(sc_if); 1896 1897 return; 1898} 1899 1900static void 1901skc_shutdown(dev) 1902 device_t dev; 1903{ 1904 struct sk_softc *sc; 1905 1906 sc = device_get_softc(dev); 1907 SK_LOCK(sc); 1908 1909 /* Turn off the 'driver is loaded' LED. */ 1910 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 1911 1912 /* 1913 * Reset the GEnesis controller. Doing this should also 1914 * assert the resets on the attached XMAC(s). 1915 */ 1916 sk_reset(sc); 1917 SK_UNLOCK(sc); 1918 1919 return; 1920} 1921 1922static void 1923sk_rxeof(sc_if) 1924 struct sk_if_softc *sc_if; 1925{ 1926 struct sk_softc *sc; 1927 struct mbuf *m; 1928 struct ifnet *ifp; 1929 struct sk_chain *cur_rx; 1930 int total_len = 0; 1931 int i; 1932 u_int32_t rxstat; 1933 1934 sc = sc_if->sk_softc; 1935 ifp = &sc_if->arpcom.ac_if; 1936 i = sc_if->sk_cdata.sk_rx_prod; 1937 cur_rx = &sc_if->sk_cdata.sk_rx_chain[i]; 1938 1939 SK_LOCK_ASSERT(sc); 1940 1941 while(!(sc_if->sk_rdata->sk_rx_ring[i].sk_ctl & SK_RXCTL_OWN)) { 1942 1943 cur_rx = &sc_if->sk_cdata.sk_rx_chain[i]; 1944 rxstat = sc_if->sk_rdata->sk_rx_ring[i].sk_xmac_rxstat; 1945 m = cur_rx->sk_mbuf; 1946 cur_rx->sk_mbuf = NULL; 1947 total_len = SK_RXBYTES(sc_if->sk_rdata->sk_rx_ring[i].sk_ctl); 1948 SK_INC(i, SK_RX_RING_CNT); 1949 1950 if (rxstat & XM_RXSTAT_ERRFRAME) { 1951 ifp->if_ierrors++; 1952 sk_newbuf(sc_if, cur_rx, m); 1953 continue; 1954 } 1955 1956 /* 1957 * Try to allocate a new jumbo buffer. If that 1958 * fails, copy the packet to mbufs and put the 1959 * jumbo buffer back in the ring so it can be 1960 * re-used. If allocating mbufs fails, then we 1961 * have to drop the packet. 1962 */ 1963 if (sk_newbuf(sc_if, cur_rx, NULL) == ENOBUFS) { 1964 struct mbuf *m0; 1965 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, 1966 ifp, NULL); 1967 sk_newbuf(sc_if, cur_rx, m); 1968 if (m0 == NULL) { 1969 printf("sk%d: no receive buffers " 1970 "available -- packet dropped!\n", 1971 sc_if->sk_unit); 1972 ifp->if_ierrors++; 1973 continue; 1974 } 1975 m = m0; 1976 } else { 1977 m->m_pkthdr.rcvif = ifp; 1978 m->m_pkthdr.len = m->m_len = total_len; 1979 } 1980 1981 ifp->if_ipackets++; 1982 SK_UNLOCK(sc); 1983 (*ifp->if_input)(ifp, m); 1984 SK_LOCK(sc); 1985 } 1986 1987 sc_if->sk_cdata.sk_rx_prod = i; 1988 1989 return; 1990} 1991 1992static void 1993sk_txeof(sc_if) 1994 struct sk_if_softc *sc_if; 1995{ 1996 struct sk_softc *sc; 1997 struct sk_tx_desc *cur_tx; 1998 struct ifnet *ifp; 1999 u_int32_t idx; 2000 2001 sc = sc_if->sk_softc; 2002 ifp = &sc_if->arpcom.ac_if; 2003 2004 /* 2005 * Go through our tx ring and free mbufs for those 2006 * frames that have been sent. 2007 */ 2008 idx = sc_if->sk_cdata.sk_tx_cons; 2009 while(idx != sc_if->sk_cdata.sk_tx_prod) { 2010 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 2011 if (cur_tx->sk_ctl & SK_TXCTL_OWN) 2012 break; 2013 if (cur_tx->sk_ctl & SK_TXCTL_LASTFRAG) 2014 ifp->if_opackets++; 2015 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 2016 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 2017 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 2018 } 2019 sc_if->sk_cdata.sk_tx_cnt--; 2020 SK_INC(idx, SK_TX_RING_CNT); 2021 } 2022 2023 if (sc_if->sk_cdata.sk_tx_cnt == 0) { 2024 ifp->if_timer = 0; 2025 } else /* nudge chip to keep tx ring moving */ 2026 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 2027 2028 if (sc_if->sk_cdata.sk_tx_cnt < SK_TX_RING_CNT - 2) 2029 ifp->if_flags &= ~IFF_OACTIVE; 2030 2031 sc_if->sk_cdata.sk_tx_cons = idx; 2032} 2033 2034static void 2035sk_tick(xsc_if) 2036 void *xsc_if; 2037{ 2038 struct sk_if_softc *sc_if; 2039 struct mii_data *mii; 2040 struct ifnet *ifp; 2041 int i; 2042 2043 sc_if = xsc_if; 2044 SK_IF_LOCK(sc_if); 2045 ifp = &sc_if->arpcom.ac_if; 2046 mii = device_get_softc(sc_if->sk_miibus); 2047 2048 if (!(ifp->if_flags & IFF_UP)) { 2049 SK_IF_UNLOCK(sc_if); 2050 return; 2051 } 2052 2053 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2054 sk_intr_bcom(sc_if); 2055 SK_IF_UNLOCK(sc_if); 2056 return; 2057 } 2058 2059 /* 2060 * According to SysKonnect, the correct way to verify that 2061 * the link has come back up is to poll bit 0 of the GPIO 2062 * register three times. This pin has the signal from the 2063 * link_sync pin connected to it; if we read the same link 2064 * state 3 times in a row, we know the link is up. 2065 */ 2066 for (i = 0; i < 3; i++) { 2067 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET) 2068 break; 2069 } 2070 2071 if (i != 3) { 2072 sc_if->sk_tick_ch = timeout(sk_tick, sc_if, hz); 2073 SK_IF_UNLOCK(sc_if); 2074 return; 2075 } 2076 2077 /* Turn the GP0 interrupt back on. */ 2078 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2079 SK_XM_READ_2(sc_if, XM_ISR); 2080 mii_tick(mii); 2081 untimeout(sk_tick, sc_if, sc_if->sk_tick_ch); 2082 2083 SK_IF_UNLOCK(sc_if); 2084 return; 2085} 2086 2087static void 2088sk_intr_bcom(sc_if) 2089 struct sk_if_softc *sc_if; 2090{ 2091 struct mii_data *mii; 2092 struct ifnet *ifp; 2093 int status; 2094 mii = device_get_softc(sc_if->sk_miibus); 2095 ifp = &sc_if->arpcom.ac_if; 2096 2097 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2098 2099 /* 2100 * Read the PHY interrupt register to make sure 2101 * we clear any pending interrupts. 2102 */ 2103 status = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, BRGPHY_MII_ISR); 2104 2105 if (!(ifp->if_flags & IFF_RUNNING)) { 2106 sk_init_xmac(sc_if); 2107 return; 2108 } 2109 2110 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) { 2111 int lstat; 2112 lstat = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, 2113 BRGPHY_MII_AUXSTS); 2114 2115 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) { 2116 mii_mediachg(mii); 2117 /* Turn off the link LED. */ 2118 SK_IF_WRITE_1(sc_if, 0, 2119 SK_LINKLED1_CTL, SK_LINKLED_OFF); 2120 sc_if->sk_link = 0; 2121 } else if (status & BRGPHY_ISR_LNK_CHG) { 2122 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 2123 BRGPHY_MII_IMR, 0xFF00); 2124 mii_tick(mii); 2125 sc_if->sk_link = 1; 2126 /* Turn on the link LED. */ 2127 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2128 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF| 2129 SK_LINKLED_BLINK_OFF); 2130 } else { 2131 mii_tick(mii); 2132 sc_if->sk_tick_ch = timeout(sk_tick, sc_if, hz); 2133 } 2134 } 2135 2136 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2137 2138 return; 2139} 2140 2141static void 2142sk_intr_xmac(sc_if) 2143 struct sk_if_softc *sc_if; 2144{ 2145 struct sk_softc *sc; 2146 u_int16_t status; 2147 2148 sc = sc_if->sk_softc; 2149 status = SK_XM_READ_2(sc_if, XM_ISR); 2150 2151 /* 2152 * Link has gone down. Start MII tick timeout to 2153 * watch for link resync. 2154 */ 2155 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) { 2156 if (status & XM_ISR_GP0_SET) { 2157 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2158 sc_if->sk_tick_ch = timeout(sk_tick, sc_if, hz); 2159 } 2160 2161 if (status & XM_ISR_AUTONEG_DONE) { 2162 sc_if->sk_tick_ch = timeout(sk_tick, sc_if, hz); 2163 } 2164 } 2165 2166 if (status & XM_IMR_TX_UNDERRUN) 2167 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO); 2168 2169 if (status & XM_IMR_RX_OVERRUN) 2170 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO); 2171 2172 status = SK_XM_READ_2(sc_if, XM_ISR); 2173 2174 return; 2175} 2176 2177static void 2178sk_intr_yukon(sc_if) 2179 struct sk_if_softc *sc_if; 2180{ 2181 int status; 2182 2183 status = SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2184 2185 return; 2186} 2187 2188static void 2189sk_intr(xsc) 2190 void *xsc; 2191{ 2192 struct sk_softc *sc = xsc; 2193 struct sk_if_softc *sc_if0 = NULL, *sc_if1 = NULL; 2194 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2195 u_int32_t status; 2196 2197 SK_LOCK(sc); 2198 2199 sc_if0 = sc->sk_if[SK_PORT_A]; 2200 sc_if1 = sc->sk_if[SK_PORT_B]; 2201 2202 if (sc_if0 != NULL) 2203 ifp0 = &sc_if0->arpcom.ac_if; 2204 if (sc_if1 != NULL) 2205 ifp1 = &sc_if1->arpcom.ac_if; 2206 2207 for (;;) { 2208 status = CSR_READ_4(sc, SK_ISSR); 2209 if (!(status & sc->sk_intrmask)) 2210 break; 2211 2212 /* Handle receive interrupts first. */ 2213 if (status & SK_ISR_RX1_EOF) { 2214 sk_rxeof(sc_if0); 2215 CSR_WRITE_4(sc, SK_BMU_RX_CSR0, 2216 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2217 } 2218 if (status & SK_ISR_RX2_EOF) { 2219 sk_rxeof(sc_if1); 2220 CSR_WRITE_4(sc, SK_BMU_RX_CSR1, 2221 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2222 } 2223 2224 /* Then transmit interrupts. */ 2225 if (status & SK_ISR_TX1_S_EOF) { 2226 sk_txeof(sc_if0); 2227 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, 2228 SK_TXBMU_CLR_IRQ_EOF); 2229 } 2230 if (status & SK_ISR_TX2_S_EOF) { 2231 sk_txeof(sc_if1); 2232 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, 2233 SK_TXBMU_CLR_IRQ_EOF); 2234 } 2235 2236 /* Then MAC interrupts. */ 2237 if (status & SK_ISR_MAC1 && ifp0->if_flags & IFF_RUNNING) { 2238 if (sc->sk_type == SK_GENESIS) 2239 sk_intr_xmac(sc_if0); 2240 else 2241 sk_intr_yukon(sc_if0); 2242 } 2243 2244 if (status & SK_ISR_MAC2 && ifp1->if_flags & IFF_RUNNING) { 2245 if (sc->sk_type == SK_GENESIS) 2246 sk_intr_xmac(sc_if1); 2247 else 2248 sk_intr_yukon(sc_if1); 2249 } 2250 2251 if (status & SK_ISR_EXTERNAL_REG) { 2252 if (ifp0 != NULL && 2253 sc_if0->sk_phytype == SK_PHYTYPE_BCOM) 2254 sk_intr_bcom(sc_if0); 2255 if (ifp1 != NULL && 2256 sc_if1->sk_phytype == SK_PHYTYPE_BCOM) 2257 sk_intr_bcom(sc_if1); 2258 } 2259 } 2260 2261 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2262 2263 if (ifp0 != NULL && !IFQ_DRV_IS_EMPTY(&ifp0->if_snd)) 2264 sk_start(ifp0); 2265 if (ifp1 != NULL && !IFQ_DRV_IS_EMPTY(&ifp1->if_snd)) 2266 sk_start(ifp1); 2267 2268 SK_UNLOCK(sc); 2269 2270 return; 2271} 2272 2273static void 2274sk_init_xmac(sc_if) 2275 struct sk_if_softc *sc_if; 2276{ 2277 struct sk_softc *sc; 2278 struct ifnet *ifp; 2279 struct sk_bcom_hack bhack[] = { 2280 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, 2281 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, 2282 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 2283 { 0, 0 } }; 2284 2285 sc = sc_if->sk_softc; 2286 ifp = &sc_if->arpcom.ac_if; 2287 2288 /* Unreset the XMAC. */ 2289 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET); 2290 DELAY(1000); 2291 2292 /* Reset the XMAC's internal state. */ 2293 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2294 2295 /* Save the XMAC II revision */ 2296 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID)); 2297 2298 /* 2299 * Perform additional initialization for external PHYs, 2300 * namely for the 1000baseTX cards that use the XMAC's 2301 * GMII mode. 2302 */ 2303 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2304 int i = 0; 2305 u_int32_t val; 2306 2307 /* Take PHY out of reset. */ 2308 val = sk_win_read_4(sc, SK_GPIO); 2309 if (sc_if->sk_port == SK_PORT_A) 2310 val |= SK_GPIO_DIR0|SK_GPIO_DAT0; 2311 else 2312 val |= SK_GPIO_DIR2|SK_GPIO_DAT2; 2313 sk_win_write_4(sc, SK_GPIO, val); 2314 2315 /* Enable GMII mode on the XMAC. */ 2316 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE); 2317 2318 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 2319 BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET); 2320 DELAY(10000); 2321 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 2322 BRGPHY_MII_IMR, 0xFFF0); 2323 2324 /* 2325 * Early versions of the BCM5400 apparently have 2326 * a bug that requires them to have their reserved 2327 * registers initialized to some magic values. I don't 2328 * know what the numbers do, I'm just the messenger. 2329 */ 2330 if (sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, 0x03) 2331 == 0x6041) { 2332 while(bhack[i].reg) { 2333 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 2334 bhack[i].reg, bhack[i].val); 2335 i++; 2336 } 2337 } 2338 } 2339 2340 /* Set station address */ 2341 SK_XM_WRITE_2(sc_if, XM_PAR0, 2342 *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[0])); 2343 SK_XM_WRITE_2(sc_if, XM_PAR1, 2344 *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[2])); 2345 SK_XM_WRITE_2(sc_if, XM_PAR2, 2346 *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[4])); 2347 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION); 2348 2349 if (ifp->if_flags & IFF_BROADCAST) { 2350 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2351 } else { 2352 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2353 } 2354 2355 /* We don't need the FCS appended to the packet. */ 2356 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS); 2357 2358 /* We want short frames padded to 60 bytes. */ 2359 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD); 2360 2361 /* 2362 * Enable the reception of all error frames. This is is 2363 * a necessary evil due to the design of the XMAC. The 2364 * XMAC's receive FIFO is only 8K in size, however jumbo 2365 * frames can be up to 9000 bytes in length. When bad 2366 * frame filtering is enabled, the XMAC's RX FIFO operates 2367 * in 'store and forward' mode. For this to work, the 2368 * entire frame has to fit into the FIFO, but that means 2369 * that jumbo frames larger than 8192 bytes will be 2370 * truncated. Disabling all bad frame filtering causes 2371 * the RX FIFO to operate in streaming mode, in which 2372 * case the XMAC will start transfering frames out of the 2373 * RX FIFO as soon as the FIFO threshold is reached. 2374 */ 2375 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES| 2376 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS| 2377 XM_MODE_RX_INRANGELEN); 2378 2379 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2380 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2381 else 2382 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2383 2384 /* 2385 * Bump up the transmit threshold. This helps hold off transmit 2386 * underruns when we're blasting traffic from both ports at once. 2387 */ 2388 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH); 2389 2390 /* Set promiscuous mode */ 2391 sk_setpromisc(sc_if); 2392 2393 /* Set multicast filter */ 2394 sk_setmulti(sc_if); 2395 2396 /* Clear and enable interrupts */ 2397 SK_XM_READ_2(sc_if, XM_ISR); 2398 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 2399 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS); 2400 else 2401 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2402 2403 /* Configure MAC arbiter */ 2404 switch(sc_if->sk_xmac_rev) { 2405 case XM_XMAC_REV_B2: 2406 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2); 2407 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2); 2408 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2); 2409 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2); 2410 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2); 2411 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2); 2412 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2); 2413 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2); 2414 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2415 break; 2416 case XM_XMAC_REV_C1: 2417 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1); 2418 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1); 2419 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1); 2420 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1); 2421 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1); 2422 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1); 2423 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1); 2424 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1); 2425 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2426 break; 2427 default: 2428 break; 2429 } 2430 sk_win_write_2(sc, SK_MACARB_CTL, 2431 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF); 2432 2433 sc_if->sk_link = 1; 2434 2435 return; 2436} 2437 2438static void 2439sk_init_yukon(sc_if) 2440 struct sk_if_softc *sc_if; 2441{ 2442 u_int32_t phy; 2443 u_int16_t reg; 2444 struct sk_softc *sc; 2445 struct ifnet *ifp; 2446 int i; 2447 2448 sc = sc_if->sk_softc; 2449 ifp = &sc_if->arpcom.ac_if; 2450 2451 /* GMAC and GPHY Reset */ 2452 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 2453 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2454 DELAY(1000); 2455 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_CLEAR); 2456 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2457 DELAY(1000); 2458 2459 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP | 2460 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE; 2461 2462 switch(sc_if->sk_softc->sk_pmd) { 2463 case IFM_1000_SX: 2464 case IFM_1000_LX: 2465 phy |= SK_GPHY_FIBER; 2466 break; 2467 2468 case IFM_1000_CX: 2469 case IFM_1000_T: 2470 phy |= SK_GPHY_COPPER; 2471 break; 2472 } 2473 2474 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET); 2475 DELAY(1000); 2476 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR); 2477 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 2478 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 2479 2480 /* unused read of the interrupt source register */ 2481 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2482 2483 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2484 2485 /* MIB Counter Clear Mode set */ 2486 reg |= YU_PAR_MIB_CLR; 2487 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2488 2489 /* MIB Counter Clear Mode clear */ 2490 reg &= ~YU_PAR_MIB_CLR; 2491 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2492 2493 /* receive control reg */ 2494 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR); 2495 2496 /* transmit parameter register */ 2497 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2498 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) ); 2499 2500 /* serial mode register */ 2501 reg = YU_SMR_DATA_BLIND(0x1c) | YU_SMR_MFL_VLAN | YU_SMR_IPG_DATA(0x1e); 2502 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2503 reg |= YU_SMR_MFL_JUMBO; 2504 SK_YU_WRITE_2(sc_if, YUKON_SMR, reg); 2505 2506 /* Setup Yukon's address */ 2507 for (i = 0; i < 3; i++) { 2508 /* Write Source Address 1 (unicast filter) */ 2509 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2510 sc_if->arpcom.ac_enaddr[i * 2] | 2511 sc_if->arpcom.ac_enaddr[i * 2 + 1] << 8); 2512 } 2513 2514 for (i = 0; i < 3; i++) { 2515 reg = sk_win_read_2(sc_if->sk_softc, 2516 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2517 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2518 } 2519 2520 /* Set promiscuous mode */ 2521 sk_setpromisc(sc_if); 2522 2523 /* Set multicast filter */ 2524 sk_setmulti(sc_if); 2525 2526 /* enable interrupt mask for counter overflows */ 2527 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2528 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2529 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2530 2531 /* Configure RX MAC FIFO */ 2532 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2533 SK_IF_WRITE_4(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON); 2534 2535 /* Configure TX MAC FIFO */ 2536 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2537 SK_IF_WRITE_4(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2538} 2539 2540/* 2541 * Note that to properly initialize any part of the GEnesis chip, 2542 * you first have to take it out of reset mode. 2543 */ 2544static void 2545sk_init(xsc) 2546 void *xsc; 2547{ 2548 struct sk_if_softc *sc_if = xsc; 2549 struct sk_softc *sc; 2550 struct ifnet *ifp; 2551 struct mii_data *mii; 2552 u_int16_t reg; 2553 2554 SK_IF_LOCK(sc_if); 2555 2556 ifp = &sc_if->arpcom.ac_if; 2557 sc = sc_if->sk_softc; 2558 mii = device_get_softc(sc_if->sk_miibus); 2559 2560 /* Cancel pending I/O and free all RX/TX buffers. */ 2561 sk_stop(sc_if); 2562 2563 if (sc->sk_type == SK_GENESIS) { 2564 /* Configure LINK_SYNC LED */ 2565 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON); 2566 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2567 SK_LINKLED_LINKSYNC_ON); 2568 2569 /* Configure RX LED */ 2570 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, 2571 SK_RXLEDCTL_COUNTER_START); 2572 2573 /* Configure TX LED */ 2574 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, 2575 SK_TXLEDCTL_COUNTER_START); 2576 } 2577 2578 /* Configure I2C registers */ 2579 2580 /* Configure XMAC(s) */ 2581 switch (sc->sk_type) { 2582 case SK_GENESIS: 2583 sk_init_xmac(sc_if); 2584 break; 2585 case SK_YUKON: 2586 sk_init_yukon(sc_if); 2587 break; 2588 } 2589 mii_mediachg(mii); 2590 2591 if (sc->sk_type == SK_GENESIS) { 2592 /* Configure MAC FIFOs */ 2593 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET); 2594 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END); 2595 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON); 2596 2597 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET); 2598 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END); 2599 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON); 2600 } 2601 2602 /* Configure transmit arbiter(s) */ 2603 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, 2604 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 2605 2606 /* Configure RAMbuffers */ 2607 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2608 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2609 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2610 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2611 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2612 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2613 2614 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET); 2615 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON); 2616 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart); 2617 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart); 2618 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart); 2619 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend); 2620 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON); 2621 2622 /* Configure BMUs */ 2623 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE); 2624 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 2625 vtophys(&sc_if->sk_rdata->sk_rx_ring[0])); 2626 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0); 2627 2628 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE); 2629 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO, 2630 vtophys(&sc_if->sk_rdata->sk_tx_ring[0])); 2631 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0); 2632 2633 /* Init descriptors */ 2634 if (sk_init_rx_ring(sc_if) == ENOBUFS) { 2635 printf("sk%d: initialization failed: no " 2636 "memory for rx buffers\n", sc_if->sk_unit); 2637 sk_stop(sc_if); 2638 SK_IF_UNLOCK(sc_if); 2639 return; 2640 } 2641 sk_init_tx_ring(sc_if); 2642 2643 /* Configure interrupt handling */ 2644 CSR_READ_4(sc, SK_ISSR); 2645 if (sc_if->sk_port == SK_PORT_A) 2646 sc->sk_intrmask |= SK_INTRS1; 2647 else 2648 sc->sk_intrmask |= SK_INTRS2; 2649 2650 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG; 2651 2652 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2653 2654 /* Start BMUs. */ 2655 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START); 2656 2657 switch(sc->sk_type) { 2658 case SK_GENESIS: 2659 /* Enable XMACs TX and RX state machines */ 2660 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE); 2661 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2662 break; 2663 case SK_YUKON: 2664 reg = SK_YU_READ_2(sc_if, YUKON_GPCR); 2665 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN; 2666 reg &= ~(YU_GPCR_SPEED_EN | YU_GPCR_DPLX_EN); 2667 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg); 2668 } 2669 2670 ifp->if_flags |= IFF_RUNNING; 2671 ifp->if_flags &= ~IFF_OACTIVE; 2672 2673 SK_IF_UNLOCK(sc_if); 2674 2675 return; 2676} 2677 2678static void 2679sk_stop(sc_if) 2680 struct sk_if_softc *sc_if; 2681{ 2682 int i; 2683 struct sk_softc *sc; 2684 struct ifnet *ifp; 2685 2686 SK_IF_LOCK(sc_if); 2687 sc = sc_if->sk_softc; 2688 ifp = &sc_if->arpcom.ac_if; 2689 2690 untimeout(sk_tick, sc_if, sc_if->sk_tick_ch); 2691 2692 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2693 u_int32_t val; 2694 2695 /* Put PHY back into reset. */ 2696 val = sk_win_read_4(sc, SK_GPIO); 2697 if (sc_if->sk_port == SK_PORT_A) { 2698 val |= SK_GPIO_DIR0; 2699 val &= ~SK_GPIO_DAT0; 2700 } else { 2701 val |= SK_GPIO_DIR2; 2702 val &= ~SK_GPIO_DAT2; 2703 } 2704 sk_win_write_4(sc, SK_GPIO, val); 2705 } 2706 2707 /* Turn off various components of this interface. */ 2708 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2709 switch (sc->sk_type) { 2710 case SK_GENESIS: 2711 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_RESET); 2712 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET); 2713 break; 2714 case SK_YUKON: 2715 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2716 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2717 break; 2718 } 2719 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2720 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2721 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE); 2722 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2723 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2724 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2725 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2726 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2727 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2728 2729 /* Disable interrupts */ 2730 if (sc_if->sk_port == SK_PORT_A) 2731 sc->sk_intrmask &= ~SK_INTRS1; 2732 else 2733 sc->sk_intrmask &= ~SK_INTRS2; 2734 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2735 2736 SK_XM_READ_2(sc_if, XM_ISR); 2737 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2738 2739 /* Free RX and TX mbufs still in the queues. */ 2740 for (i = 0; i < SK_RX_RING_CNT; i++) { 2741 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2742 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2743 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2744 } 2745 } 2746 2747 for (i = 0; i < SK_TX_RING_CNT; i++) { 2748 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2749 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2750 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2751 } 2752 } 2753 2754 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2755 SK_IF_UNLOCK(sc_if); 2756 return; 2757} 2758