if_sk.c revision 137756
1/* $OpenBSD: if_sk.c,v 2.33 2003/08/12 05:23:06 nate Exp $ */ 2 3/* 4 * Copyright (c) 1997, 1998, 1999, 2000 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34/* 35 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 36 * 37 * Permission to use, copy, modify, and distribute this software for any 38 * purpose with or without fee is hereby granted, provided that the above 39 * copyright notice and this permission notice appear in all copies. 40 * 41 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 42 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 43 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 44 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 45 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 46 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 47 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 48 */ 49 50#include <sys/cdefs.h> 51__FBSDID("$FreeBSD: head/sys/dev/sk/if_sk.c 137756 2004-11-15 22:24:32Z jmg $"); 52 53/* 54 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 55 * the SK-984x series adapters, both single port and dual port. 56 * References: 57 * The XaQti XMAC II datasheet, 58 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 59 * The SysKonnect GEnesis manual, http://www.syskonnect.com 60 * 61 * Note: XaQti has been aquired by Vitesse, and Vitesse does not have the 62 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 63 * convenience to others until Vitesse corrects this problem: 64 * 65 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 66 * 67 * Written by Bill Paul <wpaul@ee.columbia.edu> 68 * Department of Electrical Engineering 69 * Columbia University, New York City 70 */ 71/* 72 * The SysKonnect gigabit ethernet adapters consist of two main 73 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 74 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 75 * components and a PHY while the GEnesis controller provides a PCI 76 * interface with DMA support. Each card may have between 512K and 77 * 2MB of SRAM on board depending on the configuration. 78 * 79 * The SysKonnect GEnesis controller can have either one or two XMAC 80 * chips connected to it, allowing single or dual port NIC configurations. 81 * SysKonnect has the distinction of being the only vendor on the market 82 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 83 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 84 * XMAC registers. This driver takes advantage of these features to allow 85 * both XMACs to operate as independent interfaces. 86 */ 87 88#include <sys/param.h> 89#include <sys/systm.h> 90#include <sys/sockio.h> 91#include <sys/mbuf.h> 92#include <sys/malloc.h> 93#include <sys/kernel.h> 94#include <sys/module.h> 95#include <sys/socket.h> 96#include <sys/queue.h> 97 98#include <net/if.h> 99#include <net/if_arp.h> 100#include <net/ethernet.h> 101#include <net/if_dl.h> 102#include <net/if_media.h> 103 104#include <net/bpf.h> 105 106#include <vm/vm.h> /* for vtophys */ 107#include <vm/pmap.h> /* for vtophys */ 108#include <machine/bus_pio.h> 109#include <machine/bus_memio.h> 110#include <machine/bus.h> 111#include <machine/resource.h> 112#include <sys/bus.h> 113#include <sys/rman.h> 114 115#include <dev/mii/mii.h> 116#include <dev/mii/miivar.h> 117#include <dev/mii/brgphyreg.h> 118 119#include <dev/pci/pcireg.h> 120#include <dev/pci/pcivar.h> 121 122#if 0 123#define SK_USEIOSPACE 124#endif 125 126#include <pci/if_skreg.h> 127#include <pci/xmaciireg.h> 128#include <pci/yukonreg.h> 129 130MODULE_DEPEND(sk, pci, 1, 1, 1); 131MODULE_DEPEND(sk, ether, 1, 1, 1); 132MODULE_DEPEND(sk, miibus, 1, 1, 1); 133 134/* "controller miibus0" required. See GENERIC if you get errors here. */ 135#include "miibus_if.h" 136 137#ifndef lint 138static const char rcsid[] = 139 "$FreeBSD: head/sys/dev/sk/if_sk.c 137756 2004-11-15 22:24:32Z jmg $"; 140#endif 141 142static struct sk_type sk_devs[] = { 143 { 144 VENDORID_SK, 145 DEVICEID_SK_V1, 146 "SysKonnect Gigabit Ethernet (V1.0)" 147 }, 148 { 149 VENDORID_SK, 150 DEVICEID_SK_V2, 151 "SysKonnect Gigabit Ethernet (V2.0)" 152 }, 153 { 154 VENDORID_MARVELL, 155 DEVICEID_SK_V2, 156 "Marvell Gigabit Ethernet" 157 }, 158 { 159 VENDORID_MARVELL, 160 DEVICEID_BELKIN_5005, 161 "Belkin F5D5005 Gigabit Ethernet" 162 }, 163 { 164 VENDORID_3COM, 165 DEVICEID_3COM_3C940, 166 "3Com 3C940 Gigabit Ethernet" 167 }, 168 { 169 VENDORID_LINKSYS, 170 DEVICEID_LINKSYS_EG1032, 171 "Linksys EG1032 Gigabit Ethernet" 172 }, 173 { 174 VENDORID_DLINK, 175 DEVICEID_DLINK_DGE530T, 176 "D-Link DGE-530T Gigabit Ethernet" 177 }, 178 { 0, 0, NULL } 179}; 180 181static int skc_probe (device_t); 182static int skc_attach (device_t); 183static int skc_detach (device_t); 184static void skc_shutdown (device_t); 185static int sk_detach (device_t); 186static int sk_probe (device_t); 187static int sk_attach (device_t); 188static void sk_tick (void *); 189static void sk_intr (void *); 190static void sk_intr_xmac (struct sk_if_softc *); 191static void sk_intr_bcom (struct sk_if_softc *); 192static void sk_intr_yukon (struct sk_if_softc *); 193static void sk_rxeof (struct sk_if_softc *); 194static void sk_txeof (struct sk_if_softc *); 195static int sk_encap (struct sk_if_softc *, struct mbuf *, 196 u_int32_t *); 197static void sk_start (struct ifnet *); 198static int sk_ioctl (struct ifnet *, u_long, caddr_t); 199static void sk_init (void *); 200static void sk_init_xmac (struct sk_if_softc *); 201static void sk_init_yukon (struct sk_if_softc *); 202static void sk_stop (struct sk_if_softc *); 203static void sk_watchdog (struct ifnet *); 204static int sk_ifmedia_upd (struct ifnet *); 205static void sk_ifmedia_sts (struct ifnet *, struct ifmediareq *); 206static void sk_reset (struct sk_softc *); 207static int sk_newbuf (struct sk_if_softc *, 208 struct sk_chain *, struct mbuf *); 209static int sk_alloc_jumbo_mem (struct sk_if_softc *); 210static void *sk_jalloc (struct sk_if_softc *); 211static void sk_jfree (void *, void *); 212static int sk_init_rx_ring (struct sk_if_softc *); 213static void sk_init_tx_ring (struct sk_if_softc *); 214static u_int32_t sk_win_read_4 (struct sk_softc *, int); 215static u_int16_t sk_win_read_2 (struct sk_softc *, int); 216static u_int8_t sk_win_read_1 (struct sk_softc *, int); 217static void sk_win_write_4 (struct sk_softc *, int, u_int32_t); 218static void sk_win_write_2 (struct sk_softc *, int, u_int32_t); 219static void sk_win_write_1 (struct sk_softc *, int, u_int32_t); 220static u_int8_t sk_vpd_readbyte (struct sk_softc *, int); 221static void sk_vpd_read_res (struct sk_softc *, struct vpd_res *, int); 222static void sk_vpd_read (struct sk_softc *); 223 224static int sk_miibus_readreg (device_t, int, int); 225static int sk_miibus_writereg (device_t, int, int, int); 226static void sk_miibus_statchg (device_t); 227 228static int sk_xmac_miibus_readreg (struct sk_if_softc *, int, int); 229static int sk_xmac_miibus_writereg (struct sk_if_softc *, int, int, 230 int); 231static void sk_xmac_miibus_statchg (struct sk_if_softc *); 232 233static int sk_marv_miibus_readreg (struct sk_if_softc *, int, int); 234static int sk_marv_miibus_writereg (struct sk_if_softc *, int, int, 235 int); 236static void sk_marv_miibus_statchg (struct sk_if_softc *); 237 238static uint32_t sk_xmchash (const uint8_t *); 239static uint32_t sk_gmchash (const uint8_t *); 240static void sk_setfilt (struct sk_if_softc *, caddr_t, int); 241static void sk_setmulti (struct sk_if_softc *); 242static void sk_setpromisc (struct sk_if_softc *); 243 244#ifdef SK_USEIOSPACE 245#define SK_RES SYS_RES_IOPORT 246#define SK_RID SK_PCI_LOIO 247#else 248#define SK_RES SYS_RES_MEMORY 249#define SK_RID SK_PCI_LOMEM 250#endif 251 252/* 253 * Note that we have newbus methods for both the GEnesis controller 254 * itself and the XMAC(s). The XMACs are children of the GEnesis, and 255 * the miibus code is a child of the XMACs. We need to do it this way 256 * so that the miibus drivers can access the PHY registers on the 257 * right PHY. It's not quite what I had in mind, but it's the only 258 * design that achieves the desired effect. 259 */ 260static device_method_t skc_methods[] = { 261 /* Device interface */ 262 DEVMETHOD(device_probe, skc_probe), 263 DEVMETHOD(device_attach, skc_attach), 264 DEVMETHOD(device_detach, skc_detach), 265 DEVMETHOD(device_shutdown, skc_shutdown), 266 267 /* bus interface */ 268 DEVMETHOD(bus_print_child, bus_generic_print_child), 269 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 270 271 { 0, 0 } 272}; 273 274static driver_t skc_driver = { 275 "skc", 276 skc_methods, 277 sizeof(struct sk_softc) 278}; 279 280static devclass_t skc_devclass; 281 282static device_method_t sk_methods[] = { 283 /* Device interface */ 284 DEVMETHOD(device_probe, sk_probe), 285 DEVMETHOD(device_attach, sk_attach), 286 DEVMETHOD(device_detach, sk_detach), 287 DEVMETHOD(device_shutdown, bus_generic_shutdown), 288 289 /* bus interface */ 290 DEVMETHOD(bus_print_child, bus_generic_print_child), 291 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 292 293 /* MII interface */ 294 DEVMETHOD(miibus_readreg, sk_miibus_readreg), 295 DEVMETHOD(miibus_writereg, sk_miibus_writereg), 296 DEVMETHOD(miibus_statchg, sk_miibus_statchg), 297 298 { 0, 0 } 299}; 300 301static driver_t sk_driver = { 302 "sk", 303 sk_methods, 304 sizeof(struct sk_if_softc) 305}; 306 307static devclass_t sk_devclass; 308 309DRIVER_MODULE(sk, pci, skc_driver, skc_devclass, 0, 0); 310DRIVER_MODULE(sk, skc, sk_driver, sk_devclass, 0, 0); 311DRIVER_MODULE(miibus, sk, miibus_driver, miibus_devclass, 0, 0); 312 313#define SK_SETBIT(sc, reg, x) \ 314 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 315 316#define SK_CLRBIT(sc, reg, x) \ 317 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 318 319#define SK_WIN_SETBIT_4(sc, reg, x) \ 320 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) | x) 321 322#define SK_WIN_CLRBIT_4(sc, reg, x) \ 323 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) & ~x) 324 325#define SK_WIN_SETBIT_2(sc, reg, x) \ 326 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) | x) 327 328#define SK_WIN_CLRBIT_2(sc, reg, x) \ 329 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) & ~x) 330 331static u_int32_t 332sk_win_read_4(sc, reg) 333 struct sk_softc *sc; 334 int reg; 335{ 336#ifdef SK_USEIOSPACE 337 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 338 return(CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg))); 339#else 340 return(CSR_READ_4(sc, reg)); 341#endif 342} 343 344static u_int16_t 345sk_win_read_2(sc, reg) 346 struct sk_softc *sc; 347 int reg; 348{ 349#ifdef SK_USEIOSPACE 350 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 351 return(CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg))); 352#else 353 return(CSR_READ_2(sc, reg)); 354#endif 355} 356 357static u_int8_t 358sk_win_read_1(sc, reg) 359 struct sk_softc *sc; 360 int reg; 361{ 362#ifdef SK_USEIOSPACE 363 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 364 return(CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg))); 365#else 366 return(CSR_READ_1(sc, reg)); 367#endif 368} 369 370static void 371sk_win_write_4(sc, reg, val) 372 struct sk_softc *sc; 373 int reg; 374 u_int32_t val; 375{ 376#ifdef SK_USEIOSPACE 377 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 378 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), val); 379#else 380 CSR_WRITE_4(sc, reg, val); 381#endif 382 return; 383} 384 385static void 386sk_win_write_2(sc, reg, val) 387 struct sk_softc *sc; 388 int reg; 389 u_int32_t val; 390{ 391#ifdef SK_USEIOSPACE 392 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 393 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), val); 394#else 395 CSR_WRITE_2(sc, reg, val); 396#endif 397 return; 398} 399 400static void 401sk_win_write_1(sc, reg, val) 402 struct sk_softc *sc; 403 int reg; 404 u_int32_t val; 405{ 406#ifdef SK_USEIOSPACE 407 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 408 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), val); 409#else 410 CSR_WRITE_1(sc, reg, val); 411#endif 412 return; 413} 414 415/* 416 * The VPD EEPROM contains Vital Product Data, as suggested in 417 * the PCI 2.1 specification. The VPD data is separared into areas 418 * denoted by resource IDs. The SysKonnect VPD contains an ID string 419 * resource (the name of the adapter), a read-only area resource 420 * containing various key/data fields and a read/write area which 421 * can be used to store asset management information or log messages. 422 * We read the ID string and read-only into buffers attached to 423 * the controller softc structure for later use. At the moment, 424 * we only use the ID string during skc_attach(). 425 */ 426static u_int8_t 427sk_vpd_readbyte(sc, addr) 428 struct sk_softc *sc; 429 int addr; 430{ 431 int i; 432 433 sk_win_write_2(sc, SK_PCI_REG(SK_PCI_VPD_ADDR), addr); 434 for (i = 0; i < SK_TIMEOUT; i++) { 435 DELAY(1); 436 if (sk_win_read_2(sc, 437 SK_PCI_REG(SK_PCI_VPD_ADDR)) & SK_VPD_FLAG) 438 break; 439 } 440 441 if (i == SK_TIMEOUT) 442 return(0); 443 444 return(sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_DATA))); 445} 446 447static void 448sk_vpd_read_res(sc, res, addr) 449 struct sk_softc *sc; 450 struct vpd_res *res; 451 int addr; 452{ 453 int i; 454 u_int8_t *ptr; 455 456 ptr = (u_int8_t *)res; 457 for (i = 0; i < sizeof(struct vpd_res); i++) 458 ptr[i] = sk_vpd_readbyte(sc, i + addr); 459 460 return; 461} 462 463static void 464sk_vpd_read(sc) 465 struct sk_softc *sc; 466{ 467 int pos = 0, i; 468 struct vpd_res res; 469 470 if (sc->sk_vpd_prodname != NULL) 471 free(sc->sk_vpd_prodname, M_DEVBUF); 472 if (sc->sk_vpd_readonly != NULL) 473 free(sc->sk_vpd_readonly, M_DEVBUF); 474 sc->sk_vpd_prodname = NULL; 475 sc->sk_vpd_readonly = NULL; 476 sc->sk_vpd_readonly_len = 0; 477 478 sk_vpd_read_res(sc, &res, pos); 479 480 /* 481 * Bail out quietly if the eeprom appears to be missing or empty. 482 */ 483 if (res.vr_id == 0xff && res.vr_len == 0xff && res.vr_pad == 0xff) 484 return; 485 486 if (res.vr_id != VPD_RES_ID) { 487 printf("skc%d: bad VPD resource id: expected %x got %x\n", 488 sc->sk_unit, VPD_RES_ID, res.vr_id); 489 return; 490 } 491 492 pos += sizeof(res); 493 sc->sk_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 494 for (i = 0; i < res.vr_len; i++) 495 sc->sk_vpd_prodname[i] = sk_vpd_readbyte(sc, i + pos); 496 sc->sk_vpd_prodname[i] = '\0'; 497 pos += i; 498 499 sk_vpd_read_res(sc, &res, pos); 500 501 if (res.vr_id != VPD_RES_READ) { 502 printf("skc%d: bad VPD resource id: expected %x got %x\n", 503 sc->sk_unit, VPD_RES_READ, res.vr_id); 504 return; 505 } 506 507 pos += sizeof(res); 508 sc->sk_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 509 for (i = 0; i < res.vr_len; i++) 510 sc->sk_vpd_readonly[i] = sk_vpd_readbyte(sc, i + pos); 511 sc->sk_vpd_readonly_len = res.vr_len; 512 513 return; 514} 515 516static int 517sk_miibus_readreg(dev, phy, reg) 518 device_t dev; 519 int phy, reg; 520{ 521 struct sk_if_softc *sc_if; 522 523 sc_if = device_get_softc(dev); 524 525 switch(sc_if->sk_softc->sk_type) { 526 case SK_GENESIS: 527 return(sk_xmac_miibus_readreg(sc_if, phy, reg)); 528 case SK_YUKON: 529 return(sk_marv_miibus_readreg(sc_if, phy, reg)); 530 } 531 532 return(0); 533} 534 535static int 536sk_miibus_writereg(dev, phy, reg, val) 537 device_t dev; 538 int phy, reg, val; 539{ 540 struct sk_if_softc *sc_if; 541 542 sc_if = device_get_softc(dev); 543 544 switch(sc_if->sk_softc->sk_type) { 545 case SK_GENESIS: 546 return(sk_xmac_miibus_writereg(sc_if, phy, reg, val)); 547 case SK_YUKON: 548 return(sk_marv_miibus_writereg(sc_if, phy, reg, val)); 549 } 550 551 return(0); 552} 553 554static void 555sk_miibus_statchg(dev) 556 device_t dev; 557{ 558 struct sk_if_softc *sc_if; 559 560 sc_if = device_get_softc(dev); 561 562 switch(sc_if->sk_softc->sk_type) { 563 case SK_GENESIS: 564 sk_xmac_miibus_statchg(sc_if); 565 break; 566 case SK_YUKON: 567 sk_marv_miibus_statchg(sc_if); 568 break; 569 } 570 571 return; 572} 573 574static int 575sk_xmac_miibus_readreg(sc_if, phy, reg) 576 struct sk_if_softc *sc_if; 577 int phy, reg; 578{ 579 int i; 580 581 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0) 582 return(0); 583 584 SK_IF_LOCK(sc_if); 585 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 586 SK_XM_READ_2(sc_if, XM_PHY_DATA); 587 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 588 for (i = 0; i < SK_TIMEOUT; i++) { 589 DELAY(1); 590 if (SK_XM_READ_2(sc_if, XM_MMUCMD) & 591 XM_MMUCMD_PHYDATARDY) 592 break; 593 } 594 595 if (i == SK_TIMEOUT) { 596 printf("sk%d: phy failed to come ready\n", 597 sc_if->sk_unit); 598 SK_IF_UNLOCK(sc_if); 599 return(0); 600 } 601 } 602 DELAY(1); 603 i = SK_XM_READ_2(sc_if, XM_PHY_DATA); 604 SK_IF_UNLOCK(sc_if); 605 return(i); 606} 607 608static int 609sk_xmac_miibus_writereg(sc_if, phy, reg, val) 610 struct sk_if_softc *sc_if; 611 int phy, reg, val; 612{ 613 int i; 614 615 SK_IF_LOCK(sc_if); 616 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 617 for (i = 0; i < SK_TIMEOUT; i++) { 618 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 619 break; 620 } 621 622 if (i == SK_TIMEOUT) { 623 printf("sk%d: phy failed to come ready\n", sc_if->sk_unit); 624 SK_IF_UNLOCK(sc_if); 625 return(ETIMEDOUT); 626 } 627 628 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val); 629 for (i = 0; i < SK_TIMEOUT; i++) { 630 DELAY(1); 631 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 632 break; 633 } 634 SK_IF_UNLOCK(sc_if); 635 if (i == SK_TIMEOUT) 636 printf("sk%d: phy write timed out\n", sc_if->sk_unit); 637 638 return(0); 639} 640 641static void 642sk_xmac_miibus_statchg(sc_if) 643 struct sk_if_softc *sc_if; 644{ 645 struct mii_data *mii; 646 647 mii = device_get_softc(sc_if->sk_miibus); 648 649 SK_IF_LOCK(sc_if); 650 /* 651 * If this is a GMII PHY, manually set the XMAC's 652 * duplex mode accordingly. 653 */ 654 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 655 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 656 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 657 } else { 658 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 659 } 660 } 661 SK_IF_UNLOCK(sc_if); 662 663 return; 664} 665 666static int 667sk_marv_miibus_readreg(sc_if, phy, reg) 668 struct sk_if_softc *sc_if; 669 int phy, reg; 670{ 671 u_int16_t val; 672 int i; 673 674 if (phy != 0 || 675 (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER && 676 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) { 677 return(0); 678 } 679 680 SK_IF_LOCK(sc_if); 681 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 682 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 683 684 for (i = 0; i < SK_TIMEOUT; i++) { 685 DELAY(1); 686 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 687 if (val & YU_SMICR_READ_VALID) 688 break; 689 } 690 691 if (i == SK_TIMEOUT) { 692 printf("sk%d: phy failed to come ready\n", 693 sc_if->sk_unit); 694 SK_IF_UNLOCK(sc_if); 695 return(0); 696 } 697 698 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 699 SK_IF_UNLOCK(sc_if); 700 701 return(val); 702} 703 704static int 705sk_marv_miibus_writereg(sc_if, phy, reg, val) 706 struct sk_if_softc *sc_if; 707 int phy, reg, val; 708{ 709 int i; 710 711 SK_IF_LOCK(sc_if); 712 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 713 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 714 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 715 716 for (i = 0; i < SK_TIMEOUT; i++) { 717 DELAY(1); 718 if (SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY) 719 break; 720 } 721 SK_IF_UNLOCK(sc_if); 722 723 return(0); 724} 725 726static void 727sk_marv_miibus_statchg(sc_if) 728 struct sk_if_softc *sc_if; 729{ 730 return; 731} 732 733#define HASH_BITS 6 734 735static u_int32_t 736sk_xmchash(addr) 737 const uint8_t *addr; 738{ 739 uint32_t crc; 740 741 /* Compute CRC for the address value. */ 742 crc = ether_crc32_le(addr, ETHER_ADDR_LEN); 743 744 return (~crc & ((1 << HASH_BITS) - 1)); 745} 746 747/* gmchash is just a big endian crc */ 748static u_int32_t 749sk_gmchash(addr) 750 const uint8_t *addr; 751{ 752 uint32_t crc; 753 754 /* Compute CRC for the address value. */ 755 crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 756 757 return (crc & ((1 << HASH_BITS) - 1)); 758} 759 760static void 761sk_setfilt(sc_if, addr, slot) 762 struct sk_if_softc *sc_if; 763 caddr_t addr; 764 int slot; 765{ 766 int base; 767 768 base = XM_RXFILT_ENTRY(slot); 769 770 SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0])); 771 SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2])); 772 SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4])); 773 774 return; 775} 776 777static void 778sk_setmulti(sc_if) 779 struct sk_if_softc *sc_if; 780{ 781 struct sk_softc *sc = sc_if->sk_softc; 782 struct ifnet *ifp = &sc_if->arpcom.ac_if; 783 u_int32_t hashes[2] = { 0, 0 }; 784 int h = 0, i; 785 struct ifmultiaddr *ifma; 786 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 787 788 789 /* First, zot all the existing filters. */ 790 switch(sc->sk_type) { 791 case SK_GENESIS: 792 for (i = 1; i < XM_RXFILT_MAX; i++) 793 sk_setfilt(sc_if, (caddr_t)&dummy, i); 794 795 SK_XM_WRITE_4(sc_if, XM_MAR0, 0); 796 SK_XM_WRITE_4(sc_if, XM_MAR2, 0); 797 break; 798 case SK_YUKON: 799 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 800 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 801 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 802 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 803 break; 804 } 805 806 /* Now program new ones. */ 807 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 808 hashes[0] = 0xFFFFFFFF; 809 hashes[1] = 0xFFFFFFFF; 810 } else { 811 i = 1; 812 TAILQ_FOREACH_REVERSE(ifma, &ifp->if_multiaddrs, ifmultihead, ifma_link) { 813 if (ifma->ifma_addr->sa_family != AF_LINK) 814 continue; 815 /* 816 * Program the first XM_RXFILT_MAX multicast groups 817 * into the perfect filter. For all others, 818 * use the hash table. 819 */ 820 if (sc->sk_type == SK_GENESIS && i < XM_RXFILT_MAX) { 821 sk_setfilt(sc_if, 822 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i); 823 i++; 824 continue; 825 } 826 827 switch(sc->sk_type) { 828 case SK_GENESIS: 829 h = sk_xmchash( 830 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 831 break; 832 case SK_YUKON: 833 h = sk_gmchash( 834 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 835 break; 836 } 837 if (h < 32) 838 hashes[0] |= (1 << h); 839 else 840 hashes[1] |= (1 << (h - 32)); 841 } 842 } 843 844 switch(sc->sk_type) { 845 case SK_GENESIS: 846 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH| 847 XM_MODE_RX_USE_PERFECT); 848 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]); 849 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]); 850 break; 851 case SK_YUKON: 852 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 853 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 854 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 855 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 856 break; 857 } 858 859 return; 860} 861 862static void 863sk_setpromisc(sc_if) 864 struct sk_if_softc *sc_if; 865{ 866 struct sk_softc *sc = sc_if->sk_softc; 867 struct ifnet *ifp = &sc_if->arpcom.ac_if; 868 869 switch(sc->sk_type) { 870 case SK_GENESIS: 871 if (ifp->if_flags & IFF_PROMISC) { 872 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 873 } else { 874 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 875 } 876 break; 877 case SK_YUKON: 878 if (ifp->if_flags & IFF_PROMISC) { 879 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 880 YU_RCR_UFLEN | YU_RCR_MUFLEN); 881 } else { 882 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 883 YU_RCR_UFLEN | YU_RCR_MUFLEN); 884 } 885 break; 886 } 887 888 return; 889} 890 891static int 892sk_init_rx_ring(sc_if) 893 struct sk_if_softc *sc_if; 894{ 895 struct sk_chain_data *cd = &sc_if->sk_cdata; 896 struct sk_ring_data *rd = sc_if->sk_rdata; 897 int i; 898 899 bzero((char *)rd->sk_rx_ring, 900 sizeof(struct sk_rx_desc) * SK_RX_RING_CNT); 901 902 for (i = 0; i < SK_RX_RING_CNT; i++) { 903 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i]; 904 if (sk_newbuf(sc_if, &cd->sk_rx_chain[i], NULL) == ENOBUFS) 905 return(ENOBUFS); 906 if (i == (SK_RX_RING_CNT - 1)) { 907 cd->sk_rx_chain[i].sk_next = 908 &cd->sk_rx_chain[0]; 909 rd->sk_rx_ring[i].sk_next = 910 vtophys(&rd->sk_rx_ring[0]); 911 } else { 912 cd->sk_rx_chain[i].sk_next = 913 &cd->sk_rx_chain[i + 1]; 914 rd->sk_rx_ring[i].sk_next = 915 vtophys(&rd->sk_rx_ring[i + 1]); 916 } 917 } 918 919 sc_if->sk_cdata.sk_rx_prod = 0; 920 sc_if->sk_cdata.sk_rx_cons = 0; 921 922 return(0); 923} 924 925static void 926sk_init_tx_ring(sc_if) 927 struct sk_if_softc *sc_if; 928{ 929 struct sk_chain_data *cd = &sc_if->sk_cdata; 930 struct sk_ring_data *rd = sc_if->sk_rdata; 931 int i; 932 933 bzero((char *)sc_if->sk_rdata->sk_tx_ring, 934 sizeof(struct sk_tx_desc) * SK_TX_RING_CNT); 935 936 for (i = 0; i < SK_TX_RING_CNT; i++) { 937 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i]; 938 if (i == (SK_TX_RING_CNT - 1)) { 939 cd->sk_tx_chain[i].sk_next = 940 &cd->sk_tx_chain[0]; 941 rd->sk_tx_ring[i].sk_next = 942 vtophys(&rd->sk_tx_ring[0]); 943 } else { 944 cd->sk_tx_chain[i].sk_next = 945 &cd->sk_tx_chain[i + 1]; 946 rd->sk_tx_ring[i].sk_next = 947 vtophys(&rd->sk_tx_ring[i + 1]); 948 } 949 } 950 951 sc_if->sk_cdata.sk_tx_prod = 0; 952 sc_if->sk_cdata.sk_tx_cons = 0; 953 sc_if->sk_cdata.sk_tx_cnt = 0; 954 955 return; 956} 957 958static int 959sk_newbuf(sc_if, c, m) 960 struct sk_if_softc *sc_if; 961 struct sk_chain *c; 962 struct mbuf *m; 963{ 964 struct mbuf *m_new = NULL; 965 struct sk_rx_desc *r; 966 967 if (m == NULL) { 968 caddr_t *buf = NULL; 969 970 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 971 if (m_new == NULL) 972 return(ENOBUFS); 973 974 /* Allocate the jumbo buffer */ 975 buf = sk_jalloc(sc_if); 976 if (buf == NULL) { 977 m_freem(m_new); 978#ifdef SK_VERBOSE 979 printf("sk%d: jumbo allocation failed " 980 "-- packet dropped!\n", sc_if->sk_unit); 981#endif 982 return(ENOBUFS); 983 } 984 985 /* Attach the buffer to the mbuf */ 986 MEXTADD(m_new, buf, SK_JLEN, sk_jfree, 987 (struct sk_if_softc *)sc_if, 0, EXT_NET_DRV); 988 m_new->m_data = (void *)buf; 989 m_new->m_pkthdr.len = m_new->m_len = SK_JLEN; 990 } else { 991 /* 992 * We're re-using a previously allocated mbuf; 993 * be sure to re-init pointers and lengths to 994 * default values. 995 */ 996 m_new = m; 997 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 998 m_new->m_data = m_new->m_ext.ext_buf; 999 } 1000 1001 /* 1002 * Adjust alignment so packet payload begins on a 1003 * longword boundary. Mandatory for Alpha, useful on 1004 * x86 too. 1005 */ 1006 m_adj(m_new, ETHER_ALIGN); 1007 1008 r = c->sk_desc; 1009 c->sk_mbuf = m_new; 1010 r->sk_data_lo = vtophys(mtod(m_new, caddr_t)); 1011 r->sk_ctl = m_new->m_len | SK_RXSTAT; 1012 1013 return(0); 1014} 1015 1016/* 1017 * Allocate jumbo buffer storage. The SysKonnect adapters support 1018 * "jumbograms" (9K frames), although SysKonnect doesn't currently 1019 * use them in their drivers. In order for us to use them, we need 1020 * large 9K receive buffers, however standard mbuf clusters are only 1021 * 2048 bytes in size. Consequently, we need to allocate and manage 1022 * our own jumbo buffer pool. Fortunately, this does not require an 1023 * excessive amount of additional code. 1024 */ 1025static int 1026sk_alloc_jumbo_mem(sc_if) 1027 struct sk_if_softc *sc_if; 1028{ 1029 caddr_t ptr; 1030 register int i; 1031 struct sk_jpool_entry *entry; 1032 1033 /* Grab a big chunk o' storage. */ 1034 sc_if->sk_cdata.sk_jumbo_buf = contigmalloc(SK_JMEM, M_DEVBUF, 1035 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1036 1037 if (sc_if->sk_cdata.sk_jumbo_buf == NULL) { 1038 printf("sk%d: no memory for jumbo buffers!\n", sc_if->sk_unit); 1039 return(ENOBUFS); 1040 } 1041 1042 SLIST_INIT(&sc_if->sk_jfree_listhead); 1043 SLIST_INIT(&sc_if->sk_jinuse_listhead); 1044 1045 /* 1046 * Now divide it up into 9K pieces and save the addresses 1047 * in an array. 1048 */ 1049 ptr = sc_if->sk_cdata.sk_jumbo_buf; 1050 for (i = 0; i < SK_JSLOTS; i++) { 1051 sc_if->sk_cdata.sk_jslots[i] = ptr; 1052 ptr += SK_JLEN; 1053 entry = malloc(sizeof(struct sk_jpool_entry), 1054 M_DEVBUF, M_NOWAIT); 1055 if (entry == NULL) { 1056 free(sc_if->sk_cdata.sk_jumbo_buf, M_DEVBUF); 1057 sc_if->sk_cdata.sk_jumbo_buf = NULL; 1058 printf("sk%d: no memory for jumbo " 1059 "buffer queue!\n", sc_if->sk_unit); 1060 return(ENOBUFS); 1061 } 1062 entry->slot = i; 1063 SLIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 1064 entry, jpool_entries); 1065 } 1066 1067 return(0); 1068} 1069 1070/* 1071 * Allocate a jumbo buffer. 1072 */ 1073static void * 1074sk_jalloc(sc_if) 1075 struct sk_if_softc *sc_if; 1076{ 1077 struct sk_jpool_entry *entry; 1078 1079 SK_IF_LOCK_ASSERT(sc_if); 1080 1081 entry = SLIST_FIRST(&sc_if->sk_jfree_listhead); 1082 1083 if (entry == NULL) { 1084#ifdef SK_VERBOSE 1085 printf("sk%d: no free jumbo buffers\n", sc_if->sk_unit); 1086#endif 1087 return(NULL); 1088 } 1089 1090 SLIST_REMOVE_HEAD(&sc_if->sk_jfree_listhead, jpool_entries); 1091 SLIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 1092 return(sc_if->sk_cdata.sk_jslots[entry->slot]); 1093} 1094 1095/* 1096 * Release a jumbo buffer. 1097 */ 1098static void 1099sk_jfree(buf, args) 1100 void *buf; 1101 void *args; 1102{ 1103 struct sk_if_softc *sc_if; 1104 int i; 1105 struct sk_jpool_entry *entry; 1106 1107 /* Extract the softc struct pointer. */ 1108 sc_if = (struct sk_if_softc *)args; 1109 if (sc_if == NULL) 1110 panic("sk_jfree: didn't get softc pointer!"); 1111 1112 SK_IF_LOCK(sc_if); 1113 1114 /* calculate the slot this buffer belongs to */ 1115 i = ((vm_offset_t)buf 1116 - (vm_offset_t)sc_if->sk_cdata.sk_jumbo_buf) / SK_JLEN; 1117 1118 if ((i < 0) || (i >= SK_JSLOTS)) 1119 panic("sk_jfree: asked to free buffer that we don't manage!"); 1120 1121 entry = SLIST_FIRST(&sc_if->sk_jinuse_listhead); 1122 if (entry == NULL) 1123 panic("sk_jfree: buffer not in use!"); 1124 entry->slot = i; 1125 SLIST_REMOVE_HEAD(&sc_if->sk_jinuse_listhead, jpool_entries); 1126 SLIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, entry, jpool_entries); 1127 1128 SK_IF_UNLOCK(sc_if); 1129 return; 1130} 1131 1132/* 1133 * Set media options. 1134 */ 1135static int 1136sk_ifmedia_upd(ifp) 1137 struct ifnet *ifp; 1138{ 1139 struct sk_if_softc *sc_if = ifp->if_softc; 1140 struct mii_data *mii; 1141 1142 mii = device_get_softc(sc_if->sk_miibus); 1143 sk_init(sc_if); 1144 mii_mediachg(mii); 1145 1146 return(0); 1147} 1148 1149/* 1150 * Report current media status. 1151 */ 1152static void 1153sk_ifmedia_sts(ifp, ifmr) 1154 struct ifnet *ifp; 1155 struct ifmediareq *ifmr; 1156{ 1157 struct sk_if_softc *sc_if; 1158 struct mii_data *mii; 1159 1160 sc_if = ifp->if_softc; 1161 mii = device_get_softc(sc_if->sk_miibus); 1162 1163 mii_pollstat(mii); 1164 ifmr->ifm_active = mii->mii_media_active; 1165 ifmr->ifm_status = mii->mii_media_status; 1166 1167 return; 1168} 1169 1170static int 1171sk_ioctl(ifp, command, data) 1172 struct ifnet *ifp; 1173 u_long command; 1174 caddr_t data; 1175{ 1176 struct sk_if_softc *sc_if = ifp->if_softc; 1177 struct ifreq *ifr = (struct ifreq *) data; 1178 int error = 0; 1179 struct mii_data *mii; 1180 1181 SK_IF_LOCK(sc_if); 1182 1183 switch(command) { 1184 case SIOCSIFMTU: 1185 if (ifr->ifr_mtu > SK_JUMBO_MTU) 1186 error = EINVAL; 1187 else { 1188 ifp->if_mtu = ifr->ifr_mtu; 1189 sk_init(sc_if); 1190 } 1191 break; 1192 case SIOCSIFFLAGS: 1193 if (ifp->if_flags & IFF_UP) { 1194 if (ifp->if_flags & IFF_RUNNING) { 1195 if ((ifp->if_flags ^ sc_if->sk_if_flags) 1196 & IFF_PROMISC) { 1197 sk_setpromisc(sc_if); 1198 sk_setmulti(sc_if); 1199 } 1200 } else 1201 sk_init(sc_if); 1202 } else { 1203 if (ifp->if_flags & IFF_RUNNING) 1204 sk_stop(sc_if); 1205 } 1206 sc_if->sk_if_flags = ifp->if_flags; 1207 error = 0; 1208 break; 1209 case SIOCADDMULTI: 1210 case SIOCDELMULTI: 1211 sk_setmulti(sc_if); 1212 error = 0; 1213 break; 1214 case SIOCGIFMEDIA: 1215 case SIOCSIFMEDIA: 1216 mii = device_get_softc(sc_if->sk_miibus); 1217 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1218 break; 1219 default: 1220 error = ether_ioctl(ifp, command, data); 1221 break; 1222 } 1223 1224 SK_IF_UNLOCK(sc_if); 1225 1226 return(error); 1227} 1228 1229/* 1230 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device 1231 * IDs against our list and return a device name if we find a match. 1232 */ 1233static int 1234skc_probe(dev) 1235 device_t dev; 1236{ 1237 struct sk_softc *sc; 1238 struct sk_type *t = sk_devs; 1239 1240 sc = device_get_softc(dev); 1241 1242 while(t->sk_name != NULL) { 1243 if ((pci_get_vendor(dev) == t->sk_vid) && 1244 (pci_get_device(dev) == t->sk_did)) { 1245 device_set_desc(dev, t->sk_name); 1246 return(0); 1247 } 1248 t++; 1249 } 1250 1251 return(ENXIO); 1252} 1253 1254/* 1255 * Force the GEnesis into reset, then bring it out of reset. 1256 */ 1257static void 1258sk_reset(sc) 1259 struct sk_softc *sc; 1260{ 1261 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET); 1262 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET); 1263 if (sc->sk_type == SK_YUKON) 1264 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 1265 1266 DELAY(1000); 1267 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET); 1268 DELAY(2); 1269 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 1270 if (sc->sk_type == SK_YUKON) 1271 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 1272 1273 if (sc->sk_type == SK_GENESIS) { 1274 /* Configure packet arbiter */ 1275 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET); 1276 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT); 1277 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT); 1278 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT); 1279 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT); 1280 } 1281 1282 /* Enable RAM interface */ 1283 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 1284 1285 /* 1286 * Configure interrupt moderation. The moderation timer 1287 * defers interrupts specified in the interrupt moderation 1288 * timer mask based on the timeout specified in the interrupt 1289 * moderation timer init register. Each bit in the timer 1290 * register represents 18.825ns, so to specify a timeout in 1291 * microseconds, we have to multiply by 54. 1292 */ 1293 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(200)); 1294 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 1295 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 1296 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 1297 1298 return; 1299} 1300 1301static int 1302sk_probe(dev) 1303 device_t dev; 1304{ 1305 struct sk_softc *sc; 1306 1307 sc = device_get_softc(device_get_parent(dev)); 1308 1309 /* 1310 * Not much to do here. We always know there will be 1311 * at least one XMAC present, and if there are two, 1312 * skc_attach() will create a second device instance 1313 * for us. 1314 */ 1315 switch (sc->sk_type) { 1316 case SK_GENESIS: 1317 device_set_desc(dev, "XaQti Corp. XMAC II"); 1318 break; 1319 case SK_YUKON: 1320 device_set_desc(dev, "Marvell Semiconductor, Inc. Yukon"); 1321 break; 1322 } 1323 1324 return(0); 1325} 1326 1327/* 1328 * Each XMAC chip is attached as a separate logical IP interface. 1329 * Single port cards will have only one logical interface of course. 1330 */ 1331static int 1332sk_attach(dev) 1333 device_t dev; 1334{ 1335 struct sk_softc *sc; 1336 struct sk_if_softc *sc_if; 1337 struct ifnet *ifp; 1338 int i, port, error; 1339 1340 if (dev == NULL) 1341 return(EINVAL); 1342 1343 error = 0; 1344 sc_if = device_get_softc(dev); 1345 sc = device_get_softc(device_get_parent(dev)); 1346 port = *(int *)device_get_ivars(dev); 1347 free(device_get_ivars(dev), M_DEVBUF); 1348 device_set_ivars(dev, NULL); 1349 1350 sc_if->sk_dev = dev; 1351 sc_if->sk_unit = device_get_unit(dev); 1352 sc_if->sk_port = port; 1353 sc_if->sk_softc = sc; 1354 sc->sk_if[port] = sc_if; 1355 if (port == SK_PORT_A) 1356 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0; 1357 if (port == SK_PORT_B) 1358 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1; 1359 1360 /* Allocate the descriptor queues. */ 1361 sc_if->sk_rdata = contigmalloc(sizeof(struct sk_ring_data), M_DEVBUF, 1362 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1363 1364 if (sc_if->sk_rdata == NULL) { 1365 printf("sk%d: no memory for list buffers!\n", sc_if->sk_unit); 1366 error = ENOMEM; 1367 goto fail; 1368 } 1369 1370 bzero(sc_if->sk_rdata, sizeof(struct sk_ring_data)); 1371 1372 /* Try to allocate memory for jumbo buffers. */ 1373 if (sk_alloc_jumbo_mem(sc_if)) { 1374 printf("sk%d: jumbo buffer allocation failed\n", 1375 sc_if->sk_unit); 1376 error = ENOMEM; 1377 goto fail; 1378 } 1379 1380 ifp = &sc_if->arpcom.ac_if; 1381 ifp->if_softc = sc_if; 1382 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1383 ifp->if_mtu = ETHERMTU; 1384 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1385 ifp->if_ioctl = sk_ioctl; 1386 ifp->if_start = sk_start; 1387 ifp->if_watchdog = sk_watchdog; 1388 ifp->if_init = sk_init; 1389 ifp->if_baudrate = 1000000000; 1390 ifp->if_snd.ifq_maxlen = SK_TX_RING_CNT - 1; 1391 1392 callout_handle_init(&sc_if->sk_tick_ch); 1393 1394 /* 1395 * Get station address for this interface. Note that 1396 * dual port cards actually come with three station 1397 * addresses: one for each port, plus an extra. The 1398 * extra one is used by the SysKonnect driver software 1399 * as a 'virtual' station address for when both ports 1400 * are operating in failover mode. Currently we don't 1401 * use this extra address. 1402 */ 1403 SK_LOCK(sc); 1404 for (i = 0; i < ETHER_ADDR_LEN; i++) 1405 sc_if->arpcom.ac_enaddr[i] = 1406 sk_win_read_1(sc, SK_MAC0_0 + (port * 8) + i); 1407 1408 /* 1409 * Set up RAM buffer addresses. The NIC will have a certain 1410 * amount of SRAM on it, somewhere between 512K and 2MB. We 1411 * need to divide this up a) between the transmitter and 1412 * receiver and b) between the two XMACs, if this is a 1413 * dual port NIC. Our algotithm is to divide up the memory 1414 * evenly so that everyone gets a fair share. 1415 */ 1416 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) { 1417 u_int32_t chunk, val; 1418 1419 chunk = sc->sk_ramsize / 2; 1420 val = sc->sk_rboff / sizeof(u_int64_t); 1421 sc_if->sk_rx_ramstart = val; 1422 val += (chunk / sizeof(u_int64_t)); 1423 sc_if->sk_rx_ramend = val - 1; 1424 sc_if->sk_tx_ramstart = val; 1425 val += (chunk / sizeof(u_int64_t)); 1426 sc_if->sk_tx_ramend = val - 1; 1427 } else { 1428 u_int32_t chunk, val; 1429 1430 chunk = sc->sk_ramsize / 4; 1431 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) / 1432 sizeof(u_int64_t); 1433 sc_if->sk_rx_ramstart = val; 1434 val += (chunk / sizeof(u_int64_t)); 1435 sc_if->sk_rx_ramend = val - 1; 1436 sc_if->sk_tx_ramstart = val; 1437 val += (chunk / sizeof(u_int64_t)); 1438 sc_if->sk_tx_ramend = val - 1; 1439 } 1440 1441 /* Read and save PHY type and set PHY address */ 1442 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 1443 switch(sc_if->sk_phytype) { 1444 case SK_PHYTYPE_XMAC: 1445 sc_if->sk_phyaddr = SK_PHYADDR_XMAC; 1446 break; 1447 case SK_PHYTYPE_BCOM: 1448 sc_if->sk_phyaddr = SK_PHYADDR_BCOM; 1449 break; 1450 case SK_PHYTYPE_MARV_COPPER: 1451 sc_if->sk_phyaddr = SK_PHYADDR_MARV; 1452 break; 1453 default: 1454 printf("skc%d: unsupported PHY type: %d\n", 1455 sc->sk_unit, sc_if->sk_phytype); 1456 error = ENODEV; 1457 SK_UNLOCK(sc); 1458 goto fail; 1459 } 1460 1461 1462 /* 1463 * Call MI attach routine. Can't hold locks when calling into ether_*. 1464 */ 1465 SK_UNLOCK(sc); 1466 ether_ifattach(ifp, sc_if->arpcom.ac_enaddr); 1467 SK_LOCK(sc); 1468 1469 /* 1470 * Do miibus setup. 1471 */ 1472 switch (sc->sk_type) { 1473 case SK_GENESIS: 1474 sk_init_xmac(sc_if); 1475 break; 1476 case SK_YUKON: 1477 sk_init_yukon(sc_if); 1478 break; 1479 } 1480 1481 SK_UNLOCK(sc); 1482 if (mii_phy_probe(dev, &sc_if->sk_miibus, 1483 sk_ifmedia_upd, sk_ifmedia_sts)) { 1484 printf("skc%d: no PHY found!\n", sc_if->sk_unit); 1485 ether_ifdetach(ifp); 1486 error = ENXIO; 1487 goto fail; 1488 } 1489 1490fail: 1491 if (error) { 1492 /* Access should be ok even though lock has been dropped */ 1493 sc->sk_if[port] = NULL; 1494 sk_detach(dev); 1495 } 1496 1497 return(error); 1498} 1499 1500/* 1501 * Attach the interface. Allocate softc structures, do ifmedia 1502 * setup and ethernet/BPF attach. 1503 */ 1504static int 1505skc_attach(dev) 1506 device_t dev; 1507{ 1508 struct sk_softc *sc; 1509 int unit, error = 0, rid, *port; 1510 uint8_t skrs; 1511 1512 sc = device_get_softc(dev); 1513 unit = device_get_unit(dev); 1514 1515 mtx_init(&sc->sk_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1516 MTX_DEF | MTX_RECURSE); 1517 /* 1518 * Map control/status registers. 1519 */ 1520 pci_enable_busmaster(dev); 1521 1522 rid = SK_RID; 1523 sc->sk_res = bus_alloc_resource_any(dev, SK_RES, &rid, RF_ACTIVE); 1524 1525 if (sc->sk_res == NULL) { 1526 printf("sk%d: couldn't map ports/memory\n", unit); 1527 error = ENXIO; 1528 goto fail; 1529 } 1530 1531 sc->sk_btag = rman_get_bustag(sc->sk_res); 1532 sc->sk_bhandle = rman_get_bushandle(sc->sk_res); 1533 1534 /* Allocate interrupt */ 1535 rid = 0; 1536 sc->sk_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1537 RF_SHAREABLE | RF_ACTIVE); 1538 1539 if (sc->sk_irq == NULL) { 1540 printf("skc%d: couldn't map interrupt\n", unit); 1541 error = ENXIO; 1542 goto fail; 1543 } 1544 1545 /* Set adapter type */ 1546 switch (pci_get_device(dev)) { 1547 case DEVICEID_SK_V1: 1548 sc->sk_type = SK_GENESIS; 1549 break; 1550 case DEVICEID_SK_V2: 1551 case DEVICEID_BELKIN_5005: 1552 case DEVICEID_3COM_3C940: 1553 case DEVICEID_LINKSYS_EG1032: 1554 case DEVICEID_DLINK_DGE530T: 1555 sc->sk_type = SK_YUKON; 1556 break; 1557 default: 1558 printf("skc%d: unknown device!\n", unit); 1559 error = ENXIO; 1560 goto fail; 1561 } 1562 1563 /* Reset the adapter. */ 1564 sk_reset(sc); 1565 1566 sc->sk_unit = unit; 1567 1568 /* Read and save vital product data from EEPROM. */ 1569 sk_vpd_read(sc); 1570 1571 skrs = sk_win_read_1(sc, SK_EPROM0); 1572 if (sc->sk_type == SK_GENESIS) { 1573 /* Read and save RAM size and RAMbuffer offset */ 1574 switch(skrs) { 1575 case SK_RAMSIZE_512K_64: 1576 sc->sk_ramsize = 0x80000; 1577 sc->sk_rboff = SK_RBOFF_0; 1578 break; 1579 case SK_RAMSIZE_1024K_64: 1580 sc->sk_ramsize = 0x100000; 1581 sc->sk_rboff = SK_RBOFF_80000; 1582 break; 1583 case SK_RAMSIZE_1024K_128: 1584 sc->sk_ramsize = 0x100000; 1585 sc->sk_rboff = SK_RBOFF_0; 1586 break; 1587 case SK_RAMSIZE_2048K_128: 1588 sc->sk_ramsize = 0x200000; 1589 sc->sk_rboff = SK_RBOFF_0; 1590 break; 1591 default: 1592 printf("skc%d: unknown ram size: %d\n", 1593 sc->sk_unit, sk_win_read_1(sc, SK_EPROM0)); 1594 error = ENXIO; 1595 goto fail; 1596 } 1597 } else { /* SK_YUKON */ 1598 if (skrs == 0x00) { 1599 sc->sk_ramsize = 0x20000; 1600 } else { 1601 sc->sk_ramsize = skrs * (1<<12); 1602 } 1603 sc->sk_rboff = SK_RBOFF_0; 1604 } 1605 device_printf(dev, "type = %s\n", 1606 (sc->sk_type == SK_GENESIS) ? "GENESIS" : "YUKON"); 1607 device_printf(dev, "SK_EPROM0 = 0x%02x\n", skrs); 1608 device_printf(dev, "SRAM size = 0x%06x\n", sc->sk_ramsize); 1609 1610 /* Read and save physical media type */ 1611 switch(sk_win_read_1(sc, SK_PMDTYPE)) { 1612 case SK_PMD_1000BASESX: 1613 sc->sk_pmd = IFM_1000_SX; 1614 break; 1615 case SK_PMD_1000BASELX: 1616 sc->sk_pmd = IFM_1000_LX; 1617 break; 1618 case SK_PMD_1000BASECX: 1619 sc->sk_pmd = IFM_1000_CX; 1620 break; 1621 case SK_PMD_1000BASETX: 1622 sc->sk_pmd = IFM_1000_T; 1623 break; 1624 default: 1625 printf("skc%d: unknown media type: 0x%x\n", 1626 sc->sk_unit, sk_win_read_1(sc, SK_PMDTYPE)); 1627 error = ENXIO; 1628 goto fail; 1629 } 1630 1631 /* Announce the product name and more VPD data if there. */ 1632 if (sc->sk_vpd_prodname != NULL) 1633 printf("skc%d: %s\n", sc->sk_unit, sc->sk_vpd_prodname); 1634 if (sc->sk_vpd_readonly != NULL && sc->sk_vpd_readonly_len != 0) { 1635 char buf[256]; 1636 char *dp = sc->sk_vpd_readonly; 1637 uint16_t l, len = sc->sk_vpd_readonly_len; 1638 1639 while (len >= 3) { 1640 if ( (*dp == 'P' && *(dp+1) == 'N') || 1641 (*dp == 'E' && *(dp+1) == 'C') || 1642 (*dp == 'M' && *(dp+1) == 'N') || 1643 (*dp == 'S' && *(dp+1) == 'N') ) { 1644 1645 l = 0; 1646 while(l < *(dp+2)) { 1647 buf[l] = *(dp+3+l); 1648 ++l; 1649 } 1650 buf[l] = '\0'; 1651 printf("skc%d: %c%c: %s\n", 1652 sc->sk_unit, *dp, *(dp+1), buf); 1653 len -= (3 + l); 1654 dp += (3 + l); 1655 } else { 1656 len -= (3 + *(dp+2)); 1657 dp += (3 + *(dp+2)); 1658 } 1659 } 1660 } 1661 1662 /* read CHIPVER 0xb1. */ 1663 device_printf(dev, "chip ver 0x%02x\n", sk_win_read_1(sc, SK_CHIPVER)); 1664 /* read CONFIG 0x73. */ 1665 device_printf(dev, "chip conf 0x%02x\n", sk_win_read_1(sc, SK_CONFIG)); 1666 1667 sc->sk_devs[SK_PORT_A] = device_add_child(dev, "sk", -1); 1668 port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT); 1669 *port = SK_PORT_A; 1670 device_set_ivars(sc->sk_devs[SK_PORT_A], port); 1671 1672 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) { 1673 sc->sk_devs[SK_PORT_B] = device_add_child(dev, "sk", -1); 1674 port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT); 1675 *port = SK_PORT_B; 1676 device_set_ivars(sc->sk_devs[SK_PORT_B], port); 1677 } 1678 1679 /* Turn on the 'driver is loaded' LED. */ 1680 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1681 1682 bus_generic_attach(dev); 1683 1684 /* Hook interrupt last to avoid having to lock softc */ 1685 error = bus_setup_intr(dev, sc->sk_irq, INTR_TYPE_NET|INTR_MPSAFE, 1686 sk_intr, sc, &sc->sk_intrhand); 1687 1688 if (error) { 1689 printf("skc%d: couldn't set up irq\n", unit); 1690 goto fail; 1691 } 1692 1693fail: 1694 if (error) 1695 skc_detach(dev); 1696 1697 return(error); 1698} 1699 1700/* 1701 * Shutdown hardware and free up resources. This can be called any 1702 * time after the mutex has been initialized. It is called in both 1703 * the error case in attach and the normal detach case so it needs 1704 * to be careful about only freeing resources that have actually been 1705 * allocated. 1706 */ 1707static int 1708sk_detach(dev) 1709 device_t dev; 1710{ 1711 struct sk_if_softc *sc_if; 1712 struct ifnet *ifp; 1713 1714 sc_if = device_get_softc(dev); 1715 KASSERT(mtx_initialized(&sc_if->sk_softc->sk_mtx), 1716 ("sk mutex not initialized in sk_detach")); 1717 SK_IF_LOCK(sc_if); 1718 1719 ifp = &sc_if->arpcom.ac_if; 1720 /* These should only be active if attach_xmac succeeded */ 1721 if (device_is_attached(dev)) { 1722 sk_stop(sc_if); 1723 /* Can't hold locks while calling detach */ 1724 SK_IF_UNLOCK(sc_if); 1725 ether_ifdetach(ifp); 1726 SK_IF_LOCK(sc_if); 1727 } 1728 /* 1729 * We're generally called from skc_detach() which is using 1730 * device_delete_child() to get to here. It's already trashed 1731 * miibus for us, so don't do it here or we'll panic. 1732 */ 1733 /* 1734 if (sc_if->sk_miibus != NULL) 1735 device_delete_child(dev, sc_if->sk_miibus); 1736 */ 1737 bus_generic_detach(dev); 1738 if (sc_if->sk_cdata.sk_jumbo_buf != NULL) 1739 contigfree(sc_if->sk_cdata.sk_jumbo_buf, SK_JMEM, M_DEVBUF); 1740 if (sc_if->sk_rdata != NULL) { 1741 contigfree(sc_if->sk_rdata, sizeof(struct sk_ring_data), 1742 M_DEVBUF); 1743 } 1744 SK_IF_UNLOCK(sc_if); 1745 1746 return(0); 1747} 1748 1749static int 1750skc_detach(dev) 1751 device_t dev; 1752{ 1753 struct sk_softc *sc; 1754 1755 sc = device_get_softc(dev); 1756 KASSERT(mtx_initialized(&sc->sk_mtx), ("sk mutex not initialized")); 1757 1758 if (device_is_alive(dev)) { 1759 if (sc->sk_devs[SK_PORT_A] != NULL) 1760 device_delete_child(dev, sc->sk_devs[SK_PORT_A]); 1761 if (sc->sk_devs[SK_PORT_B] != NULL) 1762 device_delete_child(dev, sc->sk_devs[SK_PORT_B]); 1763 bus_generic_detach(dev); 1764 } 1765 1766 if (sc->sk_intrhand) 1767 bus_teardown_intr(dev, sc->sk_irq, sc->sk_intrhand); 1768 if (sc->sk_irq) 1769 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq); 1770 if (sc->sk_res) 1771 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res); 1772 1773 mtx_destroy(&sc->sk_mtx); 1774 1775 return(0); 1776} 1777 1778static int 1779sk_encap(sc_if, m_head, txidx) 1780 struct sk_if_softc *sc_if; 1781 struct mbuf *m_head; 1782 u_int32_t *txidx; 1783{ 1784 struct sk_tx_desc *f = NULL; 1785 struct mbuf *m; 1786 u_int32_t frag, cur, cnt = 0; 1787 1788 SK_IF_LOCK_ASSERT(sc_if); 1789 1790 m = m_head; 1791 cur = frag = *txidx; 1792 1793 /* 1794 * Start packing the mbufs in this chain into 1795 * the fragment pointers. Stop when we run out 1796 * of fragments or hit the end of the mbuf chain. 1797 */ 1798 for (m = m_head; m != NULL; m = m->m_next) { 1799 if (m->m_len != 0) { 1800 if ((SK_TX_RING_CNT - 1801 (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2) 1802 return(ENOBUFS); 1803 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1804 f->sk_data_lo = vtophys(mtod(m, vm_offset_t)); 1805 f->sk_ctl = m->m_len | SK_OPCODE_DEFAULT; 1806 if (cnt == 0) 1807 f->sk_ctl |= SK_TXCTL_FIRSTFRAG; 1808 else 1809 f->sk_ctl |= SK_TXCTL_OWN; 1810 cur = frag; 1811 SK_INC(frag, SK_TX_RING_CNT); 1812 cnt++; 1813 } 1814 } 1815 1816 if (m != NULL) 1817 return(ENOBUFS); 1818 1819 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= 1820 SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR; 1821 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1822 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |= SK_TXCTL_OWN; 1823 sc_if->sk_cdata.sk_tx_cnt += cnt; 1824 1825 *txidx = frag; 1826 1827 return(0); 1828} 1829 1830static void 1831sk_start(ifp) 1832 struct ifnet *ifp; 1833{ 1834 struct sk_softc *sc; 1835 struct sk_if_softc *sc_if; 1836 struct mbuf *m_head = NULL; 1837 u_int32_t idx; 1838 1839 sc_if = ifp->if_softc; 1840 sc = sc_if->sk_softc; 1841 1842 SK_IF_LOCK(sc_if); 1843 1844 idx = sc_if->sk_cdata.sk_tx_prod; 1845 1846 while(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1847 IF_DEQUEUE(&ifp->if_snd, m_head); 1848 if (m_head == NULL) 1849 break; 1850 1851 /* 1852 * Pack the data into the transmit ring. If we 1853 * don't have room, set the OACTIVE flag and wait 1854 * for the NIC to drain the ring. 1855 */ 1856 if (sk_encap(sc_if, m_head, &idx)) { 1857 IF_PREPEND(&ifp->if_snd, m_head); 1858 ifp->if_flags |= IFF_OACTIVE; 1859 break; 1860 } 1861 1862 /* 1863 * If there's a BPF listener, bounce a copy of this frame 1864 * to him. 1865 */ 1866 BPF_MTAP(ifp, m_head); 1867 } 1868 1869 /* Transmit */ 1870 if (idx != sc_if->sk_cdata.sk_tx_prod) { 1871 sc_if->sk_cdata.sk_tx_prod = idx; 1872 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 1873 1874 /* Set a timeout in case the chip goes out to lunch. */ 1875 ifp->if_timer = 5; 1876 } 1877 SK_IF_UNLOCK(sc_if); 1878 1879 return; 1880} 1881 1882 1883static void 1884sk_watchdog(ifp) 1885 struct ifnet *ifp; 1886{ 1887 struct sk_if_softc *sc_if; 1888 1889 sc_if = ifp->if_softc; 1890 1891 printf("sk%d: watchdog timeout\n", sc_if->sk_unit); 1892 sk_init(sc_if); 1893 1894 return; 1895} 1896 1897static void 1898skc_shutdown(dev) 1899 device_t dev; 1900{ 1901 struct sk_softc *sc; 1902 1903 sc = device_get_softc(dev); 1904 SK_LOCK(sc); 1905 1906 /* Turn off the 'driver is loaded' LED. */ 1907 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 1908 1909 /* 1910 * Reset the GEnesis controller. Doing this should also 1911 * assert the resets on the attached XMAC(s). 1912 */ 1913 sk_reset(sc); 1914 SK_UNLOCK(sc); 1915 1916 return; 1917} 1918 1919static void 1920sk_rxeof(sc_if) 1921 struct sk_if_softc *sc_if; 1922{ 1923 struct sk_softc *sc; 1924 struct mbuf *m; 1925 struct ifnet *ifp; 1926 struct sk_chain *cur_rx; 1927 int total_len = 0; 1928 int i; 1929 u_int32_t rxstat; 1930 1931 sc = sc_if->sk_softc; 1932 ifp = &sc_if->arpcom.ac_if; 1933 i = sc_if->sk_cdata.sk_rx_prod; 1934 cur_rx = &sc_if->sk_cdata.sk_rx_chain[i]; 1935 1936 SK_LOCK_ASSERT(sc); 1937 1938 while(!(sc_if->sk_rdata->sk_rx_ring[i].sk_ctl & SK_RXCTL_OWN)) { 1939 1940 cur_rx = &sc_if->sk_cdata.sk_rx_chain[i]; 1941 rxstat = sc_if->sk_rdata->sk_rx_ring[i].sk_xmac_rxstat; 1942 m = cur_rx->sk_mbuf; 1943 cur_rx->sk_mbuf = NULL; 1944 total_len = SK_RXBYTES(sc_if->sk_rdata->sk_rx_ring[i].sk_ctl); 1945 SK_INC(i, SK_RX_RING_CNT); 1946 1947 if (rxstat & XM_RXSTAT_ERRFRAME) { 1948 ifp->if_ierrors++; 1949 sk_newbuf(sc_if, cur_rx, m); 1950 continue; 1951 } 1952 1953 /* 1954 * Try to allocate a new jumbo buffer. If that 1955 * fails, copy the packet to mbufs and put the 1956 * jumbo buffer back in the ring so it can be 1957 * re-used. If allocating mbufs fails, then we 1958 * have to drop the packet. 1959 */ 1960 if (sk_newbuf(sc_if, cur_rx, NULL) == ENOBUFS) { 1961 struct mbuf *m0; 1962 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, 1963 ifp, NULL); 1964 sk_newbuf(sc_if, cur_rx, m); 1965 if (m0 == NULL) { 1966 printf("sk%d: no receive buffers " 1967 "available -- packet dropped!\n", 1968 sc_if->sk_unit); 1969 ifp->if_ierrors++; 1970 continue; 1971 } 1972 m = m0; 1973 } else { 1974 m->m_pkthdr.rcvif = ifp; 1975 m->m_pkthdr.len = m->m_len = total_len; 1976 } 1977 1978 ifp->if_ipackets++; 1979 SK_UNLOCK(sc); 1980 (*ifp->if_input)(ifp, m); 1981 SK_LOCK(sc); 1982 } 1983 1984 sc_if->sk_cdata.sk_rx_prod = i; 1985 1986 return; 1987} 1988 1989static void 1990sk_txeof(sc_if) 1991 struct sk_if_softc *sc_if; 1992{ 1993 struct sk_softc *sc; 1994 struct sk_tx_desc *cur_tx = NULL; 1995 struct ifnet *ifp; 1996 u_int32_t idx; 1997 1998 sc = sc_if->sk_softc; 1999 ifp = &sc_if->arpcom.ac_if; 2000 2001 /* 2002 * Go through our tx ring and free mbufs for those 2003 * frames that have been sent. 2004 */ 2005 idx = sc_if->sk_cdata.sk_tx_cons; 2006 while(idx != sc_if->sk_cdata.sk_tx_prod) { 2007 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 2008 if (cur_tx->sk_ctl & SK_TXCTL_OWN) 2009 break; 2010 if (cur_tx->sk_ctl & SK_TXCTL_LASTFRAG) 2011 ifp->if_opackets++; 2012 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 2013 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 2014 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 2015 } 2016 sc_if->sk_cdata.sk_tx_cnt--; 2017 SK_INC(idx, SK_TX_RING_CNT); 2018 } 2019 2020 if (sc_if->sk_cdata.sk_tx_cnt == 0) { 2021 ifp->if_timer = 0; 2022 ifp->if_flags &= ~IFF_OACTIVE; 2023 } else /* nudge chip to keep tx ring moving */ 2024 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 2025 2026 sc_if->sk_cdata.sk_tx_cons = idx; 2027 2028 return; 2029} 2030 2031static void 2032sk_tick(xsc_if) 2033 void *xsc_if; 2034{ 2035 struct sk_if_softc *sc_if; 2036 struct mii_data *mii; 2037 struct ifnet *ifp; 2038 int i; 2039 2040 sc_if = xsc_if; 2041 SK_IF_LOCK(sc_if); 2042 ifp = &sc_if->arpcom.ac_if; 2043 mii = device_get_softc(sc_if->sk_miibus); 2044 2045 if (!(ifp->if_flags & IFF_UP)) { 2046 SK_IF_UNLOCK(sc_if); 2047 return; 2048 } 2049 2050 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2051 sk_intr_bcom(sc_if); 2052 SK_IF_UNLOCK(sc_if); 2053 return; 2054 } 2055 2056 /* 2057 * According to SysKonnect, the correct way to verify that 2058 * the link has come back up is to poll bit 0 of the GPIO 2059 * register three times. This pin has the signal from the 2060 * link_sync pin connected to it; if we read the same link 2061 * state 3 times in a row, we know the link is up. 2062 */ 2063 for (i = 0; i < 3; i++) { 2064 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET) 2065 break; 2066 } 2067 2068 if (i != 3) { 2069 sc_if->sk_tick_ch = timeout(sk_tick, sc_if, hz); 2070 SK_IF_UNLOCK(sc_if); 2071 return; 2072 } 2073 2074 /* Turn the GP0 interrupt back on. */ 2075 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2076 SK_XM_READ_2(sc_if, XM_ISR); 2077 mii_tick(mii); 2078 untimeout(sk_tick, sc_if, sc_if->sk_tick_ch); 2079 2080 SK_IF_UNLOCK(sc_if); 2081 return; 2082} 2083 2084static void 2085sk_intr_bcom(sc_if) 2086 struct sk_if_softc *sc_if; 2087{ 2088 struct mii_data *mii; 2089 struct ifnet *ifp; 2090 int status; 2091 mii = device_get_softc(sc_if->sk_miibus); 2092 ifp = &sc_if->arpcom.ac_if; 2093 2094 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2095 2096 /* 2097 * Read the PHY interrupt register to make sure 2098 * we clear any pending interrupts. 2099 */ 2100 status = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, BRGPHY_MII_ISR); 2101 2102 if (!(ifp->if_flags & IFF_RUNNING)) { 2103 sk_init_xmac(sc_if); 2104 return; 2105 } 2106 2107 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) { 2108 int lstat; 2109 lstat = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, 2110 BRGPHY_MII_AUXSTS); 2111 2112 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) { 2113 mii_mediachg(mii); 2114 /* Turn off the link LED. */ 2115 SK_IF_WRITE_1(sc_if, 0, 2116 SK_LINKLED1_CTL, SK_LINKLED_OFF); 2117 sc_if->sk_link = 0; 2118 } else if (status & BRGPHY_ISR_LNK_CHG) { 2119 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 2120 BRGPHY_MII_IMR, 0xFF00); 2121 mii_tick(mii); 2122 sc_if->sk_link = 1; 2123 /* Turn on the link LED. */ 2124 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2125 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF| 2126 SK_LINKLED_BLINK_OFF); 2127 } else { 2128 mii_tick(mii); 2129 sc_if->sk_tick_ch = timeout(sk_tick, sc_if, hz); 2130 } 2131 } 2132 2133 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2134 2135 return; 2136} 2137 2138static void 2139sk_intr_xmac(sc_if) 2140 struct sk_if_softc *sc_if; 2141{ 2142 struct sk_softc *sc; 2143 u_int16_t status; 2144 2145 sc = sc_if->sk_softc; 2146 status = SK_XM_READ_2(sc_if, XM_ISR); 2147 2148 /* 2149 * Link has gone down. Start MII tick timeout to 2150 * watch for link resync. 2151 */ 2152 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) { 2153 if (status & XM_ISR_GP0_SET) { 2154 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2155 sc_if->sk_tick_ch = timeout(sk_tick, sc_if, hz); 2156 } 2157 2158 if (status & XM_ISR_AUTONEG_DONE) { 2159 sc_if->sk_tick_ch = timeout(sk_tick, sc_if, hz); 2160 } 2161 } 2162 2163 if (status & XM_IMR_TX_UNDERRUN) 2164 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO); 2165 2166 if (status & XM_IMR_RX_OVERRUN) 2167 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO); 2168 2169 status = SK_XM_READ_2(sc_if, XM_ISR); 2170 2171 return; 2172} 2173 2174static void 2175sk_intr_yukon(sc_if) 2176 struct sk_if_softc *sc_if; 2177{ 2178 int status; 2179 2180 status = SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2181 2182 return; 2183} 2184 2185static void 2186sk_intr(xsc) 2187 void *xsc; 2188{ 2189 struct sk_softc *sc = xsc; 2190 struct sk_if_softc *sc_if0 = NULL, *sc_if1 = NULL; 2191 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2192 u_int32_t status; 2193 2194 SK_LOCK(sc); 2195 2196 sc_if0 = sc->sk_if[SK_PORT_A]; 2197 sc_if1 = sc->sk_if[SK_PORT_B]; 2198 2199 if (sc_if0 != NULL) 2200 ifp0 = &sc_if0->arpcom.ac_if; 2201 if (sc_if1 != NULL) 2202 ifp1 = &sc_if1->arpcom.ac_if; 2203 2204 for (;;) { 2205 status = CSR_READ_4(sc, SK_ISSR); 2206 if (!(status & sc->sk_intrmask)) 2207 break; 2208 2209 /* Handle receive interrupts first. */ 2210 if (status & SK_ISR_RX1_EOF) { 2211 sk_rxeof(sc_if0); 2212 CSR_WRITE_4(sc, SK_BMU_RX_CSR0, 2213 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2214 } 2215 if (status & SK_ISR_RX2_EOF) { 2216 sk_rxeof(sc_if1); 2217 CSR_WRITE_4(sc, SK_BMU_RX_CSR1, 2218 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2219 } 2220 2221 /* Then transmit interrupts. */ 2222 if (status & SK_ISR_TX1_S_EOF) { 2223 sk_txeof(sc_if0); 2224 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, 2225 SK_TXBMU_CLR_IRQ_EOF); 2226 } 2227 if (status & SK_ISR_TX2_S_EOF) { 2228 sk_txeof(sc_if1); 2229 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, 2230 SK_TXBMU_CLR_IRQ_EOF); 2231 } 2232 2233 /* Then MAC interrupts. */ 2234 if (status & SK_ISR_MAC1 && ifp0->if_flags & IFF_RUNNING) { 2235 if (sc->sk_type == SK_GENESIS) 2236 sk_intr_xmac(sc_if0); 2237 else 2238 sk_intr_yukon(sc_if0); 2239 } 2240 2241 if (status & SK_ISR_MAC2 && ifp1->if_flags & IFF_RUNNING) { 2242 if (sc->sk_type == SK_GENESIS) 2243 sk_intr_xmac(sc_if1); 2244 else 2245 sk_intr_yukon(sc_if1); 2246 } 2247 2248 if (status & SK_ISR_EXTERNAL_REG) { 2249 if (ifp0 != NULL && 2250 sc_if0->sk_phytype == SK_PHYTYPE_BCOM) 2251 sk_intr_bcom(sc_if0); 2252 if (ifp1 != NULL && 2253 sc_if1->sk_phytype == SK_PHYTYPE_BCOM) 2254 sk_intr_bcom(sc_if1); 2255 } 2256 } 2257 2258 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2259 2260 if (ifp0 != NULL && ifp0->if_snd.ifq_head != NULL) 2261 sk_start(ifp0); 2262 if (ifp1 != NULL && ifp1->if_snd.ifq_head != NULL) 2263 sk_start(ifp1); 2264 2265 SK_UNLOCK(sc); 2266 2267 return; 2268} 2269 2270static void 2271sk_init_xmac(sc_if) 2272 struct sk_if_softc *sc_if; 2273{ 2274 struct sk_softc *sc; 2275 struct ifnet *ifp; 2276 struct sk_bcom_hack bhack[] = { 2277 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, 2278 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, 2279 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 2280 { 0, 0 } }; 2281 2282 sc = sc_if->sk_softc; 2283 ifp = &sc_if->arpcom.ac_if; 2284 2285 /* Unreset the XMAC. */ 2286 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET); 2287 DELAY(1000); 2288 2289 /* Reset the XMAC's internal state. */ 2290 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2291 2292 /* Save the XMAC II revision */ 2293 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID)); 2294 2295 /* 2296 * Perform additional initialization for external PHYs, 2297 * namely for the 1000baseTX cards that use the XMAC's 2298 * GMII mode. 2299 */ 2300 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2301 int i = 0; 2302 u_int32_t val; 2303 2304 /* Take PHY out of reset. */ 2305 val = sk_win_read_4(sc, SK_GPIO); 2306 if (sc_if->sk_port == SK_PORT_A) 2307 val |= SK_GPIO_DIR0|SK_GPIO_DAT0; 2308 else 2309 val |= SK_GPIO_DIR2|SK_GPIO_DAT2; 2310 sk_win_write_4(sc, SK_GPIO, val); 2311 2312 /* Enable GMII mode on the XMAC. */ 2313 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE); 2314 2315 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 2316 BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET); 2317 DELAY(10000); 2318 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 2319 BRGPHY_MII_IMR, 0xFFF0); 2320 2321 /* 2322 * Early versions of the BCM5400 apparently have 2323 * a bug that requires them to have their reserved 2324 * registers initialized to some magic values. I don't 2325 * know what the numbers do, I'm just the messenger. 2326 */ 2327 if (sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, 0x03) 2328 == 0x6041) { 2329 while(bhack[i].reg) { 2330 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 2331 bhack[i].reg, bhack[i].val); 2332 i++; 2333 } 2334 } 2335 } 2336 2337 /* Set station address */ 2338 SK_XM_WRITE_2(sc_if, XM_PAR0, 2339 *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[0])); 2340 SK_XM_WRITE_2(sc_if, XM_PAR1, 2341 *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[2])); 2342 SK_XM_WRITE_2(sc_if, XM_PAR2, 2343 *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[4])); 2344 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION); 2345 2346 if (ifp->if_flags & IFF_BROADCAST) { 2347 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2348 } else { 2349 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2350 } 2351 2352 /* We don't need the FCS appended to the packet. */ 2353 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS); 2354 2355 /* We want short frames padded to 60 bytes. */ 2356 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD); 2357 2358 /* 2359 * Enable the reception of all error frames. This is is 2360 * a necessary evil due to the design of the XMAC. The 2361 * XMAC's receive FIFO is only 8K in size, however jumbo 2362 * frames can be up to 9000 bytes in length. When bad 2363 * frame filtering is enabled, the XMAC's RX FIFO operates 2364 * in 'store and forward' mode. For this to work, the 2365 * entire frame has to fit into the FIFO, but that means 2366 * that jumbo frames larger than 8192 bytes will be 2367 * truncated. Disabling all bad frame filtering causes 2368 * the RX FIFO to operate in streaming mode, in which 2369 * case the XMAC will start transfering frames out of the 2370 * RX FIFO as soon as the FIFO threshold is reached. 2371 */ 2372 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES| 2373 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS| 2374 XM_MODE_RX_INRANGELEN); 2375 2376 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2377 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2378 else 2379 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2380 2381 /* 2382 * Bump up the transmit threshold. This helps hold off transmit 2383 * underruns when we're blasting traffic from both ports at once. 2384 */ 2385 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH); 2386 2387 /* Set promiscuous mode */ 2388 sk_setpromisc(sc_if); 2389 2390 /* Set multicast filter */ 2391 sk_setmulti(sc_if); 2392 2393 /* Clear and enable interrupts */ 2394 SK_XM_READ_2(sc_if, XM_ISR); 2395 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 2396 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS); 2397 else 2398 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2399 2400 /* Configure MAC arbiter */ 2401 switch(sc_if->sk_xmac_rev) { 2402 case XM_XMAC_REV_B2: 2403 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2); 2404 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2); 2405 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2); 2406 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2); 2407 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2); 2408 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2); 2409 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2); 2410 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2); 2411 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2412 break; 2413 case XM_XMAC_REV_C1: 2414 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1); 2415 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1); 2416 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1); 2417 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1); 2418 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1); 2419 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1); 2420 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1); 2421 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1); 2422 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2423 break; 2424 default: 2425 break; 2426 } 2427 sk_win_write_2(sc, SK_MACARB_CTL, 2428 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF); 2429 2430 sc_if->sk_link = 1; 2431 2432 return; 2433} 2434 2435static void 2436sk_init_yukon(sc_if) 2437 struct sk_if_softc *sc_if; 2438{ 2439 u_int32_t phy; 2440 u_int16_t reg; 2441 int i; 2442 2443 /* GMAC and GPHY Reset */ 2444 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 2445 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2446 DELAY(1000); 2447 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_CLEAR); 2448 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2449 DELAY(1000); 2450 2451 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP | 2452 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE; 2453 2454 switch(sc_if->sk_softc->sk_pmd) { 2455 case IFM_1000_SX: 2456 case IFM_1000_LX: 2457 phy |= SK_GPHY_FIBER; 2458 break; 2459 2460 case IFM_1000_CX: 2461 case IFM_1000_T: 2462 phy |= SK_GPHY_COPPER; 2463 break; 2464 } 2465 2466 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET); 2467 DELAY(1000); 2468 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR); 2469 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 2470 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 2471 2472 /* unused read of the interrupt source register */ 2473 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2474 2475 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2476 2477 /* MIB Counter Clear Mode set */ 2478 reg |= YU_PAR_MIB_CLR; 2479 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2480 2481 /* MIB Counter Clear Mode clear */ 2482 reg &= ~YU_PAR_MIB_CLR; 2483 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2484 2485 /* receive control reg */ 2486 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR); 2487 2488 /* transmit parameter register */ 2489 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2490 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) ); 2491 2492 /* serial mode register */ 2493 SK_YU_WRITE_2(sc_if, YUKON_SMR, YU_SMR_DATA_BLIND(0x1c) | 2494 YU_SMR_MFL_VLAN | YU_SMR_IPG_DATA(0x1e)); 2495 2496 /* Setup Yukon's address */ 2497 for (i = 0; i < 3; i++) { 2498 /* Write Source Address 1 (unicast filter) */ 2499 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2500 sc_if->arpcom.ac_enaddr[i * 2] | 2501 sc_if->arpcom.ac_enaddr[i * 2 + 1] << 8); 2502 } 2503 2504 for (i = 0; i < 3; i++) { 2505 reg = sk_win_read_2(sc_if->sk_softc, 2506 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2507 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2508 } 2509 2510 /* Set promiscuous mode */ 2511 sk_setpromisc(sc_if); 2512 2513 /* Set multicast filter */ 2514 sk_setmulti(sc_if); 2515 2516 /* enable interrupt mask for counter overflows */ 2517 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2518 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2519 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2520 2521 /* Configure RX MAC FIFO */ 2522 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2523 SK_IF_WRITE_4(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON); 2524 2525 /* Configure TX MAC FIFO */ 2526 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2527 SK_IF_WRITE_4(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2528} 2529 2530/* 2531 * Note that to properly initialize any part of the GEnesis chip, 2532 * you first have to take it out of reset mode. 2533 */ 2534static void 2535sk_init(xsc) 2536 void *xsc; 2537{ 2538 struct sk_if_softc *sc_if = xsc; 2539 struct sk_softc *sc; 2540 struct ifnet *ifp; 2541 struct mii_data *mii; 2542 u_int16_t reg; 2543 2544 SK_IF_LOCK(sc_if); 2545 2546 ifp = &sc_if->arpcom.ac_if; 2547 sc = sc_if->sk_softc; 2548 mii = device_get_softc(sc_if->sk_miibus); 2549 2550 /* Cancel pending I/O and free all RX/TX buffers. */ 2551 sk_stop(sc_if); 2552 2553 if (sc->sk_type == SK_GENESIS) { 2554 /* Configure LINK_SYNC LED */ 2555 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON); 2556 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2557 SK_LINKLED_LINKSYNC_ON); 2558 2559 /* Configure RX LED */ 2560 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, 2561 SK_RXLEDCTL_COUNTER_START); 2562 2563 /* Configure TX LED */ 2564 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, 2565 SK_TXLEDCTL_COUNTER_START); 2566 } 2567 2568 /* Configure I2C registers */ 2569 2570 /* Configure XMAC(s) */ 2571 switch (sc->sk_type) { 2572 case SK_GENESIS: 2573 sk_init_xmac(sc_if); 2574 break; 2575 case SK_YUKON: 2576 sk_init_yukon(sc_if); 2577 break; 2578 } 2579 mii_mediachg(mii); 2580 2581 if (sc->sk_type == SK_GENESIS) { 2582 /* Configure MAC FIFOs */ 2583 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET); 2584 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END); 2585 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON); 2586 2587 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET); 2588 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END); 2589 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON); 2590 } 2591 2592 /* Configure transmit arbiter(s) */ 2593 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, 2594 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 2595 2596 /* Configure RAMbuffers */ 2597 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2598 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2599 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2600 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2601 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2602 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2603 2604 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET); 2605 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON); 2606 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart); 2607 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart); 2608 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart); 2609 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend); 2610 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON); 2611 2612 /* Configure BMUs */ 2613 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE); 2614 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 2615 vtophys(&sc_if->sk_rdata->sk_rx_ring[0])); 2616 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0); 2617 2618 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE); 2619 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO, 2620 vtophys(&sc_if->sk_rdata->sk_tx_ring[0])); 2621 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0); 2622 2623 /* Init descriptors */ 2624 if (sk_init_rx_ring(sc_if) == ENOBUFS) { 2625 printf("sk%d: initialization failed: no " 2626 "memory for rx buffers\n", sc_if->sk_unit); 2627 sk_stop(sc_if); 2628 SK_IF_UNLOCK(sc_if); 2629 return; 2630 } 2631 sk_init_tx_ring(sc_if); 2632 2633 /* Configure interrupt handling */ 2634 CSR_READ_4(sc, SK_ISSR); 2635 if (sc_if->sk_port == SK_PORT_A) 2636 sc->sk_intrmask |= SK_INTRS1; 2637 else 2638 sc->sk_intrmask |= SK_INTRS2; 2639 2640 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG; 2641 2642 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2643 2644 /* Start BMUs. */ 2645 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START); 2646 2647 switch(sc->sk_type) { 2648 case SK_GENESIS: 2649 /* Enable XMACs TX and RX state machines */ 2650 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE); 2651 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2652 break; 2653 case SK_YUKON: 2654 reg = SK_YU_READ_2(sc_if, YUKON_GPCR); 2655 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN; 2656 reg &= ~(YU_GPCR_SPEED_EN | YU_GPCR_DPLX_EN); 2657 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg); 2658 } 2659 2660 ifp->if_flags |= IFF_RUNNING; 2661 ifp->if_flags &= ~IFF_OACTIVE; 2662 2663 SK_IF_UNLOCK(sc_if); 2664 2665 return; 2666} 2667 2668static void 2669sk_stop(sc_if) 2670 struct sk_if_softc *sc_if; 2671{ 2672 int i; 2673 struct sk_softc *sc; 2674 struct ifnet *ifp; 2675 2676 SK_IF_LOCK(sc_if); 2677 sc = sc_if->sk_softc; 2678 ifp = &sc_if->arpcom.ac_if; 2679 2680 untimeout(sk_tick, sc_if, sc_if->sk_tick_ch); 2681 2682 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2683 u_int32_t val; 2684 2685 /* Put PHY back into reset. */ 2686 val = sk_win_read_4(sc, SK_GPIO); 2687 if (sc_if->sk_port == SK_PORT_A) { 2688 val |= SK_GPIO_DIR0; 2689 val &= ~SK_GPIO_DAT0; 2690 } else { 2691 val |= SK_GPIO_DIR2; 2692 val &= ~SK_GPIO_DAT2; 2693 } 2694 sk_win_write_4(sc, SK_GPIO, val); 2695 } 2696 2697 /* Turn off various components of this interface. */ 2698 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2699 switch (sc->sk_type) { 2700 case SK_GENESIS: 2701 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_RESET); 2702 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET); 2703 break; 2704 case SK_YUKON: 2705 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2706 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2707 break; 2708 } 2709 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2710 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2711 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE); 2712 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2713 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2714 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2715 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2716 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2717 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2718 2719 /* Disable interrupts */ 2720 if (sc_if->sk_port == SK_PORT_A) 2721 sc->sk_intrmask &= ~SK_INTRS1; 2722 else 2723 sc->sk_intrmask &= ~SK_INTRS2; 2724 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2725 2726 SK_XM_READ_2(sc_if, XM_ISR); 2727 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2728 2729 /* Free RX and TX mbufs still in the queues. */ 2730 for (i = 0; i < SK_RX_RING_CNT; i++) { 2731 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2732 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2733 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2734 } 2735 } 2736 2737 for (i = 0; i < SK_TX_RING_CNT; i++) { 2738 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2739 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2740 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2741 } 2742 } 2743 2744 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2745 SK_IF_UNLOCK(sc_if); 2746 return; 2747} 2748