if_sk.c revision 129878
1/* $OpenBSD: if_sk.c,v 2.33 2003/08/12 05:23:06 nate Exp $ */ 2 3/* 4 * Copyright (c) 1997, 1998, 1999, 2000 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34/* 35 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 36 * 37 * Permission to use, copy, modify, and distribute this software for any 38 * purpose with or without fee is hereby granted, provided that the above 39 * copyright notice and this permission notice appear in all copies. 40 * 41 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 42 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 43 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 44 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 45 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 46 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 47 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 48 */ 49 50#include <sys/cdefs.h> 51__FBSDID("$FreeBSD: head/sys/dev/sk/if_sk.c 129878 2004-05-30 20:00:41Z phk $"); 52 53/* 54 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 55 * the SK-984x series adapters, both single port and dual port. 56 * References: 57 * The XaQti XMAC II datasheet, 58 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 59 * The SysKonnect GEnesis manual, http://www.syskonnect.com 60 * 61 * Note: XaQti has been aquired by Vitesse, and Vitesse does not have the 62 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 63 * convenience to others until Vitesse corrects this problem: 64 * 65 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 66 * 67 * Written by Bill Paul <wpaul@ee.columbia.edu> 68 * Department of Electrical Engineering 69 * Columbia University, New York City 70 */ 71/* 72 * The SysKonnect gigabit ethernet adapters consist of two main 73 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 74 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 75 * components and a PHY while the GEnesis controller provides a PCI 76 * interface with DMA support. Each card may have between 512K and 77 * 2MB of SRAM on board depending on the configuration. 78 * 79 * The SysKonnect GEnesis controller can have either one or two XMAC 80 * chips connected to it, allowing single or dual port NIC configurations. 81 * SysKonnect has the distinction of being the only vendor on the market 82 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 83 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 84 * XMAC registers. This driver takes advantage of these features to allow 85 * both XMACs to operate as independent interfaces. 86 */ 87 88#include <sys/param.h> 89#include <sys/systm.h> 90#include <sys/sockio.h> 91#include <sys/mbuf.h> 92#include <sys/malloc.h> 93#include <sys/kernel.h> 94#include <sys/module.h> 95#include <sys/socket.h> 96#include <sys/queue.h> 97 98#include <net/if.h> 99#include <net/if_arp.h> 100#include <net/ethernet.h> 101#include <net/if_dl.h> 102#include <net/if_media.h> 103 104#include <net/bpf.h> 105 106#include <vm/vm.h> /* for vtophys */ 107#include <vm/pmap.h> /* for vtophys */ 108#include <machine/bus_pio.h> 109#include <machine/bus_memio.h> 110#include <machine/bus.h> 111#include <machine/resource.h> 112#include <sys/bus.h> 113#include <sys/rman.h> 114 115#include <dev/mii/mii.h> 116#include <dev/mii/miivar.h> 117#include <dev/mii/brgphyreg.h> 118 119#include <dev/pci/pcireg.h> 120#include <dev/pci/pcivar.h> 121 122#if 0 123#define SK_USEIOSPACE 124#endif 125 126#include <pci/if_skreg.h> 127#include <pci/xmaciireg.h> 128#include <pci/yukonreg.h> 129 130MODULE_DEPEND(sk, pci, 1, 1, 1); 131MODULE_DEPEND(sk, ether, 1, 1, 1); 132MODULE_DEPEND(sk, miibus, 1, 1, 1); 133 134/* "controller miibus0" required. See GENERIC if you get errors here. */ 135#include "miibus_if.h" 136 137#ifndef lint 138static const char rcsid[] = 139 "$FreeBSD: head/sys/dev/sk/if_sk.c 129878 2004-05-30 20:00:41Z phk $"; 140#endif 141 142static struct sk_type sk_devs[] = { 143 { 144 VENDORID_SK, 145 DEVICEID_SK_V1, 146 "SysKonnect Gigabit Ethernet (V1.0)" 147 }, 148 { 149 VENDORID_SK, 150 DEVICEID_SK_V2, 151 "SysKonnect Gigabit Ethernet (V2.0)" 152 }, 153 { 154 VENDORID_MARVELL, 155 DEVICEID_SK_V2, 156 "Marvell Gigabit Ethernet" 157 }, 158 { 159 VENDORID_3COM, 160 DEVICEID_3COM_3C940, 161 "3Com 3C940 Gigabit Ethernet" 162 }, 163 { 164 VENDORID_LINKSYS, 165 DEVICEID_LINKSYS_EG1032, 166 "Linksys EG1032 Gigabit Ethernet" 167 }, 168 { 169 VENDORID_DLINK, 170 DEVICEID_DLINK_DGE530T, 171 "D-Link DGE-530T Gigabit Ethernet" 172 }, 173 { 0, 0, NULL } 174}; 175 176static int skc_probe (device_t); 177static int skc_attach (device_t); 178static int skc_detach (device_t); 179static void skc_shutdown (device_t); 180static int sk_detach (device_t); 181static int sk_probe (device_t); 182static int sk_attach (device_t); 183static void sk_tick (void *); 184static void sk_intr (void *); 185static void sk_intr_xmac (struct sk_if_softc *); 186static void sk_intr_bcom (struct sk_if_softc *); 187static void sk_intr_yukon (struct sk_if_softc *); 188static void sk_rxeof (struct sk_if_softc *); 189static void sk_txeof (struct sk_if_softc *); 190static int sk_encap (struct sk_if_softc *, struct mbuf *, 191 u_int32_t *); 192static void sk_start (struct ifnet *); 193static int sk_ioctl (struct ifnet *, u_long, caddr_t); 194static void sk_init (void *); 195static void sk_init_xmac (struct sk_if_softc *); 196static void sk_init_yukon (struct sk_if_softc *); 197static void sk_stop (struct sk_if_softc *); 198static void sk_watchdog (struct ifnet *); 199static int sk_ifmedia_upd (struct ifnet *); 200static void sk_ifmedia_sts (struct ifnet *, struct ifmediareq *); 201static void sk_reset (struct sk_softc *); 202static int sk_newbuf (struct sk_if_softc *, 203 struct sk_chain *, struct mbuf *); 204static int sk_alloc_jumbo_mem (struct sk_if_softc *); 205static void *sk_jalloc (struct sk_if_softc *); 206static void sk_jfree (void *, void *); 207static int sk_init_rx_ring (struct sk_if_softc *); 208static void sk_init_tx_ring (struct sk_if_softc *); 209static u_int32_t sk_win_read_4 (struct sk_softc *, int); 210static u_int16_t sk_win_read_2 (struct sk_softc *, int); 211static u_int8_t sk_win_read_1 (struct sk_softc *, int); 212static void sk_win_write_4 (struct sk_softc *, int, u_int32_t); 213static void sk_win_write_2 (struct sk_softc *, int, u_int32_t); 214static void sk_win_write_1 (struct sk_softc *, int, u_int32_t); 215static u_int8_t sk_vpd_readbyte (struct sk_softc *, int); 216static void sk_vpd_read_res (struct sk_softc *, struct vpd_res *, int); 217static void sk_vpd_read (struct sk_softc *); 218 219static int sk_miibus_readreg (device_t, int, int); 220static int sk_miibus_writereg (device_t, int, int, int); 221static void sk_miibus_statchg (device_t); 222 223static int sk_xmac_miibus_readreg (struct sk_if_softc *, int, int); 224static int sk_xmac_miibus_writereg (struct sk_if_softc *, int, int, 225 int); 226static void sk_xmac_miibus_statchg (struct sk_if_softc *); 227 228static int sk_marv_miibus_readreg (struct sk_if_softc *, int, int); 229static int sk_marv_miibus_writereg (struct sk_if_softc *, int, int, 230 int); 231static void sk_marv_miibus_statchg (struct sk_if_softc *); 232 233static uint32_t sk_xmchash (const uint8_t *); 234static uint32_t sk_gmchash (const uint8_t *); 235static void sk_setfilt (struct sk_if_softc *, caddr_t, int); 236static void sk_setmulti (struct sk_if_softc *); 237static void sk_setpromisc (struct sk_if_softc *); 238 239#ifdef SK_USEIOSPACE 240#define SK_RES SYS_RES_IOPORT 241#define SK_RID SK_PCI_LOIO 242#else 243#define SK_RES SYS_RES_MEMORY 244#define SK_RID SK_PCI_LOMEM 245#endif 246 247/* 248 * Note that we have newbus methods for both the GEnesis controller 249 * itself and the XMAC(s). The XMACs are children of the GEnesis, and 250 * the miibus code is a child of the XMACs. We need to do it this way 251 * so that the miibus drivers can access the PHY registers on the 252 * right PHY. It's not quite what I had in mind, but it's the only 253 * design that achieves the desired effect. 254 */ 255static device_method_t skc_methods[] = { 256 /* Device interface */ 257 DEVMETHOD(device_probe, skc_probe), 258 DEVMETHOD(device_attach, skc_attach), 259 DEVMETHOD(device_detach, skc_detach), 260 DEVMETHOD(device_shutdown, skc_shutdown), 261 262 /* bus interface */ 263 DEVMETHOD(bus_print_child, bus_generic_print_child), 264 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 265 266 { 0, 0 } 267}; 268 269static driver_t skc_driver = { 270 "skc", 271 skc_methods, 272 sizeof(struct sk_softc) 273}; 274 275static devclass_t skc_devclass; 276 277static device_method_t sk_methods[] = { 278 /* Device interface */ 279 DEVMETHOD(device_probe, sk_probe), 280 DEVMETHOD(device_attach, sk_attach), 281 DEVMETHOD(device_detach, sk_detach), 282 DEVMETHOD(device_shutdown, bus_generic_shutdown), 283 284 /* bus interface */ 285 DEVMETHOD(bus_print_child, bus_generic_print_child), 286 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 287 288 /* MII interface */ 289 DEVMETHOD(miibus_readreg, sk_miibus_readreg), 290 DEVMETHOD(miibus_writereg, sk_miibus_writereg), 291 DEVMETHOD(miibus_statchg, sk_miibus_statchg), 292 293 { 0, 0 } 294}; 295 296static driver_t sk_driver = { 297 "sk", 298 sk_methods, 299 sizeof(struct sk_if_softc) 300}; 301 302static devclass_t sk_devclass; 303 304DRIVER_MODULE(sk, pci, skc_driver, skc_devclass, 0, 0); 305DRIVER_MODULE(sk, skc, sk_driver, sk_devclass, 0, 0); 306DRIVER_MODULE(miibus, sk, miibus_driver, miibus_devclass, 0, 0); 307 308#define SK_SETBIT(sc, reg, x) \ 309 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 310 311#define SK_CLRBIT(sc, reg, x) \ 312 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 313 314#define SK_WIN_SETBIT_4(sc, reg, x) \ 315 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) | x) 316 317#define SK_WIN_CLRBIT_4(sc, reg, x) \ 318 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) & ~x) 319 320#define SK_WIN_SETBIT_2(sc, reg, x) \ 321 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) | x) 322 323#define SK_WIN_CLRBIT_2(sc, reg, x) \ 324 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) & ~x) 325 326static u_int32_t 327sk_win_read_4(sc, reg) 328 struct sk_softc *sc; 329 int reg; 330{ 331#ifdef SK_USEIOSPACE 332 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 333 return(CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg))); 334#else 335 return(CSR_READ_4(sc, reg)); 336#endif 337} 338 339static u_int16_t 340sk_win_read_2(sc, reg) 341 struct sk_softc *sc; 342 int reg; 343{ 344#ifdef SK_USEIOSPACE 345 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 346 return(CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg))); 347#else 348 return(CSR_READ_2(sc, reg)); 349#endif 350} 351 352static u_int8_t 353sk_win_read_1(sc, reg) 354 struct sk_softc *sc; 355 int reg; 356{ 357#ifdef SK_USEIOSPACE 358 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 359 return(CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg))); 360#else 361 return(CSR_READ_1(sc, reg)); 362#endif 363} 364 365static void 366sk_win_write_4(sc, reg, val) 367 struct sk_softc *sc; 368 int reg; 369 u_int32_t val; 370{ 371#ifdef SK_USEIOSPACE 372 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 373 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), val); 374#else 375 CSR_WRITE_4(sc, reg, val); 376#endif 377 return; 378} 379 380static void 381sk_win_write_2(sc, reg, val) 382 struct sk_softc *sc; 383 int reg; 384 u_int32_t val; 385{ 386#ifdef SK_USEIOSPACE 387 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 388 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), val); 389#else 390 CSR_WRITE_2(sc, reg, val); 391#endif 392 return; 393} 394 395static void 396sk_win_write_1(sc, reg, val) 397 struct sk_softc *sc; 398 int reg; 399 u_int32_t val; 400{ 401#ifdef SK_USEIOSPACE 402 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 403 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), val); 404#else 405 CSR_WRITE_1(sc, reg, val); 406#endif 407 return; 408} 409 410/* 411 * The VPD EEPROM contains Vital Product Data, as suggested in 412 * the PCI 2.1 specification. The VPD data is separared into areas 413 * denoted by resource IDs. The SysKonnect VPD contains an ID string 414 * resource (the name of the adapter), a read-only area resource 415 * containing various key/data fields and a read/write area which 416 * can be used to store asset management information or log messages. 417 * We read the ID string and read-only into buffers attached to 418 * the controller softc structure for later use. At the moment, 419 * we only use the ID string during skc_attach(). 420 */ 421static u_int8_t 422sk_vpd_readbyte(sc, addr) 423 struct sk_softc *sc; 424 int addr; 425{ 426 int i; 427 428 sk_win_write_2(sc, SK_PCI_REG(SK_PCI_VPD_ADDR), addr); 429 for (i = 0; i < SK_TIMEOUT; i++) { 430 DELAY(1); 431 if (sk_win_read_2(sc, 432 SK_PCI_REG(SK_PCI_VPD_ADDR)) & SK_VPD_FLAG) 433 break; 434 } 435 436 if (i == SK_TIMEOUT) 437 return(0); 438 439 return(sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_DATA))); 440} 441 442static void 443sk_vpd_read_res(sc, res, addr) 444 struct sk_softc *sc; 445 struct vpd_res *res; 446 int addr; 447{ 448 int i; 449 u_int8_t *ptr; 450 451 ptr = (u_int8_t *)res; 452 for (i = 0; i < sizeof(struct vpd_res); i++) 453 ptr[i] = sk_vpd_readbyte(sc, i + addr); 454 455 return; 456} 457 458static void 459sk_vpd_read(sc) 460 struct sk_softc *sc; 461{ 462 int pos = 0, i; 463 struct vpd_res res; 464 465 if (sc->sk_vpd_prodname != NULL) 466 free(sc->sk_vpd_prodname, M_DEVBUF); 467 if (sc->sk_vpd_readonly != NULL) 468 free(sc->sk_vpd_readonly, M_DEVBUF); 469 sc->sk_vpd_prodname = NULL; 470 sc->sk_vpd_readonly = NULL; 471 472 sk_vpd_read_res(sc, &res, pos); 473 474 /* 475 * Bail out quietly if the eeprom appears to be missing or empty. 476 */ 477 if (res.vr_id == 0xff && res.vr_len == 0xff && res.vr_pad == 0xff) 478 return; 479 480 if (res.vr_id != VPD_RES_ID) { 481 printf("skc%d: bad VPD resource id: expected %x got %x\n", 482 sc->sk_unit, VPD_RES_ID, res.vr_id); 483 return; 484 } 485 486 pos += sizeof(res); 487 sc->sk_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 488 for (i = 0; i < res.vr_len; i++) 489 sc->sk_vpd_prodname[i] = sk_vpd_readbyte(sc, i + pos); 490 sc->sk_vpd_prodname[i] = '\0'; 491 pos += i; 492 493 sk_vpd_read_res(sc, &res, pos); 494 495 if (res.vr_id != VPD_RES_READ) { 496 printf("skc%d: bad VPD resource id: expected %x got %x\n", 497 sc->sk_unit, VPD_RES_READ, res.vr_id); 498 return; 499 } 500 501 pos += sizeof(res); 502 sc->sk_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 503 for (i = 0; i < res.vr_len + 1; i++) 504 sc->sk_vpd_readonly[i] = sk_vpd_readbyte(sc, i + pos); 505 506 return; 507} 508 509static int 510sk_miibus_readreg(dev, phy, reg) 511 device_t dev; 512 int phy, reg; 513{ 514 struct sk_if_softc *sc_if; 515 516 sc_if = device_get_softc(dev); 517 518 switch(sc_if->sk_softc->sk_type) { 519 case SK_GENESIS: 520 return(sk_xmac_miibus_readreg(sc_if, phy, reg)); 521 case SK_YUKON: 522 return(sk_marv_miibus_readreg(sc_if, phy, reg)); 523 } 524 525 return(0); 526} 527 528static int 529sk_miibus_writereg(dev, phy, reg, val) 530 device_t dev; 531 int phy, reg, val; 532{ 533 struct sk_if_softc *sc_if; 534 535 sc_if = device_get_softc(dev); 536 537 switch(sc_if->sk_softc->sk_type) { 538 case SK_GENESIS: 539 return(sk_xmac_miibus_writereg(sc_if, phy, reg, val)); 540 case SK_YUKON: 541 return(sk_marv_miibus_writereg(sc_if, phy, reg, val)); 542 } 543 544 return(0); 545} 546 547static void 548sk_miibus_statchg(dev) 549 device_t dev; 550{ 551 struct sk_if_softc *sc_if; 552 553 sc_if = device_get_softc(dev); 554 555 switch(sc_if->sk_softc->sk_type) { 556 case SK_GENESIS: 557 sk_xmac_miibus_statchg(sc_if); 558 break; 559 case SK_YUKON: 560 sk_marv_miibus_statchg(sc_if); 561 break; 562 } 563 564 return; 565} 566 567static int 568sk_xmac_miibus_readreg(sc_if, phy, reg) 569 struct sk_if_softc *sc_if; 570 int phy, reg; 571{ 572 int i; 573 574 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0) 575 return(0); 576 577 SK_IF_LOCK(sc_if); 578 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 579 SK_XM_READ_2(sc_if, XM_PHY_DATA); 580 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 581 for (i = 0; i < SK_TIMEOUT; i++) { 582 DELAY(1); 583 if (SK_XM_READ_2(sc_if, XM_MMUCMD) & 584 XM_MMUCMD_PHYDATARDY) 585 break; 586 } 587 588 if (i == SK_TIMEOUT) { 589 printf("sk%d: phy failed to come ready\n", 590 sc_if->sk_unit); 591 SK_IF_UNLOCK(sc_if); 592 return(0); 593 } 594 } 595 DELAY(1); 596 i = SK_XM_READ_2(sc_if, XM_PHY_DATA); 597 SK_IF_UNLOCK(sc_if); 598 return(i); 599} 600 601static int 602sk_xmac_miibus_writereg(sc_if, phy, reg, val) 603 struct sk_if_softc *sc_if; 604 int phy, reg, val; 605{ 606 int i; 607 608 SK_IF_LOCK(sc_if); 609 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 610 for (i = 0; i < SK_TIMEOUT; i++) { 611 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 612 break; 613 } 614 615 if (i == SK_TIMEOUT) { 616 printf("sk%d: phy failed to come ready\n", sc_if->sk_unit); 617 SK_IF_UNLOCK(sc_if); 618 return(ETIMEDOUT); 619 } 620 621 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val); 622 for (i = 0; i < SK_TIMEOUT; i++) { 623 DELAY(1); 624 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 625 break; 626 } 627 SK_IF_UNLOCK(sc_if); 628 if (i == SK_TIMEOUT) 629 printf("sk%d: phy write timed out\n", sc_if->sk_unit); 630 631 return(0); 632} 633 634static void 635sk_xmac_miibus_statchg(sc_if) 636 struct sk_if_softc *sc_if; 637{ 638 struct mii_data *mii; 639 640 mii = device_get_softc(sc_if->sk_miibus); 641 642 SK_IF_LOCK(sc_if); 643 /* 644 * If this is a GMII PHY, manually set the XMAC's 645 * duplex mode accordingly. 646 */ 647 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 648 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 649 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 650 } else { 651 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 652 } 653 } 654 SK_IF_UNLOCK(sc_if); 655 656 return; 657} 658 659static int 660sk_marv_miibus_readreg(sc_if, phy, reg) 661 struct sk_if_softc *sc_if; 662 int phy, reg; 663{ 664 u_int16_t val; 665 int i; 666 667 if (phy != 0 || 668 (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER && 669 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) { 670 return(0); 671 } 672 673 SK_IF_LOCK(sc_if); 674 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 675 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 676 677 for (i = 0; i < SK_TIMEOUT; i++) { 678 DELAY(1); 679 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 680 if (val & YU_SMICR_READ_VALID) 681 break; 682 } 683 684 if (i == SK_TIMEOUT) { 685 printf("sk%d: phy failed to come ready\n", 686 sc_if->sk_unit); 687 SK_IF_UNLOCK(sc_if); 688 return(0); 689 } 690 691 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 692 SK_IF_UNLOCK(sc_if); 693 694 return(val); 695} 696 697static int 698sk_marv_miibus_writereg(sc_if, phy, reg, val) 699 struct sk_if_softc *sc_if; 700 int phy, reg, val; 701{ 702 int i; 703 704 SK_IF_LOCK(sc_if); 705 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 706 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 707 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 708 709 for (i = 0; i < SK_TIMEOUT; i++) { 710 DELAY(1); 711 if (SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY) 712 break; 713 } 714 SK_IF_UNLOCK(sc_if); 715 716 return(0); 717} 718 719static void 720sk_marv_miibus_statchg(sc_if) 721 struct sk_if_softc *sc_if; 722{ 723 return; 724} 725 726#define XMAC_POLY 0xEDB88320 727#define GMAC_POLY 0x04C11DB7L 728#define HASH_BITS 6 729 730static u_int32_t 731sk_xmchash(addr) 732 const uint8_t *addr; 733{ 734 uint32_t crc; 735 int idx, bit; 736 uint8_t data; 737 738 /* Compute CRC for the address value. */ 739 crc = 0xFFFFFFFF; /* initial value */ 740 741 for (idx = 0; idx < 6; idx++) { 742 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 743 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? XMAC_POLY : 0); 744 } 745 746 return (~crc & ((1 << HASH_BITS) - 1)); 747} 748 749/* gmchash is just a big endian crc */ 750static u_int32_t 751sk_gmchash(addr) 752 const uint8_t *addr; 753{ 754 uint32_t crc, carry; 755 int idx, bit; 756 uint8_t data; 757 758 /* Compute CRC for the address value. */ 759 crc = 0xFFFFFFFF; /* initial value */ 760 761 for (idx = 0; idx < 6; idx++) { 762 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) { 763 carry = ((crc & 0x80000000) ? 1 : 0) ^ (data & 0x01); 764 crc <<= 1; 765 if (carry) 766 crc = (crc ^ GMAC_POLY) | carry; 767 } 768 } 769 770 return (crc & ((1 << HASH_BITS) - 1)); 771} 772 773static void 774sk_setfilt(sc_if, addr, slot) 775 struct sk_if_softc *sc_if; 776 caddr_t addr; 777 int slot; 778{ 779 int base; 780 781 base = XM_RXFILT_ENTRY(slot); 782 783 SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0])); 784 SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2])); 785 SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4])); 786 787 return; 788} 789 790static void 791sk_setmulti(sc_if) 792 struct sk_if_softc *sc_if; 793{ 794 struct sk_softc *sc = sc_if->sk_softc; 795 struct ifnet *ifp = &sc_if->arpcom.ac_if; 796 u_int32_t hashes[2] = { 0, 0 }; 797 int h = 0, i; 798 struct ifmultiaddr *ifma; 799 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 800 801 802 /* First, zot all the existing filters. */ 803 switch(sc->sk_type) { 804 case SK_GENESIS: 805 for (i = 1; i < XM_RXFILT_MAX; i++) 806 sk_setfilt(sc_if, (caddr_t)&dummy, i); 807 808 SK_XM_WRITE_4(sc_if, XM_MAR0, 0); 809 SK_XM_WRITE_4(sc_if, XM_MAR2, 0); 810 break; 811 case SK_YUKON: 812 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 813 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 814 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 815 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 816 break; 817 } 818 819 /* Now program new ones. */ 820 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 821 hashes[0] = 0xFFFFFFFF; 822 hashes[1] = 0xFFFFFFFF; 823 } else { 824 i = 1; 825 TAILQ_FOREACH_REVERSE(ifma, &ifp->if_multiaddrs, ifmultihead, ifma_link) { 826 if (ifma->ifma_addr->sa_family != AF_LINK) 827 continue; 828 /* 829 * Program the first XM_RXFILT_MAX multicast groups 830 * into the perfect filter. For all others, 831 * use the hash table. 832 */ 833 if (sc->sk_type == SK_GENESIS && i < XM_RXFILT_MAX) { 834 sk_setfilt(sc_if, 835 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i); 836 i++; 837 continue; 838 } 839 840 switch(sc->sk_type) { 841 case SK_GENESIS: 842 h = sk_xmchash( 843 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 844 break; 845 case SK_YUKON: 846 h = sk_gmchash( 847 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 848 break; 849 } 850 if (h < 32) 851 hashes[0] |= (1 << h); 852 else 853 hashes[1] |= (1 << (h - 32)); 854 } 855 } 856 857 switch(sc->sk_type) { 858 case SK_GENESIS: 859 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH| 860 XM_MODE_RX_USE_PERFECT); 861 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]); 862 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]); 863 break; 864 case SK_YUKON: 865 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 866 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 867 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 868 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 869 break; 870 } 871 872 return; 873} 874 875static void 876sk_setpromisc(sc_if) 877 struct sk_if_softc *sc_if; 878{ 879 struct sk_softc *sc = sc_if->sk_softc; 880 struct ifnet *ifp = &sc_if->arpcom.ac_if; 881 882 switch(sc->sk_type) { 883 case SK_GENESIS: 884 if (ifp->if_flags & IFF_PROMISC) { 885 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 886 } else { 887 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 888 } 889 break; 890 case SK_YUKON: 891 if (ifp->if_flags & IFF_PROMISC) { 892 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 893 YU_RCR_UFLEN | YU_RCR_MUFLEN); 894 } else { 895 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 896 YU_RCR_UFLEN | YU_RCR_MUFLEN); 897 } 898 break; 899 } 900 901 return; 902} 903 904static int 905sk_init_rx_ring(sc_if) 906 struct sk_if_softc *sc_if; 907{ 908 struct sk_chain_data *cd = &sc_if->sk_cdata; 909 struct sk_ring_data *rd = sc_if->sk_rdata; 910 int i; 911 912 bzero((char *)rd->sk_rx_ring, 913 sizeof(struct sk_rx_desc) * SK_RX_RING_CNT); 914 915 for (i = 0; i < SK_RX_RING_CNT; i++) { 916 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i]; 917 if (sk_newbuf(sc_if, &cd->sk_rx_chain[i], NULL) == ENOBUFS) 918 return(ENOBUFS); 919 if (i == (SK_RX_RING_CNT - 1)) { 920 cd->sk_rx_chain[i].sk_next = 921 &cd->sk_rx_chain[0]; 922 rd->sk_rx_ring[i].sk_next = 923 vtophys(&rd->sk_rx_ring[0]); 924 } else { 925 cd->sk_rx_chain[i].sk_next = 926 &cd->sk_rx_chain[i + 1]; 927 rd->sk_rx_ring[i].sk_next = 928 vtophys(&rd->sk_rx_ring[i + 1]); 929 } 930 } 931 932 sc_if->sk_cdata.sk_rx_prod = 0; 933 sc_if->sk_cdata.sk_rx_cons = 0; 934 935 return(0); 936} 937 938static void 939sk_init_tx_ring(sc_if) 940 struct sk_if_softc *sc_if; 941{ 942 struct sk_chain_data *cd = &sc_if->sk_cdata; 943 struct sk_ring_data *rd = sc_if->sk_rdata; 944 int i; 945 946 bzero((char *)sc_if->sk_rdata->sk_tx_ring, 947 sizeof(struct sk_tx_desc) * SK_TX_RING_CNT); 948 949 for (i = 0; i < SK_TX_RING_CNT; i++) { 950 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i]; 951 if (i == (SK_TX_RING_CNT - 1)) { 952 cd->sk_tx_chain[i].sk_next = 953 &cd->sk_tx_chain[0]; 954 rd->sk_tx_ring[i].sk_next = 955 vtophys(&rd->sk_tx_ring[0]); 956 } else { 957 cd->sk_tx_chain[i].sk_next = 958 &cd->sk_tx_chain[i + 1]; 959 rd->sk_tx_ring[i].sk_next = 960 vtophys(&rd->sk_tx_ring[i + 1]); 961 } 962 } 963 964 sc_if->sk_cdata.sk_tx_prod = 0; 965 sc_if->sk_cdata.sk_tx_cons = 0; 966 sc_if->sk_cdata.sk_tx_cnt = 0; 967 968 return; 969} 970 971static int 972sk_newbuf(sc_if, c, m) 973 struct sk_if_softc *sc_if; 974 struct sk_chain *c; 975 struct mbuf *m; 976{ 977 struct mbuf *m_new = NULL; 978 struct sk_rx_desc *r; 979 980 if (m == NULL) { 981 caddr_t *buf = NULL; 982 983 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 984 if (m_new == NULL) 985 return(ENOBUFS); 986 987 /* Allocate the jumbo buffer */ 988 buf = sk_jalloc(sc_if); 989 if (buf == NULL) { 990 m_freem(m_new); 991#ifdef SK_VERBOSE 992 printf("sk%d: jumbo allocation failed " 993 "-- packet dropped!\n", sc_if->sk_unit); 994#endif 995 return(ENOBUFS); 996 } 997 998 /* Attach the buffer to the mbuf */ 999 MEXTADD(m_new, buf, SK_JLEN, sk_jfree, 1000 (struct sk_if_softc *)sc_if, 0, EXT_NET_DRV); 1001 m_new->m_data = (void *)buf; 1002 m_new->m_pkthdr.len = m_new->m_len = SK_JLEN; 1003 } else { 1004 /* 1005 * We're re-using a previously allocated mbuf; 1006 * be sure to re-init pointers and lengths to 1007 * default values. 1008 */ 1009 m_new = m; 1010 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 1011 m_new->m_data = m_new->m_ext.ext_buf; 1012 } 1013 1014 /* 1015 * Adjust alignment so packet payload begins on a 1016 * longword boundary. Mandatory for Alpha, useful on 1017 * x86 too. 1018 */ 1019 m_adj(m_new, ETHER_ALIGN); 1020 1021 r = c->sk_desc; 1022 c->sk_mbuf = m_new; 1023 r->sk_data_lo = vtophys(mtod(m_new, caddr_t)); 1024 r->sk_ctl = m_new->m_len | SK_RXSTAT; 1025 1026 return(0); 1027} 1028 1029/* 1030 * Allocate jumbo buffer storage. The SysKonnect adapters support 1031 * "jumbograms" (9K frames), although SysKonnect doesn't currently 1032 * use them in their drivers. In order for us to use them, we need 1033 * large 9K receive buffers, however standard mbuf clusters are only 1034 * 2048 bytes in size. Consequently, we need to allocate and manage 1035 * our own jumbo buffer pool. Fortunately, this does not require an 1036 * excessive amount of additional code. 1037 */ 1038static int 1039sk_alloc_jumbo_mem(sc_if) 1040 struct sk_if_softc *sc_if; 1041{ 1042 caddr_t ptr; 1043 register int i; 1044 struct sk_jpool_entry *entry; 1045 1046 /* Grab a big chunk o' storage. */ 1047 sc_if->sk_cdata.sk_jumbo_buf = contigmalloc(SK_JMEM, M_DEVBUF, 1048 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1049 1050 if (sc_if->sk_cdata.sk_jumbo_buf == NULL) { 1051 printf("sk%d: no memory for jumbo buffers!\n", sc_if->sk_unit); 1052 return(ENOBUFS); 1053 } 1054 1055 SLIST_INIT(&sc_if->sk_jfree_listhead); 1056 SLIST_INIT(&sc_if->sk_jinuse_listhead); 1057 1058 /* 1059 * Now divide it up into 9K pieces and save the addresses 1060 * in an array. 1061 */ 1062 ptr = sc_if->sk_cdata.sk_jumbo_buf; 1063 for (i = 0; i < SK_JSLOTS; i++) { 1064 sc_if->sk_cdata.sk_jslots[i] = ptr; 1065 ptr += SK_JLEN; 1066 entry = malloc(sizeof(struct sk_jpool_entry), 1067 M_DEVBUF, M_NOWAIT); 1068 if (entry == NULL) { 1069 free(sc_if->sk_cdata.sk_jumbo_buf, M_DEVBUF); 1070 sc_if->sk_cdata.sk_jumbo_buf = NULL; 1071 printf("sk%d: no memory for jumbo " 1072 "buffer queue!\n", sc_if->sk_unit); 1073 return(ENOBUFS); 1074 } 1075 entry->slot = i; 1076 SLIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 1077 entry, jpool_entries); 1078 } 1079 1080 return(0); 1081} 1082 1083/* 1084 * Allocate a jumbo buffer. 1085 */ 1086static void * 1087sk_jalloc(sc_if) 1088 struct sk_if_softc *sc_if; 1089{ 1090 struct sk_jpool_entry *entry; 1091 1092 entry = SLIST_FIRST(&sc_if->sk_jfree_listhead); 1093 1094 if (entry == NULL) { 1095#ifdef SK_VERBOSE 1096 printf("sk%d: no free jumbo buffers\n", sc_if->sk_unit); 1097#endif 1098 return(NULL); 1099 } 1100 1101 SLIST_REMOVE_HEAD(&sc_if->sk_jfree_listhead, jpool_entries); 1102 SLIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 1103 return(sc_if->sk_cdata.sk_jslots[entry->slot]); 1104} 1105 1106/* 1107 * Release a jumbo buffer. 1108 */ 1109static void 1110sk_jfree(buf, args) 1111 void *buf; 1112 void *args; 1113{ 1114 struct sk_if_softc *sc_if; 1115 int i; 1116 struct sk_jpool_entry *entry; 1117 1118 /* Extract the softc struct pointer. */ 1119 sc_if = (struct sk_if_softc *)args; 1120 1121 if (sc_if == NULL) 1122 panic("sk_jfree: didn't get softc pointer!"); 1123 1124 /* calculate the slot this buffer belongs to */ 1125 i = ((vm_offset_t)buf 1126 - (vm_offset_t)sc_if->sk_cdata.sk_jumbo_buf) / SK_JLEN; 1127 1128 if ((i < 0) || (i >= SK_JSLOTS)) 1129 panic("sk_jfree: asked to free buffer that we don't manage!"); 1130 1131 entry = SLIST_FIRST(&sc_if->sk_jinuse_listhead); 1132 if (entry == NULL) 1133 panic("sk_jfree: buffer not in use!"); 1134 entry->slot = i; 1135 SLIST_REMOVE_HEAD(&sc_if->sk_jinuse_listhead, jpool_entries); 1136 SLIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, entry, jpool_entries); 1137 1138 return; 1139} 1140 1141/* 1142 * Set media options. 1143 */ 1144static int 1145sk_ifmedia_upd(ifp) 1146 struct ifnet *ifp; 1147{ 1148 struct sk_if_softc *sc_if = ifp->if_softc; 1149 struct mii_data *mii; 1150 1151 mii = device_get_softc(sc_if->sk_miibus); 1152 sk_init(sc_if); 1153 mii_mediachg(mii); 1154 1155 return(0); 1156} 1157 1158/* 1159 * Report current media status. 1160 */ 1161static void 1162sk_ifmedia_sts(ifp, ifmr) 1163 struct ifnet *ifp; 1164 struct ifmediareq *ifmr; 1165{ 1166 struct sk_if_softc *sc_if; 1167 struct mii_data *mii; 1168 1169 sc_if = ifp->if_softc; 1170 mii = device_get_softc(sc_if->sk_miibus); 1171 1172 mii_pollstat(mii); 1173 ifmr->ifm_active = mii->mii_media_active; 1174 ifmr->ifm_status = mii->mii_media_status; 1175 1176 return; 1177} 1178 1179static int 1180sk_ioctl(ifp, command, data) 1181 struct ifnet *ifp; 1182 u_long command; 1183 caddr_t data; 1184{ 1185 struct sk_if_softc *sc_if = ifp->if_softc; 1186 struct ifreq *ifr = (struct ifreq *) data; 1187 int error = 0; 1188 struct mii_data *mii; 1189 1190 SK_IF_LOCK(sc_if); 1191 1192 switch(command) { 1193 case SIOCSIFMTU: 1194 if (ifr->ifr_mtu > SK_JUMBO_MTU) 1195 error = EINVAL; 1196 else { 1197 ifp->if_mtu = ifr->ifr_mtu; 1198 sk_init(sc_if); 1199 } 1200 break; 1201 case SIOCSIFFLAGS: 1202 if (ifp->if_flags & IFF_UP) { 1203 if (ifp->if_flags & IFF_RUNNING) { 1204 if ((ifp->if_flags ^ sc_if->sk_if_flags) 1205 & IFF_PROMISC) { 1206 sk_setpromisc(sc_if); 1207 sk_setmulti(sc_if); 1208 } 1209 } else 1210 sk_init(sc_if); 1211 } else { 1212 if (ifp->if_flags & IFF_RUNNING) 1213 sk_stop(sc_if); 1214 } 1215 sc_if->sk_if_flags = ifp->if_flags; 1216 error = 0; 1217 break; 1218 case SIOCADDMULTI: 1219 case SIOCDELMULTI: 1220 sk_setmulti(sc_if); 1221 error = 0; 1222 break; 1223 case SIOCGIFMEDIA: 1224 case SIOCSIFMEDIA: 1225 mii = device_get_softc(sc_if->sk_miibus); 1226 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1227 break; 1228 default: 1229 error = ether_ioctl(ifp, command, data); 1230 break; 1231 } 1232 1233 SK_IF_UNLOCK(sc_if); 1234 1235 return(error); 1236} 1237 1238/* 1239 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device 1240 * IDs against our list and return a device name if we find a match. 1241 */ 1242static int 1243skc_probe(dev) 1244 device_t dev; 1245{ 1246 struct sk_softc *sc; 1247 struct sk_type *t = sk_devs; 1248 1249 sc = device_get_softc(dev); 1250 1251 while(t->sk_name != NULL) { 1252 if ((pci_get_vendor(dev) == t->sk_vid) && 1253 (pci_get_device(dev) == t->sk_did)) { 1254 device_set_desc(dev, t->sk_name); 1255 return(0); 1256 } 1257 t++; 1258 } 1259 1260 return(ENXIO); 1261} 1262 1263/* 1264 * Force the GEnesis into reset, then bring it out of reset. 1265 */ 1266static void 1267sk_reset(sc) 1268 struct sk_softc *sc; 1269{ 1270 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET); 1271 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET); 1272 if (sc->sk_type == SK_YUKON) 1273 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 1274 1275 DELAY(1000); 1276 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET); 1277 DELAY(2); 1278 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 1279 if (sc->sk_type == SK_YUKON) 1280 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 1281 1282 if (sc->sk_type == SK_GENESIS) { 1283 /* Configure packet arbiter */ 1284 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET); 1285 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT); 1286 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT); 1287 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT); 1288 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT); 1289 } 1290 1291 /* Enable RAM interface */ 1292 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 1293 1294 /* 1295 * Configure interrupt moderation. The moderation timer 1296 * defers interrupts specified in the interrupt moderation 1297 * timer mask based on the timeout specified in the interrupt 1298 * moderation timer init register. Each bit in the timer 1299 * register represents 18.825ns, so to specify a timeout in 1300 * microseconds, we have to multiply by 54. 1301 */ 1302 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(200)); 1303 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 1304 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 1305 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 1306 1307 return; 1308} 1309 1310static int 1311sk_probe(dev) 1312 device_t dev; 1313{ 1314 struct sk_softc *sc; 1315 1316 sc = device_get_softc(device_get_parent(dev)); 1317 1318 /* 1319 * Not much to do here. We always know there will be 1320 * at least one XMAC present, and if there are two, 1321 * skc_attach() will create a second device instance 1322 * for us. 1323 */ 1324 switch (sc->sk_type) { 1325 case SK_GENESIS: 1326 device_set_desc(dev, "XaQti Corp. XMAC II"); 1327 break; 1328 case SK_YUKON: 1329 device_set_desc(dev, "Marvell Semiconductor, Inc. Yukon"); 1330 break; 1331 } 1332 1333 return(0); 1334} 1335 1336/* 1337 * Each XMAC chip is attached as a separate logical IP interface. 1338 * Single port cards will have only one logical interface of course. 1339 */ 1340static int 1341sk_attach(dev) 1342 device_t dev; 1343{ 1344 struct sk_softc *sc; 1345 struct sk_if_softc *sc_if; 1346 struct ifnet *ifp; 1347 int i, port, error; 1348 1349 if (dev == NULL) 1350 return(EINVAL); 1351 1352 error = 0; 1353 sc_if = device_get_softc(dev); 1354 sc = device_get_softc(device_get_parent(dev)); 1355 SK_LOCK(sc); 1356 port = *(int *)device_get_ivars(dev); 1357 free(device_get_ivars(dev), M_DEVBUF); 1358 device_set_ivars(dev, NULL); 1359 1360 sc_if->sk_dev = dev; 1361 sc_if->sk_unit = device_get_unit(dev); 1362 sc_if->sk_port = port; 1363 sc_if->sk_softc = sc; 1364 sc->sk_if[port] = sc_if; 1365 if (port == SK_PORT_A) 1366 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0; 1367 if (port == SK_PORT_B) 1368 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1; 1369 1370 /* 1371 * Get station address for this interface. Note that 1372 * dual port cards actually come with three station 1373 * addresses: one for each port, plus an extra. The 1374 * extra one is used by the SysKonnect driver software 1375 * as a 'virtual' station address for when both ports 1376 * are operating in failover mode. Currently we don't 1377 * use this extra address. 1378 */ 1379 for (i = 0; i < ETHER_ADDR_LEN; i++) 1380 sc_if->arpcom.ac_enaddr[i] = 1381 sk_win_read_1(sc, SK_MAC0_0 + (port * 8) + i); 1382 1383 /* 1384 * Set up RAM buffer addresses. The NIC will have a certain 1385 * amount of SRAM on it, somewhere between 512K and 2MB. We 1386 * need to divide this up a) between the transmitter and 1387 * receiver and b) between the two XMACs, if this is a 1388 * dual port NIC. Our algotithm is to divide up the memory 1389 * evenly so that everyone gets a fair share. 1390 */ 1391 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) { 1392 u_int32_t chunk, val; 1393 1394 chunk = sc->sk_ramsize / 2; 1395 val = sc->sk_rboff / sizeof(u_int64_t); 1396 sc_if->sk_rx_ramstart = val; 1397 val += (chunk / sizeof(u_int64_t)); 1398 sc_if->sk_rx_ramend = val - 1; 1399 sc_if->sk_tx_ramstart = val; 1400 val += (chunk / sizeof(u_int64_t)); 1401 sc_if->sk_tx_ramend = val - 1; 1402 } else { 1403 u_int32_t chunk, val; 1404 1405 chunk = sc->sk_ramsize / 4; 1406 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) / 1407 sizeof(u_int64_t); 1408 sc_if->sk_rx_ramstart = val; 1409 val += (chunk / sizeof(u_int64_t)); 1410 sc_if->sk_rx_ramend = val - 1; 1411 sc_if->sk_tx_ramstart = val; 1412 val += (chunk / sizeof(u_int64_t)); 1413 sc_if->sk_tx_ramend = val - 1; 1414 } 1415 1416 /* Read and save PHY type and set PHY address */ 1417 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 1418 switch(sc_if->sk_phytype) { 1419 case SK_PHYTYPE_XMAC: 1420 sc_if->sk_phyaddr = SK_PHYADDR_XMAC; 1421 break; 1422 case SK_PHYTYPE_BCOM: 1423 sc_if->sk_phyaddr = SK_PHYADDR_BCOM; 1424 break; 1425 case SK_PHYTYPE_MARV_COPPER: 1426 sc_if->sk_phyaddr = SK_PHYADDR_MARV; 1427 break; 1428 default: 1429 printf("skc%d: unsupported PHY type: %d\n", 1430 sc->sk_unit, sc_if->sk_phytype); 1431 error = ENODEV; 1432 goto fail; 1433 } 1434 1435 /* Allocate the descriptor queues. */ 1436 sc_if->sk_rdata = contigmalloc(sizeof(struct sk_ring_data), M_DEVBUF, 1437 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1438 1439 if (sc_if->sk_rdata == NULL) { 1440 printf("sk%d: no memory for list buffers!\n", sc_if->sk_unit); 1441 error = ENOMEM; 1442 goto fail; 1443 } 1444 1445 bzero(sc_if->sk_rdata, sizeof(struct sk_ring_data)); 1446 1447 /* Try to allocate memory for jumbo buffers. */ 1448 if (sk_alloc_jumbo_mem(sc_if)) { 1449 printf("sk%d: jumbo buffer allocation failed\n", 1450 sc_if->sk_unit); 1451 error = ENOMEM; 1452 goto fail; 1453 } 1454 1455 ifp = &sc_if->arpcom.ac_if; 1456 ifp->if_softc = sc_if; 1457 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1458 ifp->if_mtu = ETHERMTU; 1459 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1460 ifp->if_ioctl = sk_ioctl; 1461 ifp->if_start = sk_start; 1462 ifp->if_watchdog = sk_watchdog; 1463 ifp->if_init = sk_init; 1464 ifp->if_baudrate = 1000000000; 1465 ifp->if_snd.ifq_maxlen = SK_TX_RING_CNT - 1; 1466 1467 callout_handle_init(&sc_if->sk_tick_ch); 1468 1469 /* 1470 * Call MI attach routine. 1471 */ 1472 ether_ifattach(ifp, sc_if->arpcom.ac_enaddr); 1473 1474 /* 1475 * Do miibus setup. 1476 */ 1477 switch (sc->sk_type) { 1478 case SK_GENESIS: 1479 sk_init_xmac(sc_if); 1480 break; 1481 case SK_YUKON: 1482 sk_init_yukon(sc_if); 1483 break; 1484 } 1485 1486 if (mii_phy_probe(dev, &sc_if->sk_miibus, 1487 sk_ifmedia_upd, sk_ifmedia_sts)) { 1488 printf("skc%d: no PHY found!\n", sc_if->sk_unit); 1489 ether_ifdetach(ifp); 1490 error = ENXIO; 1491 goto fail; 1492 } 1493 1494fail: 1495 SK_UNLOCK(sc); 1496 if (error) { 1497 /* Access should be ok even though lock has been dropped */ 1498 sc->sk_if[port] = NULL; 1499 sk_detach(dev); 1500 } 1501 1502 return(error); 1503} 1504 1505/* 1506 * Attach the interface. Allocate softc structures, do ifmedia 1507 * setup and ethernet/BPF attach. 1508 */ 1509static int 1510skc_attach(dev) 1511 device_t dev; 1512{ 1513 struct sk_softc *sc; 1514 int unit, error = 0, rid, *port; 1515 1516 sc = device_get_softc(dev); 1517 unit = device_get_unit(dev); 1518 1519 mtx_init(&sc->sk_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1520 MTX_DEF | MTX_RECURSE); 1521#ifndef BURN_BRIDGES 1522 /* 1523 * Handle power management nonsense. 1524 */ 1525 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1526 u_int32_t iobase, membase, irq; 1527 1528 /* Save important PCI config data. */ 1529 iobase = pci_read_config(dev, SK_PCI_LOIO, 4); 1530 membase = pci_read_config(dev, SK_PCI_LOMEM, 4); 1531 irq = pci_read_config(dev, SK_PCI_INTLINE, 4); 1532 1533 /* Reset the power state. */ 1534 printf("skc%d: chip is in D%d power mode " 1535 "-- setting to D0\n", unit, 1536 pci_get_powerstate(dev)); 1537 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1538 1539 /* Restore PCI config data. */ 1540 pci_write_config(dev, SK_PCI_LOIO, iobase, 4); 1541 pci_write_config(dev, SK_PCI_LOMEM, membase, 4); 1542 pci_write_config(dev, SK_PCI_INTLINE, irq, 4); 1543 } 1544#endif 1545 /* 1546 * Map control/status registers. 1547 */ 1548 pci_enable_busmaster(dev); 1549 1550 rid = SK_RID; 1551 sc->sk_res = bus_alloc_resource_any(dev, SK_RES, &rid, RF_ACTIVE); 1552 1553 if (sc->sk_res == NULL) { 1554 printf("sk%d: couldn't map ports/memory\n", unit); 1555 error = ENXIO; 1556 goto fail; 1557 } 1558 1559 sc->sk_btag = rman_get_bustag(sc->sk_res); 1560 sc->sk_bhandle = rman_get_bushandle(sc->sk_res); 1561 1562 /* Allocate interrupt */ 1563 rid = 0; 1564 sc->sk_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1565 RF_SHAREABLE | RF_ACTIVE); 1566 1567 if (sc->sk_irq == NULL) { 1568 printf("skc%d: couldn't map interrupt\n", unit); 1569 error = ENXIO; 1570 goto fail; 1571 } 1572 1573 /* Set adapter type */ 1574 switch (pci_get_device(dev)) { 1575 case DEVICEID_SK_V1: 1576 sc->sk_type = SK_GENESIS; 1577 break; 1578 case DEVICEID_SK_V2: 1579 case DEVICEID_3COM_3C940: 1580 case DEVICEID_LINKSYS_EG1032: 1581 case DEVICEID_DLINK_DGE530T: 1582 sc->sk_type = SK_YUKON; 1583 break; 1584 default: 1585 printf("skc%d: unknown device!\n", unit); 1586 error = ENXIO; 1587 goto fail; 1588 } 1589 1590 /* Reset the adapter. */ 1591 sk_reset(sc); 1592 1593 sc->sk_unit = unit; 1594 1595 /* Read and save vital product data from EEPROM. */ 1596 sk_vpd_read(sc); 1597 1598 if (sc->sk_type == SK_GENESIS) { 1599 /* Read and save RAM size and RAMbuffer offset */ 1600 switch(sk_win_read_1(sc, SK_EPROM0)) { 1601 case SK_RAMSIZE_512K_64: 1602 sc->sk_ramsize = 0x80000; 1603 sc->sk_rboff = SK_RBOFF_0; 1604 break; 1605 case SK_RAMSIZE_1024K_64: 1606 sc->sk_ramsize = 0x100000; 1607 sc->sk_rboff = SK_RBOFF_80000; 1608 break; 1609 case SK_RAMSIZE_1024K_128: 1610 sc->sk_ramsize = 0x100000; 1611 sc->sk_rboff = SK_RBOFF_0; 1612 break; 1613 case SK_RAMSIZE_2048K_128: 1614 sc->sk_ramsize = 0x200000; 1615 sc->sk_rboff = SK_RBOFF_0; 1616 break; 1617 default: 1618 printf("skc%d: unknown ram size: %d\n", 1619 sc->sk_unit, sk_win_read_1(sc, SK_EPROM0)); 1620 error = ENXIO; 1621 goto fail; 1622 } 1623 } else { 1624 sc->sk_ramsize = 0x20000; 1625 sc->sk_rboff = SK_RBOFF_0; 1626 } 1627 1628 /* Read and save physical media type */ 1629 switch(sk_win_read_1(sc, SK_PMDTYPE)) { 1630 case SK_PMD_1000BASESX: 1631 sc->sk_pmd = IFM_1000_SX; 1632 break; 1633 case SK_PMD_1000BASELX: 1634 sc->sk_pmd = IFM_1000_LX; 1635 break; 1636 case SK_PMD_1000BASECX: 1637 sc->sk_pmd = IFM_1000_CX; 1638 break; 1639 case SK_PMD_1000BASETX: 1640 sc->sk_pmd = IFM_1000_T; 1641 break; 1642 default: 1643 printf("skc%d: unknown media type: 0x%x\n", 1644 sc->sk_unit, sk_win_read_1(sc, SK_PMDTYPE)); 1645 error = ENXIO; 1646 goto fail; 1647 } 1648 1649 /* Announce the product name. */ 1650 if (sc->sk_vpd_prodname != NULL) 1651 printf("skc%d: %s\n", sc->sk_unit, sc->sk_vpd_prodname); 1652 sc->sk_devs[SK_PORT_A] = device_add_child(dev, "sk", -1); 1653 port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT); 1654 *port = SK_PORT_A; 1655 device_set_ivars(sc->sk_devs[SK_PORT_A], port); 1656 1657 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) { 1658 sc->sk_devs[SK_PORT_B] = device_add_child(dev, "sk", -1); 1659 port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT); 1660 *port = SK_PORT_B; 1661 device_set_ivars(sc->sk_devs[SK_PORT_B], port); 1662 } 1663 1664 /* Turn on the 'driver is loaded' LED. */ 1665 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1666 1667 bus_generic_attach(dev); 1668 1669 /* Hook interrupt last to avoid having to lock softc */ 1670 error = bus_setup_intr(dev, sc->sk_irq, INTR_TYPE_NET, 1671 sk_intr, sc, &sc->sk_intrhand); 1672 1673 if (error) { 1674 printf("skc%d: couldn't set up irq\n", unit); 1675 goto fail; 1676 } 1677 1678fail: 1679 if (error) 1680 skc_detach(dev); 1681 1682 return(error); 1683} 1684 1685/* 1686 * Shutdown hardware and free up resources. This can be called any 1687 * time after the mutex has been initialized. It is called in both 1688 * the error case in attach and the normal detach case so it needs 1689 * to be careful about only freeing resources that have actually been 1690 * allocated. 1691 */ 1692static int 1693sk_detach(dev) 1694 device_t dev; 1695{ 1696 struct sk_if_softc *sc_if; 1697 struct ifnet *ifp; 1698 1699 sc_if = device_get_softc(dev); 1700 KASSERT(mtx_initialized(&sc_if->sk_softc->sk_mtx), 1701 ("sk mutex not initialized in sk_detach")); 1702 SK_IF_LOCK(sc_if); 1703 1704 ifp = &sc_if->arpcom.ac_if; 1705 /* These should only be active if attach_xmac succeeded */ 1706 if (device_is_attached(dev)) { 1707 sk_stop(sc_if); 1708 ether_ifdetach(ifp); 1709 } 1710 if (sc_if->sk_miibus) 1711 device_delete_child(dev, sc_if->sk_miibus); 1712 bus_generic_detach(dev); 1713 if (sc_if->sk_cdata.sk_jumbo_buf) 1714 contigfree(sc_if->sk_cdata.sk_jumbo_buf, SK_JMEM, M_DEVBUF); 1715 if (sc_if->sk_rdata) { 1716 contigfree(sc_if->sk_rdata, sizeof(struct sk_ring_data), 1717 M_DEVBUF); 1718 } 1719 SK_IF_UNLOCK(sc_if); 1720 1721 return(0); 1722} 1723 1724static int 1725skc_detach(dev) 1726 device_t dev; 1727{ 1728 struct sk_softc *sc; 1729 1730 sc = device_get_softc(dev); 1731 KASSERT(mtx_initialized(&sc->sk_mtx), ("sk mutex not initialized")); 1732 SK_LOCK(sc); 1733 1734 if (device_is_alive(dev)) { 1735 if (sc->sk_devs[SK_PORT_A] != NULL) 1736 device_delete_child(dev, sc->sk_devs[SK_PORT_A]); 1737 if (sc->sk_devs[SK_PORT_B] != NULL) 1738 device_delete_child(dev, sc->sk_devs[SK_PORT_B]); 1739 bus_generic_detach(dev); 1740 } 1741 1742 if (sc->sk_intrhand) 1743 bus_teardown_intr(dev, sc->sk_irq, sc->sk_intrhand); 1744 if (sc->sk_irq) 1745 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq); 1746 if (sc->sk_res) 1747 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res); 1748 1749 SK_UNLOCK(sc); 1750 mtx_destroy(&sc->sk_mtx); 1751 1752 return(0); 1753} 1754 1755static int 1756sk_encap(sc_if, m_head, txidx) 1757 struct sk_if_softc *sc_if; 1758 struct mbuf *m_head; 1759 u_int32_t *txidx; 1760{ 1761 struct sk_tx_desc *f = NULL; 1762 struct mbuf *m; 1763 u_int32_t frag, cur, cnt = 0; 1764 1765 m = m_head; 1766 cur = frag = *txidx; 1767 1768 /* 1769 * Start packing the mbufs in this chain into 1770 * the fragment pointers. Stop when we run out 1771 * of fragments or hit the end of the mbuf chain. 1772 */ 1773 for (m = m_head; m != NULL; m = m->m_next) { 1774 if (m->m_len != 0) { 1775 if ((SK_TX_RING_CNT - 1776 (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2) 1777 return(ENOBUFS); 1778 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1779 f->sk_data_lo = vtophys(mtod(m, vm_offset_t)); 1780 f->sk_ctl = m->m_len | SK_OPCODE_DEFAULT; 1781 if (cnt == 0) 1782 f->sk_ctl |= SK_TXCTL_FIRSTFRAG; 1783 else 1784 f->sk_ctl |= SK_TXCTL_OWN; 1785 cur = frag; 1786 SK_INC(frag, SK_TX_RING_CNT); 1787 cnt++; 1788 } 1789 } 1790 1791 if (m != NULL) 1792 return(ENOBUFS); 1793 1794 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= 1795 SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR; 1796 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1797 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |= SK_TXCTL_OWN; 1798 sc_if->sk_cdata.sk_tx_cnt += cnt; 1799 1800 *txidx = frag; 1801 1802 return(0); 1803} 1804 1805static void 1806sk_start(ifp) 1807 struct ifnet *ifp; 1808{ 1809 struct sk_softc *sc; 1810 struct sk_if_softc *sc_if; 1811 struct mbuf *m_head = NULL; 1812 u_int32_t idx; 1813 1814 sc_if = ifp->if_softc; 1815 sc = sc_if->sk_softc; 1816 1817 SK_IF_LOCK(sc_if); 1818 1819 idx = sc_if->sk_cdata.sk_tx_prod; 1820 1821 while(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1822 IF_DEQUEUE(&ifp->if_snd, m_head); 1823 if (m_head == NULL) 1824 break; 1825 1826 /* 1827 * Pack the data into the transmit ring. If we 1828 * don't have room, set the OACTIVE flag and wait 1829 * for the NIC to drain the ring. 1830 */ 1831 if (sk_encap(sc_if, m_head, &idx)) { 1832 IF_PREPEND(&ifp->if_snd, m_head); 1833 ifp->if_flags |= IFF_OACTIVE; 1834 break; 1835 } 1836 1837 /* 1838 * If there's a BPF listener, bounce a copy of this frame 1839 * to him. 1840 */ 1841 BPF_MTAP(ifp, m_head); 1842 } 1843 1844 /* Transmit */ 1845 sc_if->sk_cdata.sk_tx_prod = idx; 1846 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 1847 1848 /* Set a timeout in case the chip goes out to lunch. */ 1849 ifp->if_timer = 5; 1850 SK_IF_UNLOCK(sc_if); 1851 1852 return; 1853} 1854 1855 1856static void 1857sk_watchdog(ifp) 1858 struct ifnet *ifp; 1859{ 1860 struct sk_if_softc *sc_if; 1861 1862 sc_if = ifp->if_softc; 1863 1864 printf("sk%d: watchdog timeout\n", sc_if->sk_unit); 1865 sk_init(sc_if); 1866 1867 return; 1868} 1869 1870static void 1871skc_shutdown(dev) 1872 device_t dev; 1873{ 1874 struct sk_softc *sc; 1875 1876 sc = device_get_softc(dev); 1877 SK_LOCK(sc); 1878 1879 /* Turn off the 'driver is loaded' LED. */ 1880 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 1881 1882 /* 1883 * Reset the GEnesis controller. Doing this should also 1884 * assert the resets on the attached XMAC(s). 1885 */ 1886 sk_reset(sc); 1887 SK_UNLOCK(sc); 1888 1889 return; 1890} 1891 1892static void 1893sk_rxeof(sc_if) 1894 struct sk_if_softc *sc_if; 1895{ 1896 struct sk_softc *sc; 1897 struct mbuf *m; 1898 struct ifnet *ifp; 1899 struct sk_chain *cur_rx; 1900 int total_len = 0; 1901 int i; 1902 u_int32_t rxstat; 1903 1904 sc = sc_if->sk_softc; 1905 ifp = &sc_if->arpcom.ac_if; 1906 i = sc_if->sk_cdata.sk_rx_prod; 1907 cur_rx = &sc_if->sk_cdata.sk_rx_chain[i]; 1908 1909 SK_LOCK_ASSERT(sc); 1910 1911 while(!(sc_if->sk_rdata->sk_rx_ring[i].sk_ctl & SK_RXCTL_OWN)) { 1912 1913 cur_rx = &sc_if->sk_cdata.sk_rx_chain[i]; 1914 rxstat = sc_if->sk_rdata->sk_rx_ring[i].sk_xmac_rxstat; 1915 m = cur_rx->sk_mbuf; 1916 cur_rx->sk_mbuf = NULL; 1917 total_len = SK_RXBYTES(sc_if->sk_rdata->sk_rx_ring[i].sk_ctl); 1918 SK_INC(i, SK_RX_RING_CNT); 1919 1920 if (rxstat & XM_RXSTAT_ERRFRAME) { 1921 ifp->if_ierrors++; 1922 sk_newbuf(sc_if, cur_rx, m); 1923 continue; 1924 } 1925 1926 /* 1927 * Try to allocate a new jumbo buffer. If that 1928 * fails, copy the packet to mbufs and put the 1929 * jumbo buffer back in the ring so it can be 1930 * re-used. If allocating mbufs fails, then we 1931 * have to drop the packet. 1932 */ 1933 if (sk_newbuf(sc_if, cur_rx, NULL) == ENOBUFS) { 1934 struct mbuf *m0; 1935 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, 1936 ifp, NULL); 1937 sk_newbuf(sc_if, cur_rx, m); 1938 if (m0 == NULL) { 1939 printf("sk%d: no receive buffers " 1940 "available -- packet dropped!\n", 1941 sc_if->sk_unit); 1942 ifp->if_ierrors++; 1943 continue; 1944 } 1945 m = m0; 1946 } else { 1947 m->m_pkthdr.rcvif = ifp; 1948 m->m_pkthdr.len = m->m_len = total_len; 1949 } 1950 1951 ifp->if_ipackets++; 1952 SK_UNLOCK(sc); 1953 (*ifp->if_input)(ifp, m); 1954 SK_LOCK(sc); 1955 } 1956 1957 sc_if->sk_cdata.sk_rx_prod = i; 1958 1959 return; 1960} 1961 1962static void 1963sk_txeof(sc_if) 1964 struct sk_if_softc *sc_if; 1965{ 1966 struct sk_tx_desc *cur_tx = NULL; 1967 struct ifnet *ifp; 1968 u_int32_t idx; 1969 1970 ifp = &sc_if->arpcom.ac_if; 1971 1972 /* 1973 * Go through our tx ring and free mbufs for those 1974 * frames that have been sent. 1975 */ 1976 idx = sc_if->sk_cdata.sk_tx_cons; 1977 while(idx != sc_if->sk_cdata.sk_tx_prod) { 1978 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 1979 if (cur_tx->sk_ctl & SK_TXCTL_OWN) 1980 break; 1981 if (cur_tx->sk_ctl & SK_TXCTL_LASTFRAG) 1982 ifp->if_opackets++; 1983 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 1984 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 1985 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 1986 } 1987 sc_if->sk_cdata.sk_tx_cnt--; 1988 SK_INC(idx, SK_TX_RING_CNT); 1989 ifp->if_timer = 0; 1990 } 1991 1992 sc_if->sk_cdata.sk_tx_cons = idx; 1993 1994 if (cur_tx != NULL) 1995 ifp->if_flags &= ~IFF_OACTIVE; 1996 1997 return; 1998} 1999 2000static void 2001sk_tick(xsc_if) 2002 void *xsc_if; 2003{ 2004 struct sk_if_softc *sc_if; 2005 struct mii_data *mii; 2006 struct ifnet *ifp; 2007 int i; 2008 2009 sc_if = xsc_if; 2010 SK_IF_LOCK(sc_if); 2011 ifp = &sc_if->arpcom.ac_if; 2012 mii = device_get_softc(sc_if->sk_miibus); 2013 2014 if (!(ifp->if_flags & IFF_UP)) { 2015 SK_IF_UNLOCK(sc_if); 2016 return; 2017 } 2018 2019 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2020 sk_intr_bcom(sc_if); 2021 SK_IF_UNLOCK(sc_if); 2022 return; 2023 } 2024 2025 /* 2026 * According to SysKonnect, the correct way to verify that 2027 * the link has come back up is to poll bit 0 of the GPIO 2028 * register three times. This pin has the signal from the 2029 * link_sync pin connected to it; if we read the same link 2030 * state 3 times in a row, we know the link is up. 2031 */ 2032 for (i = 0; i < 3; i++) { 2033 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET) 2034 break; 2035 } 2036 2037 if (i != 3) { 2038 sc_if->sk_tick_ch = timeout(sk_tick, sc_if, hz); 2039 SK_IF_UNLOCK(sc_if); 2040 return; 2041 } 2042 2043 /* Turn the GP0 interrupt back on. */ 2044 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2045 SK_XM_READ_2(sc_if, XM_ISR); 2046 mii_tick(mii); 2047 untimeout(sk_tick, sc_if, sc_if->sk_tick_ch); 2048 2049 SK_IF_UNLOCK(sc_if); 2050 return; 2051} 2052 2053static void 2054sk_intr_bcom(sc_if) 2055 struct sk_if_softc *sc_if; 2056{ 2057 struct mii_data *mii; 2058 struct ifnet *ifp; 2059 int status; 2060 mii = device_get_softc(sc_if->sk_miibus); 2061 ifp = &sc_if->arpcom.ac_if; 2062 2063 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2064 2065 /* 2066 * Read the PHY interrupt register to make sure 2067 * we clear any pending interrupts. 2068 */ 2069 status = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, BRGPHY_MII_ISR); 2070 2071 if (!(ifp->if_flags & IFF_RUNNING)) { 2072 sk_init_xmac(sc_if); 2073 return; 2074 } 2075 2076 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) { 2077 int lstat; 2078 lstat = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, 2079 BRGPHY_MII_AUXSTS); 2080 2081 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) { 2082 mii_mediachg(mii); 2083 /* Turn off the link LED. */ 2084 SK_IF_WRITE_1(sc_if, 0, 2085 SK_LINKLED1_CTL, SK_LINKLED_OFF); 2086 sc_if->sk_link = 0; 2087 } else if (status & BRGPHY_ISR_LNK_CHG) { 2088 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 2089 BRGPHY_MII_IMR, 0xFF00); 2090 mii_tick(mii); 2091 sc_if->sk_link = 1; 2092 /* Turn on the link LED. */ 2093 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2094 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF| 2095 SK_LINKLED_BLINK_OFF); 2096 } else { 2097 mii_tick(mii); 2098 sc_if->sk_tick_ch = timeout(sk_tick, sc_if, hz); 2099 } 2100 } 2101 2102 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2103 2104 return; 2105} 2106 2107static void 2108sk_intr_xmac(sc_if) 2109 struct sk_if_softc *sc_if; 2110{ 2111 struct sk_softc *sc; 2112 u_int16_t status; 2113 2114 sc = sc_if->sk_softc; 2115 status = SK_XM_READ_2(sc_if, XM_ISR); 2116 2117 /* 2118 * Link has gone down. Start MII tick timeout to 2119 * watch for link resync. 2120 */ 2121 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) { 2122 if (status & XM_ISR_GP0_SET) { 2123 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2124 sc_if->sk_tick_ch = timeout(sk_tick, sc_if, hz); 2125 } 2126 2127 if (status & XM_ISR_AUTONEG_DONE) { 2128 sc_if->sk_tick_ch = timeout(sk_tick, sc_if, hz); 2129 } 2130 } 2131 2132 if (status & XM_IMR_TX_UNDERRUN) 2133 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO); 2134 2135 if (status & XM_IMR_RX_OVERRUN) 2136 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO); 2137 2138 status = SK_XM_READ_2(sc_if, XM_ISR); 2139 2140 return; 2141} 2142 2143static void 2144sk_intr_yukon(sc_if) 2145 struct sk_if_softc *sc_if; 2146{ 2147 int status; 2148 2149 status = SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2150 2151 return; 2152} 2153 2154static void 2155sk_intr(xsc) 2156 void *xsc; 2157{ 2158 struct sk_softc *sc = xsc; 2159 struct sk_if_softc *sc_if0 = NULL, *sc_if1 = NULL; 2160 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2161 u_int32_t status; 2162 2163 SK_LOCK(sc); 2164 2165 sc_if0 = sc->sk_if[SK_PORT_A]; 2166 sc_if1 = sc->sk_if[SK_PORT_B]; 2167 2168 if (sc_if0 != NULL) 2169 ifp0 = &sc_if0->arpcom.ac_if; 2170 if (sc_if1 != NULL) 2171 ifp1 = &sc_if1->arpcom.ac_if; 2172 2173 for (;;) { 2174 status = CSR_READ_4(sc, SK_ISSR); 2175 if (!(status & sc->sk_intrmask)) 2176 break; 2177 2178 /* Handle receive interrupts first. */ 2179 if (status & SK_ISR_RX1_EOF) { 2180 sk_rxeof(sc_if0); 2181 CSR_WRITE_4(sc, SK_BMU_RX_CSR0, 2182 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2183 } 2184 if (status & SK_ISR_RX2_EOF) { 2185 sk_rxeof(sc_if1); 2186 CSR_WRITE_4(sc, SK_BMU_RX_CSR1, 2187 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2188 } 2189 2190 /* Then transmit interrupts. */ 2191 if (status & SK_ISR_TX1_S_EOF) { 2192 sk_txeof(sc_if0); 2193 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, 2194 SK_TXBMU_CLR_IRQ_EOF); 2195 } 2196 if (status & SK_ISR_TX2_S_EOF) { 2197 sk_txeof(sc_if1); 2198 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, 2199 SK_TXBMU_CLR_IRQ_EOF); 2200 } 2201 2202 /* Then MAC interrupts. */ 2203 if (status & SK_ISR_MAC1 && ifp0->if_flags & IFF_RUNNING) { 2204 if (sc->sk_type == SK_GENESIS) 2205 sk_intr_xmac(sc_if0); 2206 else 2207 sk_intr_yukon(sc_if0); 2208 } 2209 2210 if (status & SK_ISR_MAC2 && ifp1->if_flags & IFF_RUNNING) { 2211 if (sc->sk_type == SK_GENESIS) 2212 sk_intr_xmac(sc_if1); 2213 else 2214 sk_intr_yukon(sc_if1); 2215 } 2216 2217 if (status & SK_ISR_EXTERNAL_REG) { 2218 if (ifp0 != NULL && 2219 sc_if0->sk_phytype == SK_PHYTYPE_BCOM) 2220 sk_intr_bcom(sc_if0); 2221 if (ifp1 != NULL && 2222 sc_if1->sk_phytype == SK_PHYTYPE_BCOM) 2223 sk_intr_bcom(sc_if1); 2224 } 2225 } 2226 2227 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2228 2229 if (ifp0 != NULL && ifp0->if_snd.ifq_head != NULL) 2230 sk_start(ifp0); 2231 if (ifp1 != NULL && ifp1->if_snd.ifq_head != NULL) 2232 sk_start(ifp1); 2233 2234 SK_UNLOCK(sc); 2235 2236 return; 2237} 2238 2239static void 2240sk_init_xmac(sc_if) 2241 struct sk_if_softc *sc_if; 2242{ 2243 struct sk_softc *sc; 2244 struct ifnet *ifp; 2245 struct sk_bcom_hack bhack[] = { 2246 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, 2247 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, 2248 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 2249 { 0, 0 } }; 2250 2251 sc = sc_if->sk_softc; 2252 ifp = &sc_if->arpcom.ac_if; 2253 2254 /* Unreset the XMAC. */ 2255 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET); 2256 DELAY(1000); 2257 2258 /* Reset the XMAC's internal state. */ 2259 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2260 2261 /* Save the XMAC II revision */ 2262 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID)); 2263 2264 /* 2265 * Perform additional initialization for external PHYs, 2266 * namely for the 1000baseTX cards that use the XMAC's 2267 * GMII mode. 2268 */ 2269 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2270 int i = 0; 2271 u_int32_t val; 2272 2273 /* Take PHY out of reset. */ 2274 val = sk_win_read_4(sc, SK_GPIO); 2275 if (sc_if->sk_port == SK_PORT_A) 2276 val |= SK_GPIO_DIR0|SK_GPIO_DAT0; 2277 else 2278 val |= SK_GPIO_DIR2|SK_GPIO_DAT2; 2279 sk_win_write_4(sc, SK_GPIO, val); 2280 2281 /* Enable GMII mode on the XMAC. */ 2282 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE); 2283 2284 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 2285 BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET); 2286 DELAY(10000); 2287 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 2288 BRGPHY_MII_IMR, 0xFFF0); 2289 2290 /* 2291 * Early versions of the BCM5400 apparently have 2292 * a bug that requires them to have their reserved 2293 * registers initialized to some magic values. I don't 2294 * know what the numbers do, I'm just the messenger. 2295 */ 2296 if (sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, 0x03) 2297 == 0x6041) { 2298 while(bhack[i].reg) { 2299 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 2300 bhack[i].reg, bhack[i].val); 2301 i++; 2302 } 2303 } 2304 } 2305 2306 /* Set station address */ 2307 SK_XM_WRITE_2(sc_if, XM_PAR0, 2308 *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[0])); 2309 SK_XM_WRITE_2(sc_if, XM_PAR1, 2310 *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[2])); 2311 SK_XM_WRITE_2(sc_if, XM_PAR2, 2312 *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[4])); 2313 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION); 2314 2315 if (ifp->if_flags & IFF_BROADCAST) { 2316 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2317 } else { 2318 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2319 } 2320 2321 /* We don't need the FCS appended to the packet. */ 2322 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS); 2323 2324 /* We want short frames padded to 60 bytes. */ 2325 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD); 2326 2327 /* 2328 * Enable the reception of all error frames. This is is 2329 * a necessary evil due to the design of the XMAC. The 2330 * XMAC's receive FIFO is only 8K in size, however jumbo 2331 * frames can be up to 9000 bytes in length. When bad 2332 * frame filtering is enabled, the XMAC's RX FIFO operates 2333 * in 'store and forward' mode. For this to work, the 2334 * entire frame has to fit into the FIFO, but that means 2335 * that jumbo frames larger than 8192 bytes will be 2336 * truncated. Disabling all bad frame filtering causes 2337 * the RX FIFO to operate in streaming mode, in which 2338 * case the XMAC will start transfering frames out of the 2339 * RX FIFO as soon as the FIFO threshold is reached. 2340 */ 2341 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES| 2342 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS| 2343 XM_MODE_RX_INRANGELEN); 2344 2345 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2346 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2347 else 2348 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2349 2350 /* 2351 * Bump up the transmit threshold. This helps hold off transmit 2352 * underruns when we're blasting traffic from both ports at once. 2353 */ 2354 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH); 2355 2356 /* Set promiscuous mode */ 2357 sk_setpromisc(sc_if); 2358 2359 /* Set multicast filter */ 2360 sk_setmulti(sc_if); 2361 2362 /* Clear and enable interrupts */ 2363 SK_XM_READ_2(sc_if, XM_ISR); 2364 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 2365 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS); 2366 else 2367 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2368 2369 /* Configure MAC arbiter */ 2370 switch(sc_if->sk_xmac_rev) { 2371 case XM_XMAC_REV_B2: 2372 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2); 2373 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2); 2374 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2); 2375 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2); 2376 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2); 2377 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2); 2378 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2); 2379 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2); 2380 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2381 break; 2382 case XM_XMAC_REV_C1: 2383 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1); 2384 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1); 2385 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1); 2386 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1); 2387 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1); 2388 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1); 2389 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1); 2390 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1); 2391 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2392 break; 2393 default: 2394 break; 2395 } 2396 sk_win_write_2(sc, SK_MACARB_CTL, 2397 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF); 2398 2399 sc_if->sk_link = 1; 2400 2401 return; 2402} 2403 2404static void sk_init_yukon(sc_if) 2405 struct sk_if_softc *sc_if; 2406{ 2407 u_int32_t phy; 2408 u_int16_t reg; 2409 int i; 2410 2411 /* GMAC and GPHY Reset */ 2412 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 2413 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2414 DELAY(1000); 2415 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_CLEAR); 2416 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2417 DELAY(1000); 2418 2419 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP | 2420 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE; 2421 2422 switch(sc_if->sk_softc->sk_pmd) { 2423 case IFM_1000_SX: 2424 case IFM_1000_LX: 2425 phy |= SK_GPHY_FIBER; 2426 break; 2427 2428 case IFM_1000_CX: 2429 case IFM_1000_T: 2430 phy |= SK_GPHY_COPPER; 2431 break; 2432 } 2433 2434 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET); 2435 DELAY(1000); 2436 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR); 2437 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 2438 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 2439 2440 /* unused read of the interrupt source register */ 2441 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2442 2443 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2444 2445 /* MIB Counter Clear Mode set */ 2446 reg |= YU_PAR_MIB_CLR; 2447 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2448 2449 /* MIB Counter Clear Mode clear */ 2450 reg &= ~YU_PAR_MIB_CLR; 2451 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2452 2453 /* receive control reg */ 2454 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR); 2455 2456 /* transmit parameter register */ 2457 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2458 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) ); 2459 2460 /* serial mode register */ 2461 SK_YU_WRITE_2(sc_if, YUKON_SMR, YU_SMR_DATA_BLIND(0x1c) | 2462 YU_SMR_MFL_VLAN | YU_SMR_IPG_DATA(0x1e)); 2463 2464 /* Setup Yukon's address */ 2465 for (i = 0; i < 3; i++) { 2466 /* Write Source Address 1 (unicast filter) */ 2467 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2468 sc_if->arpcom.ac_enaddr[i * 2] | 2469 sc_if->arpcom.ac_enaddr[i * 2 + 1] << 8); 2470 } 2471 2472 for (i = 0; i < 3; i++) { 2473 reg = sk_win_read_2(sc_if->sk_softc, 2474 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2475 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2476 } 2477 2478 /* Set promiscuous mode */ 2479 sk_setpromisc(sc_if); 2480 2481 /* Set multicast filter */ 2482 sk_setmulti(sc_if); 2483 2484 /* enable interrupt mask for counter overflows */ 2485 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2486 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2487 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2488 2489 /* Configure RX MAC FIFO */ 2490 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2491 SK_IF_WRITE_4(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON); 2492 2493 /* Configure TX MAC FIFO */ 2494 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2495 SK_IF_WRITE_4(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2496} 2497 2498/* 2499 * Note that to properly initialize any part of the GEnesis chip, 2500 * you first have to take it out of reset mode. 2501 */ 2502static void 2503sk_init(xsc) 2504 void *xsc; 2505{ 2506 struct sk_if_softc *sc_if = xsc; 2507 struct sk_softc *sc; 2508 struct ifnet *ifp; 2509 struct mii_data *mii; 2510 u_int16_t reg; 2511 2512 SK_IF_LOCK(sc_if); 2513 2514 ifp = &sc_if->arpcom.ac_if; 2515 sc = sc_if->sk_softc; 2516 mii = device_get_softc(sc_if->sk_miibus); 2517 2518 /* Cancel pending I/O and free all RX/TX buffers. */ 2519 sk_stop(sc_if); 2520 2521 if (sc->sk_type == SK_GENESIS) { 2522 /* Configure LINK_SYNC LED */ 2523 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON); 2524 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2525 SK_LINKLED_LINKSYNC_ON); 2526 2527 /* Configure RX LED */ 2528 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, 2529 SK_RXLEDCTL_COUNTER_START); 2530 2531 /* Configure TX LED */ 2532 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, 2533 SK_TXLEDCTL_COUNTER_START); 2534 } 2535 2536 /* Configure I2C registers */ 2537 2538 /* Configure XMAC(s) */ 2539 switch (sc->sk_type) { 2540 case SK_GENESIS: 2541 sk_init_xmac(sc_if); 2542 break; 2543 case SK_YUKON: 2544 sk_init_yukon(sc_if); 2545 break; 2546 } 2547 mii_mediachg(mii); 2548 2549 if (sc->sk_type == SK_GENESIS) { 2550 /* Configure MAC FIFOs */ 2551 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET); 2552 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END); 2553 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON); 2554 2555 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET); 2556 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END); 2557 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON); 2558 } 2559 2560 /* Configure transmit arbiter(s) */ 2561 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, 2562 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 2563 2564 /* Configure RAMbuffers */ 2565 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2566 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2567 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2568 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2569 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2570 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2571 2572 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET); 2573 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON); 2574 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart); 2575 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart); 2576 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart); 2577 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend); 2578 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON); 2579 2580 /* Configure BMUs */ 2581 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE); 2582 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 2583 vtophys(&sc_if->sk_rdata->sk_rx_ring[0])); 2584 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0); 2585 2586 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE); 2587 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO, 2588 vtophys(&sc_if->sk_rdata->sk_tx_ring[0])); 2589 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0); 2590 2591 /* Init descriptors */ 2592 if (sk_init_rx_ring(sc_if) == ENOBUFS) { 2593 printf("sk%d: initialization failed: no " 2594 "memory for rx buffers\n", sc_if->sk_unit); 2595 sk_stop(sc_if); 2596 SK_IF_UNLOCK(sc_if); 2597 return; 2598 } 2599 sk_init_tx_ring(sc_if); 2600 2601 /* Configure interrupt handling */ 2602 CSR_READ_4(sc, SK_ISSR); 2603 if (sc_if->sk_port == SK_PORT_A) 2604 sc->sk_intrmask |= SK_INTRS1; 2605 else 2606 sc->sk_intrmask |= SK_INTRS2; 2607 2608 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG; 2609 2610 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2611 2612 /* Start BMUs. */ 2613 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START); 2614 2615 switch(sc->sk_type) { 2616 case SK_GENESIS: 2617 /* Enable XMACs TX and RX state machines */ 2618 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE); 2619 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2620 break; 2621 case SK_YUKON: 2622 reg = SK_YU_READ_2(sc_if, YUKON_GPCR); 2623 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN; 2624 reg &= ~(YU_GPCR_SPEED_EN | YU_GPCR_DPLX_EN); 2625 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg); 2626 } 2627 2628 ifp->if_flags |= IFF_RUNNING; 2629 ifp->if_flags &= ~IFF_OACTIVE; 2630 2631 SK_IF_UNLOCK(sc_if); 2632 2633 return; 2634} 2635 2636static void 2637sk_stop(sc_if) 2638 struct sk_if_softc *sc_if; 2639{ 2640 int i; 2641 struct sk_softc *sc; 2642 struct ifnet *ifp; 2643 2644 SK_IF_LOCK(sc_if); 2645 sc = sc_if->sk_softc; 2646 ifp = &sc_if->arpcom.ac_if; 2647 2648 untimeout(sk_tick, sc_if, sc_if->sk_tick_ch); 2649 2650 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2651 u_int32_t val; 2652 2653 /* Put PHY back into reset. */ 2654 val = sk_win_read_4(sc, SK_GPIO); 2655 if (sc_if->sk_port == SK_PORT_A) { 2656 val |= SK_GPIO_DIR0; 2657 val &= ~SK_GPIO_DAT0; 2658 } else { 2659 val |= SK_GPIO_DIR2; 2660 val &= ~SK_GPIO_DAT2; 2661 } 2662 sk_win_write_4(sc, SK_GPIO, val); 2663 } 2664 2665 /* Turn off various components of this interface. */ 2666 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2667 switch (sc->sk_type) { 2668 case SK_GENESIS: 2669 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_RESET); 2670 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET); 2671 break; 2672 case SK_YUKON: 2673 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2674 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2675 break; 2676 } 2677 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2678 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2679 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE); 2680 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2681 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2682 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2683 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2684 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2685 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2686 2687 /* Disable interrupts */ 2688 if (sc_if->sk_port == SK_PORT_A) 2689 sc->sk_intrmask &= ~SK_INTRS1; 2690 else 2691 sc->sk_intrmask &= ~SK_INTRS2; 2692 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2693 2694 SK_XM_READ_2(sc_if, XM_ISR); 2695 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2696 2697 /* Free RX and TX mbufs still in the queues. */ 2698 for (i = 0; i < SK_RX_RING_CNT; i++) { 2699 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2700 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2701 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2702 } 2703 } 2704 2705 for (i = 0; i < SK_TX_RING_CNT; i++) { 2706 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2707 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2708 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2709 } 2710 } 2711 2712 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2713 SK_IF_UNLOCK(sc_if); 2714 return; 2715} 2716