if_sk.c revision 122689
1/* $OpenBSD: if_sk.c,v 2.33 2003/08/12 05:23:06 nate Exp $ */ 2 3/* 4 * Copyright (c) 1997, 1998, 1999, 2000 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34/* 35 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 36 * 37 * Permission to use, copy, modify, and distribute this software for any 38 * purpose with or without fee is hereby granted, provided that the above 39 * copyright notice and this permission notice appear in all copies. 40 * 41 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 42 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 43 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 44 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 45 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 46 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 47 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 48 */ 49 50#include <sys/cdefs.h> 51__FBSDID("$FreeBSD: head/sys/dev/sk/if_sk.c 122689 2003-11-14 19:00:32Z sam $"); 52 53/* 54 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 55 * the SK-984x series adapters, both single port and dual port. 56 * References: 57 * The XaQti XMAC II datasheet, 58 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 59 * The SysKonnect GEnesis manual, http://www.syskonnect.com 60 * 61 * Note: XaQti has been aquired by Vitesse, and Vitesse does not have the 62 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 63 * convenience to others until Vitesse corrects this problem: 64 * 65 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 66 * 67 * Written by Bill Paul <wpaul@ee.columbia.edu> 68 * Department of Electrical Engineering 69 * Columbia University, New York City 70 */ 71/* 72 * The SysKonnect gigabit ethernet adapters consist of two main 73 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 74 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 75 * components and a PHY while the GEnesis controller provides a PCI 76 * interface with DMA support. Each card may have between 512K and 77 * 2MB of SRAM on board depending on the configuration. 78 * 79 * The SysKonnect GEnesis controller can have either one or two XMAC 80 * chips connected to it, allowing single or dual port NIC configurations. 81 * SysKonnect has the distinction of being the only vendor on the market 82 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 83 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 84 * XMAC registers. This driver takes advantage of these features to allow 85 * both XMACs to operate as independent interfaces. 86 */ 87 88#include <sys/param.h> 89#include <sys/systm.h> 90#include <sys/sockio.h> 91#include <sys/mbuf.h> 92#include <sys/malloc.h> 93#include <sys/kernel.h> 94#include <sys/socket.h> 95#include <sys/queue.h> 96 97#include <net/if.h> 98#include <net/if_arp.h> 99#include <net/ethernet.h> 100#include <net/if_dl.h> 101#include <net/if_media.h> 102 103#include <net/bpf.h> 104 105#include <vm/vm.h> /* for vtophys */ 106#include <vm/pmap.h> /* for vtophys */ 107#include <machine/bus_pio.h> 108#include <machine/bus_memio.h> 109#include <machine/bus.h> 110#include <machine/resource.h> 111#include <sys/bus.h> 112#include <sys/rman.h> 113 114#include <dev/mii/mii.h> 115#include <dev/mii/miivar.h> 116#include <dev/mii/brgphyreg.h> 117 118#include <dev/pci/pcireg.h> 119#include <dev/pci/pcivar.h> 120 121#if 0 122#define SK_USEIOSPACE 123#endif 124 125#include <pci/if_skreg.h> 126#include <pci/xmaciireg.h> 127#include <pci/yukonreg.h> 128 129MODULE_DEPEND(sk, pci, 1, 1, 1); 130MODULE_DEPEND(sk, ether, 1, 1, 1); 131MODULE_DEPEND(sk, miibus, 1, 1, 1); 132 133/* "controller miibus0" required. See GENERIC if you get errors here. */ 134#include "miibus_if.h" 135 136#ifndef lint 137static const char rcsid[] = 138 "$FreeBSD: head/sys/dev/sk/if_sk.c 122689 2003-11-14 19:00:32Z sam $"; 139#endif 140 141static struct sk_type sk_devs[] = { 142 { 143 VENDORID_SK, 144 DEVICEID_SK_V1, 145 "SysKonnect Gigabit Ethernet (V1.0)" 146 }, 147 { 148 VENDORID_SK, 149 DEVICEID_SK_V2, 150 "SysKonnect Gigabit Ethernet (V2.0)" 151 }, 152 { 153 VENDORID_MARVELL, 154 DEVICEID_SK_V2, 155 "Marvell Gigabit Ethernet" 156 }, 157 { 158 VENDORID_3COM, 159 DEVICEID_3COM_3C940, 160 "3Com 3C940 Gigabit Ethernet" 161 }, 162 { 163 VENDORID_LINKSYS, 164 DEVICEID_LINKSYS_EG1032, 165 "Linksys EG1032 Gigabit Ethernet" 166 }, 167 { 0, 0, NULL } 168}; 169 170static int skc_probe (device_t); 171static int skc_attach (device_t); 172static int skc_detach (device_t); 173static void skc_shutdown (device_t); 174static int sk_detach (device_t); 175static int sk_probe (device_t); 176static int sk_attach (device_t); 177static void sk_tick (void *); 178static void sk_intr (void *); 179static void sk_intr_xmac (struct sk_if_softc *); 180static void sk_intr_bcom (struct sk_if_softc *); 181static void sk_intr_yukon (struct sk_if_softc *); 182static void sk_rxeof (struct sk_if_softc *); 183static void sk_txeof (struct sk_if_softc *); 184static int sk_encap (struct sk_if_softc *, struct mbuf *, 185 u_int32_t *); 186static void sk_start (struct ifnet *); 187static int sk_ioctl (struct ifnet *, u_long, caddr_t); 188static void sk_init (void *); 189static void sk_init_xmac (struct sk_if_softc *); 190static void sk_init_yukon (struct sk_if_softc *); 191static void sk_stop (struct sk_if_softc *); 192static void sk_watchdog (struct ifnet *); 193static int sk_ifmedia_upd (struct ifnet *); 194static void sk_ifmedia_sts (struct ifnet *, struct ifmediareq *); 195static void sk_reset (struct sk_softc *); 196static int sk_newbuf (struct sk_if_softc *, 197 struct sk_chain *, struct mbuf *); 198static int sk_alloc_jumbo_mem (struct sk_if_softc *); 199static void *sk_jalloc (struct sk_if_softc *); 200static void sk_jfree (void *, void *); 201static int sk_init_rx_ring (struct sk_if_softc *); 202static void sk_init_tx_ring (struct sk_if_softc *); 203static u_int32_t sk_win_read_4 (struct sk_softc *, int); 204static u_int16_t sk_win_read_2 (struct sk_softc *, int); 205static u_int8_t sk_win_read_1 (struct sk_softc *, int); 206static void sk_win_write_4 (struct sk_softc *, int, u_int32_t); 207static void sk_win_write_2 (struct sk_softc *, int, u_int32_t); 208static void sk_win_write_1 (struct sk_softc *, int, u_int32_t); 209static u_int8_t sk_vpd_readbyte (struct sk_softc *, int); 210static void sk_vpd_read_res (struct sk_softc *, struct vpd_res *, int); 211static void sk_vpd_read (struct sk_softc *); 212 213static int sk_miibus_readreg (device_t, int, int); 214static int sk_miibus_writereg (device_t, int, int, int); 215static void sk_miibus_statchg (device_t); 216 217static int sk_xmac_miibus_readreg (struct sk_if_softc *, int, int); 218static int sk_xmac_miibus_writereg (struct sk_if_softc *, int, int, 219 int); 220static void sk_xmac_miibus_statchg (struct sk_if_softc *); 221 222static int sk_marv_miibus_readreg (struct sk_if_softc *, int, int); 223static int sk_marv_miibus_writereg (struct sk_if_softc *, int, int, 224 int); 225static void sk_marv_miibus_statchg (struct sk_if_softc *); 226 227static u_int32_t sk_mchash (caddr_t); 228static void sk_setfilt (struct sk_if_softc *, caddr_t, int); 229static void sk_setmulti (struct sk_if_softc *); 230 231#ifdef SK_USEIOSPACE 232#define SK_RES SYS_RES_IOPORT 233#define SK_RID SK_PCI_LOIO 234#else 235#define SK_RES SYS_RES_MEMORY 236#define SK_RID SK_PCI_LOMEM 237#endif 238 239/* 240 * Note that we have newbus methods for both the GEnesis controller 241 * itself and the XMAC(s). The XMACs are children of the GEnesis, and 242 * the miibus code is a child of the XMACs. We need to do it this way 243 * so that the miibus drivers can access the PHY registers on the 244 * right PHY. It's not quite what I had in mind, but it's the only 245 * design that achieves the desired effect. 246 */ 247static device_method_t skc_methods[] = { 248 /* Device interface */ 249 DEVMETHOD(device_probe, skc_probe), 250 DEVMETHOD(device_attach, skc_attach), 251 DEVMETHOD(device_detach, skc_detach), 252 DEVMETHOD(device_shutdown, skc_shutdown), 253 254 /* bus interface */ 255 DEVMETHOD(bus_print_child, bus_generic_print_child), 256 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 257 258 { 0, 0 } 259}; 260 261static driver_t skc_driver = { 262 "skc", 263 skc_methods, 264 sizeof(struct sk_softc) 265}; 266 267static devclass_t skc_devclass; 268 269static device_method_t sk_methods[] = { 270 /* Device interface */ 271 DEVMETHOD(device_probe, sk_probe), 272 DEVMETHOD(device_attach, sk_attach), 273 DEVMETHOD(device_detach, sk_detach), 274 DEVMETHOD(device_shutdown, bus_generic_shutdown), 275 276 /* bus interface */ 277 DEVMETHOD(bus_print_child, bus_generic_print_child), 278 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 279 280 /* MII interface */ 281 DEVMETHOD(miibus_readreg, sk_miibus_readreg), 282 DEVMETHOD(miibus_writereg, sk_miibus_writereg), 283 DEVMETHOD(miibus_statchg, sk_miibus_statchg), 284 285 { 0, 0 } 286}; 287 288static driver_t sk_driver = { 289 "sk", 290 sk_methods, 291 sizeof(struct sk_if_softc) 292}; 293 294static devclass_t sk_devclass; 295 296DRIVER_MODULE(sk, pci, skc_driver, skc_devclass, 0, 0); 297DRIVER_MODULE(sk, skc, sk_driver, sk_devclass, 0, 0); 298DRIVER_MODULE(miibus, sk, miibus_driver, miibus_devclass, 0, 0); 299 300#define SK_SETBIT(sc, reg, x) \ 301 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 302 303#define SK_CLRBIT(sc, reg, x) \ 304 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 305 306#define SK_WIN_SETBIT_4(sc, reg, x) \ 307 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) | x) 308 309#define SK_WIN_CLRBIT_4(sc, reg, x) \ 310 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) & ~x) 311 312#define SK_WIN_SETBIT_2(sc, reg, x) \ 313 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) | x) 314 315#define SK_WIN_CLRBIT_2(sc, reg, x) \ 316 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) & ~x) 317 318static u_int32_t 319sk_win_read_4(sc, reg) 320 struct sk_softc *sc; 321 int reg; 322{ 323#ifdef SK_USEIOSPACE 324 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 325 return(CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg))); 326#else 327 return(CSR_READ_4(sc, reg)); 328#endif 329} 330 331static u_int16_t 332sk_win_read_2(sc, reg) 333 struct sk_softc *sc; 334 int reg; 335{ 336#ifdef SK_USEIOSPACE 337 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 338 return(CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg))); 339#else 340 return(CSR_READ_2(sc, reg)); 341#endif 342} 343 344static u_int8_t 345sk_win_read_1(sc, reg) 346 struct sk_softc *sc; 347 int reg; 348{ 349#ifdef SK_USEIOSPACE 350 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 351 return(CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg))); 352#else 353 return(CSR_READ_1(sc, reg)); 354#endif 355} 356 357static void 358sk_win_write_4(sc, reg, val) 359 struct sk_softc *sc; 360 int reg; 361 u_int32_t val; 362{ 363#ifdef SK_USEIOSPACE 364 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 365 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), val); 366#else 367 CSR_WRITE_4(sc, reg, val); 368#endif 369 return; 370} 371 372static void 373sk_win_write_2(sc, reg, val) 374 struct sk_softc *sc; 375 int reg; 376 u_int32_t val; 377{ 378#ifdef SK_USEIOSPACE 379 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 380 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), val); 381#else 382 CSR_WRITE_2(sc, reg, val); 383#endif 384 return; 385} 386 387static void 388sk_win_write_1(sc, reg, val) 389 struct sk_softc *sc; 390 int reg; 391 u_int32_t val; 392{ 393#ifdef SK_USEIOSPACE 394 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 395 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), val); 396#else 397 CSR_WRITE_1(sc, reg, val); 398#endif 399 return; 400} 401 402/* 403 * The VPD EEPROM contains Vital Product Data, as suggested in 404 * the PCI 2.1 specification. The VPD data is separared into areas 405 * denoted by resource IDs. The SysKonnect VPD contains an ID string 406 * resource (the name of the adapter), a read-only area resource 407 * containing various key/data fields and a read/write area which 408 * can be used to store asset management information or log messages. 409 * We read the ID string and read-only into buffers attached to 410 * the controller softc structure for later use. At the moment, 411 * we only use the ID string during skc_attach(). 412 */ 413static u_int8_t 414sk_vpd_readbyte(sc, addr) 415 struct sk_softc *sc; 416 int addr; 417{ 418 int i; 419 420 sk_win_write_2(sc, SK_PCI_REG(SK_PCI_VPD_ADDR), addr); 421 for (i = 0; i < SK_TIMEOUT; i++) { 422 DELAY(1); 423 if (sk_win_read_2(sc, 424 SK_PCI_REG(SK_PCI_VPD_ADDR)) & SK_VPD_FLAG) 425 break; 426 } 427 428 if (i == SK_TIMEOUT) 429 return(0); 430 431 return(sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_DATA))); 432} 433 434static void 435sk_vpd_read_res(sc, res, addr) 436 struct sk_softc *sc; 437 struct vpd_res *res; 438 int addr; 439{ 440 int i; 441 u_int8_t *ptr; 442 443 ptr = (u_int8_t *)res; 444 for (i = 0; i < sizeof(struct vpd_res); i++) 445 ptr[i] = sk_vpd_readbyte(sc, i + addr); 446 447 return; 448} 449 450static void 451sk_vpd_read(sc) 452 struct sk_softc *sc; 453{ 454 int pos = 0, i; 455 struct vpd_res res; 456 457 if (sc->sk_vpd_prodname != NULL) 458 free(sc->sk_vpd_prodname, M_DEVBUF); 459 if (sc->sk_vpd_readonly != NULL) 460 free(sc->sk_vpd_readonly, M_DEVBUF); 461 sc->sk_vpd_prodname = NULL; 462 sc->sk_vpd_readonly = NULL; 463 464 sk_vpd_read_res(sc, &res, pos); 465 466 if (res.vr_id != VPD_RES_ID) { 467 printf("skc%d: bad VPD resource id: expected %x got %x\n", 468 sc->sk_unit, VPD_RES_ID, res.vr_id); 469 return; 470 } 471 472 pos += sizeof(res); 473 sc->sk_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 474 for (i = 0; i < res.vr_len; i++) 475 sc->sk_vpd_prodname[i] = sk_vpd_readbyte(sc, i + pos); 476 sc->sk_vpd_prodname[i] = '\0'; 477 pos += i; 478 479 sk_vpd_read_res(sc, &res, pos); 480 481 if (res.vr_id != VPD_RES_READ) { 482 printf("skc%d: bad VPD resource id: expected %x got %x\n", 483 sc->sk_unit, VPD_RES_READ, res.vr_id); 484 return; 485 } 486 487 pos += sizeof(res); 488 sc->sk_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 489 for (i = 0; i < res.vr_len + 1; i++) 490 sc->sk_vpd_readonly[i] = sk_vpd_readbyte(sc, i + pos); 491 492 return; 493} 494 495static int 496sk_miibus_readreg(dev, phy, reg) 497 device_t dev; 498 int phy, reg; 499{ 500 struct sk_if_softc *sc_if; 501 502 sc_if = device_get_softc(dev); 503 504 switch(sc_if->sk_softc->sk_type) { 505 case SK_GENESIS: 506 return(sk_xmac_miibus_readreg(sc_if, phy, reg)); 507 case SK_YUKON: 508 return(sk_marv_miibus_readreg(sc_if, phy, reg)); 509 } 510 511 return(0); 512} 513 514static int 515sk_miibus_writereg(dev, phy, reg, val) 516 device_t dev; 517 int phy, reg, val; 518{ 519 struct sk_if_softc *sc_if; 520 521 sc_if = device_get_softc(dev); 522 523 switch(sc_if->sk_softc->sk_type) { 524 case SK_GENESIS: 525 return(sk_xmac_miibus_writereg(sc_if, phy, reg, val)); 526 case SK_YUKON: 527 return(sk_marv_miibus_writereg(sc_if, phy, reg, val)); 528 } 529 530 return(0); 531} 532 533static void 534sk_miibus_statchg(dev) 535 device_t dev; 536{ 537 struct sk_if_softc *sc_if; 538 539 sc_if = device_get_softc(dev); 540 541 switch(sc_if->sk_softc->sk_type) { 542 case SK_GENESIS: 543 sk_xmac_miibus_statchg(sc_if); 544 break; 545 case SK_YUKON: 546 sk_marv_miibus_statchg(sc_if); 547 break; 548 } 549 550 return; 551} 552 553static int 554sk_xmac_miibus_readreg(sc_if, phy, reg) 555 struct sk_if_softc *sc_if; 556 int phy, reg; 557{ 558 int i; 559 560 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0) 561 return(0); 562 563 SK_IF_LOCK(sc_if); 564 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 565 SK_XM_READ_2(sc_if, XM_PHY_DATA); 566 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 567 for (i = 0; i < SK_TIMEOUT; i++) { 568 DELAY(1); 569 if (SK_XM_READ_2(sc_if, XM_MMUCMD) & 570 XM_MMUCMD_PHYDATARDY) 571 break; 572 } 573 574 if (i == SK_TIMEOUT) { 575 printf("sk%d: phy failed to come ready\n", 576 sc_if->sk_unit); 577 SK_IF_UNLOCK(sc_if); 578 return(0); 579 } 580 } 581 DELAY(1); 582 i = SK_XM_READ_2(sc_if, XM_PHY_DATA); 583 SK_IF_UNLOCK(sc_if); 584 return(i); 585} 586 587static int 588sk_xmac_miibus_writereg(sc_if, phy, reg, val) 589 struct sk_if_softc *sc_if; 590 int phy, reg, val; 591{ 592 int i; 593 594 SK_IF_LOCK(sc_if); 595 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 596 for (i = 0; i < SK_TIMEOUT; i++) { 597 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 598 break; 599 } 600 601 if (i == SK_TIMEOUT) { 602 printf("sk%d: phy failed to come ready\n", sc_if->sk_unit); 603 SK_IF_UNLOCK(sc_if); 604 return(ETIMEDOUT); 605 } 606 607 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val); 608 for (i = 0; i < SK_TIMEOUT; i++) { 609 DELAY(1); 610 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 611 break; 612 } 613 SK_IF_UNLOCK(sc_if); 614 if (i == SK_TIMEOUT) 615 printf("sk%d: phy write timed out\n", sc_if->sk_unit); 616 617 return(0); 618} 619 620static void 621sk_xmac_miibus_statchg(sc_if) 622 struct sk_if_softc *sc_if; 623{ 624 struct mii_data *mii; 625 626 mii = device_get_softc(sc_if->sk_miibus); 627 628 SK_IF_LOCK(sc_if); 629 /* 630 * If this is a GMII PHY, manually set the XMAC's 631 * duplex mode accordingly. 632 */ 633 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 634 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 635 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 636 } else { 637 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 638 } 639 } 640 SK_IF_UNLOCK(sc_if); 641 642 return; 643} 644 645static int 646sk_marv_miibus_readreg(sc_if, phy, reg) 647 struct sk_if_softc *sc_if; 648 int phy, reg; 649{ 650 u_int16_t val; 651 int i; 652 653 if (phy != 0 || 654 (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER && 655 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) { 656 return(0); 657 } 658 659 SK_IF_LOCK(sc_if); 660 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 661 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 662 663 for (i = 0; i < SK_TIMEOUT; i++) { 664 DELAY(1); 665 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 666 if (val & YU_SMICR_READ_VALID) 667 break; 668 } 669 670 if (i == SK_TIMEOUT) { 671 printf("sk%d: phy failed to come ready\n", 672 sc_if->sk_unit); 673 SK_IF_UNLOCK(sc_if); 674 return(0); 675 } 676 677 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 678 SK_IF_UNLOCK(sc_if); 679 680 return(val); 681} 682 683static int 684sk_marv_miibus_writereg(sc_if, phy, reg, val) 685 struct sk_if_softc *sc_if; 686 int phy, reg, val; 687{ 688 int i; 689 690 SK_IF_LOCK(sc_if); 691 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 692 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 693 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 694 695 for (i = 0; i < SK_TIMEOUT; i++) { 696 DELAY(1); 697 if (SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY) 698 break; 699 } 700 SK_IF_UNLOCK(sc_if); 701 702 return(0); 703} 704 705static void 706sk_marv_miibus_statchg(sc_if) 707 struct sk_if_softc *sc_if; 708{ 709 return; 710} 711 712#define SK_POLY 0xEDB88320 713#define SK_BITS 6 714 715static u_int32_t 716sk_mchash(addr) 717 caddr_t addr; 718{ 719 u_int32_t crc; 720 int idx, bit; 721 u_int8_t data; 722 723 /* Compute CRC for the address value. */ 724 crc = 0xFFFFFFFF; /* initial value */ 725 726 for (idx = 0; idx < 6; idx++) { 727 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 728 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? SK_POLY : 0); 729 } 730 731 return (~crc & ((1 << SK_BITS) - 1)); 732} 733 734static void 735sk_setfilt(sc_if, addr, slot) 736 struct sk_if_softc *sc_if; 737 caddr_t addr; 738 int slot; 739{ 740 int base; 741 742 base = XM_RXFILT_ENTRY(slot); 743 744 SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0])); 745 SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2])); 746 SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4])); 747 748 return; 749} 750 751static void 752sk_setmulti(sc_if) 753 struct sk_if_softc *sc_if; 754{ 755 struct sk_softc *sc = sc_if->sk_softc; 756 struct ifnet *ifp = &sc_if->arpcom.ac_if; 757 u_int32_t hashes[2] = { 0, 0 }; 758 int h, i; 759 struct ifmultiaddr *ifma; 760 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 761 762 763 /* First, zot all the existing filters. */ 764 switch(sc->sk_type) { 765 case SK_GENESIS: 766 for (i = 1; i < XM_RXFILT_MAX; i++) 767 sk_setfilt(sc_if, (caddr_t)&dummy, i); 768 769 SK_XM_WRITE_4(sc_if, XM_MAR0, 0); 770 SK_XM_WRITE_4(sc_if, XM_MAR2, 0); 771 break; 772 case SK_YUKON: 773 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 774 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 775 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 776 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 777 break; 778 } 779 780 /* Now program new ones. */ 781 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 782 hashes[0] = 0xFFFFFFFF; 783 hashes[1] = 0xFFFFFFFF; 784 } else { 785 i = 1; 786 TAILQ_FOREACH_REVERSE(ifma, &ifp->if_multiaddrs, ifmultihead, ifma_link) { 787 if (ifma->ifma_addr->sa_family != AF_LINK) 788 continue; 789 /* 790 * Program the first XM_RXFILT_MAX multicast groups 791 * into the perfect filter. For all others, 792 * use the hash table. 793 */ 794 if (sc->sk_type == SK_GENESIS && i < XM_RXFILT_MAX) { 795 sk_setfilt(sc_if, 796 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i); 797 i++; 798 continue; 799 } 800 801 h = sk_mchash( 802 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 803 if (h < 32) 804 hashes[0] |= (1 << h); 805 else 806 hashes[1] |= (1 << (h - 32)); 807 } 808 } 809 810 switch(sc->sk_type) { 811 case SK_GENESIS: 812 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH| 813 XM_MODE_RX_USE_PERFECT); 814 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]); 815 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]); 816 break; 817 case SK_YUKON: 818 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 819 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 820 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 821 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 822 break; 823 } 824 825 return; 826} 827 828static int 829sk_init_rx_ring(sc_if) 830 struct sk_if_softc *sc_if; 831{ 832 struct sk_chain_data *cd = &sc_if->sk_cdata; 833 struct sk_ring_data *rd = sc_if->sk_rdata; 834 int i; 835 836 bzero((char *)rd->sk_rx_ring, 837 sizeof(struct sk_rx_desc) * SK_RX_RING_CNT); 838 839 for (i = 0; i < SK_RX_RING_CNT; i++) { 840 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i]; 841 if (sk_newbuf(sc_if, &cd->sk_rx_chain[i], NULL) == ENOBUFS) 842 return(ENOBUFS); 843 if (i == (SK_RX_RING_CNT - 1)) { 844 cd->sk_rx_chain[i].sk_next = 845 &cd->sk_rx_chain[0]; 846 rd->sk_rx_ring[i].sk_next = 847 vtophys(&rd->sk_rx_ring[0]); 848 } else { 849 cd->sk_rx_chain[i].sk_next = 850 &cd->sk_rx_chain[i + 1]; 851 rd->sk_rx_ring[i].sk_next = 852 vtophys(&rd->sk_rx_ring[i + 1]); 853 } 854 } 855 856 sc_if->sk_cdata.sk_rx_prod = 0; 857 sc_if->sk_cdata.sk_rx_cons = 0; 858 859 return(0); 860} 861 862static void 863sk_init_tx_ring(sc_if) 864 struct sk_if_softc *sc_if; 865{ 866 struct sk_chain_data *cd = &sc_if->sk_cdata; 867 struct sk_ring_data *rd = sc_if->sk_rdata; 868 int i; 869 870 bzero((char *)sc_if->sk_rdata->sk_tx_ring, 871 sizeof(struct sk_tx_desc) * SK_TX_RING_CNT); 872 873 for (i = 0; i < SK_TX_RING_CNT; i++) { 874 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i]; 875 if (i == (SK_TX_RING_CNT - 1)) { 876 cd->sk_tx_chain[i].sk_next = 877 &cd->sk_tx_chain[0]; 878 rd->sk_tx_ring[i].sk_next = 879 vtophys(&rd->sk_tx_ring[0]); 880 } else { 881 cd->sk_tx_chain[i].sk_next = 882 &cd->sk_tx_chain[i + 1]; 883 rd->sk_tx_ring[i].sk_next = 884 vtophys(&rd->sk_tx_ring[i + 1]); 885 } 886 } 887 888 sc_if->sk_cdata.sk_tx_prod = 0; 889 sc_if->sk_cdata.sk_tx_cons = 0; 890 sc_if->sk_cdata.sk_tx_cnt = 0; 891 892 return; 893} 894 895static int 896sk_newbuf(sc_if, c, m) 897 struct sk_if_softc *sc_if; 898 struct sk_chain *c; 899 struct mbuf *m; 900{ 901 struct mbuf *m_new = NULL; 902 struct sk_rx_desc *r; 903 904 if (m == NULL) { 905 caddr_t *buf = NULL; 906 907 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 908 if (m_new == NULL) 909 return(ENOBUFS); 910 911 /* Allocate the jumbo buffer */ 912 buf = sk_jalloc(sc_if); 913 if (buf == NULL) { 914 m_freem(m_new); 915#ifdef SK_VERBOSE 916 printf("sk%d: jumbo allocation failed " 917 "-- packet dropped!\n", sc_if->sk_unit); 918#endif 919 return(ENOBUFS); 920 } 921 922 /* Attach the buffer to the mbuf */ 923 MEXTADD(m_new, buf, SK_JLEN, sk_jfree, 924 (struct sk_if_softc *)sc_if, 0, EXT_NET_DRV); 925 m_new->m_data = (void *)buf; 926 m_new->m_pkthdr.len = m_new->m_len = SK_JLEN; 927 } else { 928 /* 929 * We're re-using a previously allocated mbuf; 930 * be sure to re-init pointers and lengths to 931 * default values. 932 */ 933 m_new = m; 934 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 935 m_new->m_data = m_new->m_ext.ext_buf; 936 } 937 938 /* 939 * Adjust alignment so packet payload begins on a 940 * longword boundary. Mandatory for Alpha, useful on 941 * x86 too. 942 */ 943 m_adj(m_new, ETHER_ALIGN); 944 945 r = c->sk_desc; 946 c->sk_mbuf = m_new; 947 r->sk_data_lo = vtophys(mtod(m_new, caddr_t)); 948 r->sk_ctl = m_new->m_len | SK_RXSTAT; 949 950 return(0); 951} 952 953/* 954 * Allocate jumbo buffer storage. The SysKonnect adapters support 955 * "jumbograms" (9K frames), although SysKonnect doesn't currently 956 * use them in their drivers. In order for us to use them, we need 957 * large 9K receive buffers, however standard mbuf clusters are only 958 * 2048 bytes in size. Consequently, we need to allocate and manage 959 * our own jumbo buffer pool. Fortunately, this does not require an 960 * excessive amount of additional code. 961 */ 962static int 963sk_alloc_jumbo_mem(sc_if) 964 struct sk_if_softc *sc_if; 965{ 966 caddr_t ptr; 967 register int i; 968 struct sk_jpool_entry *entry; 969 970 /* Grab a big chunk o' storage. */ 971 sc_if->sk_cdata.sk_jumbo_buf = contigmalloc(SK_JMEM, M_DEVBUF, 972 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 973 974 if (sc_if->sk_cdata.sk_jumbo_buf == NULL) { 975 printf("sk%d: no memory for jumbo buffers!\n", sc_if->sk_unit); 976 return(ENOBUFS); 977 } 978 979 SLIST_INIT(&sc_if->sk_jfree_listhead); 980 SLIST_INIT(&sc_if->sk_jinuse_listhead); 981 982 /* 983 * Now divide it up into 9K pieces and save the addresses 984 * in an array. 985 */ 986 ptr = sc_if->sk_cdata.sk_jumbo_buf; 987 for (i = 0; i < SK_JSLOTS; i++) { 988 sc_if->sk_cdata.sk_jslots[i] = ptr; 989 ptr += SK_JLEN; 990 entry = malloc(sizeof(struct sk_jpool_entry), 991 M_DEVBUF, M_NOWAIT); 992 if (entry == NULL) { 993 free(sc_if->sk_cdata.sk_jumbo_buf, M_DEVBUF); 994 sc_if->sk_cdata.sk_jumbo_buf = NULL; 995 printf("sk%d: no memory for jumbo " 996 "buffer queue!\n", sc_if->sk_unit); 997 return(ENOBUFS); 998 } 999 entry->slot = i; 1000 SLIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 1001 entry, jpool_entries); 1002 } 1003 1004 return(0); 1005} 1006 1007/* 1008 * Allocate a jumbo buffer. 1009 */ 1010static void * 1011sk_jalloc(sc_if) 1012 struct sk_if_softc *sc_if; 1013{ 1014 struct sk_jpool_entry *entry; 1015 1016 entry = SLIST_FIRST(&sc_if->sk_jfree_listhead); 1017 1018 if (entry == NULL) { 1019#ifdef SK_VERBOSE 1020 printf("sk%d: no free jumbo buffers\n", sc_if->sk_unit); 1021#endif 1022 return(NULL); 1023 } 1024 1025 SLIST_REMOVE_HEAD(&sc_if->sk_jfree_listhead, jpool_entries); 1026 SLIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 1027 return(sc_if->sk_cdata.sk_jslots[entry->slot]); 1028} 1029 1030/* 1031 * Release a jumbo buffer. 1032 */ 1033static void 1034sk_jfree(buf, args) 1035 void *buf; 1036 void *args; 1037{ 1038 struct sk_if_softc *sc_if; 1039 int i; 1040 struct sk_jpool_entry *entry; 1041 1042 /* Extract the softc struct pointer. */ 1043 sc_if = (struct sk_if_softc *)args; 1044 1045 if (sc_if == NULL) 1046 panic("sk_jfree: didn't get softc pointer!"); 1047 1048 /* calculate the slot this buffer belongs to */ 1049 i = ((vm_offset_t)buf 1050 - (vm_offset_t)sc_if->sk_cdata.sk_jumbo_buf) / SK_JLEN; 1051 1052 if ((i < 0) || (i >= SK_JSLOTS)) 1053 panic("sk_jfree: asked to free buffer that we don't manage!"); 1054 1055 entry = SLIST_FIRST(&sc_if->sk_jinuse_listhead); 1056 if (entry == NULL) 1057 panic("sk_jfree: buffer not in use!"); 1058 entry->slot = i; 1059 SLIST_REMOVE_HEAD(&sc_if->sk_jinuse_listhead, jpool_entries); 1060 SLIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, entry, jpool_entries); 1061 1062 return; 1063} 1064 1065/* 1066 * Set media options. 1067 */ 1068static int 1069sk_ifmedia_upd(ifp) 1070 struct ifnet *ifp; 1071{ 1072 struct sk_if_softc *sc_if = ifp->if_softc; 1073 struct mii_data *mii; 1074 1075 mii = device_get_softc(sc_if->sk_miibus); 1076 sk_init(sc_if); 1077 mii_mediachg(mii); 1078 1079 return(0); 1080} 1081 1082/* 1083 * Report current media status. 1084 */ 1085static void 1086sk_ifmedia_sts(ifp, ifmr) 1087 struct ifnet *ifp; 1088 struct ifmediareq *ifmr; 1089{ 1090 struct sk_if_softc *sc_if; 1091 struct mii_data *mii; 1092 1093 sc_if = ifp->if_softc; 1094 mii = device_get_softc(sc_if->sk_miibus); 1095 1096 mii_pollstat(mii); 1097 ifmr->ifm_active = mii->mii_media_active; 1098 ifmr->ifm_status = mii->mii_media_status; 1099 1100 return; 1101} 1102 1103static int 1104sk_ioctl(ifp, command, data) 1105 struct ifnet *ifp; 1106 u_long command; 1107 caddr_t data; 1108{ 1109 struct sk_if_softc *sc_if = ifp->if_softc; 1110 struct sk_softc *sc = sc_if->sk_softc; 1111 struct ifreq *ifr = (struct ifreq *) data; 1112 int error = 0; 1113 struct mii_data *mii; 1114 1115 SK_IF_LOCK(sc_if); 1116 1117 switch(command) { 1118 case SIOCSIFMTU: 1119 if (ifr->ifr_mtu > SK_JUMBO_MTU) 1120 error = EINVAL; 1121 else { 1122 ifp->if_mtu = ifr->ifr_mtu; 1123 sk_init(sc_if); 1124 } 1125 break; 1126 case SIOCSIFFLAGS: 1127 if (ifp->if_flags & IFF_UP) { 1128 if (ifp->if_flags & IFF_RUNNING && 1129 ifp->if_flags & IFF_PROMISC && 1130 !(sc_if->sk_if_flags & IFF_PROMISC)) { 1131 switch(sc->sk_type) { 1132 case SK_GENESIS: 1133 SK_XM_SETBIT_4(sc_if, XM_MODE, 1134 XM_MODE_RX_PROMISC); 1135 break; 1136 case SK_YUKON: 1137 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 1138 YU_RCR_UFLEN | YU_RCR_MUFLEN); 1139 break; 1140 } 1141 sk_setmulti(sc_if); 1142 } else if (ifp->if_flags & IFF_RUNNING && 1143 !(ifp->if_flags & IFF_PROMISC) && 1144 sc_if->sk_if_flags & IFF_PROMISC) { 1145 switch(sc->sk_type) { 1146 case SK_GENESIS: 1147 SK_XM_CLRBIT_4(sc_if, XM_MODE, 1148 XM_MODE_RX_PROMISC); 1149 break; 1150 case SK_YUKON: 1151 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 1152 YU_RCR_UFLEN | YU_RCR_MUFLEN); 1153 break; 1154 } 1155 sk_setmulti(sc_if); 1156 } else 1157 sk_init(sc_if); 1158 } else { 1159 if (ifp->if_flags & IFF_RUNNING) 1160 sk_stop(sc_if); 1161 } 1162 sc_if->sk_if_flags = ifp->if_flags; 1163 error = 0; 1164 break; 1165 case SIOCADDMULTI: 1166 case SIOCDELMULTI: 1167 sk_setmulti(sc_if); 1168 error = 0; 1169 break; 1170 case SIOCGIFMEDIA: 1171 case SIOCSIFMEDIA: 1172 mii = device_get_softc(sc_if->sk_miibus); 1173 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1174 break; 1175 default: 1176 error = ether_ioctl(ifp, command, data); 1177 break; 1178 } 1179 1180 SK_IF_UNLOCK(sc_if); 1181 1182 return(error); 1183} 1184 1185/* 1186 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device 1187 * IDs against our list and return a device name if we find a match. 1188 */ 1189static int 1190skc_probe(dev) 1191 device_t dev; 1192{ 1193 struct sk_softc *sc; 1194 struct sk_type *t = sk_devs; 1195 1196 sc = device_get_softc(dev); 1197 1198 while(t->sk_name != NULL) { 1199 if ((pci_get_vendor(dev) == t->sk_vid) && 1200 (pci_get_device(dev) == t->sk_did)) { 1201 device_set_desc(dev, t->sk_name); 1202 return(0); 1203 } 1204 t++; 1205 } 1206 1207 return(ENXIO); 1208} 1209 1210/* 1211 * Force the GEnesis into reset, then bring it out of reset. 1212 */ 1213static void 1214sk_reset(sc) 1215 struct sk_softc *sc; 1216{ 1217 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET); 1218 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET); 1219 if (sc->sk_type == SK_YUKON) 1220 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 1221 1222 DELAY(1000); 1223 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET); 1224 DELAY(2); 1225 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 1226 if (sc->sk_type == SK_YUKON) 1227 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 1228 1229 if (sc->sk_type == SK_GENESIS) { 1230 /* Configure packet arbiter */ 1231 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET); 1232 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT); 1233 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT); 1234 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT); 1235 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT); 1236 } 1237 1238 /* Enable RAM interface */ 1239 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 1240 1241 /* 1242 * Configure interrupt moderation. The moderation timer 1243 * defers interrupts specified in the interrupt moderation 1244 * timer mask based on the timeout specified in the interrupt 1245 * moderation timer init register. Each bit in the timer 1246 * register represents 18.825ns, so to specify a timeout in 1247 * microseconds, we have to multiply by 54. 1248 */ 1249 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(200)); 1250 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 1251 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 1252 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 1253 1254 return; 1255} 1256 1257static int 1258sk_probe(dev) 1259 device_t dev; 1260{ 1261 struct sk_softc *sc; 1262 1263 sc = device_get_softc(device_get_parent(dev)); 1264 1265 /* 1266 * Not much to do here. We always know there will be 1267 * at least one XMAC present, and if there are two, 1268 * skc_attach() will create a second device instance 1269 * for us. 1270 */ 1271 switch (sc->sk_type) { 1272 case SK_GENESIS: 1273 device_set_desc(dev, "XaQti Corp. XMAC II"); 1274 break; 1275 case SK_YUKON: 1276 device_set_desc(dev, "Marvell Semiconductor, Inc. Yukon"); 1277 break; 1278 } 1279 1280 return(0); 1281} 1282 1283/* 1284 * Each XMAC chip is attached as a separate logical IP interface. 1285 * Single port cards will have only one logical interface of course. 1286 */ 1287static int 1288sk_attach(dev) 1289 device_t dev; 1290{ 1291 struct sk_softc *sc; 1292 struct sk_if_softc *sc_if; 1293 struct ifnet *ifp; 1294 int i, port, error; 1295 1296 if (dev == NULL) 1297 return(EINVAL); 1298 1299 error = 0; 1300 sc_if = device_get_softc(dev); 1301 sc = device_get_softc(device_get_parent(dev)); 1302 SK_LOCK(sc); 1303 port = *(int *)device_get_ivars(dev); 1304 free(device_get_ivars(dev), M_DEVBUF); 1305 device_set_ivars(dev, NULL); 1306 1307 sc_if->sk_dev = dev; 1308 sc_if->sk_unit = device_get_unit(dev); 1309 sc_if->sk_port = port; 1310 sc_if->sk_softc = sc; 1311 sc->sk_if[port] = sc_if; 1312 if (port == SK_PORT_A) 1313 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0; 1314 if (port == SK_PORT_B) 1315 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1; 1316 1317 /* 1318 * Get station address for this interface. Note that 1319 * dual port cards actually come with three station 1320 * addresses: one for each port, plus an extra. The 1321 * extra one is used by the SysKonnect driver software 1322 * as a 'virtual' station address for when both ports 1323 * are operating in failover mode. Currently we don't 1324 * use this extra address. 1325 */ 1326 for (i = 0; i < ETHER_ADDR_LEN; i++) 1327 sc_if->arpcom.ac_enaddr[i] = 1328 sk_win_read_1(sc, SK_MAC0_0 + (port * 8) + i); 1329 1330 printf("sk%d: Ethernet address: %6D\n", 1331 sc_if->sk_unit, sc_if->arpcom.ac_enaddr, ":"); 1332 1333 /* 1334 * Set up RAM buffer addresses. The NIC will have a certain 1335 * amount of SRAM on it, somewhere between 512K and 2MB. We 1336 * need to divide this up a) between the transmitter and 1337 * receiver and b) between the two XMACs, if this is a 1338 * dual port NIC. Our algotithm is to divide up the memory 1339 * evenly so that everyone gets a fair share. 1340 */ 1341 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) { 1342 u_int32_t chunk, val; 1343 1344 chunk = sc->sk_ramsize / 2; 1345 val = sc->sk_rboff / sizeof(u_int64_t); 1346 sc_if->sk_rx_ramstart = val; 1347 val += (chunk / sizeof(u_int64_t)); 1348 sc_if->sk_rx_ramend = val - 1; 1349 sc_if->sk_tx_ramstart = val; 1350 val += (chunk / sizeof(u_int64_t)); 1351 sc_if->sk_tx_ramend = val - 1; 1352 } else { 1353 u_int32_t chunk, val; 1354 1355 chunk = sc->sk_ramsize / 4; 1356 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) / 1357 sizeof(u_int64_t); 1358 sc_if->sk_rx_ramstart = val; 1359 val += (chunk / sizeof(u_int64_t)); 1360 sc_if->sk_rx_ramend = val - 1; 1361 sc_if->sk_tx_ramstart = val; 1362 val += (chunk / sizeof(u_int64_t)); 1363 sc_if->sk_tx_ramend = val - 1; 1364 } 1365 1366 /* Read and save PHY type and set PHY address */ 1367 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 1368 switch(sc_if->sk_phytype) { 1369 case SK_PHYTYPE_XMAC: 1370 sc_if->sk_phyaddr = SK_PHYADDR_XMAC; 1371 break; 1372 case SK_PHYTYPE_BCOM: 1373 sc_if->sk_phyaddr = SK_PHYADDR_BCOM; 1374 break; 1375 case SK_PHYTYPE_MARV_COPPER: 1376 sc_if->sk_phyaddr = SK_PHYADDR_MARV; 1377 break; 1378 default: 1379 printf("skc%d: unsupported PHY type: %d\n", 1380 sc->sk_unit, sc_if->sk_phytype); 1381 error = ENODEV; 1382 goto fail; 1383 } 1384 1385 /* Allocate the descriptor queues. */ 1386 sc_if->sk_rdata = contigmalloc(sizeof(struct sk_ring_data), M_DEVBUF, 1387 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1388 1389 if (sc_if->sk_rdata == NULL) { 1390 printf("sk%d: no memory for list buffers!\n", sc_if->sk_unit); 1391 error = ENOMEM; 1392 goto fail; 1393 } 1394 1395 bzero(sc_if->sk_rdata, sizeof(struct sk_ring_data)); 1396 1397 /* Try to allocate memory for jumbo buffers. */ 1398 if (sk_alloc_jumbo_mem(sc_if)) { 1399 printf("sk%d: jumbo buffer allocation failed\n", 1400 sc_if->sk_unit); 1401 error = ENOMEM; 1402 goto fail; 1403 } 1404 1405 ifp = &sc_if->arpcom.ac_if; 1406 ifp->if_softc = sc_if; 1407 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1408 ifp->if_mtu = ETHERMTU; 1409 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1410 ifp->if_ioctl = sk_ioctl; 1411 ifp->if_output = ether_output; 1412 ifp->if_start = sk_start; 1413 ifp->if_watchdog = sk_watchdog; 1414 ifp->if_init = sk_init; 1415 ifp->if_baudrate = 1000000000; 1416 ifp->if_snd.ifq_maxlen = SK_TX_RING_CNT - 1; 1417 1418 callout_handle_init(&sc_if->sk_tick_ch); 1419 1420 /* 1421 * Call MI attach routine. 1422 */ 1423 ether_ifattach(ifp, sc_if->arpcom.ac_enaddr); 1424 1425 /* 1426 * Do miibus setup. 1427 */ 1428 switch (sc->sk_type) { 1429 case SK_GENESIS: 1430 sk_init_xmac(sc_if); 1431 break; 1432 case SK_YUKON: 1433 sk_init_yukon(sc_if); 1434 break; 1435 } 1436 1437 if (mii_phy_probe(dev, &sc_if->sk_miibus, 1438 sk_ifmedia_upd, sk_ifmedia_sts)) { 1439 printf("skc%d: no PHY found!\n", sc_if->sk_unit); 1440 ether_ifdetach(ifp); 1441 error = ENXIO; 1442 goto fail; 1443 } 1444 1445fail: 1446 SK_UNLOCK(sc); 1447 if (error) { 1448 /* Access should be ok even though lock has been dropped */ 1449 sc->sk_if[port] = NULL; 1450 sk_detach(dev); 1451 } 1452 1453 return(error); 1454} 1455 1456/* 1457 * Attach the interface. Allocate softc structures, do ifmedia 1458 * setup and ethernet/BPF attach. 1459 */ 1460static int 1461skc_attach(dev) 1462 device_t dev; 1463{ 1464 struct sk_softc *sc; 1465 int unit, error = 0, rid, *port; 1466 1467 sc = device_get_softc(dev); 1468 unit = device_get_unit(dev); 1469 1470 mtx_init(&sc->sk_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1471 MTX_DEF | MTX_RECURSE); 1472#ifndef BURN_BRIDGES 1473 /* 1474 * Handle power management nonsense. 1475 */ 1476 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1477 u_int32_t iobase, membase, irq; 1478 1479 /* Save important PCI config data. */ 1480 iobase = pci_read_config(dev, SK_PCI_LOIO, 4); 1481 membase = pci_read_config(dev, SK_PCI_LOMEM, 4); 1482 irq = pci_read_config(dev, SK_PCI_INTLINE, 4); 1483 1484 /* Reset the power state. */ 1485 printf("skc%d: chip is in D%d power mode " 1486 "-- setting to D0\n", unit, 1487 pci_get_powerstate(dev)); 1488 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1489 1490 /* Restore PCI config data. */ 1491 pci_write_config(dev, SK_PCI_LOIO, iobase, 4); 1492 pci_write_config(dev, SK_PCI_LOMEM, membase, 4); 1493 pci_write_config(dev, SK_PCI_INTLINE, irq, 4); 1494 } 1495#endif 1496 /* 1497 * Map control/status registers. 1498 */ 1499 pci_enable_busmaster(dev); 1500 1501 rid = SK_RID; 1502 sc->sk_res = bus_alloc_resource(dev, SK_RES, &rid, 1503 0, ~0, 1, RF_ACTIVE); 1504 1505 if (sc->sk_res == NULL) { 1506 printf("sk%d: couldn't map ports/memory\n", unit); 1507 error = ENXIO; 1508 goto fail; 1509 } 1510 1511 sc->sk_btag = rman_get_bustag(sc->sk_res); 1512 sc->sk_bhandle = rman_get_bushandle(sc->sk_res); 1513 1514 /* Allocate interrupt */ 1515 rid = 0; 1516 sc->sk_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1517 RF_SHAREABLE | RF_ACTIVE); 1518 1519 if (sc->sk_irq == NULL) { 1520 printf("skc%d: couldn't map interrupt\n", unit); 1521 error = ENXIO; 1522 goto fail; 1523 } 1524 1525 /* Set adapter type */ 1526 switch (pci_get_device(dev)) { 1527 case DEVICEID_SK_V1: 1528 sc->sk_type = SK_GENESIS; 1529 break; 1530 case DEVICEID_SK_V2: 1531 case DEVICEID_3COM_3C940: 1532 case DEVICEID_LINKSYS_EG1032: 1533 sc->sk_type = SK_YUKON; 1534 break; 1535 } 1536 1537 /* Reset the adapter. */ 1538 sk_reset(sc); 1539 1540 sc->sk_unit = unit; 1541 1542 /* Read and save vital product data from EEPROM. */ 1543 sk_vpd_read(sc); 1544 1545 if (sc->sk_type == SK_GENESIS) { 1546 /* Read and save RAM size and RAMbuffer offset */ 1547 switch(sk_win_read_1(sc, SK_EPROM0)) { 1548 case SK_RAMSIZE_512K_64: 1549 sc->sk_ramsize = 0x80000; 1550 sc->sk_rboff = SK_RBOFF_0; 1551 break; 1552 case SK_RAMSIZE_1024K_64: 1553 sc->sk_ramsize = 0x100000; 1554 sc->sk_rboff = SK_RBOFF_80000; 1555 break; 1556 case SK_RAMSIZE_1024K_128: 1557 sc->sk_ramsize = 0x100000; 1558 sc->sk_rboff = SK_RBOFF_0; 1559 break; 1560 case SK_RAMSIZE_2048K_128: 1561 sc->sk_ramsize = 0x200000; 1562 sc->sk_rboff = SK_RBOFF_0; 1563 break; 1564 default: 1565 printf("skc%d: unknown ram size: %d\n", 1566 sc->sk_unit, sk_win_read_1(sc, SK_EPROM0)); 1567 error = ENXIO; 1568 goto fail; 1569 } 1570 } else { 1571 sc->sk_ramsize = 0x20000; 1572 sc->sk_rboff = SK_RBOFF_0; 1573 } 1574 1575 /* Read and save physical media type */ 1576 switch(sk_win_read_1(sc, SK_PMDTYPE)) { 1577 case SK_PMD_1000BASESX: 1578 sc->sk_pmd = IFM_1000_SX; 1579 break; 1580 case SK_PMD_1000BASELX: 1581 sc->sk_pmd = IFM_1000_LX; 1582 break; 1583 case SK_PMD_1000BASECX: 1584 sc->sk_pmd = IFM_1000_CX; 1585 break; 1586 case SK_PMD_1000BASETX: 1587 sc->sk_pmd = IFM_1000_T; 1588 break; 1589 default: 1590 printf("skc%d: unknown media type: 0x%x\n", 1591 sc->sk_unit, sk_win_read_1(sc, SK_PMDTYPE)); 1592 error = ENXIO; 1593 goto fail; 1594 } 1595 1596 /* Announce the product name. */ 1597 printf("skc%d: %s\n", sc->sk_unit, sc->sk_vpd_prodname); 1598 sc->sk_devs[SK_PORT_A] = device_add_child(dev, "sk", -1); 1599 port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT); 1600 *port = SK_PORT_A; 1601 device_set_ivars(sc->sk_devs[SK_PORT_A], port); 1602 1603 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) { 1604 sc->sk_devs[SK_PORT_B] = device_add_child(dev, "sk", -1); 1605 port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT); 1606 *port = SK_PORT_B; 1607 device_set_ivars(sc->sk_devs[SK_PORT_B], port); 1608 } 1609 1610 /* Turn on the 'driver is loaded' LED. */ 1611 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1612 1613 bus_generic_attach(dev); 1614 1615 /* Hook interrupt last to avoid having to lock softc */ 1616 error = bus_setup_intr(dev, sc->sk_irq, INTR_TYPE_NET, 1617 sk_intr, sc, &sc->sk_intrhand); 1618 1619 if (error) { 1620 printf("skc%d: couldn't set up irq\n", unit); 1621 goto fail; 1622 } 1623 1624fail: 1625 if (error) 1626 skc_detach(dev); 1627 1628 return(error); 1629} 1630 1631/* 1632 * Shutdown hardware and free up resources. This can be called any 1633 * time after the mutex has been initialized. It is called in both 1634 * the error case in attach and the normal detach case so it needs 1635 * to be careful about only freeing resources that have actually been 1636 * allocated. 1637 */ 1638static int 1639sk_detach(dev) 1640 device_t dev; 1641{ 1642 struct sk_if_softc *sc_if; 1643 struct ifnet *ifp; 1644 1645 sc_if = device_get_softc(dev); 1646 KASSERT(mtx_initialized(&sc_if->sk_softc->sk_mtx), 1647 ("sk mutex not initialized in sk_detach")); 1648 SK_IF_LOCK(sc_if); 1649 1650 ifp = &sc_if->arpcom.ac_if; 1651 /* These should only be active if attach_xmac succeeded */ 1652 if (device_is_attached(dev)) { 1653 sk_stop(sc_if); 1654 ether_ifdetach(ifp); 1655 } 1656 if (sc_if->sk_miibus) 1657 device_delete_child(dev, sc_if->sk_miibus); 1658 bus_generic_detach(dev); 1659 if (sc_if->sk_cdata.sk_jumbo_buf) 1660 contigfree(sc_if->sk_cdata.sk_jumbo_buf, SK_JMEM, M_DEVBUF); 1661 if (sc_if->sk_rdata) { 1662 contigfree(sc_if->sk_rdata, sizeof(struct sk_ring_data), 1663 M_DEVBUF); 1664 } 1665 SK_IF_UNLOCK(sc_if); 1666 1667 return(0); 1668} 1669 1670static int 1671skc_detach(dev) 1672 device_t dev; 1673{ 1674 struct sk_softc *sc; 1675 1676 sc = device_get_softc(dev); 1677 KASSERT(mtx_initialized(&sc->sk_mtx), ("sk mutex not initialized")); 1678 SK_LOCK(sc); 1679 1680 if (device_is_alive(dev)) { 1681 if (sc->sk_devs[SK_PORT_A] != NULL) 1682 device_delete_child(dev, sc->sk_devs[SK_PORT_A]); 1683 if (sc->sk_devs[SK_PORT_B] != NULL) 1684 device_delete_child(dev, sc->sk_devs[SK_PORT_B]); 1685 bus_generic_detach(dev); 1686 } 1687 1688 if (sc->sk_intrhand) 1689 bus_teardown_intr(dev, sc->sk_irq, sc->sk_intrhand); 1690 if (sc->sk_irq) 1691 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq); 1692 if (sc->sk_res) 1693 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res); 1694 1695 SK_UNLOCK(sc); 1696 mtx_destroy(&sc->sk_mtx); 1697 1698 return(0); 1699} 1700 1701static int 1702sk_encap(sc_if, m_head, txidx) 1703 struct sk_if_softc *sc_if; 1704 struct mbuf *m_head; 1705 u_int32_t *txidx; 1706{ 1707 struct sk_tx_desc *f = NULL; 1708 struct mbuf *m; 1709 u_int32_t frag, cur, cnt = 0; 1710 1711 m = m_head; 1712 cur = frag = *txidx; 1713 1714 /* 1715 * Start packing the mbufs in this chain into 1716 * the fragment pointers. Stop when we run out 1717 * of fragments or hit the end of the mbuf chain. 1718 */ 1719 for (m = m_head; m != NULL; m = m->m_next) { 1720 if (m->m_len != 0) { 1721 if ((SK_TX_RING_CNT - 1722 (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2) 1723 return(ENOBUFS); 1724 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1725 f->sk_data_lo = vtophys(mtod(m, vm_offset_t)); 1726 f->sk_ctl = m->m_len | SK_OPCODE_DEFAULT; 1727 if (cnt == 0) 1728 f->sk_ctl |= SK_TXCTL_FIRSTFRAG; 1729 else 1730 f->sk_ctl |= SK_TXCTL_OWN; 1731 cur = frag; 1732 SK_INC(frag, SK_TX_RING_CNT); 1733 cnt++; 1734 } 1735 } 1736 1737 if (m != NULL) 1738 return(ENOBUFS); 1739 1740 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= 1741 SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR; 1742 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1743 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |= SK_TXCTL_OWN; 1744 sc_if->sk_cdata.sk_tx_cnt += cnt; 1745 1746 *txidx = frag; 1747 1748 return(0); 1749} 1750 1751static void 1752sk_start(ifp) 1753 struct ifnet *ifp; 1754{ 1755 struct sk_softc *sc; 1756 struct sk_if_softc *sc_if; 1757 struct mbuf *m_head = NULL; 1758 u_int32_t idx; 1759 1760 sc_if = ifp->if_softc; 1761 sc = sc_if->sk_softc; 1762 1763 SK_IF_LOCK(sc_if); 1764 1765 idx = sc_if->sk_cdata.sk_tx_prod; 1766 1767 while(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1768 IF_DEQUEUE(&ifp->if_snd, m_head); 1769 if (m_head == NULL) 1770 break; 1771 1772 /* 1773 * Pack the data into the transmit ring. If we 1774 * don't have room, set the OACTIVE flag and wait 1775 * for the NIC to drain the ring. 1776 */ 1777 if (sk_encap(sc_if, m_head, &idx)) { 1778 IF_PREPEND(&ifp->if_snd, m_head); 1779 ifp->if_flags |= IFF_OACTIVE; 1780 break; 1781 } 1782 1783 /* 1784 * If there's a BPF listener, bounce a copy of this frame 1785 * to him. 1786 */ 1787 BPF_MTAP(ifp, m_head); 1788 } 1789 1790 /* Transmit */ 1791 sc_if->sk_cdata.sk_tx_prod = idx; 1792 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 1793 1794 /* Set a timeout in case the chip goes out to lunch. */ 1795 ifp->if_timer = 5; 1796 SK_IF_UNLOCK(sc_if); 1797 1798 return; 1799} 1800 1801 1802static void 1803sk_watchdog(ifp) 1804 struct ifnet *ifp; 1805{ 1806 struct sk_if_softc *sc_if; 1807 1808 sc_if = ifp->if_softc; 1809 1810 printf("sk%d: watchdog timeout\n", sc_if->sk_unit); 1811 sk_init(sc_if); 1812 1813 return; 1814} 1815 1816static void 1817skc_shutdown(dev) 1818 device_t dev; 1819{ 1820 struct sk_softc *sc; 1821 1822 sc = device_get_softc(dev); 1823 SK_LOCK(sc); 1824 1825 /* Turn off the 'driver is loaded' LED. */ 1826 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 1827 1828 /* 1829 * Reset the GEnesis controller. Doing this should also 1830 * assert the resets on the attached XMAC(s). 1831 */ 1832 sk_reset(sc); 1833 SK_UNLOCK(sc); 1834 1835 return; 1836} 1837 1838static void 1839sk_rxeof(sc_if) 1840 struct sk_if_softc *sc_if; 1841{ 1842 struct sk_softc *sc; 1843 struct mbuf *m; 1844 struct ifnet *ifp; 1845 struct sk_chain *cur_rx; 1846 int total_len = 0; 1847 int i; 1848 u_int32_t rxstat; 1849 1850 sc = sc_if->sk_softc; 1851 ifp = &sc_if->arpcom.ac_if; 1852 i = sc_if->sk_cdata.sk_rx_prod; 1853 cur_rx = &sc_if->sk_cdata.sk_rx_chain[i]; 1854 1855 SK_LOCK_ASSERT(sc); 1856 1857 while(!(sc_if->sk_rdata->sk_rx_ring[i].sk_ctl & SK_RXCTL_OWN)) { 1858 1859 cur_rx = &sc_if->sk_cdata.sk_rx_chain[i]; 1860 rxstat = sc_if->sk_rdata->sk_rx_ring[i].sk_xmac_rxstat; 1861 m = cur_rx->sk_mbuf; 1862 cur_rx->sk_mbuf = NULL; 1863 total_len = SK_RXBYTES(sc_if->sk_rdata->sk_rx_ring[i].sk_ctl); 1864 SK_INC(i, SK_RX_RING_CNT); 1865 1866 if (rxstat & XM_RXSTAT_ERRFRAME) { 1867 ifp->if_ierrors++; 1868 sk_newbuf(sc_if, cur_rx, m); 1869 continue; 1870 } 1871 1872 /* 1873 * Try to allocate a new jumbo buffer. If that 1874 * fails, copy the packet to mbufs and put the 1875 * jumbo buffer back in the ring so it can be 1876 * re-used. If allocating mbufs fails, then we 1877 * have to drop the packet. 1878 */ 1879 if (sk_newbuf(sc_if, cur_rx, NULL) == ENOBUFS) { 1880 struct mbuf *m0; 1881 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, 1882 ifp, NULL); 1883 sk_newbuf(sc_if, cur_rx, m); 1884 if (m0 == NULL) { 1885 printf("sk%d: no receive buffers " 1886 "available -- packet dropped!\n", 1887 sc_if->sk_unit); 1888 ifp->if_ierrors++; 1889 continue; 1890 } 1891 m = m0; 1892 } else { 1893 m->m_pkthdr.rcvif = ifp; 1894 m->m_pkthdr.len = m->m_len = total_len; 1895 } 1896 1897 ifp->if_ipackets++; 1898 SK_UNLOCK(sc); 1899 (*ifp->if_input)(ifp, m); 1900 SK_LOCK(sc); 1901 } 1902 1903 sc_if->sk_cdata.sk_rx_prod = i; 1904 1905 return; 1906} 1907 1908static void 1909sk_txeof(sc_if) 1910 struct sk_if_softc *sc_if; 1911{ 1912 struct sk_tx_desc *cur_tx = NULL; 1913 struct ifnet *ifp; 1914 u_int32_t idx; 1915 1916 ifp = &sc_if->arpcom.ac_if; 1917 1918 /* 1919 * Go through our tx ring and free mbufs for those 1920 * frames that have been sent. 1921 */ 1922 idx = sc_if->sk_cdata.sk_tx_cons; 1923 while(idx != sc_if->sk_cdata.sk_tx_prod) { 1924 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 1925 if (cur_tx->sk_ctl & SK_TXCTL_OWN) 1926 break; 1927 if (cur_tx->sk_ctl & SK_TXCTL_LASTFRAG) 1928 ifp->if_opackets++; 1929 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 1930 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 1931 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 1932 } 1933 sc_if->sk_cdata.sk_tx_cnt--; 1934 SK_INC(idx, SK_TX_RING_CNT); 1935 ifp->if_timer = 0; 1936 } 1937 1938 sc_if->sk_cdata.sk_tx_cons = idx; 1939 1940 if (cur_tx != NULL) 1941 ifp->if_flags &= ~IFF_OACTIVE; 1942 1943 return; 1944} 1945 1946static void 1947sk_tick(xsc_if) 1948 void *xsc_if; 1949{ 1950 struct sk_if_softc *sc_if; 1951 struct mii_data *mii; 1952 struct ifnet *ifp; 1953 int i; 1954 1955 sc_if = xsc_if; 1956 SK_IF_LOCK(sc_if); 1957 ifp = &sc_if->arpcom.ac_if; 1958 mii = device_get_softc(sc_if->sk_miibus); 1959 1960 if (!(ifp->if_flags & IFF_UP)) { 1961 SK_IF_UNLOCK(sc_if); 1962 return; 1963 } 1964 1965 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 1966 sk_intr_bcom(sc_if); 1967 SK_IF_UNLOCK(sc_if); 1968 return; 1969 } 1970 1971 /* 1972 * According to SysKonnect, the correct way to verify that 1973 * the link has come back up is to poll bit 0 of the GPIO 1974 * register three times. This pin has the signal from the 1975 * link_sync pin connected to it; if we read the same link 1976 * state 3 times in a row, we know the link is up. 1977 */ 1978 for (i = 0; i < 3; i++) { 1979 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET) 1980 break; 1981 } 1982 1983 if (i != 3) { 1984 sc_if->sk_tick_ch = timeout(sk_tick, sc_if, hz); 1985 SK_IF_UNLOCK(sc_if); 1986 return; 1987 } 1988 1989 /* Turn the GP0 interrupt back on. */ 1990 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 1991 SK_XM_READ_2(sc_if, XM_ISR); 1992 mii_tick(mii); 1993 untimeout(sk_tick, sc_if, sc_if->sk_tick_ch); 1994 1995 SK_IF_UNLOCK(sc_if); 1996 return; 1997} 1998 1999static void 2000sk_intr_bcom(sc_if) 2001 struct sk_if_softc *sc_if; 2002{ 2003 struct mii_data *mii; 2004 struct ifnet *ifp; 2005 int status; 2006 mii = device_get_softc(sc_if->sk_miibus); 2007 ifp = &sc_if->arpcom.ac_if; 2008 2009 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2010 2011 /* 2012 * Read the PHY interrupt register to make sure 2013 * we clear any pending interrupts. 2014 */ 2015 status = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, BRGPHY_MII_ISR); 2016 2017 if (!(ifp->if_flags & IFF_RUNNING)) { 2018 sk_init_xmac(sc_if); 2019 return; 2020 } 2021 2022 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) { 2023 int lstat; 2024 lstat = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, 2025 BRGPHY_MII_AUXSTS); 2026 2027 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) { 2028 mii_mediachg(mii); 2029 /* Turn off the link LED. */ 2030 SK_IF_WRITE_1(sc_if, 0, 2031 SK_LINKLED1_CTL, SK_LINKLED_OFF); 2032 sc_if->sk_link = 0; 2033 } else if (status & BRGPHY_ISR_LNK_CHG) { 2034 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 2035 BRGPHY_MII_IMR, 0xFF00); 2036 mii_tick(mii); 2037 sc_if->sk_link = 1; 2038 /* Turn on the link LED. */ 2039 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2040 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF| 2041 SK_LINKLED_BLINK_OFF); 2042 } else { 2043 mii_tick(mii); 2044 sc_if->sk_tick_ch = timeout(sk_tick, sc_if, hz); 2045 } 2046 } 2047 2048 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2049 2050 return; 2051} 2052 2053static void 2054sk_intr_xmac(sc_if) 2055 struct sk_if_softc *sc_if; 2056{ 2057 struct sk_softc *sc; 2058 u_int16_t status; 2059 2060 sc = sc_if->sk_softc; 2061 status = SK_XM_READ_2(sc_if, XM_ISR); 2062 2063 /* 2064 * Link has gone down. Start MII tick timeout to 2065 * watch for link resync. 2066 */ 2067 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) { 2068 if (status & XM_ISR_GP0_SET) { 2069 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2070 sc_if->sk_tick_ch = timeout(sk_tick, sc_if, hz); 2071 } 2072 2073 if (status & XM_ISR_AUTONEG_DONE) { 2074 sc_if->sk_tick_ch = timeout(sk_tick, sc_if, hz); 2075 } 2076 } 2077 2078 if (status & XM_IMR_TX_UNDERRUN) 2079 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO); 2080 2081 if (status & XM_IMR_RX_OVERRUN) 2082 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO); 2083 2084 status = SK_XM_READ_2(sc_if, XM_ISR); 2085 2086 return; 2087} 2088 2089static void 2090sk_intr_yukon(sc_if) 2091 struct sk_if_softc *sc_if; 2092{ 2093 int status; 2094 2095 status = SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2096 2097 return; 2098} 2099 2100static void 2101sk_intr(xsc) 2102 void *xsc; 2103{ 2104 struct sk_softc *sc = xsc; 2105 struct sk_if_softc *sc_if0 = NULL, *sc_if1 = NULL; 2106 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2107 u_int32_t status; 2108 2109 SK_LOCK(sc); 2110 2111 sc_if0 = sc->sk_if[SK_PORT_A]; 2112 sc_if1 = sc->sk_if[SK_PORT_B]; 2113 2114 if (sc_if0 != NULL) 2115 ifp0 = &sc_if0->arpcom.ac_if; 2116 if (sc_if1 != NULL) 2117 ifp1 = &sc_if1->arpcom.ac_if; 2118 2119 for (;;) { 2120 status = CSR_READ_4(sc, SK_ISSR); 2121 if (!(status & sc->sk_intrmask)) 2122 break; 2123 2124 /* Handle receive interrupts first. */ 2125 if (status & SK_ISR_RX1_EOF) { 2126 sk_rxeof(sc_if0); 2127 CSR_WRITE_4(sc, SK_BMU_RX_CSR0, 2128 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2129 } 2130 if (status & SK_ISR_RX2_EOF) { 2131 sk_rxeof(sc_if1); 2132 CSR_WRITE_4(sc, SK_BMU_RX_CSR1, 2133 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2134 } 2135 2136 /* Then transmit interrupts. */ 2137 if (status & SK_ISR_TX1_S_EOF) { 2138 sk_txeof(sc_if0); 2139 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, 2140 SK_TXBMU_CLR_IRQ_EOF); 2141 } 2142 if (status & SK_ISR_TX2_S_EOF) { 2143 sk_txeof(sc_if1); 2144 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, 2145 SK_TXBMU_CLR_IRQ_EOF); 2146 } 2147 2148 /* Then MAC interrupts. */ 2149 if (status & SK_ISR_MAC1 && ifp0->if_flags & IFF_RUNNING) { 2150 if (sc->sk_type == SK_GENESIS) 2151 sk_intr_xmac(sc_if0); 2152 else 2153 sk_intr_yukon(sc_if0); 2154 } 2155 2156 if (status & SK_ISR_MAC2 && ifp1->if_flags & IFF_RUNNING) { 2157 if (sc->sk_type == SK_GENESIS) 2158 sk_intr_xmac(sc_if1); 2159 else 2160 sk_intr_yukon(sc_if0); 2161 } 2162 2163 if (status & SK_ISR_EXTERNAL_REG) { 2164 if (ifp0 != NULL && 2165 sc_if0->sk_phytype == SK_PHYTYPE_BCOM) 2166 sk_intr_bcom(sc_if0); 2167 if (ifp1 != NULL && 2168 sc_if1->sk_phytype == SK_PHYTYPE_BCOM) 2169 sk_intr_bcom(sc_if1); 2170 } 2171 } 2172 2173 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2174 2175 if (ifp0 != NULL && ifp0->if_snd.ifq_head != NULL) 2176 sk_start(ifp0); 2177 if (ifp1 != NULL && ifp1->if_snd.ifq_head != NULL) 2178 sk_start(ifp1); 2179 2180 SK_UNLOCK(sc); 2181 2182 return; 2183} 2184 2185static void 2186sk_init_xmac(sc_if) 2187 struct sk_if_softc *sc_if; 2188{ 2189 struct sk_softc *sc; 2190 struct ifnet *ifp; 2191 struct sk_bcom_hack bhack[] = { 2192 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, 2193 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, 2194 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 2195 { 0, 0 } }; 2196 2197 sc = sc_if->sk_softc; 2198 ifp = &sc_if->arpcom.ac_if; 2199 2200 /* Unreset the XMAC. */ 2201 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET); 2202 DELAY(1000); 2203 2204 /* Reset the XMAC's internal state. */ 2205 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2206 2207 /* Save the XMAC II revision */ 2208 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID)); 2209 2210 /* 2211 * Perform additional initialization for external PHYs, 2212 * namely for the 1000baseTX cards that use the XMAC's 2213 * GMII mode. 2214 */ 2215 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2216 int i = 0; 2217 u_int32_t val; 2218 2219 /* Take PHY out of reset. */ 2220 val = sk_win_read_4(sc, SK_GPIO); 2221 if (sc_if->sk_port == SK_PORT_A) 2222 val |= SK_GPIO_DIR0|SK_GPIO_DAT0; 2223 else 2224 val |= SK_GPIO_DIR2|SK_GPIO_DAT2; 2225 sk_win_write_4(sc, SK_GPIO, val); 2226 2227 /* Enable GMII mode on the XMAC. */ 2228 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE); 2229 2230 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 2231 BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET); 2232 DELAY(10000); 2233 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 2234 BRGPHY_MII_IMR, 0xFFF0); 2235 2236 /* 2237 * Early versions of the BCM5400 apparently have 2238 * a bug that requires them to have their reserved 2239 * registers initialized to some magic values. I don't 2240 * know what the numbers do, I'm just the messenger. 2241 */ 2242 if (sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, 0x03) 2243 == 0x6041) { 2244 while(bhack[i].reg) { 2245 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 2246 bhack[i].reg, bhack[i].val); 2247 i++; 2248 } 2249 } 2250 } 2251 2252 /* Set station address */ 2253 SK_XM_WRITE_2(sc_if, XM_PAR0, 2254 *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[0])); 2255 SK_XM_WRITE_2(sc_if, XM_PAR1, 2256 *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[2])); 2257 SK_XM_WRITE_2(sc_if, XM_PAR2, 2258 *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[4])); 2259 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION); 2260 2261 if (ifp->if_flags & IFF_PROMISC) { 2262 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2263 } else { 2264 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2265 } 2266 2267 if (ifp->if_flags & IFF_BROADCAST) { 2268 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2269 } else { 2270 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2271 } 2272 2273 /* We don't need the FCS appended to the packet. */ 2274 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS); 2275 2276 /* We want short frames padded to 60 bytes. */ 2277 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD); 2278 2279 /* 2280 * Enable the reception of all error frames. This is is 2281 * a necessary evil due to the design of the XMAC. The 2282 * XMAC's receive FIFO is only 8K in size, however jumbo 2283 * frames can be up to 9000 bytes in length. When bad 2284 * frame filtering is enabled, the XMAC's RX FIFO operates 2285 * in 'store and forward' mode. For this to work, the 2286 * entire frame has to fit into the FIFO, but that means 2287 * that jumbo frames larger than 8192 bytes will be 2288 * truncated. Disabling all bad frame filtering causes 2289 * the RX FIFO to operate in streaming mode, in which 2290 * case the XMAC will start transfering frames out of the 2291 * RX FIFO as soon as the FIFO threshold is reached. 2292 */ 2293 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES| 2294 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS| 2295 XM_MODE_RX_INRANGELEN); 2296 2297 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2298 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2299 else 2300 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2301 2302 /* 2303 * Bump up the transmit threshold. This helps hold off transmit 2304 * underruns when we're blasting traffic from both ports at once. 2305 */ 2306 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH); 2307 2308 /* Set multicast filter */ 2309 sk_setmulti(sc_if); 2310 2311 /* Clear and enable interrupts */ 2312 SK_XM_READ_2(sc_if, XM_ISR); 2313 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 2314 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS); 2315 else 2316 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2317 2318 /* Configure MAC arbiter */ 2319 switch(sc_if->sk_xmac_rev) { 2320 case XM_XMAC_REV_B2: 2321 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2); 2322 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2); 2323 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2); 2324 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2); 2325 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2); 2326 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2); 2327 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2); 2328 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2); 2329 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2330 break; 2331 case XM_XMAC_REV_C1: 2332 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1); 2333 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1); 2334 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1); 2335 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1); 2336 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1); 2337 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1); 2338 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1); 2339 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1); 2340 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2341 break; 2342 default: 2343 break; 2344 } 2345 sk_win_write_2(sc, SK_MACARB_CTL, 2346 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF); 2347 2348 sc_if->sk_link = 1; 2349 2350 return; 2351} 2352 2353static void sk_init_yukon(sc_if) 2354 struct sk_if_softc *sc_if; 2355{ 2356 u_int32_t phy; 2357 u_int16_t reg; 2358 int i; 2359 2360 /* GMAC and GPHY Reset */ 2361 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 2362 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2363 DELAY(1000); 2364 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_CLEAR); 2365 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2366 DELAY(1000); 2367 2368 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP | 2369 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE; 2370 2371 switch(sc_if->sk_softc->sk_pmd) { 2372 case IFM_1000_SX: 2373 case IFM_1000_LX: 2374 phy |= SK_GPHY_FIBER; 2375 break; 2376 2377 case IFM_1000_CX: 2378 case IFM_1000_T: 2379 phy |= SK_GPHY_COPPER; 2380 break; 2381 } 2382 2383 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET); 2384 DELAY(1000); 2385 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR); 2386 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 2387 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 2388 2389 /* unused read of the interrupt source register */ 2390 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2391 2392 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2393 2394 /* MIB Counter Clear Mode set */ 2395 reg |= YU_PAR_MIB_CLR; 2396 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2397 2398 /* MIB Counter Clear Mode clear */ 2399 reg &= ~YU_PAR_MIB_CLR; 2400 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2401 2402 /* receive control reg */ 2403 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_UFLEN | YU_RCR_MUFLEN | 2404 YU_RCR_CRCR); 2405 2406 /* transmit parameter register */ 2407 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2408 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) ); 2409 2410 /* serial mode register */ 2411 SK_YU_WRITE_2(sc_if, YUKON_SMR, YU_SMR_DATA_BLIND(0x1c) | 2412 YU_SMR_MFL_VLAN | YU_SMR_IPG_DATA(0x1e)); 2413 2414 /* Setup Yukon's address */ 2415 for (i = 0; i < 3; i++) { 2416 /* Write Source Address 1 (unicast filter) */ 2417 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2418 sc_if->arpcom.ac_enaddr[i * 2] | 2419 sc_if->arpcom.ac_enaddr[i * 2 + 1] << 8); 2420 } 2421 2422 for (i = 0; i < 3; i++) { 2423 reg = sk_win_read_2(sc_if->sk_softc, 2424 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2425 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2426 } 2427 2428 /* clear all Multicast filter hash registers */ 2429 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 2430 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 2431 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 2432 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 2433 2434 /* enable interrupt mask for counter overflows */ 2435 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2436 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2437 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2438 2439 /* Configure RX MAC FIFO */ 2440 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2441 SK_IF_WRITE_4(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON); 2442 2443 /* Configure TX MAC FIFO */ 2444 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2445 SK_IF_WRITE_4(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2446} 2447 2448/* 2449 * Note that to properly initialize any part of the GEnesis chip, 2450 * you first have to take it out of reset mode. 2451 */ 2452static void 2453sk_init(xsc) 2454 void *xsc; 2455{ 2456 struct sk_if_softc *sc_if = xsc; 2457 struct sk_softc *sc; 2458 struct ifnet *ifp; 2459 struct mii_data *mii; 2460 u_int16_t reg; 2461 2462 SK_IF_LOCK(sc_if); 2463 2464 ifp = &sc_if->arpcom.ac_if; 2465 sc = sc_if->sk_softc; 2466 mii = device_get_softc(sc_if->sk_miibus); 2467 2468 /* Cancel pending I/O and free all RX/TX buffers. */ 2469 sk_stop(sc_if); 2470 2471 if (sc->sk_type == SK_GENESIS) { 2472 /* Configure LINK_SYNC LED */ 2473 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON); 2474 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2475 SK_LINKLED_LINKSYNC_ON); 2476 2477 /* Configure RX LED */ 2478 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, 2479 SK_RXLEDCTL_COUNTER_START); 2480 2481 /* Configure TX LED */ 2482 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, 2483 SK_TXLEDCTL_COUNTER_START); 2484 } 2485 2486 /* Configure I2C registers */ 2487 2488 /* Configure XMAC(s) */ 2489 switch (sc->sk_type) { 2490 case SK_GENESIS: 2491 sk_init_xmac(sc_if); 2492 break; 2493 case SK_YUKON: 2494 sk_init_yukon(sc_if); 2495 break; 2496 } 2497 mii_mediachg(mii); 2498 2499 if (sc->sk_type == SK_GENESIS) { 2500 /* Configure MAC FIFOs */ 2501 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET); 2502 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END); 2503 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON); 2504 2505 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET); 2506 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END); 2507 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON); 2508 } 2509 2510 /* Configure transmit arbiter(s) */ 2511 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, 2512 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 2513 2514 /* Configure RAMbuffers */ 2515 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2516 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2517 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2518 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2519 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2520 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2521 2522 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET); 2523 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON); 2524 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart); 2525 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart); 2526 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart); 2527 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend); 2528 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON); 2529 2530 /* Configure BMUs */ 2531 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE); 2532 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 2533 vtophys(&sc_if->sk_rdata->sk_rx_ring[0])); 2534 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0); 2535 2536 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE); 2537 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO, 2538 vtophys(&sc_if->sk_rdata->sk_tx_ring[0])); 2539 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0); 2540 2541 /* Init descriptors */ 2542 if (sk_init_rx_ring(sc_if) == ENOBUFS) { 2543 printf("sk%d: initialization failed: no " 2544 "memory for rx buffers\n", sc_if->sk_unit); 2545 sk_stop(sc_if); 2546 SK_IF_UNLOCK(sc_if); 2547 return; 2548 } 2549 sk_init_tx_ring(sc_if); 2550 2551 /* Configure interrupt handling */ 2552 CSR_READ_4(sc, SK_ISSR); 2553 if (sc_if->sk_port == SK_PORT_A) 2554 sc->sk_intrmask |= SK_INTRS1; 2555 else 2556 sc->sk_intrmask |= SK_INTRS2; 2557 2558 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG; 2559 2560 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2561 2562 /* Start BMUs. */ 2563 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START); 2564 2565 switch(sc->sk_type) { 2566 case SK_GENESIS: 2567 /* Enable XMACs TX and RX state machines */ 2568 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE); 2569 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2570 break; 2571 case SK_YUKON: 2572 reg = SK_YU_READ_2(sc_if, YUKON_GPCR); 2573 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN; 2574 reg &= ~(YU_GPCR_SPEED_EN | YU_GPCR_DPLX_EN); 2575 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg); 2576 } 2577 2578 ifp->if_flags |= IFF_RUNNING; 2579 ifp->if_flags &= ~IFF_OACTIVE; 2580 2581 SK_IF_UNLOCK(sc_if); 2582 2583 return; 2584} 2585 2586static void 2587sk_stop(sc_if) 2588 struct sk_if_softc *sc_if; 2589{ 2590 int i; 2591 struct sk_softc *sc; 2592 struct ifnet *ifp; 2593 2594 SK_IF_LOCK(sc_if); 2595 sc = sc_if->sk_softc; 2596 ifp = &sc_if->arpcom.ac_if; 2597 2598 untimeout(sk_tick, sc_if, sc_if->sk_tick_ch); 2599 2600 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2601 u_int32_t val; 2602 2603 /* Put PHY back into reset. */ 2604 val = sk_win_read_4(sc, SK_GPIO); 2605 if (sc_if->sk_port == SK_PORT_A) { 2606 val |= SK_GPIO_DIR0; 2607 val &= ~SK_GPIO_DAT0; 2608 } else { 2609 val |= SK_GPIO_DIR2; 2610 val &= ~SK_GPIO_DAT2; 2611 } 2612 sk_win_write_4(sc, SK_GPIO, val); 2613 } 2614 2615 /* Turn off various components of this interface. */ 2616 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2617 switch (sc->sk_type) { 2618 case SK_GENESIS: 2619 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_RESET); 2620 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET); 2621 break; 2622 case SK_YUKON: 2623 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2624 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2625 break; 2626 } 2627 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2628 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2629 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE); 2630 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2631 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2632 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2633 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2634 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2635 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2636 2637 /* Disable interrupts */ 2638 if (sc_if->sk_port == SK_PORT_A) 2639 sc->sk_intrmask &= ~SK_INTRS1; 2640 else 2641 sc->sk_intrmask &= ~SK_INTRS2; 2642 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2643 2644 SK_XM_READ_2(sc_if, XM_ISR); 2645 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2646 2647 /* Free RX and TX mbufs still in the queues. */ 2648 for (i = 0; i < SK_RX_RING_CNT; i++) { 2649 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2650 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2651 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2652 } 2653 } 2654 2655 for (i = 0; i < SK_TX_RING_CNT; i++) { 2656 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2657 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2658 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2659 } 2660 } 2661 2662 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2663 SK_IF_UNLOCK(sc_if); 2664 return; 2665} 2666