if_sk.c revision 113545
1/* 2 * Copyright (c) 1997, 1998, 1999, 2000 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33/* 34 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 35 * the SK-984x series adapters, both single port and dual port. 36 * References: 37 * The XaQti XMAC II datasheet, 38 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 39 * The SysKonnect GEnesis manual, http://www.syskonnect.com 40 * 41 * Note: XaQti has been aquired by Vitesse, and Vitesse does not have the 42 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 43 * convenience to others until Vitesse corrects this problem: 44 * 45 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 46 * 47 * Written by Bill Paul <wpaul@ee.columbia.edu> 48 * Department of Electrical Engineering 49 * Columbia University, New York City 50 */ 51 52/* 53 * The SysKonnect gigabit ethernet adapters consist of two main 54 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 55 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 56 * components and a PHY while the GEnesis controller provides a PCI 57 * interface with DMA support. Each card may have between 512K and 58 * 2MB of SRAM on board depending on the configuration. 59 * 60 * The SysKonnect GEnesis controller can have either one or two XMAC 61 * chips connected to it, allowing single or dual port NIC configurations. 62 * SysKonnect has the distinction of being the only vendor on the market 63 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 64 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 65 * XMAC registers. This driver takes advantage of these features to allow 66 * both XMACs to operate as independent interfaces. 67 */ 68 69#include <sys/cdefs.h> 70__FBSDID("$FreeBSD: head/sys/dev/sk/if_sk.c 113545 2003-04-16 03:16:57Z mdodd $"); 71 72#include <sys/param.h> 73#include <sys/systm.h> 74#include <sys/sockio.h> 75#include <sys/mbuf.h> 76#include <sys/malloc.h> 77#include <sys/kernel.h> 78#include <sys/socket.h> 79#include <sys/queue.h> 80 81#include <net/if.h> 82#include <net/if_arp.h> 83#include <net/ethernet.h> 84#include <net/if_dl.h> 85#include <net/if_media.h> 86 87#include <net/bpf.h> 88 89#include <vm/vm.h> /* for vtophys */ 90#include <vm/pmap.h> /* for vtophys */ 91#include <machine/bus_pio.h> 92#include <machine/bus_memio.h> 93#include <machine/bus.h> 94#include <machine/resource.h> 95#include <sys/bus.h> 96#include <sys/rman.h> 97 98#include <dev/mii/mii.h> 99#include <dev/mii/miivar.h> 100#include <dev/mii/brgphyreg.h> 101 102#include <pci/pcireg.h> 103#include <pci/pcivar.h> 104 105#define SK_USEIOSPACE 106 107#include <pci/if_skreg.h> 108#include <pci/xmaciireg.h> 109 110MODULE_DEPEND(sk, pci, 1, 1, 1); 111MODULE_DEPEND(sk, ether, 1, 1, 1); 112MODULE_DEPEND(sk, miibus, 1, 1, 1); 113 114/* "controller miibus0" required. See GENERIC if you get errors here. */ 115#include "miibus_if.h" 116 117#ifndef lint 118static const char rcsid[] = 119 "$FreeBSD: head/sys/dev/sk/if_sk.c 113545 2003-04-16 03:16:57Z mdodd $"; 120#endif 121 122static struct sk_type sk_devs[] = { 123 { SK_VENDORID, SK_DEVICEID_GE, "SysKonnect Gigabit Ethernet" }, 124 { 0, 0, NULL } 125}; 126 127static int sk_probe (device_t); 128static int sk_attach (device_t); 129static int sk_detach (device_t); 130static int sk_detach_xmac (device_t); 131static int sk_probe_xmac (device_t); 132static int sk_attach_xmac (device_t); 133static void sk_tick (void *); 134static void sk_intr (void *); 135static void sk_intr_xmac (struct sk_if_softc *); 136static void sk_intr_bcom (struct sk_if_softc *); 137static void sk_rxeof (struct sk_if_softc *); 138static void sk_txeof (struct sk_if_softc *); 139static int sk_encap (struct sk_if_softc *, struct mbuf *, 140 u_int32_t *); 141static void sk_start (struct ifnet *); 142static int sk_ioctl (struct ifnet *, u_long, caddr_t); 143static void sk_init (void *); 144static void sk_init_xmac (struct sk_if_softc *); 145static void sk_stop (struct sk_if_softc *); 146static void sk_watchdog (struct ifnet *); 147static void sk_shutdown (device_t); 148static int sk_ifmedia_upd (struct ifnet *); 149static void sk_ifmedia_sts (struct ifnet *, struct ifmediareq *); 150static void sk_reset (struct sk_softc *); 151static int sk_newbuf (struct sk_if_softc *, 152 struct sk_chain *, struct mbuf *); 153static int sk_alloc_jumbo_mem (struct sk_if_softc *); 154static void *sk_jalloc (struct sk_if_softc *); 155static void sk_jfree (void *, void *); 156static int sk_init_rx_ring (struct sk_if_softc *); 157static void sk_init_tx_ring (struct sk_if_softc *); 158static u_int32_t sk_win_read_4 (struct sk_softc *, int); 159static u_int16_t sk_win_read_2 (struct sk_softc *, int); 160static u_int8_t sk_win_read_1 (struct sk_softc *, int); 161static void sk_win_write_4 (struct sk_softc *, int, u_int32_t); 162static void sk_win_write_2 (struct sk_softc *, int, u_int32_t); 163static void sk_win_write_1 (struct sk_softc *, int, u_int32_t); 164static u_int8_t sk_vpd_readbyte (struct sk_softc *, int); 165static void sk_vpd_read_res (struct sk_softc *, struct vpd_res *, int); 166static void sk_vpd_read (struct sk_softc *); 167 168static int sk_miibus_readreg (device_t, int, int); 169static int sk_miibus_writereg (device_t, int, int, int); 170static void sk_miibus_statchg (device_t); 171 172static u_int32_t sk_calchash (caddr_t); 173static void sk_setfilt (struct sk_if_softc *, caddr_t, int); 174static void sk_setmulti (struct sk_if_softc *); 175 176#ifdef SK_USEIOSPACE 177#define SK_RES SYS_RES_IOPORT 178#define SK_RID SK_PCI_LOIO 179#else 180#define SK_RES SYS_RES_MEMORY 181#define SK_RID SK_PCI_LOMEM 182#endif 183 184/* 185 * Note that we have newbus methods for both the GEnesis controller 186 * itself and the XMAC(s). The XMACs are children of the GEnesis, and 187 * the miibus code is a child of the XMACs. We need to do it this way 188 * so that the miibus drivers can access the PHY registers on the 189 * right PHY. It's not quite what I had in mind, but it's the only 190 * design that achieves the desired effect. 191 */ 192static device_method_t skc_methods[] = { 193 /* Device interface */ 194 DEVMETHOD(device_probe, sk_probe), 195 DEVMETHOD(device_attach, sk_attach), 196 DEVMETHOD(device_detach, sk_detach), 197 DEVMETHOD(device_shutdown, sk_shutdown), 198 199 /* bus interface */ 200 DEVMETHOD(bus_print_child, bus_generic_print_child), 201 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 202 203 { 0, 0 } 204}; 205 206static driver_t skc_driver = { 207 "skc", 208 skc_methods, 209 sizeof(struct sk_softc) 210}; 211 212static devclass_t skc_devclass; 213 214static device_method_t sk_methods[] = { 215 /* Device interface */ 216 DEVMETHOD(device_probe, sk_probe_xmac), 217 DEVMETHOD(device_attach, sk_attach_xmac), 218 DEVMETHOD(device_detach, sk_detach_xmac), 219 DEVMETHOD(device_shutdown, bus_generic_shutdown), 220 221 /* bus interface */ 222 DEVMETHOD(bus_print_child, bus_generic_print_child), 223 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 224 225 /* MII interface */ 226 DEVMETHOD(miibus_readreg, sk_miibus_readreg), 227 DEVMETHOD(miibus_writereg, sk_miibus_writereg), 228 DEVMETHOD(miibus_statchg, sk_miibus_statchg), 229 230 { 0, 0 } 231}; 232 233static driver_t sk_driver = { 234 "sk", 235 sk_methods, 236 sizeof(struct sk_if_softc) 237}; 238 239static devclass_t sk_devclass; 240 241DRIVER_MODULE(sk, pci, skc_driver, skc_devclass, 0, 0); 242DRIVER_MODULE(sk, skc, sk_driver, sk_devclass, 0, 0); 243DRIVER_MODULE(miibus, sk, miibus_driver, miibus_devclass, 0, 0); 244 245#define SK_SETBIT(sc, reg, x) \ 246 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 247 248#define SK_CLRBIT(sc, reg, x) \ 249 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 250 251#define SK_WIN_SETBIT_4(sc, reg, x) \ 252 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) | x) 253 254#define SK_WIN_CLRBIT_4(sc, reg, x) \ 255 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) & ~x) 256 257#define SK_WIN_SETBIT_2(sc, reg, x) \ 258 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) | x) 259 260#define SK_WIN_CLRBIT_2(sc, reg, x) \ 261 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) & ~x) 262 263static u_int32_t 264sk_win_read_4(sc, reg) 265 struct sk_softc *sc; 266 int reg; 267{ 268 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 269 return(CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg))); 270} 271 272static u_int16_t 273sk_win_read_2(sc, reg) 274 struct sk_softc *sc; 275 int reg; 276{ 277 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 278 return(CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg))); 279} 280 281static u_int8_t 282sk_win_read_1(sc, reg) 283 struct sk_softc *sc; 284 int reg; 285{ 286 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 287 return(CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg))); 288} 289 290static void 291sk_win_write_4(sc, reg, val) 292 struct sk_softc *sc; 293 int reg; 294 u_int32_t val; 295{ 296 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 297 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), val); 298 return; 299} 300 301static void 302sk_win_write_2(sc, reg, val) 303 struct sk_softc *sc; 304 int reg; 305 u_int32_t val; 306{ 307 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 308 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), (u_int32_t)val); 309 return; 310} 311 312static void 313sk_win_write_1(sc, reg, val) 314 struct sk_softc *sc; 315 int reg; 316 u_int32_t val; 317{ 318 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 319 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), val); 320 return; 321} 322 323/* 324 * The VPD EEPROM contains Vital Product Data, as suggested in 325 * the PCI 2.1 specification. The VPD data is separared into areas 326 * denoted by resource IDs. The SysKonnect VPD contains an ID string 327 * resource (the name of the adapter), a read-only area resource 328 * containing various key/data fields and a read/write area which 329 * can be used to store asset management information or log messages. 330 * We read the ID string and read-only into buffers attached to 331 * the controller softc structure for later use. At the moment, 332 * we only use the ID string during sk_attach(). 333 */ 334static u_int8_t 335sk_vpd_readbyte(sc, addr) 336 struct sk_softc *sc; 337 int addr; 338{ 339 int i; 340 341 sk_win_write_2(sc, SK_PCI_REG(SK_PCI_VPD_ADDR), addr); 342 for (i = 0; i < SK_TIMEOUT; i++) { 343 DELAY(1); 344 if (sk_win_read_2(sc, 345 SK_PCI_REG(SK_PCI_VPD_ADDR)) & SK_VPD_FLAG) 346 break; 347 } 348 349 if (i == SK_TIMEOUT) 350 return(0); 351 352 return(sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_DATA))); 353} 354 355static void 356sk_vpd_read_res(sc, res, addr) 357 struct sk_softc *sc; 358 struct vpd_res *res; 359 int addr; 360{ 361 int i; 362 u_int8_t *ptr; 363 364 ptr = (u_int8_t *)res; 365 for (i = 0; i < sizeof(struct vpd_res); i++) 366 ptr[i] = sk_vpd_readbyte(sc, i + addr); 367 368 return; 369} 370 371static void 372sk_vpd_read(sc) 373 struct sk_softc *sc; 374{ 375 int pos = 0, i; 376 struct vpd_res res; 377 378 if (sc->sk_vpd_prodname != NULL) 379 free(sc->sk_vpd_prodname, M_DEVBUF); 380 if (sc->sk_vpd_readonly != NULL) 381 free(sc->sk_vpd_readonly, M_DEVBUF); 382 sc->sk_vpd_prodname = NULL; 383 sc->sk_vpd_readonly = NULL; 384 385 sk_vpd_read_res(sc, &res, pos); 386 387 if (res.vr_id != VPD_RES_ID) { 388 printf("skc%d: bad VPD resource id: expected %x got %x\n", 389 sc->sk_unit, VPD_RES_ID, res.vr_id); 390 return; 391 } 392 393 pos += sizeof(res); 394 sc->sk_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 395 for (i = 0; i < res.vr_len; i++) 396 sc->sk_vpd_prodname[i] = sk_vpd_readbyte(sc, i + pos); 397 sc->sk_vpd_prodname[i] = '\0'; 398 pos += i; 399 400 sk_vpd_read_res(sc, &res, pos); 401 402 if (res.vr_id != VPD_RES_READ) { 403 printf("skc%d: bad VPD resource id: expected %x got %x\n", 404 sc->sk_unit, VPD_RES_READ, res.vr_id); 405 return; 406 } 407 408 pos += sizeof(res); 409 sc->sk_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 410 for (i = 0; i < res.vr_len + 1; i++) 411 sc->sk_vpd_readonly[i] = sk_vpd_readbyte(sc, i + pos); 412 413 return; 414} 415 416static int 417sk_miibus_readreg(dev, phy, reg) 418 device_t dev; 419 int phy, reg; 420{ 421 struct sk_if_softc *sc_if; 422 int i; 423 424 sc_if = device_get_softc(dev); 425 426 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0) 427 return(0); 428 429 SK_IF_LOCK(sc_if); 430 431 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 432 SK_XM_READ_2(sc_if, XM_PHY_DATA); 433 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 434 for (i = 0; i < SK_TIMEOUT; i++) { 435 DELAY(1); 436 if (SK_XM_READ_2(sc_if, XM_MMUCMD) & 437 XM_MMUCMD_PHYDATARDY) 438 break; 439 } 440 441 if (i == SK_TIMEOUT) { 442 printf("sk%d: phy failed to come ready\n", 443 sc_if->sk_unit); 444 return(0); 445 } 446 } 447 DELAY(1); 448 i = SK_XM_READ_2(sc_if, XM_PHY_DATA); 449 SK_IF_UNLOCK(sc_if); 450 return(i); 451} 452 453static int 454sk_miibus_writereg(dev, phy, reg, val) 455 device_t dev; 456 int phy, reg, val; 457{ 458 struct sk_if_softc *sc_if; 459 int i; 460 461 sc_if = device_get_softc(dev); 462 SK_IF_LOCK(sc_if); 463 464 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 465 for (i = 0; i < SK_TIMEOUT; i++) { 466 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 467 break; 468 } 469 470 if (i == SK_TIMEOUT) { 471 printf("sk%d: phy failed to come ready\n", sc_if->sk_unit); 472 return(ETIMEDOUT); 473 } 474 475 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val); 476 for (i = 0; i < SK_TIMEOUT; i++) { 477 DELAY(1); 478 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 479 break; 480 } 481 482 SK_IF_UNLOCK(sc_if); 483 484 if (i == SK_TIMEOUT) 485 printf("sk%d: phy write timed out\n", sc_if->sk_unit); 486 487 return(0); 488} 489 490static void 491sk_miibus_statchg(dev) 492 device_t dev; 493{ 494 struct sk_if_softc *sc_if; 495 struct mii_data *mii; 496 497 sc_if = device_get_softc(dev); 498 mii = device_get_softc(sc_if->sk_miibus); 499 SK_IF_LOCK(sc_if); 500 /* 501 * If this is a GMII PHY, manually set the XMAC's 502 * duplex mode accordingly. 503 */ 504 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 505 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 506 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 507 } else { 508 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 509 } 510 } 511 SK_IF_UNLOCK(sc_if); 512 513 return; 514} 515 516#define SK_POLY 0xEDB88320 517#define SK_BITS 6 518 519static u_int32_t 520sk_calchash(addr) 521 caddr_t addr; 522{ 523 u_int32_t idx, bit, data, crc; 524 525 /* Compute CRC for the address value. */ 526 crc = 0xFFFFFFFF; /* initial value */ 527 528 for (idx = 0; idx < 6; idx++) { 529 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 530 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? SK_POLY : 0); 531 } 532 533 return (~crc & ((1 << SK_BITS) - 1)); 534} 535 536static void 537sk_setfilt(sc_if, addr, slot) 538 struct sk_if_softc *sc_if; 539 caddr_t addr; 540 int slot; 541{ 542 int base; 543 544 base = XM_RXFILT_ENTRY(slot); 545 546 SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0])); 547 SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2])); 548 SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4])); 549 550 return; 551} 552 553static void 554sk_setmulti(sc_if) 555 struct sk_if_softc *sc_if; 556{ 557 struct ifnet *ifp; 558 u_int32_t hashes[2] = { 0, 0 }; 559 int h, i; 560 struct ifmultiaddr *ifma; 561 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 562 563 ifp = &sc_if->arpcom.ac_if; 564 565 /* First, zot all the existing filters. */ 566 for (i = 1; i < XM_RXFILT_MAX; i++) 567 sk_setfilt(sc_if, (caddr_t)&dummy, i); 568 SK_XM_WRITE_4(sc_if, XM_MAR0, 0); 569 SK_XM_WRITE_4(sc_if, XM_MAR2, 0); 570 571 /* Now program new ones. */ 572 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 573 hashes[0] = 0xFFFFFFFF; 574 hashes[1] = 0xFFFFFFFF; 575 } else { 576 i = 1; 577 TAILQ_FOREACH_REVERSE(ifma, &ifp->if_multiaddrs, ifmultihead, ifma_link) { 578 if (ifma->ifma_addr->sa_family != AF_LINK) 579 continue; 580 /* 581 * Program the first XM_RXFILT_MAX multicast groups 582 * into the perfect filter. For all others, 583 * use the hash table. 584 */ 585 if (i < XM_RXFILT_MAX) { 586 sk_setfilt(sc_if, 587 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i); 588 i++; 589 continue; 590 } 591 592 h = sk_calchash( 593 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 594 if (h < 32) 595 hashes[0] |= (1 << h); 596 else 597 hashes[1] |= (1 << (h - 32)); 598 } 599 } 600 601 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH| 602 XM_MODE_RX_USE_PERFECT); 603 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]); 604 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]); 605 606 return; 607} 608 609static int 610sk_init_rx_ring(sc_if) 611 struct sk_if_softc *sc_if; 612{ 613 struct sk_chain_data *cd; 614 struct sk_ring_data *rd; 615 int i; 616 617 cd = &sc_if->sk_cdata; 618 rd = sc_if->sk_rdata; 619 620 bzero((char *)rd->sk_rx_ring, 621 sizeof(struct sk_rx_desc) * SK_RX_RING_CNT); 622 623 for (i = 0; i < SK_RX_RING_CNT; i++) { 624 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i]; 625 if (sk_newbuf(sc_if, &cd->sk_rx_chain[i], NULL) == ENOBUFS) 626 return(ENOBUFS); 627 if (i == (SK_RX_RING_CNT - 1)) { 628 cd->sk_rx_chain[i].sk_next = 629 &cd->sk_rx_chain[0]; 630 rd->sk_rx_ring[i].sk_next = 631 vtophys(&rd->sk_rx_ring[0]); 632 } else { 633 cd->sk_rx_chain[i].sk_next = 634 &cd->sk_rx_chain[i + 1]; 635 rd->sk_rx_ring[i].sk_next = 636 vtophys(&rd->sk_rx_ring[i + 1]); 637 } 638 } 639 640 sc_if->sk_cdata.sk_rx_prod = 0; 641 sc_if->sk_cdata.sk_rx_cons = 0; 642 643 return(0); 644} 645 646static void 647sk_init_tx_ring(sc_if) 648 struct sk_if_softc *sc_if; 649{ 650 struct sk_chain_data *cd; 651 struct sk_ring_data *rd; 652 int i; 653 654 cd = &sc_if->sk_cdata; 655 rd = sc_if->sk_rdata; 656 657 bzero((char *)sc_if->sk_rdata->sk_tx_ring, 658 sizeof(struct sk_tx_desc) * SK_TX_RING_CNT); 659 660 for (i = 0; i < SK_TX_RING_CNT; i++) { 661 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i]; 662 if (i == (SK_TX_RING_CNT - 1)) { 663 cd->sk_tx_chain[i].sk_next = 664 &cd->sk_tx_chain[0]; 665 rd->sk_tx_ring[i].sk_next = 666 vtophys(&rd->sk_tx_ring[0]); 667 } else { 668 cd->sk_tx_chain[i].sk_next = 669 &cd->sk_tx_chain[i + 1]; 670 rd->sk_tx_ring[i].sk_next = 671 vtophys(&rd->sk_tx_ring[i + 1]); 672 } 673 } 674 675 sc_if->sk_cdata.sk_tx_prod = 0; 676 sc_if->sk_cdata.sk_tx_cons = 0; 677 sc_if->sk_cdata.sk_tx_cnt = 0; 678 679 return; 680} 681 682static int 683sk_newbuf(sc_if, c, m) 684 struct sk_if_softc *sc_if; 685 struct sk_chain *c; 686 struct mbuf *m; 687{ 688 struct mbuf *m_new = NULL; 689 struct sk_rx_desc *r; 690 691 if (m == NULL) { 692 caddr_t *buf = NULL; 693 694 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 695 if (m_new == NULL) 696 return(ENOBUFS); 697 698 /* Allocate the jumbo buffer */ 699 buf = sk_jalloc(sc_if); 700 if (buf == NULL) { 701 m_freem(m_new); 702#ifdef SK_VERBOSE 703 printf("sk%d: jumbo allocation failed " 704 "-- packet dropped!\n", sc_if->sk_unit); 705#endif 706 return(ENOBUFS); 707 } 708 709 /* Attach the buffer to the mbuf */ 710 MEXTADD(m_new, buf, SK_JLEN, sk_jfree, 711 (struct sk_if_softc *)sc_if, 0, EXT_NET_DRV); 712 m_new->m_data = (void *)buf; 713 m_new->m_pkthdr.len = m_new->m_len = SK_JLEN; 714 } else { 715 /* 716 * We're re-using a previously allocated mbuf; 717 * be sure to re-init pointers and lengths to 718 * default values. 719 */ 720 m_new = m; 721 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 722 m_new->m_data = m_new->m_ext.ext_buf; 723 } 724 725 /* 726 * Adjust alignment so packet payload begins on a 727 * longword boundary. Mandatory for Alpha, useful on 728 * x86 too. 729 */ 730 m_adj(m_new, ETHER_ALIGN); 731 732 r = c->sk_desc; 733 c->sk_mbuf = m_new; 734 r->sk_data_lo = vtophys(mtod(m_new, caddr_t)); 735 r->sk_ctl = m_new->m_len | SK_RXSTAT; 736 737 return(0); 738} 739 740/* 741 * Allocate jumbo buffer storage. The SysKonnect adapters support 742 * "jumbograms" (9K frames), although SysKonnect doesn't currently 743 * use them in their drivers. In order for us to use them, we need 744 * large 9K receive buffers, however standard mbuf clusters are only 745 * 2048 bytes in size. Consequently, we need to allocate and manage 746 * our own jumbo buffer pool. Fortunately, this does not require an 747 * excessive amount of additional code. 748 */ 749static int 750sk_alloc_jumbo_mem(sc_if) 751 struct sk_if_softc *sc_if; 752{ 753 caddr_t ptr; 754 register int i; 755 struct sk_jpool_entry *entry; 756 757 /* Grab a big chunk o' storage. */ 758 sc_if->sk_cdata.sk_jumbo_buf = contigmalloc(SK_JMEM, M_DEVBUF, 759 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 760 761 if (sc_if->sk_cdata.sk_jumbo_buf == NULL) { 762 printf("sk%d: no memory for jumbo buffers!\n", sc_if->sk_unit); 763 return(ENOBUFS); 764 } 765 766 SLIST_INIT(&sc_if->sk_jfree_listhead); 767 SLIST_INIT(&sc_if->sk_jinuse_listhead); 768 769 /* 770 * Now divide it up into 9K pieces and save the addresses 771 * in an array. 772 */ 773 ptr = sc_if->sk_cdata.sk_jumbo_buf; 774 for (i = 0; i < SK_JSLOTS; i++) { 775 sc_if->sk_cdata.sk_jslots[i] = ptr; 776 ptr += SK_JLEN; 777 entry = malloc(sizeof(struct sk_jpool_entry), 778 M_DEVBUF, M_NOWAIT); 779 if (entry == NULL) { 780 free(sc_if->sk_cdata.sk_jumbo_buf, M_DEVBUF); 781 sc_if->sk_cdata.sk_jumbo_buf = NULL; 782 printf("sk%d: no memory for jumbo " 783 "buffer queue!\n", sc_if->sk_unit); 784 return(ENOBUFS); 785 } 786 entry->slot = i; 787 SLIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 788 entry, jpool_entries); 789 } 790 791 return(0); 792} 793 794/* 795 * Allocate a jumbo buffer. 796 */ 797static void * 798sk_jalloc(sc_if) 799 struct sk_if_softc *sc_if; 800{ 801 struct sk_jpool_entry *entry; 802 803 entry = SLIST_FIRST(&sc_if->sk_jfree_listhead); 804 805 if (entry == NULL) { 806#ifdef SK_VERBOSE 807 printf("sk%d: no free jumbo buffers\n", sc_if->sk_unit); 808#endif 809 return(NULL); 810 } 811 812 SLIST_REMOVE_HEAD(&sc_if->sk_jfree_listhead, jpool_entries); 813 SLIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 814 return(sc_if->sk_cdata.sk_jslots[entry->slot]); 815} 816 817/* 818 * Release a jumbo buffer. 819 */ 820static void 821sk_jfree(buf, args) 822 void *buf; 823 void *args; 824{ 825 struct sk_if_softc *sc_if; 826 int i; 827 struct sk_jpool_entry *entry; 828 829 /* Extract the softc struct pointer. */ 830 sc_if = (struct sk_if_softc *)args; 831 832 if (sc_if == NULL) 833 panic("sk_jfree: didn't get softc pointer!"); 834 835 /* calculate the slot this buffer belongs to */ 836 i = ((vm_offset_t)buf 837 - (vm_offset_t)sc_if->sk_cdata.sk_jumbo_buf) / SK_JLEN; 838 839 if ((i < 0) || (i >= SK_JSLOTS)) 840 panic("sk_jfree: asked to free buffer that we don't manage!"); 841 842 entry = SLIST_FIRST(&sc_if->sk_jinuse_listhead); 843 if (entry == NULL) 844 panic("sk_jfree: buffer not in use!"); 845 entry->slot = i; 846 SLIST_REMOVE_HEAD(&sc_if->sk_jinuse_listhead, jpool_entries); 847 SLIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, entry, jpool_entries); 848 849 return; 850} 851 852/* 853 * Set media options. 854 */ 855static int 856sk_ifmedia_upd(ifp) 857 struct ifnet *ifp; 858{ 859 struct sk_if_softc *sc_if; 860 struct mii_data *mii; 861 862 sc_if = ifp->if_softc; 863 mii = device_get_softc(sc_if->sk_miibus); 864 sk_init(sc_if); 865 mii_mediachg(mii); 866 867 return(0); 868} 869 870/* 871 * Report current media status. 872 */ 873static void 874sk_ifmedia_sts(ifp, ifmr) 875 struct ifnet *ifp; 876 struct ifmediareq *ifmr; 877{ 878 struct sk_if_softc *sc_if; 879 struct mii_data *mii; 880 881 sc_if = ifp->if_softc; 882 mii = device_get_softc(sc_if->sk_miibus); 883 884 mii_pollstat(mii); 885 ifmr->ifm_active = mii->mii_media_active; 886 ifmr->ifm_status = mii->mii_media_status; 887 888 return; 889} 890 891static int 892sk_ioctl(ifp, command, data) 893 struct ifnet *ifp; 894 u_long command; 895 caddr_t data; 896{ 897 struct sk_if_softc *sc_if = ifp->if_softc; 898 struct ifreq *ifr = (struct ifreq *) data; 899 int error = 0; 900 struct mii_data *mii; 901 902 SK_IF_LOCK(sc_if); 903 904 switch(command) { 905 case SIOCSIFMTU: 906 if (ifr->ifr_mtu > SK_JUMBO_MTU) 907 error = EINVAL; 908 else { 909 ifp->if_mtu = ifr->ifr_mtu; 910 sk_init(sc_if); 911 } 912 break; 913 case SIOCSIFFLAGS: 914 if (ifp->if_flags & IFF_UP) { 915 if (ifp->if_flags & IFF_RUNNING && 916 ifp->if_flags & IFF_PROMISC && 917 !(sc_if->sk_if_flags & IFF_PROMISC)) { 918 SK_XM_SETBIT_4(sc_if, XM_MODE, 919 XM_MODE_RX_PROMISC); 920 sk_setmulti(sc_if); 921 } else if (ifp->if_flags & IFF_RUNNING && 922 !(ifp->if_flags & IFF_PROMISC) && 923 sc_if->sk_if_flags & IFF_PROMISC) { 924 SK_XM_CLRBIT_4(sc_if, XM_MODE, 925 XM_MODE_RX_PROMISC); 926 sk_setmulti(sc_if); 927 } else 928 sk_init(sc_if); 929 } else { 930 if (ifp->if_flags & IFF_RUNNING) 931 sk_stop(sc_if); 932 } 933 sc_if->sk_if_flags = ifp->if_flags; 934 error = 0; 935 break; 936 case SIOCADDMULTI: 937 case SIOCDELMULTI: 938 sk_setmulti(sc_if); 939 error = 0; 940 break; 941 case SIOCGIFMEDIA: 942 case SIOCSIFMEDIA: 943 mii = device_get_softc(sc_if->sk_miibus); 944 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 945 break; 946 default: 947 error = ether_ioctl(ifp, command, data); 948 break; 949 } 950 951 SK_IF_UNLOCK(sc_if); 952 953 return(error); 954} 955 956/* 957 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device 958 * IDs against our list and return a device name if we find a match. 959 */ 960static int 961sk_probe(dev) 962 device_t dev; 963{ 964 struct sk_type *t; 965 966 t = sk_devs; 967 968 while(t->sk_name != NULL) { 969 if ((pci_get_vendor(dev) == t->sk_vid) && 970 (pci_get_device(dev) == t->sk_did)) { 971 device_set_desc(dev, t->sk_name); 972 return(0); 973 } 974 t++; 975 } 976 977 return(ENXIO); 978} 979 980/* 981 * Force the GEnesis into reset, then bring it out of reset. 982 */ 983static void 984sk_reset(sc) 985 struct sk_softc *sc; 986{ 987 CSR_WRITE_4(sc, SK_CSR, SK_CSR_SW_RESET); 988 CSR_WRITE_4(sc, SK_CSR, SK_CSR_MASTER_RESET); 989 DELAY(1000); 990 CSR_WRITE_4(sc, SK_CSR, SK_CSR_SW_UNRESET); 991 CSR_WRITE_4(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 992 993 /* Configure packet arbiter */ 994 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET); 995 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT); 996 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT); 997 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT); 998 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT); 999 1000 /* Enable RAM interface */ 1001 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 1002 1003 /* 1004 * Configure interrupt moderation. The moderation timer 1005 * defers interrupts specified in the interrupt moderation 1006 * timer mask based on the timeout specified in the interrupt 1007 * moderation timer init register. Each bit in the timer 1008 * register represents 18.825ns, so to specify a timeout in 1009 * microseconds, we have to multiply by 54. 1010 */ 1011 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(200)); 1012 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 1013 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 1014 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 1015 1016 return; 1017} 1018 1019static int 1020sk_probe_xmac(dev) 1021 device_t dev; 1022{ 1023 /* 1024 * Not much to do here. We always know there will be 1025 * at least one XMAC present, and if there are two, 1026 * sk_attach() will create a second device instance 1027 * for us. 1028 */ 1029 device_set_desc(dev, "XaQti Corp. XMAC II"); 1030 1031 return(0); 1032} 1033 1034/* 1035 * Each XMAC chip is attached as a separate logical IP interface. 1036 * Single port cards will have only one logical interface of course. 1037 */ 1038static int 1039sk_attach_xmac(dev) 1040 device_t dev; 1041{ 1042 struct sk_softc *sc; 1043 struct sk_if_softc *sc_if; 1044 struct ifnet *ifp; 1045 int i, port, error; 1046 1047 if (dev == NULL) 1048 return(EINVAL); 1049 1050 error = 0; 1051 sc_if = device_get_softc(dev); 1052 sc = device_get_softc(device_get_parent(dev)); 1053 SK_LOCK(sc); 1054 port = *(int *)device_get_ivars(dev); 1055 free(device_get_ivars(dev), M_DEVBUF); 1056 device_set_ivars(dev, NULL); 1057 1058 sc_if->sk_dev = dev; 1059 sc_if->sk_unit = device_get_unit(dev); 1060 sc_if->sk_port = port; 1061 sc_if->sk_softc = sc; 1062 sc->sk_if[port] = sc_if; 1063 if (port == SK_PORT_A) 1064 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0; 1065 if (port == SK_PORT_B) 1066 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1; 1067 1068 /* 1069 * Get station address for this interface. Note that 1070 * dual port cards actually come with three station 1071 * addresses: one for each port, plus an extra. The 1072 * extra one is used by the SysKonnect driver software 1073 * as a 'virtual' station address for when both ports 1074 * are operating in failover mode. Currently we don't 1075 * use this extra address. 1076 */ 1077 for (i = 0; i < ETHER_ADDR_LEN; i++) 1078 sc_if->arpcom.ac_enaddr[i] = 1079 sk_win_read_1(sc, SK_MAC0_0 + (port * 8) + i); 1080 1081 printf("sk%d: Ethernet address: %6D\n", 1082 sc_if->sk_unit, sc_if->arpcom.ac_enaddr, ":"); 1083 1084 /* 1085 * Set up RAM buffer addresses. The NIC will have a certain 1086 * amount of SRAM on it, somewhere between 512K and 2MB. We 1087 * need to divide this up a) between the transmitter and 1088 * receiver and b) between the two XMACs, if this is a 1089 * dual port NIC. Our algotithm is to divide up the memory 1090 * evenly so that everyone gets a fair share. 1091 */ 1092 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) { 1093 u_int32_t chunk, val; 1094 1095 chunk = sc->sk_ramsize / 2; 1096 val = sc->sk_rboff / sizeof(u_int64_t); 1097 sc_if->sk_rx_ramstart = val; 1098 val += (chunk / sizeof(u_int64_t)); 1099 sc_if->sk_rx_ramend = val - 1; 1100 sc_if->sk_tx_ramstart = val; 1101 val += (chunk / sizeof(u_int64_t)); 1102 sc_if->sk_tx_ramend = val - 1; 1103 } else { 1104 u_int32_t chunk, val; 1105 1106 chunk = sc->sk_ramsize / 4; 1107 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) / 1108 sizeof(u_int64_t); 1109 sc_if->sk_rx_ramstart = val; 1110 val += (chunk / sizeof(u_int64_t)); 1111 sc_if->sk_rx_ramend = val - 1; 1112 sc_if->sk_tx_ramstart = val; 1113 val += (chunk / sizeof(u_int64_t)); 1114 sc_if->sk_tx_ramend = val - 1; 1115 } 1116 1117 /* Read and save PHY type and set PHY address */ 1118 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 1119 switch(sc_if->sk_phytype) { 1120 case SK_PHYTYPE_XMAC: 1121 sc_if->sk_phyaddr = SK_PHYADDR_XMAC; 1122 break; 1123 case SK_PHYTYPE_BCOM: 1124 sc_if->sk_phyaddr = SK_PHYADDR_BCOM; 1125 break; 1126 default: 1127 printf("skc%d: unsupported PHY type: %d\n", 1128 sc->sk_unit, sc_if->sk_phytype); 1129 error = ENODEV; 1130 goto fail_xmac; 1131 } 1132 1133 /* Allocate the descriptor queues. */ 1134 sc_if->sk_rdata = contigmalloc(sizeof(struct sk_ring_data), M_DEVBUF, 1135 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1136 1137 if (sc_if->sk_rdata == NULL) { 1138 printf("sk%d: no memory for list buffers!\n", sc_if->sk_unit); 1139 error = ENOMEM; 1140 goto fail_xmac; 1141 } 1142 1143 bzero(sc_if->sk_rdata, sizeof(struct sk_ring_data)); 1144 1145 /* Try to allocate memory for jumbo buffers. */ 1146 if (sk_alloc_jumbo_mem(sc_if)) { 1147 printf("sk%d: jumbo buffer allocation failed\n", 1148 sc_if->sk_unit); 1149 error = ENOMEM; 1150 goto fail_xmac; 1151 } 1152 1153 ifp = &sc_if->arpcom.ac_if; 1154 ifp->if_softc = sc_if; 1155 ifp->if_unit = sc_if->sk_unit; 1156 ifp->if_name = "sk"; 1157 ifp->if_mtu = ETHERMTU; 1158 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1159 ifp->if_ioctl = sk_ioctl; 1160 ifp->if_output = ether_output; 1161 ifp->if_start = sk_start; 1162 ifp->if_watchdog = sk_watchdog; 1163 ifp->if_init = sk_init; 1164 ifp->if_baudrate = 1000000000; 1165 ifp->if_snd.ifq_maxlen = SK_TX_RING_CNT - 1; 1166 1167 callout_handle_init(&sc_if->sk_tick_ch); 1168 1169 /* 1170 * Call MI attach routine. 1171 */ 1172 ether_ifattach(ifp, sc_if->arpcom.ac_enaddr); 1173 1174 /* 1175 * Do miibus setup. 1176 */ 1177 sk_init_xmac(sc_if); 1178 if (mii_phy_probe(dev, &sc_if->sk_miibus, 1179 sk_ifmedia_upd, sk_ifmedia_sts)) { 1180 printf("skc%d: no PHY found!\n", sc_if->sk_unit); 1181 error = ENXIO; 1182 goto fail_xmac; 1183 } 1184 1185fail_xmac: 1186 SK_UNLOCK(sc); 1187 if (error) { 1188 /* Access should be ok even though lock has been dropped */ 1189 sc->sk_if[port] = NULL; 1190 sk_detach_xmac(dev); 1191 } 1192 1193 return(error); 1194} 1195 1196/* 1197 * Attach the interface. Allocate softc structures, do ifmedia 1198 * setup and ethernet/BPF attach. 1199 */ 1200static int 1201sk_attach(dev) 1202 device_t dev; 1203{ 1204 struct sk_softc *sc; 1205 int unit, error = 0, rid, *port; 1206 1207 sc = device_get_softc(dev); 1208 unit = device_get_unit(dev); 1209 1210 mtx_init(&sc->sk_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1211 MTX_DEF | MTX_RECURSE); 1212 1213 /* 1214 * Handle power management nonsense. 1215 */ 1216 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1217 u_int32_t iobase, membase, irq; 1218 1219 /* Save important PCI config data. */ 1220 iobase = pci_read_config(dev, SK_PCI_LOIO, 4); 1221 membase = pci_read_config(dev, SK_PCI_LOMEM, 4); 1222 irq = pci_read_config(dev, SK_PCI_INTLINE, 4); 1223 1224 /* Reset the power state. */ 1225 printf("skc%d: chip is in D%d power mode " 1226 "-- setting to D0\n", unit, 1227 pci_get_powerstate(dev)); 1228 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1229 1230 /* Restore PCI config data. */ 1231 pci_write_config(dev, SK_PCI_LOIO, iobase, 4); 1232 pci_write_config(dev, SK_PCI_LOMEM, membase, 4); 1233 pci_write_config(dev, SK_PCI_INTLINE, irq, 4); 1234 } 1235 1236 /* 1237 * Map control/status registers. 1238 */ 1239 pci_enable_busmaster(dev); 1240 1241 rid = SK_RID; 1242 sc->sk_res = bus_alloc_resource(dev, SK_RES, &rid, 1243 0, ~0, 1, RF_ACTIVE); 1244 1245 if (sc->sk_res == NULL) { 1246 printf("sk%d: couldn't map ports/memory\n", unit); 1247 error = ENXIO; 1248 goto fail; 1249 } 1250 1251 sc->sk_btag = rman_get_bustag(sc->sk_res); 1252 sc->sk_bhandle = rman_get_bushandle(sc->sk_res); 1253 1254 /* Allocate interrupt */ 1255 rid = 0; 1256 sc->sk_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1257 RF_SHAREABLE | RF_ACTIVE); 1258 1259 if (sc->sk_irq == NULL) { 1260 printf("skc%d: couldn't map interrupt\n", unit); 1261 error = ENXIO; 1262 goto fail; 1263 } 1264 1265 /* Reset the adapter. */ 1266 sk_reset(sc); 1267 1268 sc->sk_unit = unit; 1269 1270 /* Read and save vital product data from EEPROM. */ 1271 sk_vpd_read(sc); 1272 1273 /* Read and save RAM size and RAMbuffer offset */ 1274 switch(sk_win_read_1(sc, SK_EPROM0)) { 1275 case SK_RAMSIZE_512K_64: 1276 sc->sk_ramsize = 0x80000; 1277 sc->sk_rboff = SK_RBOFF_0; 1278 break; 1279 case SK_RAMSIZE_1024K_64: 1280 sc->sk_ramsize = 0x100000; 1281 sc->sk_rboff = SK_RBOFF_80000; 1282 break; 1283 case SK_RAMSIZE_1024K_128: 1284 sc->sk_ramsize = 0x100000; 1285 sc->sk_rboff = SK_RBOFF_0; 1286 break; 1287 case SK_RAMSIZE_2048K_128: 1288 sc->sk_ramsize = 0x200000; 1289 sc->sk_rboff = SK_RBOFF_0; 1290 break; 1291 default: 1292 printf("skc%d: unknown ram size: %d\n", 1293 sc->sk_unit, sk_win_read_1(sc, SK_EPROM0)); 1294 error = ENXIO; 1295 goto fail; 1296 } 1297 1298 /* Read and save physical media type */ 1299 switch(sk_win_read_1(sc, SK_PMDTYPE)) { 1300 case SK_PMD_1000BASESX: 1301 sc->sk_pmd = IFM_1000_SX; 1302 break; 1303 case SK_PMD_1000BASELX: 1304 sc->sk_pmd = IFM_1000_LX; 1305 break; 1306 case SK_PMD_1000BASECX: 1307 sc->sk_pmd = IFM_1000_CX; 1308 break; 1309 case SK_PMD_1000BASETX: 1310 sc->sk_pmd = IFM_1000_T; 1311 break; 1312 default: 1313 printf("skc%d: unknown media type: 0x%x\n", 1314 sc->sk_unit, sk_win_read_1(sc, SK_PMDTYPE)); 1315 error = ENXIO; 1316 goto fail; 1317 } 1318 1319 /* Announce the product name. */ 1320 printf("skc%d: %s\n", sc->sk_unit, sc->sk_vpd_prodname); 1321 sc->sk_devs[SK_PORT_A] = device_add_child(dev, "sk", -1); 1322 port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT); 1323 *port = SK_PORT_A; 1324 device_set_ivars(sc->sk_devs[SK_PORT_A], port); 1325 1326 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) { 1327 sc->sk_devs[SK_PORT_B] = device_add_child(dev, "sk", -1); 1328 port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT); 1329 *port = SK_PORT_B; 1330 device_set_ivars(sc->sk_devs[SK_PORT_B], port); 1331 } 1332 1333 /* Turn on the 'driver is loaded' LED. */ 1334 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1335 1336 bus_generic_attach(dev); 1337 1338 error = bus_setup_intr(dev, sc->sk_irq, INTR_TYPE_NET, 1339 sk_intr, sc, &sc->sk_intrhand); 1340 1341 if (error) { 1342 printf("skc%d: couldn't set up irq\n", unit); 1343 goto fail; 1344 } 1345 1346fail: 1347 if (error) 1348 sk_detach(dev); 1349 1350 return(error); 1351} 1352 1353static int 1354sk_detach_xmac(dev) 1355 device_t dev; 1356{ 1357 struct sk_softc *sc; 1358 struct sk_if_softc *sc_if; 1359 struct ifnet *ifp; 1360 1361 sc = device_get_softc(device_get_parent(dev)); 1362 sc_if = device_get_softc(dev); 1363 KASSERT(mtx_initialized(&sc_if->sk_softc->sk_mtx), 1364 ("sk mutex not initialized in sk_detach_xmac")); 1365 SK_IF_LOCK(sc_if); 1366 1367 ifp = &sc_if->arpcom.ac_if; 1368 if (device_is_alive(dev)) { 1369 if (bus_child_present(dev)) 1370 sk_stop(sc_if); 1371 ether_ifdetach(ifp); 1372 device_delete_child(dev, sc_if->sk_miibus); 1373 bus_generic_detach(dev); 1374 } 1375 if (sc_if->sk_cdata.sk_jumbo_buf) 1376 contigfree(sc_if->sk_cdata.sk_jumbo_buf, SK_JMEM, M_DEVBUF); 1377 if (sc_if->sk_rdata) { 1378 contigfree(sc_if->sk_rdata, sizeof(struct sk_ring_data), 1379 M_DEVBUF); 1380 } 1381 SK_IF_UNLOCK(sc_if); 1382 1383 return(0); 1384} 1385 1386static int 1387sk_detach(dev) 1388 device_t dev; 1389{ 1390 struct sk_softc *sc; 1391 1392 sc = device_get_softc(dev); 1393 KASSERT(mtx_initialized(&sc->sk_mtx), ("sk mutex not initialized")); 1394 SK_LOCK(sc); 1395 1396 if (device_is_alive(dev)) { 1397 if (sc->sk_devs[SK_PORT_A] != NULL) 1398 device_delete_child(dev, sc->sk_devs[SK_PORT_A]); 1399 if (sc->sk_devs[SK_PORT_B] != NULL) 1400 device_delete_child(dev, sc->sk_devs[SK_PORT_B]); 1401 bus_generic_detach(dev); 1402 } 1403 1404 if (sc->sk_intrhand) 1405 bus_teardown_intr(dev, sc->sk_irq, sc->sk_intrhand); 1406 if (sc->sk_irq) 1407 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq); 1408 if (sc->sk_res) 1409 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res); 1410 1411 SK_UNLOCK(sc); 1412 mtx_destroy(&sc->sk_mtx); 1413 1414 return(0); 1415} 1416 1417static int 1418sk_encap(sc_if, m_head, txidx) 1419 struct sk_if_softc *sc_if; 1420 struct mbuf *m_head; 1421 u_int32_t *txidx; 1422{ 1423 struct sk_tx_desc *f = NULL; 1424 struct mbuf *m; 1425 u_int32_t frag, cur, cnt = 0; 1426 1427 m = m_head; 1428 cur = frag = *txidx; 1429 1430 /* 1431 * Start packing the mbufs in this chain into 1432 * the fragment pointers. Stop when we run out 1433 * of fragments or hit the end of the mbuf chain. 1434 */ 1435 for (m = m_head; m != NULL; m = m->m_next) { 1436 if (m->m_len != 0) { 1437 if ((SK_TX_RING_CNT - 1438 (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2) 1439 return(ENOBUFS); 1440 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1441 f->sk_data_lo = vtophys(mtod(m, vm_offset_t)); 1442 f->sk_ctl = m->m_len | SK_OPCODE_DEFAULT; 1443 if (cnt == 0) 1444 f->sk_ctl |= SK_TXCTL_FIRSTFRAG; 1445 else 1446 f->sk_ctl |= SK_TXCTL_OWN; 1447 cur = frag; 1448 SK_INC(frag, SK_TX_RING_CNT); 1449 cnt++; 1450 } 1451 } 1452 1453 if (m != NULL) 1454 return(ENOBUFS); 1455 1456 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= 1457 SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR; 1458 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1459 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |= SK_TXCTL_OWN; 1460 sc_if->sk_cdata.sk_tx_cnt += cnt; 1461 1462 *txidx = frag; 1463 1464 return(0); 1465} 1466 1467static void 1468sk_start(ifp) 1469 struct ifnet *ifp; 1470{ 1471 struct sk_softc *sc; 1472 struct sk_if_softc *sc_if; 1473 struct mbuf *m_head = NULL; 1474 u_int32_t idx; 1475 1476 sc_if = ifp->if_softc; 1477 sc = sc_if->sk_softc; 1478 1479 SK_IF_LOCK(sc_if); 1480 1481 idx = sc_if->sk_cdata.sk_tx_prod; 1482 1483 while(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1484 IF_DEQUEUE(&ifp->if_snd, m_head); 1485 if (m_head == NULL) 1486 break; 1487 1488 /* 1489 * Pack the data into the transmit ring. If we 1490 * don't have room, set the OACTIVE flag and wait 1491 * for the NIC to drain the ring. 1492 */ 1493 if (sk_encap(sc_if, m_head, &idx)) { 1494 IF_PREPEND(&ifp->if_snd, m_head); 1495 ifp->if_flags |= IFF_OACTIVE; 1496 break; 1497 } 1498 1499 /* 1500 * If there's a BPF listener, bounce a copy of this frame 1501 * to him. 1502 */ 1503 BPF_MTAP(ifp, m_head); 1504 } 1505 1506 /* Transmit */ 1507 sc_if->sk_cdata.sk_tx_prod = idx; 1508 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 1509 1510 /* Set a timeout in case the chip goes out to lunch. */ 1511 ifp->if_timer = 5; 1512 SK_IF_UNLOCK(sc_if); 1513 1514 return; 1515} 1516 1517 1518static void 1519sk_watchdog(ifp) 1520 struct ifnet *ifp; 1521{ 1522 struct sk_if_softc *sc_if; 1523 1524 sc_if = ifp->if_softc; 1525 1526 printf("sk%d: watchdog timeout\n", sc_if->sk_unit); 1527 sk_init(sc_if); 1528 1529 return; 1530} 1531 1532static void 1533sk_shutdown(dev) 1534 device_t dev; 1535{ 1536 struct sk_softc *sc; 1537 1538 sc = device_get_softc(dev); 1539 SK_LOCK(sc); 1540 1541 /* Turn off the 'driver is loaded' LED. */ 1542 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 1543 1544 /* 1545 * Reset the GEnesis controller. Doing this should also 1546 * assert the resets on the attached XMAC(s). 1547 */ 1548 sk_reset(sc); 1549 SK_UNLOCK(sc); 1550 1551 return; 1552} 1553 1554static void 1555sk_rxeof(sc_if) 1556 struct sk_if_softc *sc_if; 1557{ 1558 struct mbuf *m; 1559 struct ifnet *ifp; 1560 struct sk_chain *cur_rx; 1561 int total_len = 0; 1562 int i; 1563 u_int32_t rxstat; 1564 1565 ifp = &sc_if->arpcom.ac_if; 1566 i = sc_if->sk_cdata.sk_rx_prod; 1567 cur_rx = &sc_if->sk_cdata.sk_rx_chain[i]; 1568 1569 while(!(sc_if->sk_rdata->sk_rx_ring[i].sk_ctl & SK_RXCTL_OWN)) { 1570 1571 cur_rx = &sc_if->sk_cdata.sk_rx_chain[i]; 1572 rxstat = sc_if->sk_rdata->sk_rx_ring[i].sk_xmac_rxstat; 1573 m = cur_rx->sk_mbuf; 1574 cur_rx->sk_mbuf = NULL; 1575 total_len = SK_RXBYTES(sc_if->sk_rdata->sk_rx_ring[i].sk_ctl); 1576 SK_INC(i, SK_RX_RING_CNT); 1577 1578 if (rxstat & XM_RXSTAT_ERRFRAME) { 1579 ifp->if_ierrors++; 1580 sk_newbuf(sc_if, cur_rx, m); 1581 continue; 1582 } 1583 1584 /* 1585 * Try to allocate a new jumbo buffer. If that 1586 * fails, copy the packet to mbufs and put the 1587 * jumbo buffer back in the ring so it can be 1588 * re-used. If allocating mbufs fails, then we 1589 * have to drop the packet. 1590 */ 1591 if (sk_newbuf(sc_if, cur_rx, NULL) == ENOBUFS) { 1592 struct mbuf *m0; 1593 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, 1594 ifp, NULL); 1595 sk_newbuf(sc_if, cur_rx, m); 1596 if (m0 == NULL) { 1597 printf("sk%d: no receive buffers " 1598 "available -- packet dropped!\n", 1599 sc_if->sk_unit); 1600 ifp->if_ierrors++; 1601 continue; 1602 } 1603 m = m0; 1604 } else { 1605 m->m_pkthdr.rcvif = ifp; 1606 m->m_pkthdr.len = m->m_len = total_len; 1607 } 1608 1609 ifp->if_ipackets++; 1610 (*ifp->if_input)(ifp, m); 1611 } 1612 1613 sc_if->sk_cdata.sk_rx_prod = i; 1614 1615 return; 1616} 1617 1618static void 1619sk_txeof(sc_if) 1620 struct sk_if_softc *sc_if; 1621{ 1622 struct sk_tx_desc *cur_tx = NULL; 1623 struct ifnet *ifp; 1624 u_int32_t idx; 1625 1626 ifp = &sc_if->arpcom.ac_if; 1627 1628 /* 1629 * Go through our tx ring and free mbufs for those 1630 * frames that have been sent. 1631 */ 1632 idx = sc_if->sk_cdata.sk_tx_cons; 1633 while(idx != sc_if->sk_cdata.sk_tx_prod) { 1634 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 1635 if (cur_tx->sk_ctl & SK_TXCTL_OWN) 1636 break; 1637 if (cur_tx->sk_ctl & SK_TXCTL_LASTFRAG) 1638 ifp->if_opackets++; 1639 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 1640 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 1641 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 1642 } 1643 sc_if->sk_cdata.sk_tx_cnt--; 1644 SK_INC(idx, SK_TX_RING_CNT); 1645 ifp->if_timer = 0; 1646 } 1647 1648 sc_if->sk_cdata.sk_tx_cons = idx; 1649 1650 if (cur_tx != NULL) 1651 ifp->if_flags &= ~IFF_OACTIVE; 1652 1653 return; 1654} 1655 1656static void 1657sk_tick(xsc_if) 1658 void *xsc_if; 1659{ 1660 struct sk_if_softc *sc_if; 1661 struct mii_data *mii; 1662 struct ifnet *ifp; 1663 int i; 1664 1665 sc_if = xsc_if; 1666 SK_IF_LOCK(sc_if); 1667 ifp = &sc_if->arpcom.ac_if; 1668 mii = device_get_softc(sc_if->sk_miibus); 1669 1670 if (!(ifp->if_flags & IFF_UP)) { 1671 SK_IF_UNLOCK(sc_if); 1672 return; 1673 } 1674 1675 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 1676 sk_intr_bcom(sc_if); 1677 SK_IF_UNLOCK(sc_if); 1678 return; 1679 } 1680 1681 /* 1682 * According to SysKonnect, the correct way to verify that 1683 * the link has come back up is to poll bit 0 of the GPIO 1684 * register three times. This pin has the signal from the 1685 * link_sync pin connected to it; if we read the same link 1686 * state 3 times in a row, we know the link is up. 1687 */ 1688 for (i = 0; i < 3; i++) { 1689 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET) 1690 break; 1691 } 1692 1693 if (i != 3) { 1694 sc_if->sk_tick_ch = timeout(sk_tick, sc_if, hz); 1695 SK_IF_UNLOCK(sc_if); 1696 return; 1697 } 1698 1699 /* Turn the GP0 interrupt back on. */ 1700 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 1701 SK_XM_READ_2(sc_if, XM_ISR); 1702 mii_tick(mii); 1703 untimeout(sk_tick, sc_if, sc_if->sk_tick_ch); 1704 1705 SK_IF_UNLOCK(sc_if); 1706 return; 1707} 1708 1709static void 1710sk_intr_bcom(sc_if) 1711 struct sk_if_softc *sc_if; 1712{ 1713 struct sk_softc *sc; 1714 struct mii_data *mii; 1715 struct ifnet *ifp; 1716 int status; 1717 1718 sc = sc_if->sk_softc; 1719 mii = device_get_softc(sc_if->sk_miibus); 1720 ifp = &sc_if->arpcom.ac_if; 1721 1722 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 1723 1724 /* 1725 * Read the PHY interrupt register to make sure 1726 * we clear any pending interrupts. 1727 */ 1728 status = sk_miibus_readreg(sc_if->sk_dev, 1729 SK_PHYADDR_BCOM, BRGPHY_MII_ISR); 1730 1731 if (!(ifp->if_flags & IFF_RUNNING)) { 1732 sk_init_xmac(sc_if); 1733 return; 1734 } 1735 1736 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) { 1737 int lstat; 1738 lstat = sk_miibus_readreg(sc_if->sk_dev, 1739 SK_PHYADDR_BCOM, BRGPHY_MII_AUXSTS); 1740 1741 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) { 1742 mii_mediachg(mii); 1743 /* Turn off the link LED. */ 1744 SK_IF_WRITE_1(sc_if, 0, 1745 SK_LINKLED1_CTL, SK_LINKLED_OFF); 1746 sc_if->sk_link = 0; 1747 } else if (status & BRGPHY_ISR_LNK_CHG) { 1748 sk_miibus_writereg(sc_if->sk_dev, SK_PHYADDR_BCOM, 1749 BRGPHY_MII_IMR, 0xFF00); 1750 mii_tick(mii); 1751 sc_if->sk_link = 1; 1752 /* Turn on the link LED. */ 1753 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 1754 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF| 1755 SK_LINKLED_BLINK_OFF); 1756 } else { 1757 mii_tick(mii); 1758 sc_if->sk_tick_ch = timeout(sk_tick, sc_if, hz); 1759 } 1760 } 1761 1762 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 1763 1764 return; 1765} 1766 1767static void 1768sk_intr_xmac(sc_if) 1769 struct sk_if_softc *sc_if; 1770{ 1771 struct sk_softc *sc; 1772 u_int16_t status; 1773 struct mii_data *mii; 1774 1775 sc = sc_if->sk_softc; 1776 mii = device_get_softc(sc_if->sk_miibus); 1777 status = SK_XM_READ_2(sc_if, XM_ISR); 1778 1779 /* 1780 * Link has gone down. Start MII tick timeout to 1781 * watch for link resync. 1782 */ 1783 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) { 1784 if (status & XM_ISR_GP0_SET) { 1785 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 1786 sc_if->sk_tick_ch = timeout(sk_tick, sc_if, hz); 1787 } 1788 1789 if (status & XM_ISR_AUTONEG_DONE) { 1790 sc_if->sk_tick_ch = timeout(sk_tick, sc_if, hz); 1791 } 1792 } 1793 1794 if (status & XM_IMR_TX_UNDERRUN) 1795 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO); 1796 1797 if (status & XM_IMR_RX_OVERRUN) 1798 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO); 1799 1800 status = SK_XM_READ_2(sc_if, XM_ISR); 1801 1802 return; 1803} 1804 1805static void 1806sk_intr(xsc) 1807 void *xsc; 1808{ 1809 struct sk_softc *sc = xsc; 1810 struct sk_if_softc *sc_if0 = NULL, *sc_if1 = NULL; 1811 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 1812 u_int32_t status; 1813 1814 SK_LOCK(sc); 1815 1816 sc_if0 = sc->sk_if[SK_PORT_A]; 1817 sc_if1 = sc->sk_if[SK_PORT_B]; 1818 1819 if (sc_if0 != NULL) 1820 ifp0 = &sc_if0->arpcom.ac_if; 1821 if (sc_if1 != NULL) 1822 ifp1 = &sc_if1->arpcom.ac_if; 1823 1824 for (;;) { 1825 status = CSR_READ_4(sc, SK_ISSR); 1826 if (!(status & sc->sk_intrmask)) 1827 break; 1828 1829 /* Handle receive interrupts first. */ 1830 if (status & SK_ISR_RX1_EOF) { 1831 sk_rxeof(sc_if0); 1832 CSR_WRITE_4(sc, SK_BMU_RX_CSR0, 1833 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 1834 } 1835 if (status & SK_ISR_RX2_EOF) { 1836 sk_rxeof(sc_if1); 1837 CSR_WRITE_4(sc, SK_BMU_RX_CSR1, 1838 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 1839 } 1840 1841 /* Then transmit interrupts. */ 1842 if (status & SK_ISR_TX1_S_EOF) { 1843 sk_txeof(sc_if0); 1844 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, 1845 SK_TXBMU_CLR_IRQ_EOF); 1846 } 1847 if (status & SK_ISR_TX2_S_EOF) { 1848 sk_txeof(sc_if1); 1849 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, 1850 SK_TXBMU_CLR_IRQ_EOF); 1851 } 1852 1853 /* Then MAC interrupts. */ 1854 if (status & SK_ISR_MAC1 && 1855 ifp0->if_flags & IFF_RUNNING) 1856 sk_intr_xmac(sc_if0); 1857 1858 if (status & SK_ISR_MAC2 && 1859 ifp1->if_flags & IFF_RUNNING) 1860 sk_intr_xmac(sc_if1); 1861 1862 if (status & SK_ISR_EXTERNAL_REG) { 1863 if (ifp0 != NULL) 1864 sk_intr_bcom(sc_if0); 1865 if (ifp1 != NULL) 1866 sk_intr_bcom(sc_if1); 1867 } 1868 } 1869 1870 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 1871 1872 if (ifp0 != NULL && ifp0->if_snd.ifq_head != NULL) 1873 sk_start(ifp0); 1874 if (ifp1 != NULL && ifp1->if_snd.ifq_head != NULL) 1875 sk_start(ifp1); 1876 1877 SK_UNLOCK(sc); 1878 1879 return; 1880} 1881 1882static void 1883sk_init_xmac(sc_if) 1884 struct sk_if_softc *sc_if; 1885{ 1886 struct sk_softc *sc; 1887 struct ifnet *ifp; 1888 struct sk_bcom_hack bhack[] = { 1889 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, 1890 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, 1891 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 1892 { 0, 0 } }; 1893 1894 sc = sc_if->sk_softc; 1895 ifp = &sc_if->arpcom.ac_if; 1896 1897 /* Unreset the XMAC. */ 1898 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET); 1899 DELAY(1000); 1900 1901 /* Reset the XMAC's internal state. */ 1902 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 1903 1904 /* Save the XMAC II revision */ 1905 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID)); 1906 1907 /* 1908 * Perform additional initialization for external PHYs, 1909 * namely for the 1000baseTX cards that use the XMAC's 1910 * GMII mode. 1911 */ 1912 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 1913 int i = 0; 1914 u_int32_t val; 1915 1916 /* Take PHY out of reset. */ 1917 val = sk_win_read_4(sc, SK_GPIO); 1918 if (sc_if->sk_port == SK_PORT_A) 1919 val |= SK_GPIO_DIR0|SK_GPIO_DAT0; 1920 else 1921 val |= SK_GPIO_DIR2|SK_GPIO_DAT2; 1922 sk_win_write_4(sc, SK_GPIO, val); 1923 1924 /* Enable GMII mode on the XMAC. */ 1925 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE); 1926 1927 sk_miibus_writereg(sc_if->sk_dev, SK_PHYADDR_BCOM, 1928 BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET); 1929 DELAY(10000); 1930 sk_miibus_writereg(sc_if->sk_dev, SK_PHYADDR_BCOM, 1931 BRGPHY_MII_IMR, 0xFFF0); 1932 1933 /* 1934 * Early versions of the BCM5400 apparently have 1935 * a bug that requires them to have their reserved 1936 * registers initialized to some magic values. I don't 1937 * know what the numbers do, I'm just the messenger. 1938 */ 1939 if (sk_miibus_readreg(sc_if->sk_dev, 1940 SK_PHYADDR_BCOM, 0x03) == 0x6041) { 1941 while(bhack[i].reg) { 1942 sk_miibus_writereg(sc_if->sk_dev, 1943 SK_PHYADDR_BCOM, bhack[i].reg, 1944 bhack[i].val); 1945 i++; 1946 } 1947 } 1948 } 1949 1950 /* Set station address */ 1951 SK_XM_WRITE_2(sc_if, XM_PAR0, 1952 *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[0])); 1953 SK_XM_WRITE_2(sc_if, XM_PAR1, 1954 *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[2])); 1955 SK_XM_WRITE_2(sc_if, XM_PAR2, 1956 *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[4])); 1957 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION); 1958 1959 if (ifp->if_flags & IFF_PROMISC) { 1960 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 1961 } else { 1962 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 1963 } 1964 1965 if (ifp->if_flags & IFF_BROADCAST) { 1966 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 1967 } else { 1968 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 1969 } 1970 1971 /* We don't need the FCS appended to the packet. */ 1972 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS); 1973 1974 /* We want short frames padded to 60 bytes. */ 1975 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD); 1976 1977 /* 1978 * Enable the reception of all error frames. This is is 1979 * a necessary evil due to the design of the XMAC. The 1980 * XMAC's receive FIFO is only 8K in size, however jumbo 1981 * frames can be up to 9000 bytes in length. When bad 1982 * frame filtering is enabled, the XMAC's RX FIFO operates 1983 * in 'store and forward' mode. For this to work, the 1984 * entire frame has to fit into the FIFO, but that means 1985 * that jumbo frames larger than 8192 bytes will be 1986 * truncated. Disabling all bad frame filtering causes 1987 * the RX FIFO to operate in streaming mode, in which 1988 * case the XMAC will start transfering frames out of the 1989 * RX FIFO as soon as the FIFO threshold is reached. 1990 */ 1991 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES| 1992 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS| 1993 XM_MODE_RX_INRANGELEN); 1994 1995 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 1996 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 1997 else 1998 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 1999 2000 /* 2001 * Bump up the transmit threshold. This helps hold off transmit 2002 * underruns when we're blasting traffic from both ports at once. 2003 */ 2004 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH); 2005 2006 /* Set multicast filter */ 2007 sk_setmulti(sc_if); 2008 2009 /* Clear and enable interrupts */ 2010 SK_XM_READ_2(sc_if, XM_ISR); 2011 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 2012 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS); 2013 else 2014 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2015 2016 /* Configure MAC arbiter */ 2017 switch(sc_if->sk_xmac_rev) { 2018 case XM_XMAC_REV_B2: 2019 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2); 2020 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2); 2021 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2); 2022 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2); 2023 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2); 2024 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2); 2025 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2); 2026 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2); 2027 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2028 break; 2029 case XM_XMAC_REV_C1: 2030 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1); 2031 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1); 2032 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1); 2033 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1); 2034 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1); 2035 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1); 2036 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1); 2037 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1); 2038 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2039 break; 2040 default: 2041 break; 2042 } 2043 sk_win_write_2(sc, SK_MACARB_CTL, 2044 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF); 2045 2046 sc_if->sk_link = 1; 2047 2048 return; 2049} 2050 2051/* 2052 * Note that to properly initialize any part of the GEnesis chip, 2053 * you first have to take it out of reset mode. 2054 */ 2055static void 2056sk_init(xsc) 2057 void *xsc; 2058{ 2059 struct sk_if_softc *sc_if = xsc; 2060 struct sk_softc *sc; 2061 struct ifnet *ifp; 2062 struct mii_data *mii; 2063 2064 SK_IF_LOCK(sc_if); 2065 2066 ifp = &sc_if->arpcom.ac_if; 2067 sc = sc_if->sk_softc; 2068 mii = device_get_softc(sc_if->sk_miibus); 2069 2070 /* Cancel pending I/O and free all RX/TX buffers. */ 2071 sk_stop(sc_if); 2072 2073 /* Configure LINK_SYNC LED */ 2074 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON); 2075 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_ON); 2076 2077 /* Configure RX LED */ 2078 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_START); 2079 2080 /* Configure TX LED */ 2081 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_TXLEDCTL_COUNTER_START); 2082 2083 /* Configure I2C registers */ 2084 2085 /* Configure XMAC(s) */ 2086 sk_init_xmac(sc_if); 2087 mii_mediachg(mii); 2088 2089 /* Configure MAC FIFOs */ 2090 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET); 2091 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END); 2092 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON); 2093 2094 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET); 2095 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END); 2096 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON); 2097 2098 /* Configure transmit arbiter(s) */ 2099 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, 2100 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 2101 2102 /* Configure RAMbuffers */ 2103 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2104 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2105 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2106 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2107 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2108 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2109 2110 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET); 2111 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON); 2112 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart); 2113 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart); 2114 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart); 2115 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend); 2116 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON); 2117 2118 /* Configure BMUs */ 2119 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE); 2120 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 2121 vtophys(&sc_if->sk_rdata->sk_rx_ring[0])); 2122 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0); 2123 2124 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE); 2125 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO, 2126 vtophys(&sc_if->sk_rdata->sk_tx_ring[0])); 2127 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0); 2128 2129 /* Init descriptors */ 2130 if (sk_init_rx_ring(sc_if) == ENOBUFS) { 2131 printf("sk%d: initialization failed: no " 2132 "memory for rx buffers\n", sc_if->sk_unit); 2133 sk_stop(sc_if); 2134 SK_IF_UNLOCK(sc_if); 2135 return; 2136 } 2137 sk_init_tx_ring(sc_if); 2138 2139 /* Configure interrupt handling */ 2140 CSR_READ_4(sc, SK_ISSR); 2141 if (sc_if->sk_port == SK_PORT_A) 2142 sc->sk_intrmask |= SK_INTRS1; 2143 else 2144 sc->sk_intrmask |= SK_INTRS2; 2145 2146 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG; 2147 2148 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2149 2150 /* Start BMUs. */ 2151 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START); 2152 2153 /* Enable XMACs TX and RX state machines */ 2154 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE); 2155 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2156 2157 ifp->if_flags |= IFF_RUNNING; 2158 ifp->if_flags &= ~IFF_OACTIVE; 2159 2160 SK_IF_UNLOCK(sc_if); 2161 2162 return; 2163} 2164 2165static void 2166sk_stop(sc_if) 2167 struct sk_if_softc *sc_if; 2168{ 2169 int i; 2170 struct sk_softc *sc; 2171 struct ifnet *ifp; 2172 2173 SK_IF_LOCK(sc_if); 2174 sc = sc_if->sk_softc; 2175 ifp = &sc_if->arpcom.ac_if; 2176 2177 untimeout(sk_tick, sc_if, sc_if->sk_tick_ch); 2178 2179 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2180 u_int32_t val; 2181 2182 /* Put PHY back into reset. */ 2183 val = sk_win_read_4(sc, SK_GPIO); 2184 if (sc_if->sk_port == SK_PORT_A) { 2185 val |= SK_GPIO_DIR0; 2186 val &= ~SK_GPIO_DAT0; 2187 } else { 2188 val |= SK_GPIO_DIR2; 2189 val &= ~SK_GPIO_DAT2; 2190 } 2191 sk_win_write_4(sc, SK_GPIO, val); 2192 } 2193 2194 /* Turn off various components of this interface. */ 2195 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2196 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_RESET); 2197 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET); 2198 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2199 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2200 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE); 2201 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2202 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2203 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2204 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2205 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2206 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2207 2208 /* Disable interrupts */ 2209 if (sc_if->sk_port == SK_PORT_A) 2210 sc->sk_intrmask &= ~SK_INTRS1; 2211 else 2212 sc->sk_intrmask &= ~SK_INTRS2; 2213 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2214 2215 SK_XM_READ_2(sc_if, XM_ISR); 2216 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2217 2218 /* Free RX and TX mbufs still in the queues. */ 2219 for (i = 0; i < SK_RX_RING_CNT; i++) { 2220 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2221 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2222 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2223 } 2224 } 2225 2226 for (i = 0; i < SK_TX_RING_CNT; i++) { 2227 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2228 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2229 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2230 } 2231 } 2232 2233 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2234 SK_IF_UNLOCK(sc_if); 2235 return; 2236} 2237