1195801Smav/*- 2195801Smav * Copyright (c) 2009 Alexander Motin <mav@FreeBSD.org> 3195801Smav * All rights reserved. 4195801Smav * 5195801Smav * Redistribution and use in source and binary forms, with or without 6195801Smav * modification, are permitted provided that the following conditions 7195801Smav * are met: 8195801Smav * 1. Redistributions of source code must retain the above copyright 9195801Smav * notice, this list of conditions and the following disclaimer, 10195801Smav * without modification, immediately at the beginning of the file. 11195801Smav * 2. Redistributions in binary form must reproduce the above copyright 12195801Smav * notice, this list of conditions and the following disclaimer in the 13195801Smav * documentation and/or other materials provided with the distribution. 14195801Smav * 15195801Smav * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16195801Smav * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17195801Smav * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18195801Smav * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19195801Smav * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20195801Smav * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21195801Smav * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22195801Smav * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23195801Smav * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24195801Smav * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25195801Smav * 26195801Smav * $FreeBSD$ 27195801Smav */ 28195801Smav 29195801Smav/* ATA register defines */ 30195801Smav#define ATA_DATA 0 /* (RW) data */ 31195801Smav 32195801Smav#define ATA_FEATURE 1 /* (W) feature */ 33195801Smav#define ATA_F_DMA 0x01 /* enable DMA */ 34195801Smav#define ATA_F_OVL 0x02 /* enable overlap */ 35195801Smav 36195801Smav#define ATA_COUNT 2 /* (W) sector count */ 37195801Smav 38195801Smav#define ATA_SECTOR 3 /* (RW) sector # */ 39195801Smav#define ATA_CYL_LSB 4 /* (RW) cylinder# LSB */ 40195801Smav#define ATA_CYL_MSB 5 /* (RW) cylinder# MSB */ 41195801Smav#define ATA_DRIVE 6 /* (W) Sector/Drive/Head */ 42195801Smav#define ATA_D_LBA 0x40 /* use LBA addressing */ 43195801Smav#define ATA_D_IBM 0xa0 /* 512 byte sectors, ECC */ 44195801Smav 45195801Smav#define ATA_COMMAND 7 /* (W) command */ 46195801Smav 47195801Smav#define ATA_ERROR 8 /* (R) error */ 48195801Smav#define ATA_E_ILI 0x01 /* illegal length */ 49195801Smav#define ATA_E_NM 0x02 /* no media */ 50195801Smav#define ATA_E_ABORT 0x04 /* command aborted */ 51195801Smav#define ATA_E_MCR 0x08 /* media change request */ 52195801Smav#define ATA_E_IDNF 0x10 /* ID not found */ 53195801Smav#define ATA_E_MC 0x20 /* media changed */ 54195801Smav#define ATA_E_UNC 0x40 /* uncorrectable data */ 55195801Smav#define ATA_E_ICRC 0x80 /* UDMA crc error */ 56195801Smav#define ATA_E_ATAPI_SENSE_MASK 0xf0 /* ATAPI sense key mask */ 57195801Smav 58195801Smav#define ATA_IREASON 9 /* (R) interrupt reason */ 59195801Smav#define ATA_I_CMD 0x01 /* cmd (1) | data (0) */ 60195801Smav#define ATA_I_IN 0x02 /* read (1) | write (0) */ 61195801Smav#define ATA_I_RELEASE 0x04 /* released bus (1) */ 62195801Smav#define ATA_I_TAGMASK 0xf8 /* tag mask */ 63195801Smav 64195801Smav#define ATA_STATUS 10 /* (R) status */ 65195801Smav#define ATA_ALTSTAT 11 /* (R) alternate status */ 66195801Smav#define ATA_S_ERROR 0x01 /* error */ 67195801Smav#define ATA_S_INDEX 0x02 /* index */ 68195801Smav#define ATA_S_CORR 0x04 /* data corrected */ 69195801Smav#define ATA_S_DRQ 0x08 /* data request */ 70195801Smav#define ATA_S_DSC 0x10 /* drive seek completed */ 71195801Smav#define ATA_S_SERVICE 0x10 /* drive needs service */ 72195801Smav#define ATA_S_DWF 0x20 /* drive write fault */ 73195801Smav#define ATA_S_DMA 0x20 /* DMA ready */ 74195801Smav#define ATA_S_READY 0x40 /* drive ready */ 75195801Smav#define ATA_S_BUSY 0x80 /* busy */ 76195801Smav 77195801Smav#define ATA_CONTROL 12 /* (W) control */ 78195801Smav#define ATA_A_IDS 0x02 /* disable interrupts */ 79195801Smav#define ATA_A_RESET 0x04 /* RESET controller */ 80195801Smav#define ATA_A_4BIT 0x08 /* 4 head bits */ 81195801Smav#define ATA_A_HOB 0x80 /* High Order Byte enable */ 82195801Smav 83195801Smav/* SATA register defines */ 84195801Smav#define ATA_SSTATUS 13 85195801Smav#define ATA_SS_DET_MASK 0x0000000f 86195801Smav#define ATA_SS_DET_NO_DEVICE 0x00000000 87195801Smav#define ATA_SS_DET_DEV_PRESENT 0x00000001 88195801Smav#define ATA_SS_DET_PHY_ONLINE 0x00000003 89195801Smav#define ATA_SS_DET_PHY_OFFLINE 0x00000004 90195801Smav 91195801Smav#define ATA_SS_SPD_MASK 0x000000f0 92195801Smav#define ATA_SS_SPD_NO_SPEED 0x00000000 93195801Smav#define ATA_SS_SPD_GEN1 0x00000010 94195801Smav#define ATA_SS_SPD_GEN2 0x00000020 95279963Smav#define ATA_SS_SPD_GEN3 0x00000030 96195801Smav 97195801Smav#define ATA_SS_IPM_MASK 0x00000f00 98195801Smav#define ATA_SS_IPM_NO_DEVICE 0x00000000 99195801Smav#define ATA_SS_IPM_ACTIVE 0x00000100 100195801Smav#define ATA_SS_IPM_PARTIAL 0x00000200 101195801Smav#define ATA_SS_IPM_SLUMBER 0x00000600 102195801Smav 103195801Smav#define ATA_SERROR 14 104195801Smav#define ATA_SE_DATA_CORRECTED 0x00000001 105195801Smav#define ATA_SE_COMM_CORRECTED 0x00000002 106195801Smav#define ATA_SE_DATA_ERR 0x00000100 107195801Smav#define ATA_SE_COMM_ERR 0x00000200 108195801Smav#define ATA_SE_PROT_ERR 0x00000400 109195801Smav#define ATA_SE_HOST_ERR 0x00000800 110195801Smav#define ATA_SE_PHY_CHANGED 0x00010000 111195801Smav#define ATA_SE_PHY_IERROR 0x00020000 112195801Smav#define ATA_SE_COMM_WAKE 0x00040000 113195801Smav#define ATA_SE_DECODE_ERR 0x00080000 114195801Smav#define ATA_SE_PARITY_ERR 0x00100000 115195801Smav#define ATA_SE_CRC_ERR 0x00200000 116195801Smav#define ATA_SE_HANDSHAKE_ERR 0x00400000 117195801Smav#define ATA_SE_LINKSEQ_ERR 0x00800000 118195801Smav#define ATA_SE_TRANSPORT_ERR 0x01000000 119195801Smav#define ATA_SE_UNKNOWN_FIS 0x02000000 120195801Smav 121195801Smav#define ATA_SCONTROL 15 122195801Smav#define ATA_SC_DET_MASK 0x0000000f 123195801Smav#define ATA_SC_DET_IDLE 0x00000000 124195801Smav#define ATA_SC_DET_RESET 0x00000001 125195801Smav#define ATA_SC_DET_DISABLE 0x00000004 126195801Smav 127195801Smav#define ATA_SC_SPD_MASK 0x000000f0 128195801Smav#define ATA_SC_SPD_NO_SPEED 0x00000000 129195801Smav#define ATA_SC_SPD_SPEED_GEN1 0x00000010 130195801Smav#define ATA_SC_SPD_SPEED_GEN2 0x00000020 131279963Smav#define ATA_SC_SPD_SPEED_GEN3 0x00000030 132195801Smav 133195801Smav#define ATA_SC_IPM_MASK 0x00000f00 134195801Smav#define ATA_SC_IPM_NONE 0x00000000 135195801Smav#define ATA_SC_IPM_DIS_PARTIAL 0x00000100 136195801Smav#define ATA_SC_IPM_DIS_SLUMBER 0x00000200 137195801Smav 138195801Smav#define ATA_SACTIVE 16 139195801Smav 140195801Smav/* 141195801Smav * Global registers 142195801Smav */ 143195801Smav#define SIIS_GCTL 0x0040 /* Global Control */ 144195801Smav#define SIIS_GCTL_GRESET 0x80000000 /* Global Reset */ 145195801Smav#define SIIS_GCTL_MSIACK 0x40000000 /* MSI Ack */ 146195801Smav#define SIIS_GCTL_I2C_IE 0x20000000 /* I2C int enable */ 147195801Smav#define SIIS_GCTL_300CAP 0x01000000 /* 3Gb/s capable (R) */ 148195801Smav#define SIIS_GCTL_PIE(n) (1 << (n)) /* Port int enable */ 149195801Smav#define SIIS_IS 0x0044 /* Interrupt Status */ 150195801Smav#define SIIS_IS_I2C 0x20000000 /* I2C Int Status */ 151195801Smav#define SIIS_IS_PORT(n) (1 << (n)) /* Port interrupt stat */ 152195801Smav#define SIIS_PHYCONF 0x0048 /* PHY Configuration */ 153195801Smav#define SIIS_BIST_CTL 0x0050 154195801Smav#define SIIS_BIST_PATTERN 0x0054 /* 32 bit pattern */ 155195801Smav#define SIIS_BIST_STATUS 0x0058 156195801Smav#define SIIS_I2C_CTL 0x0060 157195801Smav#define SIIS_I2C_STS 0x0064 158195801Smav#define SIIS_I2C_SADDR 0x0068 159195801Smav#define SIIS_I2C_DATA 0x006C 160195801Smav#define SIIS_FLASH_ADDR 0x0070 161195801Smav#define SIIS_GPIO 0x0074 162195801Smav 163195801Smav/* 164195801Smav * Port registers 165195801Smav */ 166195801Smav 167195801Smav#define SIIS_P_LRAM 0x0000 168195801Smav#define SIIS_P_LRAM_SLOT(i) (SIIS_P_LRAM + i * 128) 169195801Smav#define SIIS_P_PMPSTS(i) (0x0F80 + i * 8) 170195801Smav#define SIIS_P_PMPQACT(i) (0x0F80 + i * 8 + 4) 171195801Smav#define SIIS_P_STS 0x1000 172195801Smav#define SIIS_P_CTLSET 0x1000 173195801Smav#define SIIS_P_CTLCLR 0x1004 174195801Smav#define SIIS_P_CTL_READY 0x80000000 175195801Smav#define SIIS_P_CTL_OOBB 0x02000000 176195801Smav#define SIIS_P_CTL_ACT 0x001F0000 177195801Smav#define SIIS_P_CTL_ACT_SHIFT 16 178195801Smav#define SIIS_P_CTL_LED_ON 0x00008000 179195801Smav#define SIIS_P_CTL_AIA 0x00004000 180195801Smav#define SIIS_P_CTL_PME 0x00002000 181195801Smav#define SIIS_P_CTL_IA 0x00001000 182195801Smav#define SIIS_P_CTL_IR 0x00000800 183195801Smav#define SIIS_P_CTL_32BIT 0x00000400 184195801Smav#define SIIS_P_CTL_SCR_DIS 0x00000200 185195801Smav#define SIIS_P_CTL_CONT_DIS 0x00000100 186195801Smav#define SIIS_P_CTL_TBIST 0x00000080 187195801Smav#define SIIS_P_CTL_RESUME 0x00000040 188195801Smav#define SIIS_P_CTL_PLENGTH 0x00000020 189195801Smav#define SIIS_P_CTL_LED_DIS 0x00000010 190195801Smav#define SIIS_P_CTL_INT_NCOR 0x00000008 191195801Smav#define SIIS_P_CTL_PORT_INIT 0x00000004 192195801Smav#define SIIS_P_CTL_DEV_RESET 0x00000002 193195801Smav#define SIIS_P_CTL_PORT_RESET 0x00000001 194195801Smav#define SIIS_P_IS 0x1008 195195801Smav#define SIIS_P_IX_SDBN 0x00000800 196195801Smav#define SIIS_P_IX_HS_ET 0x00000400 197195801Smav#define SIIS_P_IX_CRC_ET 0x00000200 198195801Smav#define SIIS_P_IX_8_10_ET 0x00000100 199195801Smav#define SIIS_P_IX_DEX 0x00000080 200195801Smav#define SIIS_P_IX_UNRECFIS 0x00000040 201195801Smav#define SIIS_P_IX_COMWAKE 0x00000020 202195801Smav#define SIIS_P_IX_PHYRDYCHG 0x00000010 203195801Smav#define SIIS_P_IX_PMCHG 0x00000008 204195801Smav#define SIIS_P_IX_READY 0x00000004 205195801Smav#define SIIS_P_IX_COMMERR 0x00000002 206195801Smav#define SIIS_P_IX_COMMCOMP 0x00000001 207195801Smav#define SIIS_P_IX_ENABLED SIIS_P_IX_COMMCOMP | SIIS_P_IX_COMMERR | \ 208195801Smav SIIS_P_IX_PHYRDYCHG | SIIS_P_IX_SDBN 209195801Smav#define SIIS_P_IESET 0x1010 210195801Smav#define SIIS_P_IECLR 0x1014 211195801Smav#define SIIS_P_CACTU 0x101C 212195801Smav#define SIIS_P_CMDEFIFO 0x1020 213195801Smav#define SIIS_P_CMDERR 0x1024 214195801Smav#define SIIS_P_CMDERR_DEV 1 215195801Smav#define SIIS_P_CMDERR_SDB 2 216195801Smav#define SIIS_P_CMDERR_DATAFIS 3 217195801Smav#define SIIS_P_CMDERR_SENDFIS 4 218195801Smav#define SIIS_P_CMDERR_INCSTATE 5 219195801Smav#define SIIS_P_CMDERR_DIRECTION 6 220195801Smav#define SIIS_P_CMDERR_UNDERRUN 7 221195801Smav#define SIIS_P_CMDERR_OVERRUN 8 222195801Smav#define SIIS_P_CMDERR_LLOVERRUN 9 223195801Smav#define SIIS_P_CMDERR_PPE 11 224195801Smav#define SIIS_P_CMDERR_SGTALIGN 16 225195801Smav#define SIIS_P_CMDERR_PCITASGT 17 226195801Smav#define SIIS_P_CMDERR_OCIMASGT 18 227195801Smav#define SIIS_P_CMDERR_PCIPESGT 19 228195801Smav#define SIIS_P_CMDERR_PRBALIGN 24 229195801Smav#define SIIS_P_CMDERR_PCITAPRB 25 230195801Smav#define SIIS_P_CMDERR_PCIMAPRB 26 231195801Smav#define SIIS_P_CMDERR_PCIPEPRB 27 232195801Smav#define SIIS_P_CMDERR_PCITADATA 33 233195801Smav#define SIIS_P_CMDERR_PCIMADATA 34 234195801Smav#define SIIS_P_CMDERR_PCIPEDATA 35 235195801Smav#define SIIS_P_CMDERR_SERVICE 36 236195801Smav#define SIIS_P_FISCFG 0x1028 237195801Smav#define SIIS_P_PCIEFIFOTH 0x102C 238195801Smav#define SIIS_P_8_10_DEC_ERR 0x1040 239195801Smav#define SIIS_P_CRC_ERR 0x1044 240195801Smav#define SIIS_P_HS_ERR 0x1048 241195801Smav#define SIIS_P_PHYCFG 0x1050 242195801Smav#define SIIS_P_SS 0x1800 243195801Smav#define SIIS_P_SS_ATTN 0x80000000 244195801Smav#define SIIS_P_CACTL(i) (0x1C00 + i * 8) 245195801Smav#define SIIS_P_CACTH(i) (0x1C00 + i * 8 + 4) 246195801Smav#define SIIS_P_CTX 0x1E04 247195801Smav#define SIIS_P_CTX_SLOT 0x0000001F 248195801Smav#define SIIS_P_CTX_SLOT_SHIFT 0 249195801Smav#define SIIS_P_CTX_PMP 0x000001E0 250195801Smav#define SIIS_P_CTX_PMP_SHIFT 5 251195801Smav 252195801Smav#define SIIS_P_SCTL 0x1F00 253195801Smav#define SIIS_P_SSTS 0x1F04 254195801Smav#define SIIS_P_SERR 0x1F08 255195801Smav#define SIIS_P_SACT 0x1F0C 256195801Smav#define SIIS_P_SNTF 0x1F10 257195801Smav 258195801Smav#define SIIS_MAX_PORTS 4 259195801Smav#define SIIS_MAX_SLOTS 31 260195801Smav 261195801Smav#define SIIS_OFFSET 0x100 262195801Smav#define SIIS_STEP 0x80 263195801Smav 264195801Smav/* Just to be sure, if building as module. */ 265195801Smav#if MAXPHYS < 512 * 1024 266195801Smav#undef MAXPHYS 267195801Smav#define MAXPHYS 512 * 1024 268195801Smav#endif 269195801Smav/* Pessimistic prognosis on number of required S/G entries */ 270195801Smav#define SIIS_SG_ENTRIES (roundup(btoc(MAXPHYS), 4) + 1) 271195801Smav/* Command tables. Up to 32 commands, Each, 128byte aligned. */ 272195801Smav#define SIIS_CT_OFFSET 0 273195801Smav#define SIIS_CT_SIZE (32 + 16 + SIIS_SG_ENTRIES * 16) 274195801Smav/* Total main work area. */ 275195801Smav#define SIIS_WORK_SIZE (SIIS_CT_OFFSET + SIIS_CT_SIZE * SIIS_MAX_SLOTS) 276195801Smav 277195801Smavstruct siis_dma_prd { 278195801Smav u_int64_t dba; 279195801Smav u_int32_t dbc; 280195801Smav u_int32_t control; 281195801Smav#define SIIS_PRD_TRM 0x80000000 282195801Smav#define SIIS_PRD_LNK 0x40000000 283195801Smav#define SIIS_PRD_DRD 0x20000000 284195801Smav#define SIIS_PRD_XCF 0x10000000 285195801Smav} __packed; 286195801Smav 287195801Smavstruct siis_cmd_ata { 288195801Smav struct siis_dma_prd prd[1 + SIIS_SG_ENTRIES]; 289195801Smav} __packed; 290195801Smav 291195801Smavstruct siis_cmd_atapi { 292195801Smav u_int8_t ccb[16]; 293195801Smav struct siis_dma_prd prd[SIIS_SG_ENTRIES]; 294195801Smav} __packed; 295195801Smav 296195801Smavstruct siis_cmd { 297195801Smav u_int16_t control; 298195801Smav#define SIIS_PRB_PROTOCOL_OVERRIDE 0x0001 299195801Smav#define SIIS_PRB_RETRANSMIT 0x0002 300195801Smav#define SIIS_PRB_EXTERNAL_COMMAND 0x0004 301195801Smav#define SIIS_PRB_RECEIVE 0x0008 302195801Smav#define SIIS_PRB_PACKET_READ 0x0010 303195801Smav#define SIIS_PRB_PACKET_WRITE 0x0020 304195801Smav#define SIIS_PRB_INTERRUPT_MASK 0x0040 305195801Smav#define SIIS_PRB_SOFT_RESET 0x0080 306195801Smav u_int16_t protocol_override; 307201222Smav#define SIIS_PRB_PROTO_PACKET 0x0001 308201222Smav#define SIIS_PRB_PROTO_TCQ 0x0002 309201222Smav#define SIIS_PRB_PROTO_NCQ 0x0004 310201222Smav#define SIIS_PRB_PROTO_READ 0x0008 311201222Smav#define SIIS_PRB_PROTO_WRITE 0x0010 312201222Smav#define SIIS_PRB_PROTO_TRANSPARENT 0x0020 313195801Smav u_int32_t transfer_count; 314195801Smav u_int8_t fis[24]; 315195801Smav union { 316195801Smav struct siis_cmd_ata ata; 317195801Smav struct siis_cmd_atapi atapi; 318195801Smav } u; 319195801Smav} __packed; 320195801Smav 321195801Smav/* misc defines */ 322195801Smav#define ATA_IRQ_RID 0 323195801Smav#define ATA_INTR_FLAGS (INTR_MPSAFE|INTR_TYPE_BIO|INTR_ENTROPY) 324195801Smav 325195801Smavstruct ata_dmaslot { 326195801Smav bus_dmamap_t data_map; /* data DMA map */ 327195801Smav int nsegs; /* Number of segs loaded */ 328195801Smav}; 329195801Smav 330195801Smav/* structure holding DMA related information */ 331195801Smavstruct ata_dma { 332195801Smav bus_dma_tag_t work_tag; /* workspace DMA tag */ 333195801Smav bus_dmamap_t work_map; /* workspace DMA map */ 334195801Smav uint8_t *work; /* workspace */ 335195801Smav bus_addr_t work_bus; /* bus address of work */ 336195801Smav bus_dma_tag_t data_tag; /* data DMA tag */ 337195801Smav}; 338195801Smav 339195801Smavenum siis_slot_states { 340195801Smav SIIS_SLOT_EMPTY, 341195801Smav SIIS_SLOT_LOADING, 342195801Smav SIIS_SLOT_RUNNING, 343195801Smav SIIS_SLOT_WAITING 344195801Smav}; 345195801Smav 346195801Smavstruct siis_slot { 347195801Smav device_t dev; /* Device handle */ 348195801Smav u_int8_t slot; /* Number of this slot */ 349195801Smav enum siis_slot_states state; /* Slot state */ 350195801Smav union ccb *ccb; /* CCB occupying slot */ 351195801Smav struct ata_dmaslot dma; /* DMA data of this slot */ 352195801Smav struct callout timeout; /* Execution timeout */ 353195801Smav}; 354195801Smav 355199747Smavstruct siis_device { 356199821Smav int revision; 357199747Smav int mode; 358199747Smav u_int bytecount; 359203376Smav u_int atapi; 360199747Smav u_int tags; 361207499Smav u_int caps; 362199747Smav}; 363199747Smav 364195801Smav/* structure describing an ATA channel */ 365195801Smavstruct siis_channel { 366195801Smav device_t dev; /* Device handle */ 367195801Smav int unit; /* Physical channel */ 368195801Smav struct resource *r_mem; /* Memory of this channel */ 369195801Smav struct resource *r_irq; /* Interrupt of this channel */ 370195801Smav void *ih; /* Interrupt handle */ 371195801Smav struct ata_dma dma; /* DMA data */ 372195801Smav struct cam_sim *sim; 373195801Smav struct cam_path *path; 374217883Smav struct cdev *led; /* Activity led led(4) cdev. */ 375200217Smav int quirks; 376195801Smav int pm_level; /* power management level */ 377195801Smav 378195801Smav struct siis_slot slot[SIIS_MAX_SLOTS]; 379195801Smav union ccb *hold[SIIS_MAX_SLOTS]; 380195801Smav struct mtx mtx; /* state lock */ 381195801Smav int devices; /* What is present */ 382195801Smav int pm_present; /* PM presence reported */ 383199747Smav uint32_t oslots; /* Occupied slots */ 384195801Smav uint32_t rslots; /* Running slots */ 385195801Smav uint32_t aslots; /* Slots with atomic commands */ 386195801Smav uint32_t eslots; /* Slots in error */ 387198852Smav uint32_t toslots; /* Slots in timeout */ 388195801Smav int numrslots; /* Number of running slots */ 389195801Smav int numtslots[SIIS_MAX_SLOTS]; /* Number of tagged slots */ 390220830Smav int numhslots; /* Number of held slots */ 391220566Smav int recoverycmd; /* Our READ LOG active */ 392298955Spfg int fatalerr; /* Fatal error happened */ 393195801Smav int recovery; /* Some slots are in error */ 394195801Smav union ccb *frozen; /* Frozen command */ 395199747Smav 396199747Smav struct siis_device user[16]; /* User-specified settings */ 397199747Smav struct siis_device curr[16]; /* Current settings */ 398195801Smav}; 399195801Smav 400195801Smav/* structure describing a SIIS controller */ 401195801Smavstruct siis_controller { 402195801Smav device_t dev; 403195801Smav int r_grid; 404195801Smav struct resource *r_gmem; 405195801Smav int r_rid; 406195801Smav struct resource *r_mem; 407195801Smav struct rman sc_iomem; 408195801Smav struct siis_controller_irq { 409195801Smav struct resource *r_irq; 410195801Smav void *handle; 411195801Smav int r_irq_rid; 412195801Smav } irq; 413200217Smav int quirks; 414195801Smav int channels; 415200223Smav uint32_t gctl; 416195801Smav struct { 417195801Smav void (*function)(void *); 418195801Smav void *argument; 419195801Smav } interrupt[SIIS_MAX_PORTS]; 420195801Smav}; 421195801Smav 422195801Smavenum siis_err_type { 423195801Smav SIIS_ERR_NONE, /* No error */ 424195801Smav SIIS_ERR_INVALID, /* Error detected by us before submitting. */ 425195801Smav SIIS_ERR_INNOCENT, /* Innocent victim. */ 426195801Smav SIIS_ERR_TFE, /* Task File Error. */ 427195801Smav SIIS_ERR_SATA, /* SATA error. */ 428195801Smav SIIS_ERR_TIMEOUT, /* Command execution timeout. */ 429195801Smav SIIS_ERR_NCQ, /* NCQ command error. CCB should be put on hold 430195801Smav * until READ LOG executed to reveal error. */ 431195801Smav}; 432195801Smav 433195801Smav/* macros to hide busspace uglyness */ 434195801Smav#define ATA_INB(res, offset) \ 435195801Smav bus_read_1((res), (offset)) 436195801Smav#define ATA_INW(res, offset) \ 437195801Smav bus_read_2((res), (offset)) 438195801Smav#define ATA_INL(res, offset) \ 439195801Smav bus_read_4((res), (offset)) 440195801Smav#define ATA_INSW(res, offset, addr, count) \ 441195801Smav bus_read_multi_2((res), (offset), (addr), (count)) 442195801Smav#define ATA_INSW_STRM(res, offset, addr, count) \ 443195801Smav bus_read_multi_stream_2((res), (offset), (addr), (count)) 444195801Smav#define ATA_INSL(res, offset, addr, count) \ 445195801Smav bus_read_multi_4((res), (offset), (addr), (count)) 446195801Smav#define ATA_INSL_STRM(res, offset, addr, count) \ 447195801Smav bus_read_multi_stream_4((res), (offset), (addr), (count)) 448195801Smav#define ATA_OUTB(res, offset, value) \ 449195801Smav bus_write_1((res), (offset), (value)) 450195801Smav#define ATA_OUTW(res, offset, value) \ 451195801Smav bus_write_2((res), (offset), (value)) 452195801Smav#define ATA_OUTL(res, offset, value) \ 453195801Smav bus_write_4((res), (offset), (value)) 454195801Smav#define ATA_OUTSW(res, offset, addr, count) \ 455195801Smav bus_write_multi_2((res), (offset), (addr), (count)) 456195801Smav#define ATA_OUTSW_STRM(res, offset, addr, count) \ 457195801Smav bus_write_multi_stream_2((res), (offset), (addr), (count)) 458195801Smav#define ATA_OUTSL(res, offset, addr, count) \ 459195801Smav bus_write_multi_4((res), (offset), (addr), (count)) 460195801Smav#define ATA_OUTSL_STRM(res, offset, addr, count) \ 461195801Smav bus_write_multi_stream_4((res), (offset), (addr), (count)) 462