1/*- 2 * Copyright (c) 2009 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29/* ATA register defines */ 30#define ATA_DATA 0 /* (RW) data */ 31 32#define ATA_FEATURE 1 /* (W) feature */ 33#define ATA_F_DMA 0x01 /* enable DMA */ 34#define ATA_F_OVL 0x02 /* enable overlap */ 35 36#define ATA_COUNT 2 /* (W) sector count */ 37 38#define ATA_SECTOR 3 /* (RW) sector # */ 39#define ATA_CYL_LSB 4 /* (RW) cylinder# LSB */ 40#define ATA_CYL_MSB 5 /* (RW) cylinder# MSB */ 41#define ATA_DRIVE 6 /* (W) Sector/Drive/Head */ 42#define ATA_D_LBA 0x40 /* use LBA addressing */ 43#define ATA_D_IBM 0xa0 /* 512 byte sectors, ECC */ 44 45#define ATA_COMMAND 7 /* (W) command */ 46 47#define ATA_ERROR 8 /* (R) error */ 48#define ATA_E_ILI 0x01 /* illegal length */ 49#define ATA_E_NM 0x02 /* no media */ 50#define ATA_E_ABORT 0x04 /* command aborted */ 51#define ATA_E_MCR 0x08 /* media change request */ 52#define ATA_E_IDNF 0x10 /* ID not found */ 53#define ATA_E_MC 0x20 /* media changed */ 54#define ATA_E_UNC 0x40 /* uncorrectable data */ 55#define ATA_E_ICRC 0x80 /* UDMA crc error */ 56#define ATA_E_ATAPI_SENSE_MASK 0xf0 /* ATAPI sense key mask */ 57 58#define ATA_IREASON 9 /* (R) interrupt reason */ 59#define ATA_I_CMD 0x01 /* cmd (1) | data (0) */ 60#define ATA_I_IN 0x02 /* read (1) | write (0) */ 61#define ATA_I_RELEASE 0x04 /* released bus (1) */ 62#define ATA_I_TAGMASK 0xf8 /* tag mask */ 63 64#define ATA_STATUS 10 /* (R) status */ 65#define ATA_ALTSTAT 11 /* (R) alternate status */ 66#define ATA_S_ERROR 0x01 /* error */ 67#define ATA_S_INDEX 0x02 /* index */ 68#define ATA_S_CORR 0x04 /* data corrected */ 69#define ATA_S_DRQ 0x08 /* data request */ 70#define ATA_S_DSC 0x10 /* drive seek completed */ 71#define ATA_S_SERVICE 0x10 /* drive needs service */ 72#define ATA_S_DWF 0x20 /* drive write fault */ 73#define ATA_S_DMA 0x20 /* DMA ready */ 74#define ATA_S_READY 0x40 /* drive ready */ 75#define ATA_S_BUSY 0x80 /* busy */ 76 77#define ATA_CONTROL 12 /* (W) control */ 78#define ATA_A_IDS 0x02 /* disable interrupts */ 79#define ATA_A_RESET 0x04 /* RESET controller */ 80#define ATA_A_4BIT 0x08 /* 4 head bits */ 81#define ATA_A_HOB 0x80 /* High Order Byte enable */ 82 83/* SATA register defines */ 84#define ATA_SSTATUS 13 85#define ATA_SS_DET_MASK 0x0000000f 86#define ATA_SS_DET_NO_DEVICE 0x00000000 87#define ATA_SS_DET_DEV_PRESENT 0x00000001 88#define ATA_SS_DET_PHY_ONLINE 0x00000003 89#define ATA_SS_DET_PHY_OFFLINE 0x00000004 90 91#define ATA_SS_SPD_MASK 0x000000f0 92#define ATA_SS_SPD_NO_SPEED 0x00000000 93#define ATA_SS_SPD_GEN1 0x00000010 94#define ATA_SS_SPD_GEN2 0x00000020 95#define ATA_SS_SPD_GEN3 0x00000030 96 97#define ATA_SS_IPM_MASK 0x00000f00 98#define ATA_SS_IPM_NO_DEVICE 0x00000000 99#define ATA_SS_IPM_ACTIVE 0x00000100 100#define ATA_SS_IPM_PARTIAL 0x00000200 101#define ATA_SS_IPM_SLUMBER 0x00000600 102 103#define ATA_SERROR 14 104#define ATA_SE_DATA_CORRECTED 0x00000001 105#define ATA_SE_COMM_CORRECTED 0x00000002 106#define ATA_SE_DATA_ERR 0x00000100 107#define ATA_SE_COMM_ERR 0x00000200 108#define ATA_SE_PROT_ERR 0x00000400 109#define ATA_SE_HOST_ERR 0x00000800 110#define ATA_SE_PHY_CHANGED 0x00010000 111#define ATA_SE_PHY_IERROR 0x00020000 112#define ATA_SE_COMM_WAKE 0x00040000 113#define ATA_SE_DECODE_ERR 0x00080000 114#define ATA_SE_PARITY_ERR 0x00100000 115#define ATA_SE_CRC_ERR 0x00200000 116#define ATA_SE_HANDSHAKE_ERR 0x00400000 117#define ATA_SE_LINKSEQ_ERR 0x00800000 118#define ATA_SE_TRANSPORT_ERR 0x01000000 119#define ATA_SE_UNKNOWN_FIS 0x02000000 120 121#define ATA_SCONTROL 15 122#define ATA_SC_DET_MASK 0x0000000f 123#define ATA_SC_DET_IDLE 0x00000000 124#define ATA_SC_DET_RESET 0x00000001 125#define ATA_SC_DET_DISABLE 0x00000004 126 127#define ATA_SC_SPD_MASK 0x000000f0 128#define ATA_SC_SPD_NO_SPEED 0x00000000 129#define ATA_SC_SPD_SPEED_GEN1 0x00000010 130#define ATA_SC_SPD_SPEED_GEN2 0x00000020 131#define ATA_SC_SPD_SPEED_GEN3 0x00000030 132 133#define ATA_SC_IPM_MASK 0x00000f00 134#define ATA_SC_IPM_NONE 0x00000000 135#define ATA_SC_IPM_DIS_PARTIAL 0x00000100 136#define ATA_SC_IPM_DIS_SLUMBER 0x00000200 137 138#define ATA_SACTIVE 16 139 140/* 141 * Global registers 142 */ 143#define SIIS_GCTL 0x0040 /* Global Control */ 144#define SIIS_GCTL_GRESET 0x80000000 /* Global Reset */ 145#define SIIS_GCTL_MSIACK 0x40000000 /* MSI Ack */ 146#define SIIS_GCTL_I2C_IE 0x20000000 /* I2C int enable */ 147#define SIIS_GCTL_300CAP 0x01000000 /* 3Gb/s capable (R) */ 148#define SIIS_GCTL_PIE(n) (1 << (n)) /* Port int enable */ 149#define SIIS_IS 0x0044 /* Interrupt Status */ 150#define SIIS_IS_I2C 0x20000000 /* I2C Int Status */ 151#define SIIS_IS_PORT(n) (1 << (n)) /* Port interrupt stat */ 152#define SIIS_PHYCONF 0x0048 /* PHY Configuration */ 153#define SIIS_BIST_CTL 0x0050 154#define SIIS_BIST_PATTERN 0x0054 /* 32 bit pattern */ 155#define SIIS_BIST_STATUS 0x0058 156#define SIIS_I2C_CTL 0x0060 157#define SIIS_I2C_STS 0x0064 158#define SIIS_I2C_SADDR 0x0068 159#define SIIS_I2C_DATA 0x006C 160#define SIIS_FLASH_ADDR 0x0070 161#define SIIS_GPIO 0x0074 162 163/* 164 * Port registers 165 */ 166 167#define SIIS_P_LRAM 0x0000 168#define SIIS_P_LRAM_SLOT(i) (SIIS_P_LRAM + i * 128) 169#define SIIS_P_PMPSTS(i) (0x0F80 + i * 8) 170#define SIIS_P_PMPQACT(i) (0x0F80 + i * 8 + 4) 171#define SIIS_P_STS 0x1000 172#define SIIS_P_CTLSET 0x1000 173#define SIIS_P_CTLCLR 0x1004 174#define SIIS_P_CTL_READY 0x80000000 175#define SIIS_P_CTL_OOBB 0x02000000 176#define SIIS_P_CTL_ACT 0x001F0000 177#define SIIS_P_CTL_ACT_SHIFT 16 178#define SIIS_P_CTL_LED_ON 0x00008000 179#define SIIS_P_CTL_AIA 0x00004000 180#define SIIS_P_CTL_PME 0x00002000 181#define SIIS_P_CTL_IA 0x00001000 182#define SIIS_P_CTL_IR 0x00000800 183#define SIIS_P_CTL_32BIT 0x00000400 184#define SIIS_P_CTL_SCR_DIS 0x00000200 185#define SIIS_P_CTL_CONT_DIS 0x00000100 186#define SIIS_P_CTL_TBIST 0x00000080 187#define SIIS_P_CTL_RESUME 0x00000040 188#define SIIS_P_CTL_PLENGTH 0x00000020 189#define SIIS_P_CTL_LED_DIS 0x00000010 190#define SIIS_P_CTL_INT_NCOR 0x00000008 191#define SIIS_P_CTL_PORT_INIT 0x00000004 192#define SIIS_P_CTL_DEV_RESET 0x00000002 193#define SIIS_P_CTL_PORT_RESET 0x00000001 194#define SIIS_P_IS 0x1008 195#define SIIS_P_IX_SDBN 0x00000800 196#define SIIS_P_IX_HS_ET 0x00000400 197#define SIIS_P_IX_CRC_ET 0x00000200 198#define SIIS_P_IX_8_10_ET 0x00000100 199#define SIIS_P_IX_DEX 0x00000080 200#define SIIS_P_IX_UNRECFIS 0x00000040 201#define SIIS_P_IX_COMWAKE 0x00000020 202#define SIIS_P_IX_PHYRDYCHG 0x00000010 203#define SIIS_P_IX_PMCHG 0x00000008 204#define SIIS_P_IX_READY 0x00000004 205#define SIIS_P_IX_COMMERR 0x00000002 206#define SIIS_P_IX_COMMCOMP 0x00000001 207#define SIIS_P_IX_ENABLED SIIS_P_IX_COMMCOMP | SIIS_P_IX_COMMERR | \ 208 SIIS_P_IX_PHYRDYCHG | SIIS_P_IX_SDBN 209#define SIIS_P_IESET 0x1010 210#define SIIS_P_IECLR 0x1014 211#define SIIS_P_CACTU 0x101C 212#define SIIS_P_CMDEFIFO 0x1020 213#define SIIS_P_CMDERR 0x1024 214#define SIIS_P_CMDERR_DEV 1 215#define SIIS_P_CMDERR_SDB 2 216#define SIIS_P_CMDERR_DATAFIS 3 217#define SIIS_P_CMDERR_SENDFIS 4 218#define SIIS_P_CMDERR_INCSTATE 5 219#define SIIS_P_CMDERR_DIRECTION 6 220#define SIIS_P_CMDERR_UNDERRUN 7 221#define SIIS_P_CMDERR_OVERRUN 8 222#define SIIS_P_CMDERR_LLOVERRUN 9 223#define SIIS_P_CMDERR_PPE 11 224#define SIIS_P_CMDERR_SGTALIGN 16 225#define SIIS_P_CMDERR_PCITASGT 17 226#define SIIS_P_CMDERR_OCIMASGT 18 227#define SIIS_P_CMDERR_PCIPESGT 19 228#define SIIS_P_CMDERR_PRBALIGN 24 229#define SIIS_P_CMDERR_PCITAPRB 25 230#define SIIS_P_CMDERR_PCIMAPRB 26 231#define SIIS_P_CMDERR_PCIPEPRB 27 232#define SIIS_P_CMDERR_PCITADATA 33 233#define SIIS_P_CMDERR_PCIMADATA 34 234#define SIIS_P_CMDERR_PCIPEDATA 35 235#define SIIS_P_CMDERR_SERVICE 36 236#define SIIS_P_FISCFG 0x1028 237#define SIIS_P_PCIEFIFOTH 0x102C 238#define SIIS_P_8_10_DEC_ERR 0x1040 239#define SIIS_P_CRC_ERR 0x1044 240#define SIIS_P_HS_ERR 0x1048 241#define SIIS_P_PHYCFG 0x1050 242#define SIIS_P_SS 0x1800 243#define SIIS_P_SS_ATTN 0x80000000 244#define SIIS_P_CACTL(i) (0x1C00 + i * 8) 245#define SIIS_P_CACTH(i) (0x1C00 + i * 8 + 4) 246#define SIIS_P_CTX 0x1E04 247#define SIIS_P_CTX_SLOT 0x0000001F 248#define SIIS_P_CTX_SLOT_SHIFT 0 249#define SIIS_P_CTX_PMP 0x000001E0 250#define SIIS_P_CTX_PMP_SHIFT 5 251 252#define SIIS_P_SCTL 0x1F00 253#define SIIS_P_SSTS 0x1F04 254#define SIIS_P_SERR 0x1F08 255#define SIIS_P_SACT 0x1F0C 256#define SIIS_P_SNTF 0x1F10 257 258#define SIIS_MAX_PORTS 4 259#define SIIS_MAX_SLOTS 31 260 261#define SIIS_OFFSET 0x100 262#define SIIS_STEP 0x80 263 264/* Just to be sure, if building as module. */ 265#if MAXPHYS < 512 * 1024 266#undef MAXPHYS 267#define MAXPHYS 512 * 1024 268#endif 269/* Pessimistic prognosis on number of required S/G entries */ 270#define SIIS_SG_ENTRIES (roundup(btoc(MAXPHYS), 4) + 1) 271/* Command tables. Up to 32 commands, Each, 128byte aligned. */ 272#define SIIS_CT_OFFSET 0 273#define SIIS_CT_SIZE (32 + 16 + SIIS_SG_ENTRIES * 16) 274/* Total main work area. */ 275#define SIIS_WORK_SIZE (SIIS_CT_OFFSET + SIIS_CT_SIZE * SIIS_MAX_SLOTS) 276 277struct siis_dma_prd { 278 u_int64_t dba; 279 u_int32_t dbc; 280 u_int32_t control; 281#define SIIS_PRD_TRM 0x80000000 282#define SIIS_PRD_LNK 0x40000000 283#define SIIS_PRD_DRD 0x20000000 284#define SIIS_PRD_XCF 0x10000000 285} __packed; 286 287struct siis_cmd_ata { 288 struct siis_dma_prd prd[1 + SIIS_SG_ENTRIES]; 289} __packed; 290 291struct siis_cmd_atapi { 292 u_int8_t ccb[16]; 293 struct siis_dma_prd prd[SIIS_SG_ENTRIES]; 294} __packed; 295 296struct siis_cmd { 297 u_int16_t control; 298#define SIIS_PRB_PROTOCOL_OVERRIDE 0x0001 299#define SIIS_PRB_RETRANSMIT 0x0002 300#define SIIS_PRB_EXTERNAL_COMMAND 0x0004 301#define SIIS_PRB_RECEIVE 0x0008 302#define SIIS_PRB_PACKET_READ 0x0010 303#define SIIS_PRB_PACKET_WRITE 0x0020 304#define SIIS_PRB_INTERRUPT_MASK 0x0040 305#define SIIS_PRB_SOFT_RESET 0x0080 306 u_int16_t protocol_override; 307#define SIIS_PRB_PROTO_PACKET 0x0001 308#define SIIS_PRB_PROTO_TCQ 0x0002 309#define SIIS_PRB_PROTO_NCQ 0x0004 310#define SIIS_PRB_PROTO_READ 0x0008 311#define SIIS_PRB_PROTO_WRITE 0x0010 312#define SIIS_PRB_PROTO_TRANSPARENT 0x0020 313 u_int32_t transfer_count; 314 u_int8_t fis[24]; 315 union { 316 struct siis_cmd_ata ata; 317 struct siis_cmd_atapi atapi; 318 } u; 319} __packed; 320 321/* misc defines */ 322#define ATA_IRQ_RID 0 323#define ATA_INTR_FLAGS (INTR_MPSAFE|INTR_TYPE_BIO|INTR_ENTROPY) 324 325struct ata_dmaslot { 326 bus_dmamap_t data_map; /* data DMA map */ 327 int nsegs; /* Number of segs loaded */ 328}; 329 330/* structure holding DMA related information */ 331struct ata_dma { 332 bus_dma_tag_t work_tag; /* workspace DMA tag */ 333 bus_dmamap_t work_map; /* workspace DMA map */ 334 uint8_t *work; /* workspace */ 335 bus_addr_t work_bus; /* bus address of work */ 336 bus_dma_tag_t data_tag; /* data DMA tag */ 337}; 338 339enum siis_slot_states { 340 SIIS_SLOT_EMPTY, 341 SIIS_SLOT_LOADING, 342 SIIS_SLOT_RUNNING, 343 SIIS_SLOT_WAITING 344}; 345 346struct siis_slot { 347 device_t dev; /* Device handle */ 348 u_int8_t slot; /* Number of this slot */ 349 enum siis_slot_states state; /* Slot state */ 350 union ccb *ccb; /* CCB occupying slot */ 351 struct ata_dmaslot dma; /* DMA data of this slot */ 352 struct callout timeout; /* Execution timeout */ 353}; 354 355struct siis_device { 356 int revision; 357 int mode; 358 u_int bytecount; 359 u_int atapi; 360 u_int tags; 361 u_int caps; 362}; 363 364/* structure describing an ATA channel */ 365struct siis_channel { 366 device_t dev; /* Device handle */ 367 int unit; /* Physical channel */ 368 struct resource *r_mem; /* Memory of this channel */ 369 struct resource *r_irq; /* Interrupt of this channel */ 370 void *ih; /* Interrupt handle */ 371 struct ata_dma dma; /* DMA data */ 372 struct cam_sim *sim; 373 struct cam_path *path; 374 struct cdev *led; /* Activity led led(4) cdev. */ 375 int quirks; 376 int pm_level; /* power management level */ 377 378 struct siis_slot slot[SIIS_MAX_SLOTS]; 379 union ccb *hold[SIIS_MAX_SLOTS]; 380 struct mtx mtx; /* state lock */ 381 int devices; /* What is present */ 382 int pm_present; /* PM presence reported */ 383 uint32_t oslots; /* Occupied slots */ 384 uint32_t rslots; /* Running slots */ 385 uint32_t aslots; /* Slots with atomic commands */ 386 uint32_t eslots; /* Slots in error */ 387 uint32_t toslots; /* Slots in timeout */ 388 int numrslots; /* Number of running slots */ 389 int numtslots[SIIS_MAX_SLOTS]; /* Number of tagged slots */ 390 int numhslots; /* Number of held slots */ 391 int recoverycmd; /* Our READ LOG active */ 392 int fatalerr; /* Fatal error happened */ 393 int recovery; /* Some slots are in error */ 394 union ccb *frozen; /* Frozen command */ 395 396 struct siis_device user[16]; /* User-specified settings */ 397 struct siis_device curr[16]; /* Current settings */ 398}; 399 400/* structure describing a SIIS controller */ 401struct siis_controller { 402 device_t dev; 403 int r_grid; 404 struct resource *r_gmem; 405 int r_rid; 406 struct resource *r_mem; 407 struct rman sc_iomem; 408 struct siis_controller_irq { 409 struct resource *r_irq; 410 void *handle; 411 int r_irq_rid; 412 } irq; 413 int quirks; 414 int channels; 415 uint32_t gctl; 416 struct { 417 void (*function)(void *); 418 void *argument; 419 } interrupt[SIIS_MAX_PORTS]; 420}; 421 422enum siis_err_type { 423 SIIS_ERR_NONE, /* No error */ 424 SIIS_ERR_INVALID, /* Error detected by us before submitting. */ 425 SIIS_ERR_INNOCENT, /* Innocent victim. */ 426 SIIS_ERR_TFE, /* Task File Error. */ 427 SIIS_ERR_SATA, /* SATA error. */ 428 SIIS_ERR_TIMEOUT, /* Command execution timeout. */ 429 SIIS_ERR_NCQ, /* NCQ command error. CCB should be put on hold 430 * until READ LOG executed to reveal error. */ 431}; 432 433/* macros to hide busspace uglyness */ 434#define ATA_INB(res, offset) \ 435 bus_read_1((res), (offset)) 436#define ATA_INW(res, offset) \ 437 bus_read_2((res), (offset)) 438#define ATA_INL(res, offset) \ 439 bus_read_4((res), (offset)) 440#define ATA_INSW(res, offset, addr, count) \ 441 bus_read_multi_2((res), (offset), (addr), (count)) 442#define ATA_INSW_STRM(res, offset, addr, count) \ 443 bus_read_multi_stream_2((res), (offset), (addr), (count)) 444#define ATA_INSL(res, offset, addr, count) \ 445 bus_read_multi_4((res), (offset), (addr), (count)) 446#define ATA_INSL_STRM(res, offset, addr, count) \ 447 bus_read_multi_stream_4((res), (offset), (addr), (count)) 448#define ATA_OUTB(res, offset, value) \ 449 bus_write_1((res), (offset), (value)) 450#define ATA_OUTW(res, offset, value) \ 451 bus_write_2((res), (offset), (value)) 452#define ATA_OUTL(res, offset, value) \ 453 bus_write_4((res), (offset), (value)) 454#define ATA_OUTSW(res, offset, addr, count) \ 455 bus_write_multi_2((res), (offset), (addr), (count)) 456#define ATA_OUTSW_STRM(res, offset, addr, count) \ 457 bus_write_multi_stream_2((res), (offset), (addr), (count)) 458#define ATA_OUTSL(res, offset, addr, count) \ 459 bus_write_multi_4((res), (offset), (addr), (count)) 460#define ATA_OUTSL_STRM(res, offset, addr, count) \ 461 bus_write_multi_stream_4((res), (offset), (addr), (count)) 462