1/*-
2 * Copyright (c) 2015-2016 Solarflare Communications Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,
9 *    this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 *    this list of conditions and the following disclaimer in the documentation
12 *    and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
29 */
30
31#include <sys/cdefs.h>
32__FBSDID("$FreeBSD: stable/11/sys/dev/sfxge/common/medford_nic.c 342445 2018-12-25 07:27:45Z arybchik $");
33
34#include "efx.h"
35#include "efx_impl.h"
36
37
38#if EFSYS_OPT_MEDFORD
39
40static	__checkReturn	efx_rc_t
41efx_mcdi_get_rxdp_config(
42	__in		efx_nic_t *enp,
43	__out		uint32_t *end_paddingp)
44{
45	efx_mcdi_req_t req;
46	EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_RXDP_CONFIG_IN_LEN,
47		MC_CMD_GET_RXDP_CONFIG_OUT_LEN);
48	uint32_t end_padding;
49	efx_rc_t rc;
50
51	req.emr_cmd = MC_CMD_GET_RXDP_CONFIG;
52	req.emr_in_buf = payload;
53	req.emr_in_length = MC_CMD_GET_RXDP_CONFIG_IN_LEN;
54	req.emr_out_buf = payload;
55	req.emr_out_length = MC_CMD_GET_RXDP_CONFIG_OUT_LEN;
56
57	efx_mcdi_execute(enp, &req);
58	if (req.emr_rc != 0) {
59		rc = req.emr_rc;
60		goto fail1;
61	}
62
63	if (MCDI_OUT_DWORD_FIELD(req, GET_RXDP_CONFIG_OUT_DATA,
64				    GET_RXDP_CONFIG_OUT_PAD_HOST_DMA) == 0) {
65		/* RX DMA end padding is disabled */
66		end_padding = 0;
67	} else {
68		switch (MCDI_OUT_DWORD_FIELD(req, GET_RXDP_CONFIG_OUT_DATA,
69					    GET_RXDP_CONFIG_OUT_PAD_HOST_LEN)) {
70		case MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_64:
71			end_padding = 64;
72			break;
73		case MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_128:
74			end_padding = 128;
75			break;
76		case MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_256:
77			end_padding = 256;
78			break;
79		default:
80			rc = ENOTSUP;
81			goto fail2;
82		}
83	}
84
85	*end_paddingp = end_padding;
86
87	return (0);
88
89fail2:
90	EFSYS_PROBE(fail2);
91fail1:
92	EFSYS_PROBE1(fail1, efx_rc_t, rc);
93
94	return (rc);
95}
96
97static	__checkReturn	efx_rc_t
98medford_nic_get_required_pcie_bandwidth(
99	__in		efx_nic_t *enp,
100	__out		uint32_t *bandwidth_mbpsp)
101{
102	uint32_t port_modes;
103	uint32_t current_mode;
104	uint32_t bandwidth;
105	efx_rc_t rc;
106
107	if ((rc = efx_mcdi_get_port_modes(enp, &port_modes,
108				    &current_mode)) != 0) {
109		/* No port mode info available. */
110		bandwidth = 0;
111		goto out;
112	}
113
114	if ((rc = ef10_nic_get_port_mode_bandwidth(current_mode,
115						    &bandwidth)) != 0)
116		goto fail1;
117
118out:
119	*bandwidth_mbpsp = bandwidth;
120
121	return (0);
122
123fail1:
124	EFSYS_PROBE1(fail1, efx_rc_t, rc);
125
126	return (rc);
127}
128
129	__checkReturn	efx_rc_t
130medford_board_cfg(
131	__in		efx_nic_t *enp)
132{
133	efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip);
134	efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
135	uint8_t mac_addr[6] = { 0 };
136	uint32_t board_type = 0;
137	ef10_link_state_t els;
138	efx_port_t *epp = &(enp->en_port);
139	uint32_t port;
140	uint32_t pf;
141	uint32_t vf;
142	uint32_t mask;
143	uint32_t sysclk, dpcpu_clk;
144	uint32_t base, nvec;
145	uint32_t end_padding;
146	uint32_t bandwidth;
147	efx_rc_t rc;
148
149	/*
150	 * FIXME: Likely to be incomplete and incorrect.
151	 * Parts of this should be shared with Huntington.
152	 */
153
154	if ((rc = efx_mcdi_get_port_assignment(enp, &port)) != 0)
155		goto fail1;
156
157	/*
158	 * NOTE: The MCDI protocol numbers ports from zero.
159	 * The common code MCDI interface numbers ports from one.
160	 */
161	emip->emi_port = port + 1;
162
163	if ((rc = ef10_external_port_mapping(enp, port,
164		    &encp->enc_external_port)) != 0)
165		goto fail2;
166
167	/*
168	 * Get PCIe function number from firmware (used for
169	 * per-function privilege and dynamic config info).
170	 *  - PCIe PF: pf = PF number, vf = 0xffff.
171	 *  - PCIe VF: pf = parent PF, vf = VF number.
172	 */
173	if ((rc = efx_mcdi_get_function_info(enp, &pf, &vf)) != 0)
174		goto fail3;
175
176	encp->enc_pf = pf;
177	encp->enc_vf = vf;
178
179	/* MAC address for this function */
180	if (EFX_PCI_FUNCTION_IS_PF(encp)) {
181		rc = efx_mcdi_get_mac_address_pf(enp, mac_addr);
182#if EFSYS_OPT_ALLOW_UNCONFIGURED_NIC
183		/* Disable static config checking for Medford NICs, ONLY
184		 * for manufacturing test and setup at the factory, to
185		 * allow the static config to be installed.
186		 */
187#else /* EFSYS_OPT_ALLOW_UNCONFIGURED_NIC */
188		if ((rc == 0) && (mac_addr[0] & 0x02)) {
189			/*
190			 * If the static config does not include a global MAC
191			 * address pool then the board may return a locally
192			 * administered MAC address (this should only happen on
193			 * incorrectly programmed boards).
194			 */
195			rc = EINVAL;
196		}
197#endif /* EFSYS_OPT_ALLOW_UNCONFIGURED_NIC */
198	} else {
199		rc = efx_mcdi_get_mac_address_vf(enp, mac_addr);
200	}
201	if (rc != 0)
202		goto fail4;
203
204	EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr);
205
206	/* Board configuration */
207	rc = efx_mcdi_get_board_cfg(enp, &board_type, NULL, NULL);
208	if (rc != 0) {
209		/* Unprivileged functions may not be able to read board cfg */
210		if (rc == EACCES)
211			board_type = 0;
212		else
213			goto fail5;
214	}
215
216	encp->enc_board_type = board_type;
217	encp->enc_clk_mult = 1; /* not used for Medford */
218
219	/* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */
220	if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0)
221		goto fail6;
222
223	/* Obtain the default PHY advertised capabilities */
224	if ((rc = ef10_phy_get_link(enp, &els)) != 0)
225		goto fail7;
226	epp->ep_default_adv_cap_mask = els.els_adv_cap_mask;
227	epp->ep_adv_cap_mask = els.els_adv_cap_mask;
228
229	/*
230	 * Enable firmware workarounds for hardware errata.
231	 * Expected responses are:
232	 *  - 0 (zero):
233	 *	Success: workaround enabled or disabled as requested.
234	 *  - MC_CMD_ERR_ENOSYS (reported as ENOTSUP):
235	 *	Firmware does not support the MC_CMD_WORKAROUND request.
236	 *	(assume that the workaround is not supported).
237	 *  - MC_CMD_ERR_ENOENT (reported as ENOENT):
238	 *	Firmware does not support the requested workaround.
239	 *  - MC_CMD_ERR_EPERM  (reported as EACCES):
240	 *	Unprivileged function cannot enable/disable workarounds.
241	 *
242	 * See efx_mcdi_request_errcode() for MCDI error translations.
243	 */
244
245
246	if (EFX_PCI_FUNCTION_IS_VF(encp)) {
247		/*
248		 * Interrupt testing does not work for VFs. See bug50084.
249		 * FIXME: Does this still  apply to Medford?
250		 */
251		encp->enc_bug41750_workaround = B_TRUE;
252	}
253
254	/* Chained multicast is always enabled on Medford */
255	encp->enc_bug26807_workaround = B_TRUE;
256
257	/*
258	 * If the bug61265 workaround is enabled, then interrupt holdoff timers
259	 * cannot be controlled by timer table writes, so MCDI must be used
260	 * (timer table writes can still be used for wakeup timers).
261	 */
262	rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG61265, B_TRUE,
263	    NULL);
264	if ((rc == 0) || (rc == EACCES))
265		encp->enc_bug61265_workaround = B_TRUE;
266	else if ((rc == ENOTSUP) || (rc == ENOENT))
267		encp->enc_bug61265_workaround = B_FALSE;
268	else
269		goto fail8;
270
271	/* Get clock frequencies (in MHz). */
272	if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0)
273		goto fail9;
274
275	/*
276	 * The Medford timer quantum is 1536 dpcpu_clk cycles, documented for
277	 * the EV_TMR_VAL field of EV_TIMER_TBL. Scale for MHz and ns units.
278	 */
279	encp->enc_evq_timer_quantum_ns = 1536000UL / dpcpu_clk; /* 1536 cycles */
280	encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
281		    FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000;
282
283	/* Check capabilities of running datapath firmware */
284	if ((rc = ef10_get_datapath_caps(enp)) != 0)
285		goto fail10;
286
287	/* Alignment for receive packet DMA buffers */
288	encp->enc_rx_buf_align_start = 1;
289
290	/* Get the RX DMA end padding alignment configuration */
291	if ((rc = efx_mcdi_get_rxdp_config(enp, &end_padding)) != 0) {
292		if (rc != EACCES)
293			goto fail11;
294
295		/* Assume largest tail padding size supported by hardware */
296		end_padding = 256;
297	}
298	encp->enc_rx_buf_align_end = end_padding;
299
300	/* Alignment for WPTR updates */
301	encp->enc_rx_push_align = EF10_RX_WPTR_ALIGN;
302
303	encp->enc_tx_dma_desc_size_max = EFX_MASK32(ESF_DZ_RX_KER_BYTE_CNT);
304	/* No boundary crossing limits */
305	encp->enc_tx_dma_desc_boundary = 0;
306
307	/*
308	 * Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use
309	 * MC_CMD_GET_RESOURCE_LIMITS here as that reports the available
310	 * resources (allocated to this PCIe function), which is zero until
311	 * after we have allocated VIs.
312	 */
313	encp->enc_evq_limit = 1024;
314	encp->enc_rxq_limit = EFX_RXQ_LIMIT_TARGET;
315	encp->enc_txq_limit = EFX_TXQ_LIMIT_TARGET;
316
317	/*
318	 * The maximum supported transmit queue size is 2048. TXQs with 4096
319	 * descriptors are not supported as the top bit is used for vfifo
320	 * stuffing.
321	 */
322	encp->enc_txq_max_ndescs = 2048;
323
324	encp->enc_buftbl_limit = 0xFFFFFFFF;
325
326	encp->enc_piobuf_limit = MEDFORD_PIOBUF_NBUFS;
327	encp->enc_piobuf_size = MEDFORD_PIOBUF_SIZE;
328	encp->enc_piobuf_min_alloc_size = MEDFORD_MIN_PIO_ALLOC_SIZE;
329
330	/*
331	 * Get the current privilege mask. Note that this may be modified
332	 * dynamically, so this value is informational only. DO NOT use
333	 * the privilege mask to check for sufficient privileges, as that
334	 * can result in time-of-check/time-of-use bugs.
335	 */
336	if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0)
337		goto fail12;
338	encp->enc_privilege_mask = mask;
339
340	/* Get interrupt vector limits */
341	if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {
342		if (EFX_PCI_FUNCTION_IS_PF(encp))
343			goto fail13;
344
345		/* Ignore error (cannot query vector limits from a VF). */
346		base = 0;
347		nvec = 1024;
348	}
349	encp->enc_intr_vec_base = base;
350	encp->enc_intr_limit = nvec;
351
352	/*
353	 * Maximum number of bytes into the frame the TCP header can start for
354	 * firmware assisted TSO to work.
355	 */
356	encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT;
357
358	/*
359	 * Medford stores a single global copy of VPD, not per-PF as on
360	 * Huntington.
361	 */
362	encp->enc_vpd_is_global = B_TRUE;
363
364	rc = medford_nic_get_required_pcie_bandwidth(enp, &bandwidth);
365	if (rc != 0)
366		goto fail14;
367	encp->enc_required_pcie_bandwidth_mbps = bandwidth;
368	encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3;
369
370	return (0);
371
372fail14:
373	EFSYS_PROBE(fail14);
374fail13:
375	EFSYS_PROBE(fail13);
376fail12:
377	EFSYS_PROBE(fail12);
378fail11:
379	EFSYS_PROBE(fail11);
380fail10:
381	EFSYS_PROBE(fail10);
382fail9:
383	EFSYS_PROBE(fail9);
384fail8:
385	EFSYS_PROBE(fail8);
386fail7:
387	EFSYS_PROBE(fail7);
388fail6:
389	EFSYS_PROBE(fail6);
390fail5:
391	EFSYS_PROBE(fail5);
392fail4:
393	EFSYS_PROBE(fail4);
394fail3:
395	EFSYS_PROBE(fail3);
396fail2:
397	EFSYS_PROBE(fail2);
398fail1:
399	EFSYS_PROBE1(fail1, efx_rc_t, rc);
400
401	return (rc);
402}
403
404#endif	/* EFSYS_OPT_MEDFORD */
405