1/*-
2 * Copyright (c) 2007-2016 Solarflare Communications Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,
9 *    this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 *    this list of conditions and the following disclaimer in the documentation
12 *    and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
29 *
30 * $FreeBSD: stable/11/sys/dev/sfxge/common/efx_impl.h 342441 2018-12-25 07:21:35Z arybchik $
31 */
32
33#ifndef	_SYS_EFX_IMPL_H
34#define	_SYS_EFX_IMPL_H
35
36#include "efx.h"
37#include "efx_regs.h"
38#include "efx_regs_ef10.h"
39
40/* FIXME: Add definition for driver generated software events */
41#ifndef	ESE_DZ_EV_CODE_DRV_GEN_EV
42#define	ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV
43#endif
44
45
46#if EFSYS_OPT_SIENA
47#include "siena_impl.h"
48#endif	/* EFSYS_OPT_SIENA */
49
50#if EFSYS_OPT_HUNTINGTON
51#include "hunt_impl.h"
52#endif	/* EFSYS_OPT_HUNTINGTON */
53
54#if EFSYS_OPT_MEDFORD
55#include "medford_impl.h"
56#endif	/* EFSYS_OPT_MEDFORD */
57
58#if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
59#include "ef10_impl.h"
60#endif	/* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
61
62#ifdef	__cplusplus
63extern "C" {
64#endif
65
66#define	EFX_MOD_MCDI		0x00000001
67#define	EFX_MOD_PROBE		0x00000002
68#define	EFX_MOD_NVRAM		0x00000004
69#define	EFX_MOD_VPD		0x00000008
70#define	EFX_MOD_NIC		0x00000010
71#define	EFX_MOD_INTR		0x00000020
72#define	EFX_MOD_EV		0x00000040
73#define	EFX_MOD_RX		0x00000080
74#define	EFX_MOD_TX		0x00000100
75#define	EFX_MOD_PORT		0x00000200
76#define	EFX_MOD_MON		0x00000400
77#define	EFX_MOD_FILTER		0x00001000
78#define	EFX_MOD_LIC		0x00002000
79
80#define	EFX_RESET_PHY		0x00000001
81#define	EFX_RESET_RXQ_ERR	0x00000002
82#define	EFX_RESET_TXQ_ERR	0x00000004
83
84typedef enum efx_mac_type_e {
85	EFX_MAC_INVALID = 0,
86	EFX_MAC_SIENA,
87	EFX_MAC_HUNTINGTON,
88	EFX_MAC_MEDFORD,
89	EFX_MAC_NTYPES
90} efx_mac_type_t;
91
92typedef struct efx_ev_ops_s {
93	efx_rc_t	(*eevo_init)(efx_nic_t *);
94	void		(*eevo_fini)(efx_nic_t *);
95	efx_rc_t	(*eevo_qcreate)(efx_nic_t *, unsigned int,
96					  efsys_mem_t *, size_t, uint32_t,
97					  uint32_t, uint32_t, efx_evq_t *);
98	void		(*eevo_qdestroy)(efx_evq_t *);
99	efx_rc_t	(*eevo_qprime)(efx_evq_t *, unsigned int);
100	void		(*eevo_qpost)(efx_evq_t *, uint16_t);
101	efx_rc_t	(*eevo_qmoderate)(efx_evq_t *, unsigned int);
102#if EFSYS_OPT_QSTATS
103	void		(*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *);
104#endif
105} efx_ev_ops_t;
106
107typedef struct efx_tx_ops_s {
108	efx_rc_t	(*etxo_init)(efx_nic_t *);
109	void		(*etxo_fini)(efx_nic_t *);
110	efx_rc_t	(*etxo_qcreate)(efx_nic_t *,
111					unsigned int, unsigned int,
112					efsys_mem_t *, size_t,
113					uint32_t, uint16_t,
114					efx_evq_t *, efx_txq_t *,
115					unsigned int *);
116	void		(*etxo_qdestroy)(efx_txq_t *);
117	efx_rc_t	(*etxo_qpost)(efx_txq_t *, efx_buffer_t *,
118				      unsigned int, unsigned int,
119				      unsigned int *);
120	void		(*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int);
121	efx_rc_t	(*etxo_qpace)(efx_txq_t *, unsigned int);
122	efx_rc_t	(*etxo_qflush)(efx_txq_t *);
123	void		(*etxo_qenable)(efx_txq_t *);
124	efx_rc_t	(*etxo_qpio_enable)(efx_txq_t *);
125	void		(*etxo_qpio_disable)(efx_txq_t *);
126	efx_rc_t	(*etxo_qpio_write)(efx_txq_t *, uint8_t *, size_t,
127					   size_t);
128	efx_rc_t	(*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int,
129					   unsigned int *);
130	efx_rc_t	(*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *,
131				      unsigned int, unsigned int,
132				      unsigned int *);
133	void		(*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t,
134						size_t, boolean_t,
135						efx_desc_t *);
136	void		(*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t,
137						uint32_t, uint8_t,
138						efx_desc_t *);
139	void		(*etxo_qdesc_tso2_create)(efx_txq_t *, uint16_t,
140						uint32_t, uint16_t,
141						efx_desc_t *, int);
142	void		(*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t,
143						efx_desc_t *);
144	void		(*etxo_qdesc_checksum_create)(efx_txq_t *, uint16_t,
145						efx_desc_t *);
146#if EFSYS_OPT_QSTATS
147	void		(*etxo_qstats_update)(efx_txq_t *,
148					      efsys_stat_t *);
149#endif
150} efx_tx_ops_t;
151
152typedef struct efx_rx_ops_s {
153	efx_rc_t	(*erxo_init)(efx_nic_t *);
154	void		(*erxo_fini)(efx_nic_t *);
155#if EFSYS_OPT_RX_SCATTER
156	efx_rc_t	(*erxo_scatter_enable)(efx_nic_t *, unsigned int);
157#endif
158#if EFSYS_OPT_RX_SCALE
159	efx_rc_t	(*erxo_scale_mode_set)(efx_nic_t *, efx_rx_hash_alg_t,
160					       efx_rx_hash_type_t, boolean_t);
161	efx_rc_t	(*erxo_scale_key_set)(efx_nic_t *, uint8_t *, size_t);
162	efx_rc_t	(*erxo_scale_tbl_set)(efx_nic_t *, unsigned int *,
163					      size_t);
164	uint32_t	(*erxo_prefix_hash)(efx_nic_t *, efx_rx_hash_alg_t,
165					    uint8_t *);
166#endif /* EFSYS_OPT_RX_SCALE */
167	efx_rc_t	(*erxo_prefix_pktlen)(efx_nic_t *, uint8_t *,
168					      uint16_t *);
169	void		(*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t,
170				      unsigned int, unsigned int,
171				      unsigned int);
172	void		(*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *);
173	efx_rc_t	(*erxo_qflush)(efx_rxq_t *);
174	void		(*erxo_qenable)(efx_rxq_t *);
175	efx_rc_t	(*erxo_qcreate)(efx_nic_t *enp, unsigned int,
176					unsigned int, efx_rxq_type_t,
177					efsys_mem_t *, size_t, uint32_t,
178					efx_evq_t *, efx_rxq_t *);
179	void		(*erxo_qdestroy)(efx_rxq_t *);
180} efx_rx_ops_t;
181
182typedef struct efx_mac_ops_s {
183	efx_rc_t	(*emo_poll)(efx_nic_t *, efx_link_mode_t *);
184	efx_rc_t	(*emo_up)(efx_nic_t *, boolean_t *);
185	efx_rc_t	(*emo_addr_set)(efx_nic_t *);
186	efx_rc_t	(*emo_pdu_set)(efx_nic_t *);
187	efx_rc_t	(*emo_pdu_get)(efx_nic_t *, size_t *);
188	efx_rc_t	(*emo_reconfigure)(efx_nic_t *);
189	efx_rc_t	(*emo_multicast_list_set)(efx_nic_t *);
190	efx_rc_t	(*emo_filter_default_rxq_set)(efx_nic_t *,
191						      efx_rxq_t *, boolean_t);
192	void		(*emo_filter_default_rxq_clear)(efx_nic_t *);
193#if EFSYS_OPT_LOOPBACK
194	efx_rc_t	(*emo_loopback_set)(efx_nic_t *, efx_link_mode_t,
195					    efx_loopback_type_t);
196#endif	/* EFSYS_OPT_LOOPBACK */
197#if EFSYS_OPT_MAC_STATS
198	efx_rc_t	(*emo_stats_get_mask)(efx_nic_t *, uint32_t *, size_t);
199	efx_rc_t	(*emo_stats_upload)(efx_nic_t *, efsys_mem_t *);
200	efx_rc_t	(*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *,
201					      uint16_t, boolean_t);
202	efx_rc_t	(*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
203					    efsys_stat_t *, uint32_t *);
204#endif	/* EFSYS_OPT_MAC_STATS */
205} efx_mac_ops_t;
206
207typedef struct efx_phy_ops_s {
208	efx_rc_t	(*epo_power)(efx_nic_t *, boolean_t); /* optional */
209	efx_rc_t	(*epo_reset)(efx_nic_t *);
210	efx_rc_t	(*epo_reconfigure)(efx_nic_t *);
211	efx_rc_t	(*epo_verify)(efx_nic_t *);
212	efx_rc_t	(*epo_oui_get)(efx_nic_t *, uint32_t *);
213#if EFSYS_OPT_PHY_STATS
214	efx_rc_t	(*epo_stats_update)(efx_nic_t *, efsys_mem_t *,
215					    uint32_t *);
216#endif	/* EFSYS_OPT_PHY_STATS */
217#if EFSYS_OPT_BIST
218	efx_rc_t	(*epo_bist_enable_offline)(efx_nic_t *);
219	efx_rc_t	(*epo_bist_start)(efx_nic_t *, efx_bist_type_t);
220	efx_rc_t	(*epo_bist_poll)(efx_nic_t *, efx_bist_type_t,
221					 efx_bist_result_t *, uint32_t *,
222					 unsigned long *, size_t);
223	void		(*epo_bist_stop)(efx_nic_t *, efx_bist_type_t);
224#endif	/* EFSYS_OPT_BIST */
225} efx_phy_ops_t;
226
227#if EFSYS_OPT_FILTER
228typedef struct efx_filter_ops_s {
229	efx_rc_t	(*efo_init)(efx_nic_t *);
230	void		(*efo_fini)(efx_nic_t *);
231	efx_rc_t	(*efo_restore)(efx_nic_t *);
232	efx_rc_t	(*efo_add)(efx_nic_t *, efx_filter_spec_t *,
233				   boolean_t may_replace);
234	efx_rc_t	(*efo_delete)(efx_nic_t *, efx_filter_spec_t *);
235	efx_rc_t	(*efo_supported_filters)(efx_nic_t *, uint32_t *,
236				   size_t, size_t *);
237	efx_rc_t	(*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t,
238				   boolean_t, boolean_t, boolean_t,
239				   uint8_t const *, uint32_t);
240} efx_filter_ops_t;
241
242extern	__checkReturn	efx_rc_t
243efx_filter_reconfigure(
244	__in				efx_nic_t *enp,
245	__in_ecount(6)			uint8_t const *mac_addr,
246	__in				boolean_t all_unicst,
247	__in				boolean_t mulcst,
248	__in				boolean_t all_mulcst,
249	__in				boolean_t brdcst,
250	__in_ecount(6*count)		uint8_t const *addrs,
251	__in				uint32_t count);
252
253#endif /* EFSYS_OPT_FILTER */
254
255
256typedef struct efx_port_s {
257	efx_mac_type_t		ep_mac_type;
258	uint32_t		ep_phy_type;
259	uint8_t			ep_port;
260	uint32_t		ep_mac_pdu;
261	uint8_t			ep_mac_addr[6];
262	efx_link_mode_t		ep_link_mode;
263	boolean_t		ep_all_unicst;
264	boolean_t		ep_mulcst;
265	boolean_t		ep_all_mulcst;
266	boolean_t		ep_brdcst;
267	unsigned int		ep_fcntl;
268	boolean_t		ep_fcntl_autoneg;
269	efx_oword_t		ep_multicst_hash[2];
270	uint8_t			ep_mulcst_addr_list[EFX_MAC_ADDR_LEN *
271						    EFX_MAC_MULTICAST_LIST_MAX];
272	uint32_t		ep_mulcst_addr_count;
273#if EFSYS_OPT_LOOPBACK
274	efx_loopback_type_t	ep_loopback_type;
275	efx_link_mode_t		ep_loopback_link_mode;
276#endif	/* EFSYS_OPT_LOOPBACK */
277#if EFSYS_OPT_PHY_FLAGS
278	uint32_t		ep_phy_flags;
279#endif	/* EFSYS_OPT_PHY_FLAGS */
280#if EFSYS_OPT_PHY_LED_CONTROL
281	efx_phy_led_mode_t	ep_phy_led_mode;
282#endif	/* EFSYS_OPT_PHY_LED_CONTROL */
283	efx_phy_media_type_t	ep_fixed_port_type;
284	efx_phy_media_type_t	ep_module_type;
285	uint32_t		ep_adv_cap_mask;
286	uint32_t		ep_lp_cap_mask;
287	uint32_t		ep_default_adv_cap_mask;
288	uint32_t		ep_phy_cap_mask;
289	boolean_t		ep_mac_drain;
290#if EFSYS_OPT_BIST
291	efx_bist_type_t		ep_current_bist;
292#endif
293	const efx_mac_ops_t	*ep_emop;
294	const efx_phy_ops_t	*ep_epop;
295} efx_port_t;
296
297typedef struct efx_mon_ops_s {
298#if EFSYS_OPT_MON_STATS
299	efx_rc_t	(*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
300					    efx_mon_stat_value_t *);
301#endif	/* EFSYS_OPT_MON_STATS */
302} efx_mon_ops_t;
303
304typedef struct efx_mon_s {
305	efx_mon_type_t		em_type;
306	const efx_mon_ops_t	*em_emop;
307} efx_mon_t;
308
309typedef struct efx_intr_ops_s {
310	efx_rc_t	(*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *);
311	void		(*eio_enable)(efx_nic_t *);
312	void		(*eio_disable)(efx_nic_t *);
313	void		(*eio_disable_unlocked)(efx_nic_t *);
314	efx_rc_t	(*eio_trigger)(efx_nic_t *, unsigned int);
315	void		(*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *);
316	void		(*eio_status_message)(efx_nic_t *, unsigned int,
317				 boolean_t *);
318	void		(*eio_fatal)(efx_nic_t *);
319	void		(*eio_fini)(efx_nic_t *);
320} efx_intr_ops_t;
321
322typedef struct efx_intr_s {
323	const efx_intr_ops_t	*ei_eiop;
324	efsys_mem_t		*ei_esmp;
325	efx_intr_type_t		ei_type;
326	unsigned int		ei_level;
327} efx_intr_t;
328
329typedef struct efx_nic_ops_s {
330	efx_rc_t	(*eno_probe)(efx_nic_t *);
331	efx_rc_t	(*eno_board_cfg)(efx_nic_t *);
332	efx_rc_t	(*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*);
333	efx_rc_t	(*eno_reset)(efx_nic_t *);
334	efx_rc_t	(*eno_init)(efx_nic_t *);
335	efx_rc_t	(*eno_get_vi_pool)(efx_nic_t *, uint32_t *);
336	efx_rc_t	(*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t,
337					uint32_t *, size_t *);
338#if EFSYS_OPT_DIAG
339	efx_rc_t	(*eno_register_test)(efx_nic_t *);
340#endif	/* EFSYS_OPT_DIAG */
341	void		(*eno_fini)(efx_nic_t *);
342	void		(*eno_unprobe)(efx_nic_t *);
343} efx_nic_ops_t;
344
345#ifndef EFX_TXQ_LIMIT_TARGET
346#define	EFX_TXQ_LIMIT_TARGET 259
347#endif
348#ifndef EFX_RXQ_LIMIT_TARGET
349#define	EFX_RXQ_LIMIT_TARGET 512
350#endif
351#ifndef EFX_TXQ_DC_SIZE
352#define	EFX_TXQ_DC_SIZE 1 /* 16 descriptors */
353#endif
354#ifndef EFX_RXQ_DC_SIZE
355#define	EFX_RXQ_DC_SIZE 3 /* 64 descriptors */
356#endif
357
358#if EFSYS_OPT_FILTER
359
360typedef struct siena_filter_spec_s {
361	uint8_t		sfs_type;
362	uint32_t	sfs_flags;
363	uint32_t	sfs_dmaq_id;
364	uint32_t	sfs_dword[3];
365} siena_filter_spec_t;
366
367typedef enum siena_filter_type_e {
368	EFX_SIENA_FILTER_RX_TCP_FULL,	/* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
369	EFX_SIENA_FILTER_RX_TCP_WILD,	/* TCP/IPv4 {dIP,dTCP,  -,   -} */
370	EFX_SIENA_FILTER_RX_UDP_FULL,	/* UDP/IPv4 {dIP,dUDP,sIP,sUDP} */
371	EFX_SIENA_FILTER_RX_UDP_WILD,	/* UDP/IPv4 {dIP,dUDP,  -,   -} */
372	EFX_SIENA_FILTER_RX_MAC_FULL,	/* Ethernet {dMAC,VLAN} */
373	EFX_SIENA_FILTER_RX_MAC_WILD,	/* Ethernet {dMAC,   -} */
374
375	EFX_SIENA_FILTER_TX_TCP_FULL,	/* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
376	EFX_SIENA_FILTER_TX_TCP_WILD,	/* TCP/IPv4 {  -,   -,sIP,sTCP} */
377	EFX_SIENA_FILTER_TX_UDP_FULL,	/* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */
378	EFX_SIENA_FILTER_TX_UDP_WILD,	/* UDP/IPv4 {  -,   -,sIP,sUDP} */
379	EFX_SIENA_FILTER_TX_MAC_FULL,	/* Ethernet {sMAC,VLAN} */
380	EFX_SIENA_FILTER_TX_MAC_WILD,	/* Ethernet {sMAC,   -} */
381
382	EFX_SIENA_FILTER_NTYPES
383} siena_filter_type_t;
384
385typedef enum siena_filter_tbl_id_e {
386	EFX_SIENA_FILTER_TBL_RX_IP = 0,
387	EFX_SIENA_FILTER_TBL_RX_MAC,
388	EFX_SIENA_FILTER_TBL_TX_IP,
389	EFX_SIENA_FILTER_TBL_TX_MAC,
390	EFX_SIENA_FILTER_NTBLS
391} siena_filter_tbl_id_t;
392
393typedef struct siena_filter_tbl_s {
394	int			sft_size;	/* number of entries */
395	int			sft_used;	/* active count */
396	uint32_t		*sft_bitmap;	/* active bitmap */
397	siena_filter_spec_t	*sft_spec;	/* array of saved specs */
398} siena_filter_tbl_t;
399
400typedef struct siena_filter_s {
401	siena_filter_tbl_t	sf_tbl[EFX_SIENA_FILTER_NTBLS];
402	unsigned int		sf_depth[EFX_SIENA_FILTER_NTYPES];
403} siena_filter_t;
404
405typedef struct efx_filter_s {
406#if EFSYS_OPT_SIENA
407	siena_filter_t		*ef_siena_filter;
408#endif /* EFSYS_OPT_SIENA */
409#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
410	ef10_filter_table_t	*ef_ef10_filter_table;
411#endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
412} efx_filter_t;
413
414extern			void
415siena_filter_tbl_clear(
416	__in		efx_nic_t *enp,
417	__in		siena_filter_tbl_id_t tbl);
418
419#endif	/* EFSYS_OPT_FILTER */
420
421#if EFSYS_OPT_MCDI
422
423typedef struct efx_mcdi_ops_s {
424	efx_rc_t	(*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *);
425	void		(*emco_send_request)(efx_nic_t *, void *, size_t,
426					void *, size_t);
427	efx_rc_t	(*emco_poll_reboot)(efx_nic_t *);
428	boolean_t	(*emco_poll_response)(efx_nic_t *);
429	void		(*emco_read_response)(efx_nic_t *, void *, size_t, size_t);
430	void		(*emco_fini)(efx_nic_t *);
431	efx_rc_t	(*emco_feature_supported)(efx_nic_t *,
432					    efx_mcdi_feature_id_t, boolean_t *);
433	void		(*emco_get_timeout)(efx_nic_t *, efx_mcdi_req_t *,
434					    uint32_t *);
435} efx_mcdi_ops_t;
436
437typedef struct efx_mcdi_s {
438	const efx_mcdi_ops_t		*em_emcop;
439	const efx_mcdi_transport_t	*em_emtp;
440	efx_mcdi_iface_t		em_emip;
441} efx_mcdi_t;
442
443#endif /* EFSYS_OPT_MCDI */
444
445#if EFSYS_OPT_NVRAM
446typedef struct efx_nvram_ops_s {
447#if EFSYS_OPT_DIAG
448	efx_rc_t	(*envo_test)(efx_nic_t *);
449#endif	/* EFSYS_OPT_DIAG */
450	efx_rc_t	(*envo_type_to_partn)(efx_nic_t *, efx_nvram_type_t,
451					    uint32_t *);
452	efx_rc_t	(*envo_partn_size)(efx_nic_t *, uint32_t, size_t *);
453	efx_rc_t	(*envo_partn_rw_start)(efx_nic_t *, uint32_t, size_t *);
454	efx_rc_t	(*envo_partn_read)(efx_nic_t *, uint32_t,
455					    unsigned int, caddr_t, size_t);
456	efx_rc_t	(*envo_partn_erase)(efx_nic_t *, uint32_t,
457					    unsigned int, size_t);
458	efx_rc_t	(*envo_partn_write)(efx_nic_t *, uint32_t,
459					    unsigned int, caddr_t, size_t);
460	efx_rc_t	(*envo_partn_rw_finish)(efx_nic_t *, uint32_t);
461	efx_rc_t	(*envo_partn_get_version)(efx_nic_t *, uint32_t,
462					    uint32_t *, uint16_t *);
463	efx_rc_t	(*envo_partn_set_version)(efx_nic_t *, uint32_t,
464					    uint16_t *);
465	efx_rc_t	(*envo_buffer_validate)(efx_nic_t *, uint32_t,
466					    caddr_t, size_t);
467} efx_nvram_ops_t;
468#endif /* EFSYS_OPT_NVRAM */
469
470#if EFSYS_OPT_VPD
471typedef struct efx_vpd_ops_s {
472	efx_rc_t	(*evpdo_init)(efx_nic_t *);
473	efx_rc_t	(*evpdo_size)(efx_nic_t *, size_t *);
474	efx_rc_t	(*evpdo_read)(efx_nic_t *, caddr_t, size_t);
475	efx_rc_t	(*evpdo_verify)(efx_nic_t *, caddr_t, size_t);
476	efx_rc_t	(*evpdo_reinit)(efx_nic_t *, caddr_t, size_t);
477	efx_rc_t	(*evpdo_get)(efx_nic_t *, caddr_t, size_t,
478					efx_vpd_value_t *);
479	efx_rc_t	(*evpdo_set)(efx_nic_t *, caddr_t, size_t,
480					efx_vpd_value_t *);
481	efx_rc_t	(*evpdo_next)(efx_nic_t *, caddr_t, size_t,
482					efx_vpd_value_t *, unsigned int *);
483	efx_rc_t	(*evpdo_write)(efx_nic_t *, caddr_t, size_t);
484	void		(*evpdo_fini)(efx_nic_t *);
485} efx_vpd_ops_t;
486#endif	/* EFSYS_OPT_VPD */
487
488#if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
489
490	__checkReturn		efx_rc_t
491efx_mcdi_nvram_partitions(
492	__in			efx_nic_t *enp,
493	__out_bcount(size)	caddr_t data,
494	__in			size_t size,
495	__out			unsigned int *npartnp);
496
497	__checkReturn		efx_rc_t
498efx_mcdi_nvram_metadata(
499	__in			efx_nic_t *enp,
500	__in			uint32_t partn,
501	__out			uint32_t *subtypep,
502	__out_ecount(4)		uint16_t version[4],
503	__out_bcount_opt(size)	char *descp,
504	__in			size_t size);
505
506	__checkReturn		efx_rc_t
507efx_mcdi_nvram_info(
508	__in			efx_nic_t *enp,
509	__in			uint32_t partn,
510	__out_opt		size_t *sizep,
511	__out_opt		uint32_t *addressp,
512	__out_opt		uint32_t *erase_sizep,
513	__out_opt		uint32_t *write_sizep);
514
515	__checkReturn		efx_rc_t
516efx_mcdi_nvram_update_start(
517	__in			efx_nic_t *enp,
518	__in			uint32_t partn);
519
520	__checkReturn		efx_rc_t
521efx_mcdi_nvram_read(
522	__in			efx_nic_t *enp,
523	__in			uint32_t partn,
524	__in			uint32_t offset,
525	__out_bcount(size)	caddr_t data,
526	__in			size_t size,
527	__in			uint32_t mode);
528
529	__checkReturn		efx_rc_t
530efx_mcdi_nvram_erase(
531	__in			efx_nic_t *enp,
532	__in			uint32_t partn,
533	__in			uint32_t offset,
534	__in			size_t size);
535
536	__checkReturn		efx_rc_t
537efx_mcdi_nvram_write(
538	__in			efx_nic_t *enp,
539	__in			uint32_t partn,
540	__in			uint32_t offset,
541	__in_bcount(size)	caddr_t data,
542	__in			size_t size);
543
544	__checkReturn		efx_rc_t
545efx_mcdi_nvram_update_finish(
546	__in			efx_nic_t *enp,
547	__in			uint32_t partn,
548	__in			boolean_t reboot,
549	__out_opt		uint32_t *resultp);
550
551#if EFSYS_OPT_DIAG
552
553	__checkReturn		efx_rc_t
554efx_mcdi_nvram_test(
555	__in			efx_nic_t *enp,
556	__in			uint32_t partn);
557
558#endif	/* EFSYS_OPT_DIAG */
559
560#endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */
561
562#if EFSYS_OPT_LICENSING
563
564typedef struct efx_lic_ops_s {
565	efx_rc_t	(*elo_update_licenses)(efx_nic_t *);
566	efx_rc_t	(*elo_get_key_stats)(efx_nic_t *, efx_key_stats_t *);
567	efx_rc_t	(*elo_app_state)(efx_nic_t *, uint64_t, boolean_t *);
568	efx_rc_t	(*elo_get_id)(efx_nic_t *, size_t, uint32_t *,
569				      size_t *, uint8_t *);
570	efx_rc_t	(*elo_find_start)
571				(efx_nic_t *, caddr_t, size_t, uint32_t *);
572	efx_rc_t	(*elo_find_end)(efx_nic_t *, caddr_t, size_t,
573				uint32_t, uint32_t *);
574	boolean_t	(*elo_find_key)(efx_nic_t *, caddr_t, size_t,
575				uint32_t, uint32_t *, uint32_t *);
576	boolean_t	(*elo_validate_key)(efx_nic_t *,
577				caddr_t, uint32_t);
578	efx_rc_t	(*elo_read_key)(efx_nic_t *,
579				caddr_t, size_t, uint32_t, uint32_t,
580				caddr_t, size_t, uint32_t *);
581	efx_rc_t	(*elo_write_key)(efx_nic_t *,
582				caddr_t, size_t, uint32_t,
583				caddr_t, uint32_t, uint32_t *);
584	efx_rc_t	(*elo_delete_key)(efx_nic_t *,
585				caddr_t, size_t, uint32_t,
586				uint32_t, uint32_t, uint32_t *);
587	efx_rc_t	(*elo_create_partition)(efx_nic_t *,
588				caddr_t, size_t);
589	efx_rc_t	(*elo_finish_partition)(efx_nic_t *,
590				caddr_t, size_t);
591} efx_lic_ops_t;
592
593#endif
594
595typedef struct efx_drv_cfg_s {
596	uint32_t		edc_min_vi_count;
597	uint32_t		edc_max_vi_count;
598
599	uint32_t		edc_max_piobuf_count;
600	uint32_t		edc_pio_alloc_size;
601} efx_drv_cfg_t;
602
603struct efx_nic_s {
604	uint32_t		en_magic;
605	efx_family_t		en_family;
606	uint32_t		en_features;
607	efsys_identifier_t	*en_esip;
608	efsys_lock_t		*en_eslp;
609	efsys_bar_t		*en_esbp;
610	unsigned int		en_mod_flags;
611	unsigned int		en_reset_flags;
612	efx_nic_cfg_t		en_nic_cfg;
613	efx_drv_cfg_t		en_drv_cfg;
614	efx_port_t		en_port;
615	efx_mon_t		en_mon;
616	efx_intr_t		en_intr;
617	uint32_t		en_ev_qcount;
618	uint32_t		en_rx_qcount;
619	uint32_t		en_tx_qcount;
620	const efx_nic_ops_t	*en_enop;
621	const efx_ev_ops_t	*en_eevop;
622	const efx_tx_ops_t	*en_etxop;
623	const efx_rx_ops_t	*en_erxop;
624#if EFSYS_OPT_FILTER
625	efx_filter_t		en_filter;
626	const efx_filter_ops_t	*en_efop;
627#endif	/* EFSYS_OPT_FILTER */
628#if EFSYS_OPT_MCDI
629	efx_mcdi_t		en_mcdi;
630#endif	/* EFSYS_OPT_MCDI */
631#if EFSYS_OPT_NVRAM
632	efx_nvram_type_t	en_nvram_locked;
633	const efx_nvram_ops_t	*en_envop;
634#endif	/* EFSYS_OPT_NVRAM */
635#if EFSYS_OPT_VPD
636	const efx_vpd_ops_t	*en_evpdop;
637#endif	/* EFSYS_OPT_VPD */
638#if EFSYS_OPT_RX_SCALE
639	efx_rx_hash_support_t	en_hash_support;
640	efx_rx_scale_support_t	en_rss_support;
641	uint32_t		en_rss_context;
642#endif	/* EFSYS_OPT_RX_SCALE */
643	uint32_t		en_vport_id;
644#if EFSYS_OPT_LICENSING
645	const efx_lic_ops_t	*en_elop;
646	boolean_t		en_licensing_supported;
647#endif
648	union {
649#if EFSYS_OPT_SIENA
650		struct {
651#if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
652			unsigned int		enu_partn_mask;
653#endif	/* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
654#if EFSYS_OPT_VPD
655			caddr_t			enu_svpd;
656			size_t			enu_svpd_length;
657#endif	/* EFSYS_OPT_VPD */
658			int			enu_unused;
659		} siena;
660#endif	/* EFSYS_OPT_SIENA */
661		int	enu_unused;
662	} en_u;
663#if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
664	union en_arch {
665		struct {
666			int			ena_vi_base;
667			int			ena_vi_count;
668			int			ena_vi_shift;
669#if EFSYS_OPT_VPD
670			caddr_t			ena_svpd;
671			size_t			ena_svpd_length;
672#endif	/* EFSYS_OPT_VPD */
673			efx_piobuf_handle_t	ena_piobuf_handle[EF10_MAX_PIOBUF_NBUFS];
674			uint32_t		ena_piobuf_count;
675			uint32_t		ena_pio_alloc_map[EF10_MAX_PIOBUF_NBUFS];
676			uint32_t		ena_pio_write_vi_base;
677			/* Memory BAR mapping regions */
678			uint32_t		ena_uc_mem_map_offset;
679			size_t			ena_uc_mem_map_size;
680			uint32_t		ena_wc_mem_map_offset;
681			size_t			ena_wc_mem_map_size;
682		} ef10;
683	} en_arch;
684#endif	/* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
685};
686
687
688#define	EFX_NIC_MAGIC	0x02121996
689
690typedef	boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *,
691    const efx_ev_callbacks_t *, void *);
692
693typedef struct efx_evq_rxq_state_s {
694	unsigned int			eers_rx_read_ptr;
695	unsigned int			eers_rx_mask;
696} efx_evq_rxq_state_t;
697
698struct efx_evq_s {
699	uint32_t			ee_magic;
700	efx_nic_t			*ee_enp;
701	unsigned int			ee_index;
702	unsigned int			ee_mask;
703	efsys_mem_t			*ee_esmp;
704#if EFSYS_OPT_QSTATS
705	uint32_t			ee_stat[EV_NQSTATS];
706#endif	/* EFSYS_OPT_QSTATS */
707
708	efx_ev_handler_t		ee_rx;
709	efx_ev_handler_t		ee_tx;
710	efx_ev_handler_t		ee_driver;
711	efx_ev_handler_t		ee_global;
712	efx_ev_handler_t		ee_drv_gen;
713#if EFSYS_OPT_MCDI
714	efx_ev_handler_t		ee_mcdi;
715#endif	/* EFSYS_OPT_MCDI */
716
717	efx_evq_rxq_state_t		ee_rxq_state[EFX_EV_RX_NLABELS];
718
719	uint32_t			ee_flags;
720};
721
722#define	EFX_EVQ_MAGIC	0x08081997
723
724#define	EFX_EVQ_SIENA_TIMER_QUANTUM_NS	6144 /* 768 cycles */
725
726struct efx_rxq_s {
727	uint32_t			er_magic;
728	efx_nic_t			*er_enp;
729	efx_evq_t			*er_eep;
730	unsigned int			er_index;
731	unsigned int			er_label;
732	unsigned int			er_mask;
733	efsys_mem_t			*er_esmp;
734};
735
736#define	EFX_RXQ_MAGIC	0x15022005
737
738struct efx_txq_s {
739	uint32_t			et_magic;
740	efx_nic_t			*et_enp;
741	unsigned int			et_index;
742	unsigned int			et_mask;
743	efsys_mem_t			*et_esmp;
744#if EFSYS_OPT_HUNTINGTON
745	uint32_t			et_pio_bufnum;
746	uint32_t			et_pio_blknum;
747	uint32_t			et_pio_write_offset;
748	uint32_t			et_pio_offset;
749	size_t				et_pio_size;
750#endif
751#if EFSYS_OPT_QSTATS
752	uint32_t			et_stat[TX_NQSTATS];
753#endif	/* EFSYS_OPT_QSTATS */
754};
755
756#define	EFX_TXQ_MAGIC	0x05092005
757
758#define	EFX_MAC_ADDR_COPY(_dst, _src)					\
759	do {								\
760		(_dst)[0] = (_src)[0];					\
761		(_dst)[1] = (_src)[1];					\
762		(_dst)[2] = (_src)[2];					\
763		(_dst)[3] = (_src)[3];					\
764		(_dst)[4] = (_src)[4];					\
765		(_dst)[5] = (_src)[5];					\
766	_NOTE(CONSTANTCONDITION)					\
767	} while (B_FALSE)
768
769#define	EFX_MAC_BROADCAST_ADDR_SET(_dst)				\
770	do {								\
771		uint16_t *_d = (uint16_t *)(_dst);			\
772		_d[0] = 0xffff;						\
773		_d[1] = 0xffff;						\
774		_d[2] = 0xffff;						\
775	_NOTE(CONSTANTCONDITION)					\
776	} while (B_FALSE)
777
778#if EFSYS_OPT_CHECK_REG
779#define	EFX_CHECK_REG(_enp, _reg)					\
780	do {								\
781		const char *name = #_reg;				\
782		char min = name[4];					\
783		char max = name[5];					\
784		char rev;						\
785									\
786		switch ((_enp)->en_family) {				\
787		case EFX_FAMILY_SIENA:					\
788			rev = 'C';					\
789			break;						\
790									\
791		case EFX_FAMILY_HUNTINGTON:				\
792			rev = 'D';					\
793			break;						\
794									\
795		case EFX_FAMILY_MEDFORD:				\
796			rev = 'E';					\
797			break;						\
798									\
799		default:						\
800			rev = '?';					\
801			break;						\
802		}							\
803									\
804		EFSYS_ASSERT3S(rev, >=, min);				\
805		EFSYS_ASSERT3S(rev, <=, max);				\
806									\
807	_NOTE(CONSTANTCONDITION)					\
808	} while (B_FALSE)
809#else
810#define	EFX_CHECK_REG(_enp, _reg) do {					\
811	_NOTE(CONSTANTCONDITION)					\
812	} while (B_FALSE)
813#endif
814
815#define	EFX_BAR_READD(_enp, _reg, _edp, _lock)				\
816	do {								\
817		EFX_CHECK_REG((_enp), (_reg));				\
818		EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST,		\
819		    (_edp), (_lock));					\
820		EFSYS_PROBE3(efx_bar_readd, const char *, #_reg,	\
821		    uint32_t, _reg ## _OFST,				\
822		    uint32_t, (_edp)->ed_u32[0]);			\
823	_NOTE(CONSTANTCONDITION)					\
824	} while (B_FALSE)
825
826#define	EFX_BAR_WRITED(_enp, _reg, _edp, _lock)				\
827	do {								\
828		EFX_CHECK_REG((_enp), (_reg));				\
829		EFSYS_PROBE3(efx_bar_writed, const char *, #_reg,	\
830		    uint32_t, _reg ## _OFST,				\
831		    uint32_t, (_edp)->ed_u32[0]);			\
832		EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST,	\
833		    (_edp), (_lock));					\
834	_NOTE(CONSTANTCONDITION)					\
835	} while (B_FALSE)
836
837#define	EFX_BAR_READQ(_enp, _reg, _eqp)					\
838	do {								\
839		EFX_CHECK_REG((_enp), (_reg));				\
840		EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST,		\
841		    (_eqp));						\
842		EFSYS_PROBE4(efx_bar_readq, const char *, #_reg,	\
843		    uint32_t, _reg ## _OFST,				\
844		    uint32_t, (_eqp)->eq_u32[1],			\
845		    uint32_t, (_eqp)->eq_u32[0]);			\
846	_NOTE(CONSTANTCONDITION)					\
847	} while (B_FALSE)
848
849#define	EFX_BAR_WRITEQ(_enp, _reg, _eqp)				\
850	do {								\
851		EFX_CHECK_REG((_enp), (_reg));				\
852		EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg,	\
853		    uint32_t, _reg ## _OFST,				\
854		    uint32_t, (_eqp)->eq_u32[1],			\
855		    uint32_t, (_eqp)->eq_u32[0]);			\
856		EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST,	\
857		    (_eqp));						\
858	_NOTE(CONSTANTCONDITION)					\
859	} while (B_FALSE)
860
861#define	EFX_BAR_READO(_enp, _reg, _eop)					\
862	do {								\
863		EFX_CHECK_REG((_enp), (_reg));				\
864		EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST,		\
865		    (_eop), B_TRUE);					\
866		EFSYS_PROBE6(efx_bar_reado, const char *, #_reg,	\
867		    uint32_t, _reg ## _OFST,				\
868		    uint32_t, (_eop)->eo_u32[3],			\
869		    uint32_t, (_eop)->eo_u32[2],			\
870		    uint32_t, (_eop)->eo_u32[1],			\
871		    uint32_t, (_eop)->eo_u32[0]);			\
872	_NOTE(CONSTANTCONDITION)					\
873	} while (B_FALSE)
874
875#define	EFX_BAR_WRITEO(_enp, _reg, _eop)				\
876	do {								\
877		EFX_CHECK_REG((_enp), (_reg));				\
878		EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg,	\
879		    uint32_t, _reg ## _OFST,				\
880		    uint32_t, (_eop)->eo_u32[3],			\
881		    uint32_t, (_eop)->eo_u32[2],			\
882		    uint32_t, (_eop)->eo_u32[1],			\
883		    uint32_t, (_eop)->eo_u32[0]);			\
884		EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST,	\
885		    (_eop), B_TRUE);					\
886	_NOTE(CONSTANTCONDITION)					\
887	} while (B_FALSE)
888
889#define	EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock)		\
890	do {								\
891		EFX_CHECK_REG((_enp), (_reg));				\
892		EFSYS_BAR_READD((_enp)->en_esbp,			\
893		    (_reg ## _OFST + ((_index) * _reg ## _STEP)),	\
894		    (_edp), (_lock));					\
895		EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg,	\
896		    uint32_t, (_index),					\
897		    uint32_t, _reg ## _OFST,				\
898		    uint32_t, (_edp)->ed_u32[0]);			\
899	_NOTE(CONSTANTCONDITION)					\
900	} while (B_FALSE)
901
902#define	EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock)		\
903	do {								\
904		EFX_CHECK_REG((_enp), (_reg));				\
905		EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,	\
906		    uint32_t, (_index),					\
907		    uint32_t, _reg ## _OFST,				\
908		    uint32_t, (_edp)->ed_u32[0]);			\
909		EFSYS_BAR_WRITED((_enp)->en_esbp,			\
910		    (_reg ## _OFST + ((_index) * _reg ## _STEP)),	\
911		    (_edp), (_lock));					\
912	_NOTE(CONSTANTCONDITION)					\
913	} while (B_FALSE)
914
915#define	EFX_BAR_TBL_WRITED2(_enp, _reg, _index, _edp, _lock)		\
916	do {								\
917		EFX_CHECK_REG((_enp), (_reg));				\
918		EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,	\
919		    uint32_t, (_index),					\
920		    uint32_t, _reg ## _OFST,				\
921		    uint32_t, (_edp)->ed_u32[0]);			\
922		EFSYS_BAR_WRITED((_enp)->en_esbp,			\
923		    (_reg ## _OFST +					\
924		    (2 * sizeof (efx_dword_t)) +			\
925		    ((_index) * _reg ## _STEP)),			\
926		    (_edp), (_lock));					\
927	_NOTE(CONSTANTCONDITION)					\
928	} while (B_FALSE)
929
930#define	EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock)		\
931	do {								\
932		EFX_CHECK_REG((_enp), (_reg));				\
933		EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,	\
934		    uint32_t, (_index),					\
935		    uint32_t, _reg ## _OFST,				\
936		    uint32_t, (_edp)->ed_u32[0]);			\
937		EFSYS_BAR_WRITED((_enp)->en_esbp,			\
938		    (_reg ## _OFST +					\
939		    (3 * sizeof (efx_dword_t)) +			\
940		    ((_index) * _reg ## _STEP)),			\
941		    (_edp), (_lock));					\
942	_NOTE(CONSTANTCONDITION)					\
943	} while (B_FALSE)
944
945#define	EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp)			\
946	do {								\
947		EFX_CHECK_REG((_enp), (_reg));				\
948		EFSYS_BAR_READQ((_enp)->en_esbp,			\
949		    (_reg ## _OFST + ((_index) * _reg ## _STEP)),	\
950		    (_eqp));						\
951		EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg,	\
952		    uint32_t, (_index),					\
953		    uint32_t, _reg ## _OFST,				\
954		    uint32_t, (_eqp)->eq_u32[1],			\
955		    uint32_t, (_eqp)->eq_u32[0]);			\
956	_NOTE(CONSTANTCONDITION)					\
957	} while (B_FALSE)
958
959#define	EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp)			\
960	do {								\
961		EFX_CHECK_REG((_enp), (_reg));				\
962		EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg,	\
963		    uint32_t, (_index),					\
964		    uint32_t, _reg ## _OFST,				\
965		    uint32_t, (_eqp)->eq_u32[1],			\
966		    uint32_t, (_eqp)->eq_u32[0]);			\
967		EFSYS_BAR_WRITEQ((_enp)->en_esbp,			\
968		    (_reg ## _OFST + ((_index) * _reg ## _STEP)),	\
969		    (_eqp));						\
970	_NOTE(CONSTANTCONDITION)					\
971	} while (B_FALSE)
972
973#define	EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock)		\
974	do {								\
975		EFX_CHECK_REG((_enp), (_reg));				\
976		EFSYS_BAR_READO((_enp)->en_esbp,			\
977		    (_reg ## _OFST + ((_index) * _reg ## _STEP)),	\
978		    (_eop), (_lock));					\
979		EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg,	\
980		    uint32_t, (_index),					\
981		    uint32_t, _reg ## _OFST,				\
982		    uint32_t, (_eop)->eo_u32[3],			\
983		    uint32_t, (_eop)->eo_u32[2],			\
984		    uint32_t, (_eop)->eo_u32[1],			\
985		    uint32_t, (_eop)->eo_u32[0]);			\
986	_NOTE(CONSTANTCONDITION)					\
987	} while (B_FALSE)
988
989#define	EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock)		\
990	do {								\
991		EFX_CHECK_REG((_enp), (_reg));				\
992		EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg,	\
993		    uint32_t, (_index),					\
994		    uint32_t, _reg ## _OFST,				\
995		    uint32_t, (_eop)->eo_u32[3],			\
996		    uint32_t, (_eop)->eo_u32[2],			\
997		    uint32_t, (_eop)->eo_u32[1],			\
998		    uint32_t, (_eop)->eo_u32[0]);			\
999		EFSYS_BAR_WRITEO((_enp)->en_esbp,			\
1000		    (_reg ## _OFST + ((_index) * _reg ## _STEP)),	\
1001		    (_eop), (_lock));					\
1002	_NOTE(CONSTANTCONDITION)					\
1003	} while (B_FALSE)
1004
1005/*
1006 * Allow drivers to perform optimised 128-bit doorbell writes.
1007 * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
1008 * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid
1009 * the need for locking in the host, and are the only ones known to be safe to
1010 * use 128-bites write with.
1011 */
1012#define	EFX_BAR_TBL_DOORBELL_WRITEO(_enp, _reg, _index, _eop)		\
1013	do {								\
1014		EFX_CHECK_REG((_enp), (_reg));				\
1015		EFSYS_PROBE7(efx_bar_tbl_doorbell_writeo,		\
1016		    const char *,					\
1017		    #_reg,						\
1018		    uint32_t, (_index),					\
1019		    uint32_t, _reg ## _OFST,				\
1020		    uint32_t, (_eop)->eo_u32[3],			\
1021		    uint32_t, (_eop)->eo_u32[2],			\
1022		    uint32_t, (_eop)->eo_u32[1],			\
1023		    uint32_t, (_eop)->eo_u32[0]);			\
1024		EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp,		\
1025		    (_reg ## _OFST + ((_index) * _reg ## _STEP)),	\
1026		    (_eop));						\
1027	_NOTE(CONSTANTCONDITION)					\
1028	} while (B_FALSE)
1029
1030#define	EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr)	\
1031	do {								\
1032		unsigned int _new = (_wptr);				\
1033		unsigned int _old = (_owptr);				\
1034									\
1035		if ((_new) >= (_old))					\
1036			EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),		\
1037			    (_old) * sizeof (efx_desc_t),		\
1038			    ((_new) - (_old)) * sizeof (efx_desc_t));	\
1039		else							\
1040			/*						\
1041			 * It is cheaper to sync entire map than sync	\
1042			 * two parts especially when offset/size are	\
1043			 * ignored and entire map is synced in any case.\
1044			 */						\
1045			EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),		\
1046			    0,						\
1047			    (_entries) * sizeof (efx_desc_t));		\
1048	_NOTE(CONSTANTCONDITION)					\
1049	} while (B_FALSE)
1050
1051extern	__checkReturn	efx_rc_t
1052efx_mac_select(
1053	__in		efx_nic_t *enp);
1054
1055extern	void
1056efx_mac_multicast_hash_compute(
1057	__in_ecount(6*count)		uint8_t const *addrs,
1058	__in				int count,
1059	__out				efx_oword_t *hash_low,
1060	__out				efx_oword_t *hash_high);
1061
1062extern	__checkReturn	efx_rc_t
1063efx_phy_probe(
1064	__in		efx_nic_t *enp);
1065
1066extern			void
1067efx_phy_unprobe(
1068	__in		efx_nic_t *enp);
1069
1070#if EFSYS_OPT_VPD
1071
1072/* VPD utility functions */
1073
1074extern	__checkReturn		efx_rc_t
1075efx_vpd_hunk_length(
1076	__in_bcount(size)	caddr_t data,
1077	__in			size_t size,
1078	__out			size_t *lengthp);
1079
1080extern	__checkReturn		efx_rc_t
1081efx_vpd_hunk_verify(
1082	__in_bcount(size)	caddr_t data,
1083	__in			size_t size,
1084	__out_opt		boolean_t *cksummedp);
1085
1086extern	__checkReturn		efx_rc_t
1087efx_vpd_hunk_reinit(
1088	__in_bcount(size)	caddr_t data,
1089	__in			size_t size,
1090	__in			boolean_t wantpid);
1091
1092extern	__checkReturn		efx_rc_t
1093efx_vpd_hunk_get(
1094	__in_bcount(size)	caddr_t data,
1095	__in			size_t size,
1096	__in			efx_vpd_tag_t tag,
1097	__in			efx_vpd_keyword_t keyword,
1098	__out			unsigned int *payloadp,
1099	__out			uint8_t *paylenp);
1100
1101extern	__checkReturn			efx_rc_t
1102efx_vpd_hunk_next(
1103	__in_bcount(size)		caddr_t data,
1104	__in				size_t size,
1105	__out				efx_vpd_tag_t *tagp,
1106	__out				efx_vpd_keyword_t *keyword,
1107	__out_opt			unsigned int *payloadp,
1108	__out_opt			uint8_t *paylenp,
1109	__inout				unsigned int *contp);
1110
1111extern	__checkReturn		efx_rc_t
1112efx_vpd_hunk_set(
1113	__in_bcount(size)	caddr_t data,
1114	__in			size_t size,
1115	__in			efx_vpd_value_t *evvp);
1116
1117#endif	/* EFSYS_OPT_VPD */
1118
1119#if EFSYS_OPT_MCDI
1120
1121extern	__checkReturn		efx_rc_t
1122efx_mcdi_set_workaround(
1123	__in			efx_nic_t *enp,
1124	__in			uint32_t type,
1125	__in			boolean_t enabled,
1126	__out_opt		uint32_t *flagsp);
1127
1128extern	__checkReturn		efx_rc_t
1129efx_mcdi_get_workarounds(
1130	__in			efx_nic_t *enp,
1131	__out_opt		uint32_t *implementedp,
1132	__out_opt		uint32_t *enabledp);
1133
1134#endif /* EFSYS_OPT_MCDI */
1135
1136#if EFSYS_OPT_MAC_STATS
1137
1138/*
1139 * Closed range of stats (i.e. the first and the last are included).
1140 * The last must be greater or equal (if the range is one item only) to
1141 * the first.
1142 */
1143struct efx_mac_stats_range {
1144	efx_mac_stat_t		first;
1145	efx_mac_stat_t		last;
1146};
1147
1148extern					efx_rc_t
1149efx_mac_stats_mask_add_ranges(
1150	__inout_bcount(mask_size)	uint32_t *maskp,
1151	__in				size_t mask_size,
1152	__in_ecount(rng_count)		const struct efx_mac_stats_range *rngp,
1153	__in				unsigned int rng_count);
1154
1155#endif	/* EFSYS_OPT_MAC_STATS */
1156
1157#ifdef	__cplusplus
1158}
1159#endif
1160
1161#endif	/* _SYS_EFX_IMPL_H */
1162