efx.h revision 350409 
1/*-
2 * Copyright (c) 2006-2016 Solarflare Communications Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,
9 *    this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 *    this list of conditions and the following disclaimer in the documentation
12 *    and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
29 *
30 * $FreeBSD: stable/11/sys/dev/sfxge/common/efx.h 350409 2019-07-29 10:41:21Z arybchik $
31 */
32
33#ifndef	_SYS_EFX_H
34#define	_SYS_EFX_H
35
36#include "efsys.h"
37#include "efx_check.h"
38#include "efx_phy_ids.h"
39
40#ifdef	__cplusplus
41extern "C" {
42#endif
43
44#define	EFX_STATIC_ASSERT(_cond)		\
45	((void)sizeof(char[(_cond) ? 1 : -1]))
46
47#define	EFX_ARRAY_SIZE(_array)			\
48	(sizeof(_array) / sizeof((_array)[0]))
49
50#define	EFX_FIELD_OFFSET(_type, _field)		\
51	((size_t) &(((_type *)0)->_field))
52
53/* Round value up to the nearest power of two. */
54#define	EFX_P2ROUNDUP(_type, _value, _align)	\
55	(-(-(_type)(_value) & -(_type)(_align)))
56
57/* Return codes */
58
59typedef __success(return == 0) int efx_rc_t;
60
61
62/* Chip families */
63
64typedef enum efx_family_e {
65	EFX_FAMILY_INVALID,
66	EFX_FAMILY_FALCON,	/* Obsolete and not supported */
67	EFX_FAMILY_SIENA,
68	EFX_FAMILY_HUNTINGTON,
69	EFX_FAMILY_MEDFORD,
70	EFX_FAMILY_NTYPES
71} efx_family_t;
72
73extern	__checkReturn	efx_rc_t
74efx_family(
75	__in		uint16_t venid,
76	__in		uint16_t devid,
77	__out		efx_family_t *efp);
78
79
80#define	EFX_PCI_VENID_SFC			0x1924
81
82#define	EFX_PCI_DEVID_FALCON			0x0710	/* SFC4000 */
83
84#define	EFX_PCI_DEVID_BETHPAGE			0x0803	/* SFC9020 */
85#define	EFX_PCI_DEVID_SIENA			0x0813	/* SFL9021 */
86#define	EFX_PCI_DEVID_SIENA_F1_UNINIT		0x0810
87
88#define	EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT	0x0901
89#define	EFX_PCI_DEVID_FARMINGDALE		0x0903	/* SFC9120 PF */
90#define	EFX_PCI_DEVID_GREENPORT			0x0923	/* SFC9140 PF */
91
92#define	EFX_PCI_DEVID_FARMINGDALE_VF		0x1903	/* SFC9120 VF */
93#define	EFX_PCI_DEVID_GREENPORT_VF		0x1923	/* SFC9140 VF */
94
95#define	EFX_PCI_DEVID_MEDFORD_PF_UNINIT		0x0913
96#define	EFX_PCI_DEVID_MEDFORD			0x0A03	/* SFC9240 PF */
97#define	EFX_PCI_DEVID_MEDFORD_VF		0x1A03	/* SFC9240 VF */
98
99#define	EFX_MEM_BAR	2
100
101/* Error codes */
102
103enum {
104	EFX_ERR_INVALID,
105	EFX_ERR_SRAM_OOB,
106	EFX_ERR_BUFID_DC_OOB,
107	EFX_ERR_MEM_PERR,
108	EFX_ERR_RBUF_OWN,
109	EFX_ERR_TBUF_OWN,
110	EFX_ERR_RDESQ_OWN,
111	EFX_ERR_TDESQ_OWN,
112	EFX_ERR_EVQ_OWN,
113	EFX_ERR_EVFF_OFLO,
114	EFX_ERR_ILL_ADDR,
115	EFX_ERR_SRAM_PERR,
116	EFX_ERR_NCODES
117};
118
119/* Calculate the IEEE 802.3 CRC32 of a MAC addr */
120extern	__checkReturn		uint32_t
121efx_crc32_calculate(
122	__in			uint32_t crc_init,
123	__in_ecount(length)	uint8_t const *input,
124	__in			int length);
125
126
127/* Type prototypes */
128
129typedef struct efx_rxq_s	efx_rxq_t;
130
131/* NIC */
132
133typedef struct efx_nic_s	efx_nic_t;
134
135extern	__checkReturn	efx_rc_t
136efx_nic_create(
137	__in		efx_family_t family,
138	__in		efsys_identifier_t *esip,
139	__in		efsys_bar_t *esbp,
140	__in		efsys_lock_t *eslp,
141	__deref_out	efx_nic_t **enpp);
142
143extern	__checkReturn	efx_rc_t
144efx_nic_probe(
145	__in		efx_nic_t *enp);
146
147extern	__checkReturn	efx_rc_t
148efx_nic_init(
149	__in		efx_nic_t *enp);
150
151extern	__checkReturn	efx_rc_t
152efx_nic_reset(
153	__in		efx_nic_t *enp);
154
155#if EFSYS_OPT_DIAG
156
157extern	__checkReturn	efx_rc_t
158efx_nic_register_test(
159	__in		efx_nic_t *enp);
160
161#endif	/* EFSYS_OPT_DIAG */
162
163extern		void
164efx_nic_fini(
165	__in		efx_nic_t *enp);
166
167extern		void
168efx_nic_unprobe(
169	__in		efx_nic_t *enp);
170
171extern		void
172efx_nic_destroy(
173	__in	efx_nic_t *enp);
174
175#define	EFX_PCIE_LINK_SPEED_GEN1		1
176#define	EFX_PCIE_LINK_SPEED_GEN2		2
177#define	EFX_PCIE_LINK_SPEED_GEN3		3
178
179typedef enum efx_pcie_link_performance_e {
180	EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH,
181	EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH,
182	EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY,
183	EFX_PCIE_LINK_PERFORMANCE_OPTIMAL
184} efx_pcie_link_performance_t;
185
186extern	__checkReturn	efx_rc_t
187efx_nic_calculate_pcie_link_bandwidth(
188	__in		uint32_t pcie_link_width,
189	__in		uint32_t pcie_link_gen,
190	__out		uint32_t *bandwidth_mbpsp);
191
192extern	__checkReturn	efx_rc_t
193efx_nic_check_pcie_link_speed(
194	__in		efx_nic_t *enp,
195	__in		uint32_t pcie_link_width,
196	__in		uint32_t pcie_link_gen,
197	__out		efx_pcie_link_performance_t *resultp);
198
199#if EFSYS_OPT_MCDI
200
201#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
202/* Huntington and Medford require MCDIv2 commands */
203#define	WITH_MCDI_V2 1
204#endif
205
206typedef struct efx_mcdi_req_s efx_mcdi_req_t;
207
208typedef enum efx_mcdi_exception_e {
209	EFX_MCDI_EXCEPTION_MC_REBOOT,
210	EFX_MCDI_EXCEPTION_MC_BADASSERT,
211} efx_mcdi_exception_t;
212
213#if EFSYS_OPT_MCDI_LOGGING
214typedef enum efx_log_msg_e {
215	EFX_LOG_INVALID,
216	EFX_LOG_MCDI_REQUEST,
217	EFX_LOG_MCDI_RESPONSE,
218} efx_log_msg_t;
219#endif /* EFSYS_OPT_MCDI_LOGGING */
220
221typedef struct efx_mcdi_transport_s {
222	void		*emt_context;
223	efsys_mem_t	*emt_dma_mem;
224	void		(*emt_execute)(void *, efx_mcdi_req_t *);
225	void		(*emt_ev_cpl)(void *);
226	void		(*emt_exception)(void *, efx_mcdi_exception_t);
227#if EFSYS_OPT_MCDI_LOGGING
228	void		(*emt_logger)(void *, efx_log_msg_t,
229					void *, size_t, void *, size_t);
230#endif /* EFSYS_OPT_MCDI_LOGGING */
231#if EFSYS_OPT_MCDI_PROXY_AUTH
232	void		(*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t);
233#endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
234} efx_mcdi_transport_t;
235
236extern	__checkReturn	efx_rc_t
237efx_mcdi_init(
238	__in		efx_nic_t *enp,
239	__in		const efx_mcdi_transport_t *mtp);
240
241extern	__checkReturn	efx_rc_t
242efx_mcdi_reboot(
243	__in		efx_nic_t *enp);
244
245			void
246efx_mcdi_new_epoch(
247	__in		efx_nic_t *enp);
248
249extern			void
250efx_mcdi_get_timeout(
251	__in		efx_nic_t *enp,
252	__in		efx_mcdi_req_t *emrp,
253	__out		uint32_t *usec_timeoutp);
254
255extern			void
256efx_mcdi_request_start(
257	__in		efx_nic_t *enp,
258	__in		efx_mcdi_req_t *emrp,
259	__in		boolean_t ev_cpl);
260
261extern	__checkReturn	boolean_t
262efx_mcdi_request_poll(
263	__in		efx_nic_t *enp);
264
265extern	__checkReturn	boolean_t
266efx_mcdi_request_abort(
267	__in		efx_nic_t *enp);
268
269extern			void
270efx_mcdi_fini(
271	__in		efx_nic_t *enp);
272
273#endif	/* EFSYS_OPT_MCDI */
274
275/* INTR */
276
277#define	EFX_NINTR_SIENA 1024
278
279typedef enum efx_intr_type_e {
280	EFX_INTR_INVALID = 0,
281	EFX_INTR_LINE,
282	EFX_INTR_MESSAGE,
283	EFX_INTR_NTYPES
284} efx_intr_type_t;
285
286#define	EFX_INTR_SIZE	(sizeof (efx_oword_t))
287
288extern	__checkReturn	efx_rc_t
289efx_intr_init(
290	__in		efx_nic_t *enp,
291	__in		efx_intr_type_t type,
292	__in		efsys_mem_t *esmp);
293
294extern			void
295efx_intr_enable(
296	__in		efx_nic_t *enp);
297
298extern			void
299efx_intr_disable(
300	__in		efx_nic_t *enp);
301
302extern			void
303efx_intr_disable_unlocked(
304	__in		efx_nic_t *enp);
305
306#define	EFX_INTR_NEVQS	32
307
308extern	__checkReturn	efx_rc_t
309efx_intr_trigger(
310	__in		efx_nic_t *enp,
311	__in		unsigned int level);
312
313extern			void
314efx_intr_status_line(
315	__in		efx_nic_t *enp,
316	__out		boolean_t *fatalp,
317	__out		uint32_t *maskp);
318
319extern			void
320efx_intr_status_message(
321	__in		efx_nic_t *enp,
322	__in		unsigned int message,
323	__out		boolean_t *fatalp);
324
325extern			void
326efx_intr_fatal(
327	__in		efx_nic_t *enp);
328
329extern			void
330efx_intr_fini(
331	__in		efx_nic_t *enp);
332
333/* MAC */
334
335#if EFSYS_OPT_MAC_STATS
336
337/* START MKCONFIG GENERATED EfxHeaderMacBlock e323546097fd7c65 */
338typedef enum efx_mac_stat_e {
339	EFX_MAC_RX_OCTETS,
340	EFX_MAC_RX_PKTS,
341	EFX_MAC_RX_UNICST_PKTS,
342	EFX_MAC_RX_MULTICST_PKTS,
343	EFX_MAC_RX_BRDCST_PKTS,
344	EFX_MAC_RX_PAUSE_PKTS,
345	EFX_MAC_RX_LE_64_PKTS,
346	EFX_MAC_RX_65_TO_127_PKTS,
347	EFX_MAC_RX_128_TO_255_PKTS,
348	EFX_MAC_RX_256_TO_511_PKTS,
349	EFX_MAC_RX_512_TO_1023_PKTS,
350	EFX_MAC_RX_1024_TO_15XX_PKTS,
351	EFX_MAC_RX_GE_15XX_PKTS,
352	EFX_MAC_RX_ERRORS,
353	EFX_MAC_RX_FCS_ERRORS,
354	EFX_MAC_RX_DROP_EVENTS,
355	EFX_MAC_RX_FALSE_CARRIER_ERRORS,
356	EFX_MAC_RX_SYMBOL_ERRORS,
357	EFX_MAC_RX_ALIGN_ERRORS,
358	EFX_MAC_RX_INTERNAL_ERRORS,
359	EFX_MAC_RX_JABBER_PKTS,
360	EFX_MAC_RX_LANE0_CHAR_ERR,
361	EFX_MAC_RX_LANE1_CHAR_ERR,
362	EFX_MAC_RX_LANE2_CHAR_ERR,
363	EFX_MAC_RX_LANE3_CHAR_ERR,
364	EFX_MAC_RX_LANE0_DISP_ERR,
365	EFX_MAC_RX_LANE1_DISP_ERR,
366	EFX_MAC_RX_LANE2_DISP_ERR,
367	EFX_MAC_RX_LANE3_DISP_ERR,
368	EFX_MAC_RX_MATCH_FAULT,
369	EFX_MAC_RX_NODESC_DROP_CNT,
370	EFX_MAC_TX_OCTETS,
371	EFX_MAC_TX_PKTS,
372	EFX_MAC_TX_UNICST_PKTS,
373	EFX_MAC_TX_MULTICST_PKTS,
374	EFX_MAC_TX_BRDCST_PKTS,
375	EFX_MAC_TX_PAUSE_PKTS,
376	EFX_MAC_TX_LE_64_PKTS,
377	EFX_MAC_TX_65_TO_127_PKTS,
378	EFX_MAC_TX_128_TO_255_PKTS,
379	EFX_MAC_TX_256_TO_511_PKTS,
380	EFX_MAC_TX_512_TO_1023_PKTS,
381	EFX_MAC_TX_1024_TO_15XX_PKTS,
382	EFX_MAC_TX_GE_15XX_PKTS,
383	EFX_MAC_TX_ERRORS,
384	EFX_MAC_TX_SGL_COL_PKTS,
385	EFX_MAC_TX_MULT_COL_PKTS,
386	EFX_MAC_TX_EX_COL_PKTS,
387	EFX_MAC_TX_LATE_COL_PKTS,
388	EFX_MAC_TX_DEF_PKTS,
389	EFX_MAC_TX_EX_DEF_PKTS,
390	EFX_MAC_PM_TRUNC_BB_OVERFLOW,
391	EFX_MAC_PM_DISCARD_BB_OVERFLOW,
392	EFX_MAC_PM_TRUNC_VFIFO_FULL,
393	EFX_MAC_PM_DISCARD_VFIFO_FULL,
394	EFX_MAC_PM_TRUNC_QBB,
395	EFX_MAC_PM_DISCARD_QBB,
396	EFX_MAC_PM_DISCARD_MAPPING,
397	EFX_MAC_RXDP_Q_DISABLED_PKTS,
398	EFX_MAC_RXDP_DI_DROPPED_PKTS,
399	EFX_MAC_RXDP_STREAMING_PKTS,
400	EFX_MAC_RXDP_HLB_FETCH,
401	EFX_MAC_RXDP_HLB_WAIT,
402	EFX_MAC_VADAPTER_RX_UNICAST_PACKETS,
403	EFX_MAC_VADAPTER_RX_UNICAST_BYTES,
404	EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS,
405	EFX_MAC_VADAPTER_RX_MULTICAST_BYTES,
406	EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS,
407	EFX_MAC_VADAPTER_RX_BROADCAST_BYTES,
408	EFX_MAC_VADAPTER_RX_BAD_PACKETS,
409	EFX_MAC_VADAPTER_RX_BAD_BYTES,
410	EFX_MAC_VADAPTER_RX_OVERFLOW,
411	EFX_MAC_VADAPTER_TX_UNICAST_PACKETS,
412	EFX_MAC_VADAPTER_TX_UNICAST_BYTES,
413	EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS,
414	EFX_MAC_VADAPTER_TX_MULTICAST_BYTES,
415	EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS,
416	EFX_MAC_VADAPTER_TX_BROADCAST_BYTES,
417	EFX_MAC_VADAPTER_TX_BAD_PACKETS,
418	EFX_MAC_VADAPTER_TX_BAD_BYTES,
419	EFX_MAC_VADAPTER_TX_OVERFLOW,
420	EFX_MAC_NSTATS
421} efx_mac_stat_t;
422
423/* END MKCONFIG GENERATED EfxHeaderMacBlock */
424
425#endif	/* EFSYS_OPT_MAC_STATS */
426
427typedef enum efx_link_mode_e {
428	EFX_LINK_UNKNOWN = 0,
429	EFX_LINK_DOWN,
430	EFX_LINK_10HDX,
431	EFX_LINK_10FDX,
432	EFX_LINK_100HDX,
433	EFX_LINK_100FDX,
434	EFX_LINK_1000HDX,
435	EFX_LINK_1000FDX,
436	EFX_LINK_10000FDX,
437	EFX_LINK_40000FDX,
438	EFX_LINK_NMODES
439} efx_link_mode_t;
440
441#define	EFX_MAC_ADDR_LEN 6
442
443#define	EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t *)_address)[0] & 0x01)
444
445#define	EFX_MAC_MULTICAST_LIST_MAX	256
446
447#define	EFX_MAC_SDU_MAX	9202
448
449#define	EFX_MAC_PDU_ADJUSTMENT					\
450	(/* EtherII */ 14					\
451	    + /* VLAN */ 4					\
452	    + /* CRC */ 4					\
453	    + /* bug16011 */ 16)				\
454
455#define	EFX_MAC_PDU(_sdu)					\
456	EFX_P2ROUNDUP(size_t, (_sdu) + EFX_MAC_PDU_ADJUSTMENT, 8)
457
458/*
459 * Due to the EFX_P2ROUNDUP in EFX_MAC_PDU(), EFX_MAC_SDU_FROM_PDU() may give
460 * the SDU rounded up slightly.
461 */
462#define	EFX_MAC_SDU_FROM_PDU(_pdu)	((_pdu) - EFX_MAC_PDU_ADJUSTMENT)
463
464#define	EFX_MAC_PDU_MIN	60
465#define	EFX_MAC_PDU_MAX	EFX_MAC_PDU(EFX_MAC_SDU_MAX)
466
467extern	__checkReturn	efx_rc_t
468efx_mac_pdu_get(
469	__in		efx_nic_t *enp,
470	__out		size_t *pdu);
471
472extern	__checkReturn	efx_rc_t
473efx_mac_pdu_set(
474	__in		efx_nic_t *enp,
475	__in		size_t pdu);
476
477extern	__checkReturn	efx_rc_t
478efx_mac_addr_set(
479	__in		efx_nic_t *enp,
480	__in		uint8_t *addr);
481
482extern	__checkReturn			efx_rc_t
483efx_mac_filter_set(
484	__in				efx_nic_t *enp,
485	__in				boolean_t all_unicst,
486	__in				boolean_t mulcst,
487	__in				boolean_t all_mulcst,
488	__in				boolean_t brdcst);
489
490extern	__checkReturn	efx_rc_t
491efx_mac_multicast_list_set(
492	__in				efx_nic_t *enp,
493	__in_ecount(6*count)		uint8_t const *addrs,
494	__in				int count);
495
496extern	__checkReturn	efx_rc_t
497efx_mac_filter_default_rxq_set(
498	__in		efx_nic_t *enp,
499	__in		efx_rxq_t *erp,
500	__in		boolean_t using_rss);
501
502extern			void
503efx_mac_filter_default_rxq_clear(
504	__in		efx_nic_t *enp);
505
506extern	__checkReturn	efx_rc_t
507efx_mac_drain(
508	__in		efx_nic_t *enp,
509	__in		boolean_t enabled);
510
511extern	__checkReturn	efx_rc_t
512efx_mac_up(
513	__in		efx_nic_t *enp,
514	__out		boolean_t *mac_upp);
515
516#define	EFX_FCNTL_RESPOND	0x00000001
517#define	EFX_FCNTL_GENERATE	0x00000002
518
519extern	__checkReturn	efx_rc_t
520efx_mac_fcntl_set(
521	__in		efx_nic_t *enp,
522	__in		unsigned int fcntl,
523	__in		boolean_t autoneg);
524
525extern			void
526efx_mac_fcntl_get(
527	__in		efx_nic_t *enp,
528	__out		unsigned int *fcntl_wantedp,
529	__out		unsigned int *fcntl_linkp);
530
531
532#if EFSYS_OPT_MAC_STATS
533
534#if EFSYS_OPT_NAMES
535
536extern	__checkReturn			const char *
537efx_mac_stat_name(
538	__in				efx_nic_t *enp,
539	__in				unsigned int id);
540
541#endif	/* EFSYS_OPT_NAMES */
542
543#define	EFX_MAC_STATS_MASK_BITS_PER_PAGE	(8 * sizeof (uint32_t))
544
545#define	EFX_MAC_STATS_MASK_NPAGES				\
546	(EFX_P2ROUNDUP(uint32_t, EFX_MAC_NSTATS,		\
547		       EFX_MAC_STATS_MASK_BITS_PER_PAGE) /	\
548	    EFX_MAC_STATS_MASK_BITS_PER_PAGE)
549
550/*
551 * Get mask of MAC statistics supported by the hardware.
552 *
553 * If mask_size is insufficient to return the mask, EINVAL error is
554 * returned. EFX_MAC_STATS_MASK_NPAGES multiplied by size of the page
555 * (which is sizeof (uint32_t)) is sufficient.
556 */
557extern	__checkReturn			efx_rc_t
558efx_mac_stats_get_mask(
559	__in				efx_nic_t *enp,
560	__out_bcount(mask_size)		uint32_t *maskp,
561	__in				size_t mask_size);
562
563#define	EFX_MAC_STAT_SUPPORTED(_mask, _stat)	\
564	((_mask)[(_stat) / EFX_MAC_STATS_MASK_BITS_PER_PAGE] &	\
565	 (1ULL << ((_stat) & (EFX_MAC_STATS_MASK_BITS_PER_PAGE - 1))))
566
567#define	EFX_MAC_STATS_SIZE 0x400
568
569/*
570 * Upload mac statistics supported by the hardware into the given buffer.
571 *
572 * The reference buffer must be at least %EFX_MAC_STATS_SIZE bytes,
573 * and page aligned.
574 *
575 * The hardware will only DMA statistics that it understands (of course).
576 * Drivers should not make any assumptions about which statistics are
577 * supported, especially when the statistics are generated by firmware.
578 *
579 * Thus, drivers should zero this buffer before use, so that not-understood
580 * statistics read back as zero.
581 */
582extern	__checkReturn			efx_rc_t
583efx_mac_stats_upload(
584	__in				efx_nic_t *enp,
585	__in				efsys_mem_t *esmp);
586
587extern	__checkReturn			efx_rc_t
588efx_mac_stats_periodic(
589	__in				efx_nic_t *enp,
590	__in				efsys_mem_t *esmp,
591	__in				uint16_t period_ms,
592	__in				boolean_t events);
593
594extern	__checkReturn			efx_rc_t
595efx_mac_stats_update(
596	__in				efx_nic_t *enp,
597	__in				efsys_mem_t *esmp,
598	__inout_ecount(EFX_MAC_NSTATS)	efsys_stat_t *stat,
599	__inout_opt			uint32_t *generationp);
600
601#endif	/* EFSYS_OPT_MAC_STATS */
602
603/* MON */
604
605typedef enum efx_mon_type_e {
606	EFX_MON_INVALID = 0,
607	EFX_MON_SFC90X0,
608	EFX_MON_SFC91X0,
609	EFX_MON_SFC92X0,
610	EFX_MON_NTYPES
611} efx_mon_type_t;
612
613#if EFSYS_OPT_NAMES
614
615extern		const char *
616efx_mon_name(
617	__in	efx_nic_t *enp);
618
619#endif	/* EFSYS_OPT_NAMES */
620
621extern	__checkReturn	efx_rc_t
622efx_mon_init(
623	__in		efx_nic_t *enp);
624
625#if EFSYS_OPT_MON_STATS
626
627#define	EFX_MON_STATS_PAGE_SIZE 0x100
628#define	EFX_MON_MASK_ELEMENT_SIZE 32
629
630/* START MKCONFIG GENERATED MonitorHeaderStatsBlock 5d4ee5185e419abe */
631typedef enum efx_mon_stat_e {
632	EFX_MON_STAT_2_5V,
633	EFX_MON_STAT_VCCP1,
634	EFX_MON_STAT_VCC,
635	EFX_MON_STAT_5V,
636	EFX_MON_STAT_12V,
637	EFX_MON_STAT_VCCP2,
638	EFX_MON_STAT_EXT_TEMP,
639	EFX_MON_STAT_INT_TEMP,
640	EFX_MON_STAT_AIN1,
641	EFX_MON_STAT_AIN2,
642	EFX_MON_STAT_INT_COOLING,
643	EFX_MON_STAT_EXT_COOLING,
644	EFX_MON_STAT_1V,
645	EFX_MON_STAT_1_2V,
646	EFX_MON_STAT_1_8V,
647	EFX_MON_STAT_3_3V,
648	EFX_MON_STAT_1_2VA,
649	EFX_MON_STAT_VREF,
650	EFX_MON_STAT_VAOE,
651	EFX_MON_STAT_AOE_TEMP,
652	EFX_MON_STAT_PSU_AOE_TEMP,
653	EFX_MON_STAT_PSU_TEMP,
654	EFX_MON_STAT_FAN0,
655	EFX_MON_STAT_FAN1,
656	EFX_MON_STAT_FAN2,
657	EFX_MON_STAT_FAN3,
658	EFX_MON_STAT_FAN4,
659	EFX_MON_STAT_VAOE_IN,
660	EFX_MON_STAT_IAOE,
661	EFX_MON_STAT_IAOE_IN,
662	EFX_MON_STAT_NIC_POWER,
663	EFX_MON_STAT_0_9V,
664	EFX_MON_STAT_I0_9V,
665	EFX_MON_STAT_I1_2V,
666	EFX_MON_STAT_0_9V_ADC,
667	EFX_MON_STAT_INT_TEMP2,
668	EFX_MON_STAT_VREG_TEMP,
669	EFX_MON_STAT_VREG_0_9V_TEMP,
670	EFX_MON_STAT_VREG_1_2V_TEMP,
671	EFX_MON_STAT_INT_VPTAT,
672	EFX_MON_STAT_INT_ADC_TEMP,
673	EFX_MON_STAT_EXT_VPTAT,
674	EFX_MON_STAT_EXT_ADC_TEMP,
675	EFX_MON_STAT_AMBIENT_TEMP,
676	EFX_MON_STAT_AIRFLOW,
677	EFX_MON_STAT_VDD08D_VSS08D_CSR,
678	EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC,
679	EFX_MON_STAT_HOTPOINT_TEMP,
680	EFX_MON_STAT_PHY_POWER_SWITCH_PORT0,
681	EFX_MON_STAT_PHY_POWER_SWITCH_PORT1,
682	EFX_MON_STAT_MUM_VCC,
683	EFX_MON_STAT_0V9_A,
684	EFX_MON_STAT_I0V9_A,
685	EFX_MON_STAT_0V9_A_TEMP,
686	EFX_MON_STAT_0V9_B,
687	EFX_MON_STAT_I0V9_B,
688	EFX_MON_STAT_0V9_B_TEMP,
689	EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY,
690	EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXT_ADC,
691	EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY,
692	EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXT_ADC,
693	EFX_MON_STAT_CONTROLLER_MASTER_VPTAT,
694	EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP,
695	EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXT_ADC,
696	EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXT_ADC,
697	EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT,
698	EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP,
699	EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXT_ADC,
700	EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXT_ADC,
701	EFX_MON_STAT_SODIMM_VOUT,
702	EFX_MON_STAT_SODIMM_0_TEMP,
703	EFX_MON_STAT_SODIMM_1_TEMP,
704	EFX_MON_STAT_PHY0_VCC,
705	EFX_MON_STAT_PHY1_VCC,
706	EFX_MON_STAT_CONTROLLER_TDIODE_TEMP,
707	EFX_MON_STAT_BOARD_FRONT_TEMP,
708	EFX_MON_STAT_BOARD_BACK_TEMP,
709	EFX_MON_NSTATS
710} efx_mon_stat_t;
711
712/* END MKCONFIG GENERATED MonitorHeaderStatsBlock */
713
714typedef enum efx_mon_stat_state_e {
715	EFX_MON_STAT_STATE_OK = 0,
716	EFX_MON_STAT_STATE_WARNING = 1,
717	EFX_MON_STAT_STATE_FATAL = 2,
718	EFX_MON_STAT_STATE_BROKEN = 3,
719	EFX_MON_STAT_STATE_NO_READING = 4,
720} efx_mon_stat_state_t;
721
722typedef struct efx_mon_stat_value_s {
723	uint16_t	emsv_value;
724	uint16_t	emsv_state;
725} efx_mon_stat_value_t;
726
727#if EFSYS_OPT_NAMES
728
729extern					const char *
730efx_mon_stat_name(
731	__in				efx_nic_t *enp,
732	__in				efx_mon_stat_t id);
733
734#endif	/* EFSYS_OPT_NAMES */
735
736extern	__checkReturn			efx_rc_t
737efx_mon_stats_update(
738	__in				efx_nic_t *enp,
739	__in				efsys_mem_t *esmp,
740	__inout_ecount(EFX_MON_NSTATS)	efx_mon_stat_value_t *values);
741
742#endif	/* EFSYS_OPT_MON_STATS */
743
744extern		void
745efx_mon_fini(
746	__in	efx_nic_t *enp);
747
748/* PHY */
749
750extern	__checkReturn	efx_rc_t
751efx_phy_verify(
752	__in		efx_nic_t *enp);
753
754#if EFSYS_OPT_PHY_LED_CONTROL
755
756typedef enum efx_phy_led_mode_e {
757	EFX_PHY_LED_DEFAULT = 0,
758	EFX_PHY_LED_OFF,
759	EFX_PHY_LED_ON,
760	EFX_PHY_LED_FLASH,
761	EFX_PHY_LED_NMODES
762} efx_phy_led_mode_t;
763
764extern	__checkReturn	efx_rc_t
765efx_phy_led_set(
766	__in	efx_nic_t *enp,
767	__in	efx_phy_led_mode_t mode);
768
769#endif	/* EFSYS_OPT_PHY_LED_CONTROL */
770
771extern	__checkReturn	efx_rc_t
772efx_port_init(
773	__in		efx_nic_t *enp);
774
775#if EFSYS_OPT_LOOPBACK
776
777typedef enum efx_loopback_type_e {
778	EFX_LOOPBACK_OFF = 0,
779	EFX_LOOPBACK_DATA = 1,
780	EFX_LOOPBACK_GMAC = 2,
781	EFX_LOOPBACK_XGMII = 3,
782	EFX_LOOPBACK_XGXS = 4,
783	EFX_LOOPBACK_XAUI = 5,
784	EFX_LOOPBACK_GMII = 6,
785	EFX_LOOPBACK_SGMII = 7,
786	EFX_LOOPBACK_XGBR = 8,
787	EFX_LOOPBACK_XFI = 9,
788	EFX_LOOPBACK_XAUI_FAR = 10,
789	EFX_LOOPBACK_GMII_FAR = 11,
790	EFX_LOOPBACK_SGMII_FAR = 12,
791	EFX_LOOPBACK_XFI_FAR = 13,
792	EFX_LOOPBACK_GPHY = 14,
793	EFX_LOOPBACK_PHY_XS = 15,
794	EFX_LOOPBACK_PCS = 16,
795	EFX_LOOPBACK_PMA_PMD = 17,
796	EFX_LOOPBACK_XPORT = 18,
797	EFX_LOOPBACK_XGMII_WS = 19,
798	EFX_LOOPBACK_XAUI_WS = 20,
799	EFX_LOOPBACK_XAUI_WS_FAR = 21,
800	EFX_LOOPBACK_XAUI_WS_NEAR = 22,
801	EFX_LOOPBACK_GMII_WS = 23,
802	EFX_LOOPBACK_XFI_WS = 24,
803	EFX_LOOPBACK_XFI_WS_FAR = 25,
804	EFX_LOOPBACK_PHYXS_WS = 26,
805	EFX_LOOPBACK_PMA_INT = 27,
806	EFX_LOOPBACK_SD_NEAR = 28,
807	EFX_LOOPBACK_SD_FAR = 29,
808	EFX_LOOPBACK_PMA_INT_WS = 30,
809	EFX_LOOPBACK_SD_FEP2_WS = 31,
810	EFX_LOOPBACK_SD_FEP1_5_WS = 32,
811	EFX_LOOPBACK_SD_FEP_WS = 33,
812	EFX_LOOPBACK_SD_FES_WS = 34,
813	EFX_LOOPBACK_NTYPES
814} efx_loopback_type_t;
815
816typedef enum efx_loopback_kind_e {
817	EFX_LOOPBACK_KIND_OFF = 0,
818	EFX_LOOPBACK_KIND_ALL,
819	EFX_LOOPBACK_KIND_MAC,
820	EFX_LOOPBACK_KIND_PHY,
821	EFX_LOOPBACK_NKINDS
822} efx_loopback_kind_t;
823
824extern			void
825efx_loopback_mask(
826	__in	efx_loopback_kind_t loopback_kind,
827	__out	efx_qword_t *maskp);
828
829extern	__checkReturn	efx_rc_t
830efx_port_loopback_set(
831	__in	efx_nic_t *enp,
832	__in	efx_link_mode_t link_mode,
833	__in	efx_loopback_type_t type);
834
835#if EFSYS_OPT_NAMES
836
837extern	__checkReturn	const char *
838efx_loopback_type_name(
839	__in		efx_nic_t *enp,
840	__in		efx_loopback_type_t type);
841
842#endif	/* EFSYS_OPT_NAMES */
843
844#endif	/* EFSYS_OPT_LOOPBACK */
845
846extern	__checkReturn	efx_rc_t
847efx_port_poll(
848	__in		efx_nic_t *enp,
849	__out_opt	efx_link_mode_t	*link_modep);
850
851extern		void
852efx_port_fini(
853	__in	efx_nic_t *enp);
854
855typedef enum efx_phy_cap_type_e {
856	EFX_PHY_CAP_INVALID = 0,
857	EFX_PHY_CAP_10HDX,
858	EFX_PHY_CAP_10FDX,
859	EFX_PHY_CAP_100HDX,
860	EFX_PHY_CAP_100FDX,
861	EFX_PHY_CAP_1000HDX,
862	EFX_PHY_CAP_1000FDX,
863	EFX_PHY_CAP_10000FDX,
864	EFX_PHY_CAP_PAUSE,
865	EFX_PHY_CAP_ASYM,
866	EFX_PHY_CAP_AN,
867	EFX_PHY_CAP_40000FDX,
868	EFX_PHY_CAP_NTYPES
869} efx_phy_cap_type_t;
870
871
872#define	EFX_PHY_CAP_CURRENT	0x00000000
873#define	EFX_PHY_CAP_DEFAULT	0x00000001
874#define	EFX_PHY_CAP_PERM	0x00000002
875
876extern		void
877efx_phy_adv_cap_get(
878	__in		efx_nic_t *enp,
879	__in		uint32_t flag,
880	__out		uint32_t *maskp);
881
882extern	__checkReturn	efx_rc_t
883efx_phy_adv_cap_set(
884	__in		efx_nic_t *enp,
885	__in		uint32_t mask);
886
887extern			void
888efx_phy_lp_cap_get(
889	__in		efx_nic_t *enp,
890	__out		uint32_t *maskp);
891
892extern	__checkReturn	efx_rc_t
893efx_phy_oui_get(
894	__in		efx_nic_t *enp,
895	__out		uint32_t *ouip);
896
897typedef enum efx_phy_media_type_e {
898	EFX_PHY_MEDIA_INVALID = 0,
899	EFX_PHY_MEDIA_XAUI,
900	EFX_PHY_MEDIA_CX4,
901	EFX_PHY_MEDIA_KX4,
902	EFX_PHY_MEDIA_XFP,
903	EFX_PHY_MEDIA_SFP_PLUS,
904	EFX_PHY_MEDIA_BASE_T,
905	EFX_PHY_MEDIA_QSFP_PLUS,
906	EFX_PHY_MEDIA_NTYPES
907} efx_phy_media_type_t;
908
909/* Get the type of medium currently used.  If the board has ports for
910 * modules, a module is present, and we recognise the media type of
911 * the module, then this will be the media type of the module.
912 * Otherwise it will be the media type of the port.
913 */
914extern			void
915efx_phy_media_type_get(
916	__in		efx_nic_t *enp,
917	__out		efx_phy_media_type_t *typep);
918
919extern	__checkReturn		efx_rc_t
920efx_phy_module_get_info(
921	__in			efx_nic_t *enp,
922	__in			uint8_t dev_addr,
923	__in			uint8_t offset,
924	__in			uint8_t len,
925	__out_bcount(len)	uint8_t *data);
926
927#if EFSYS_OPT_PHY_STATS
928
929/* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */
930typedef enum efx_phy_stat_e {
931	EFX_PHY_STAT_OUI,
932	EFX_PHY_STAT_PMA_PMD_LINK_UP,
933	EFX_PHY_STAT_PMA_PMD_RX_FAULT,
934	EFX_PHY_STAT_PMA_PMD_TX_FAULT,
935	EFX_PHY_STAT_PMA_PMD_REV_A,
936	EFX_PHY_STAT_PMA_PMD_REV_B,
937	EFX_PHY_STAT_PMA_PMD_REV_C,
938	EFX_PHY_STAT_PMA_PMD_REV_D,
939	EFX_PHY_STAT_PCS_LINK_UP,
940	EFX_PHY_STAT_PCS_RX_FAULT,
941	EFX_PHY_STAT_PCS_TX_FAULT,
942	EFX_PHY_STAT_PCS_BER,
943	EFX_PHY_STAT_PCS_BLOCK_ERRORS,
944	EFX_PHY_STAT_PHY_XS_LINK_UP,
945	EFX_PHY_STAT_PHY_XS_RX_FAULT,
946	EFX_PHY_STAT_PHY_XS_TX_FAULT,
947	EFX_PHY_STAT_PHY_XS_ALIGN,
948	EFX_PHY_STAT_PHY_XS_SYNC_A,
949	EFX_PHY_STAT_PHY_XS_SYNC_B,
950	EFX_PHY_STAT_PHY_XS_SYNC_C,
951	EFX_PHY_STAT_PHY_XS_SYNC_D,
952	EFX_PHY_STAT_AN_LINK_UP,
953	EFX_PHY_STAT_AN_MASTER,
954	EFX_PHY_STAT_AN_LOCAL_RX_OK,
955	EFX_PHY_STAT_AN_REMOTE_RX_OK,
956	EFX_PHY_STAT_CL22EXT_LINK_UP,
957	EFX_PHY_STAT_SNR_A,
958	EFX_PHY_STAT_SNR_B,
959	EFX_PHY_STAT_SNR_C,
960	EFX_PHY_STAT_SNR_D,
961	EFX_PHY_STAT_PMA_PMD_SIGNAL_A,
962	EFX_PHY_STAT_PMA_PMD_SIGNAL_B,
963	EFX_PHY_STAT_PMA_PMD_SIGNAL_C,
964	EFX_PHY_STAT_PMA_PMD_SIGNAL_D,
965	EFX_PHY_STAT_AN_COMPLETE,
966	EFX_PHY_STAT_PMA_PMD_REV_MAJOR,
967	EFX_PHY_STAT_PMA_PMD_REV_MINOR,
968	EFX_PHY_STAT_PMA_PMD_REV_MICRO,
969	EFX_PHY_STAT_PCS_FW_VERSION_0,
970	EFX_PHY_STAT_PCS_FW_VERSION_1,
971	EFX_PHY_STAT_PCS_FW_VERSION_2,
972	EFX_PHY_STAT_PCS_FW_VERSION_3,
973	EFX_PHY_STAT_PCS_FW_BUILD_YY,
974	EFX_PHY_STAT_PCS_FW_BUILD_MM,
975	EFX_PHY_STAT_PCS_FW_BUILD_DD,
976	EFX_PHY_STAT_PCS_OP_MODE,
977	EFX_PHY_NSTATS
978} efx_phy_stat_t;
979
980/* END MKCONFIG GENERATED PhyHeaderStatsBlock */
981
982#if EFSYS_OPT_NAMES
983
984extern					const char *
985efx_phy_stat_name(
986	__in				efx_nic_t *enp,
987	__in				efx_phy_stat_t stat);
988
989#endif	/* EFSYS_OPT_NAMES */
990
991#define	EFX_PHY_STATS_SIZE 0x100
992
993extern	__checkReturn			efx_rc_t
994efx_phy_stats_update(
995	__in				efx_nic_t *enp,
996	__in				efsys_mem_t *esmp,
997	__inout_ecount(EFX_PHY_NSTATS)	uint32_t *stat);
998
999#endif	/* EFSYS_OPT_PHY_STATS */
1000
1001
1002#if EFSYS_OPT_BIST
1003
1004typedef enum efx_bist_type_e {
1005	EFX_BIST_TYPE_UNKNOWN,
1006	EFX_BIST_TYPE_PHY_NORMAL,
1007	EFX_BIST_TYPE_PHY_CABLE_SHORT,
1008	EFX_BIST_TYPE_PHY_CABLE_LONG,
1009	EFX_BIST_TYPE_MC_MEM,	/* Test the MC DMEM and IMEM */
1010	EFX_BIST_TYPE_SAT_MEM,	/* Test the DMEM and IMEM of satellite cpus*/
1011	EFX_BIST_TYPE_REG,	/* Test the register memories */
1012	EFX_BIST_TYPE_NTYPES,
1013} efx_bist_type_t;
1014
1015typedef enum efx_bist_result_e {
1016	EFX_BIST_RESULT_UNKNOWN,
1017	EFX_BIST_RESULT_RUNNING,
1018	EFX_BIST_RESULT_PASSED,
1019	EFX_BIST_RESULT_FAILED,
1020} efx_bist_result_t;
1021
1022typedef enum efx_phy_cable_status_e {
1023	EFX_PHY_CABLE_STATUS_OK,
1024	EFX_PHY_CABLE_STATUS_INVALID,
1025	EFX_PHY_CABLE_STATUS_OPEN,
1026	EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT,
1027	EFX_PHY_CABLE_STATUS_INTERPAIRSHORT,
1028	EFX_PHY_CABLE_STATUS_BUSY,
1029} efx_phy_cable_status_t;
1030
1031typedef enum efx_bist_value_e {
1032	EFX_BIST_PHY_CABLE_LENGTH_A,
1033	EFX_BIST_PHY_CABLE_LENGTH_B,
1034	EFX_BIST_PHY_CABLE_LENGTH_C,
1035	EFX_BIST_PHY_CABLE_LENGTH_D,
1036	EFX_BIST_PHY_CABLE_STATUS_A,
1037	EFX_BIST_PHY_CABLE_STATUS_B,
1038	EFX_BIST_PHY_CABLE_STATUS_C,
1039	EFX_BIST_PHY_CABLE_STATUS_D,
1040	EFX_BIST_FAULT_CODE,
1041	/* Memory BIST specific values. These match to the MC_CMD_BIST_POLL
1042	 * response. */
1043	EFX_BIST_MEM_TEST,
1044	EFX_BIST_MEM_ADDR,
1045	EFX_BIST_MEM_BUS,
1046	EFX_BIST_MEM_EXPECT,
1047	EFX_BIST_MEM_ACTUAL,
1048	EFX_BIST_MEM_ECC,
1049	EFX_BIST_MEM_ECC_PARITY,
1050	EFX_BIST_MEM_ECC_FATAL,
1051	EFX_BIST_NVALUES,
1052} efx_bist_value_t;
1053
1054extern	__checkReturn		efx_rc_t
1055efx_bist_enable_offline(
1056	__in			efx_nic_t *enp);
1057
1058extern	__checkReturn		efx_rc_t
1059efx_bist_start(
1060	__in			efx_nic_t *enp,
1061	__in			efx_bist_type_t type);
1062
1063extern	__checkReturn		efx_rc_t
1064efx_bist_poll(
1065	__in			efx_nic_t *enp,
1066	__in			efx_bist_type_t type,
1067	__out			efx_bist_result_t *resultp,
1068	__out_opt		uint32_t *value_maskp,
1069	__out_ecount_opt(count)	unsigned long *valuesp,
1070	__in			size_t count);
1071
1072extern				void
1073efx_bist_stop(
1074	__in			efx_nic_t *enp,
1075	__in			efx_bist_type_t type);
1076
1077#endif	/* EFSYS_OPT_BIST */
1078
1079#define	EFX_FEATURE_IPV6		0x00000001
1080#define	EFX_FEATURE_LFSR_HASH_INSERT	0x00000002
1081#define	EFX_FEATURE_LINK_EVENTS		0x00000004
1082#define	EFX_FEATURE_PERIODIC_MAC_STATS	0x00000008
1083#define	EFX_FEATURE_MCDI		0x00000020
1084#define	EFX_FEATURE_LOOKAHEAD_SPLIT	0x00000040
1085#define	EFX_FEATURE_MAC_HEADER_FILTERS	0x00000080
1086#define	EFX_FEATURE_TURBO		0x00000100
1087#define	EFX_FEATURE_MCDI_DMA		0x00000200
1088#define	EFX_FEATURE_TX_SRC_FILTERS	0x00000400
1089#define	EFX_FEATURE_PIO_BUFFERS		0x00000800
1090#define	EFX_FEATURE_FW_ASSISTED_TSO	0x00001000
1091#define	EFX_FEATURE_FW_ASSISTED_TSO_V2	0x00002000
1092#define	EFX_FEATURE_TXQ_CKSUM_OP_DESC	0x00008000
1093
1094typedef enum efx_tunnel_protocol_e {
1095	EFX_TUNNEL_PROTOCOL_NONE = 0,
1096	EFX_TUNNEL_PROTOCOL_VXLAN,
1097	EFX_TUNNEL_PROTOCOL_GENEVE,
1098	EFX_TUNNEL_PROTOCOL_NVGRE,
1099	EFX_TUNNEL_NPROTOS
1100} efx_tunnel_protocol_t;
1101
1102typedef struct efx_nic_cfg_s {
1103	uint32_t		enc_board_type;
1104	uint32_t		enc_phy_type;
1105#if EFSYS_OPT_NAMES
1106	char			enc_phy_name[21];
1107#endif
1108	char			enc_phy_revision[21];
1109	efx_mon_type_t		enc_mon_type;
1110#if EFSYS_OPT_MON_STATS
1111	uint32_t		enc_mon_stat_dma_buf_size;
1112	uint32_t		enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32];
1113#endif
1114	unsigned int		enc_features;
1115	uint8_t			enc_mac_addr[6];
1116	uint8_t			enc_port;	/* PHY port number */
1117	uint32_t		enc_intr_vec_base;
1118	uint32_t		enc_intr_limit;
1119	uint32_t		enc_evq_limit;
1120	uint32_t		enc_txq_limit;
1121	uint32_t		enc_rxq_limit;
1122	uint32_t		enc_txq_max_ndescs;
1123	uint32_t		enc_buftbl_limit;
1124	uint32_t		enc_piobuf_limit;
1125	uint32_t		enc_piobuf_size;
1126	uint32_t		enc_piobuf_min_alloc_size;
1127	uint32_t		enc_evq_timer_quantum_ns;
1128	uint32_t		enc_evq_timer_max_us;
1129	uint32_t		enc_clk_mult;
1130	uint32_t		enc_rx_prefix_size;
1131	uint32_t		enc_rx_buf_align_start;
1132	uint32_t		enc_rx_buf_align_end;
1133#if EFSYS_OPT_LOOPBACK
1134	efx_qword_t		enc_loopback_types[EFX_LINK_NMODES];
1135#endif	/* EFSYS_OPT_LOOPBACK */
1136#if EFSYS_OPT_PHY_FLAGS
1137	uint32_t		enc_phy_flags_mask;
1138#endif	/* EFSYS_OPT_PHY_FLAGS */
1139#if EFSYS_OPT_PHY_LED_CONTROL
1140	uint32_t		enc_led_mask;
1141#endif	/* EFSYS_OPT_PHY_LED_CONTROL */
1142#if EFSYS_OPT_PHY_STATS
1143	uint64_t		enc_phy_stat_mask;
1144#endif	/* EFSYS_OPT_PHY_STATS */
1145#if EFSYS_OPT_MCDI
1146	uint8_t			enc_mcdi_mdio_channel;
1147#if EFSYS_OPT_PHY_STATS
1148	uint32_t		enc_mcdi_phy_stat_mask;
1149#endif	/* EFSYS_OPT_PHY_STATS */
1150#if EFSYS_OPT_MON_STATS
1151	uint32_t		*enc_mcdi_sensor_maskp;
1152	uint32_t		enc_mcdi_sensor_mask_size;
1153#endif	/* EFSYS_OPT_MON_STATS */
1154#endif	/* EFSYS_OPT_MCDI */
1155#if EFSYS_OPT_BIST
1156	uint32_t		enc_bist_mask;
1157#endif	/* EFSYS_OPT_BIST */
1158#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
1159	uint32_t		enc_pf;
1160	uint32_t		enc_vf;
1161	uint32_t		enc_privilege_mask;
1162#endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
1163	boolean_t		enc_bug26807_workaround;
1164	boolean_t		enc_bug35388_workaround;
1165	boolean_t		enc_bug41750_workaround;
1166	boolean_t		enc_bug61265_workaround;
1167	boolean_t		enc_rx_batching_enabled;
1168	/* Maximum number of descriptors completed in an rx event. */
1169	uint32_t		enc_rx_batch_max;
1170	/* Number of rx descriptors the hardware requires for a push. */
1171	uint32_t		enc_rx_push_align;
1172	/* Maximum amount of data in DMA descriptor */
1173	uint32_t		enc_tx_dma_desc_size_max;
1174	/*
1175	 * Boundary which DMA descriptor data must not cross or 0 if no
1176	 * limitation.
1177	 */
1178	uint32_t		enc_tx_dma_desc_boundary;
1179	/*
1180	 * Maximum number of bytes into the packet the TCP header can start for
1181	 * the hardware to apply TSO packet edits.
1182	 */
1183	uint32_t		enc_tx_tso_tcp_header_offset_limit;
1184	boolean_t		enc_fw_assisted_tso_enabled;
1185	boolean_t		enc_fw_assisted_tso_v2_enabled;
1186	/* Number of TSO contexts on the NIC (FATSOv2) */
1187	uint32_t		enc_fw_assisted_tso_v2_n_contexts;
1188	boolean_t		enc_hw_tx_insert_vlan_enabled;
1189	/* Number of PFs on the NIC */
1190	uint32_t		enc_hw_pf_count;
1191	/* Datapath firmware vadapter/vport/vswitch support */
1192	boolean_t		enc_datapath_cap_evb;
1193	boolean_t		enc_rx_disable_scatter_supported;
1194	boolean_t		enc_allow_set_mac_with_installed_filters;
1195	boolean_t		enc_enhanced_set_mac_supported;
1196	boolean_t		enc_init_evq_v2_supported;
1197	boolean_t		enc_pm_and_rxdp_counters;
1198	boolean_t		enc_mac_stats_40g_tx_size_bins;
1199	uint32_t		enc_tunnel_encapsulations_supported;
1200	/* External port identifier */
1201	uint8_t			enc_external_port;
1202	uint32_t		enc_mcdi_max_payload_length;
1203	/* VPD may be per-PF or global */
1204	boolean_t		enc_vpd_is_global;
1205	/* Minimum unidirectional bandwidth in Mb/s to max out all ports */
1206	uint32_t		enc_required_pcie_bandwidth_mbps;
1207	uint32_t		enc_max_pcie_link_gen;
1208	/* Firmware verifies integrity of NVRAM updates */
1209	uint32_t		enc_fw_verified_nvram_update_required;
1210} efx_nic_cfg_t;
1211
1212#define	EFX_PCI_FUNCTION_IS_PF(_encp)	((_encp)->enc_vf == 0xffff)
1213#define	EFX_PCI_FUNCTION_IS_VF(_encp)	((_encp)->enc_vf != 0xffff)
1214
1215#define	EFX_PCI_FUNCTION(_encp)	\
1216	(EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf)
1217
1218#define	EFX_PCI_VF_PARENT(_encp)	((_encp)->enc_pf)
1219
1220extern			const efx_nic_cfg_t *
1221efx_nic_cfg_get(
1222	__in		efx_nic_t *enp);
1223
1224/* Driver resource limits (minimum required/maximum usable). */
1225typedef struct efx_drv_limits_s {
1226	uint32_t	edl_min_evq_count;
1227	uint32_t	edl_max_evq_count;
1228
1229	uint32_t	edl_min_rxq_count;
1230	uint32_t	edl_max_rxq_count;
1231
1232	uint32_t	edl_min_txq_count;
1233	uint32_t	edl_max_txq_count;
1234
1235	/* PIO blocks (sub-allocated from piobuf) */
1236	uint32_t	edl_min_pio_alloc_size;
1237	uint32_t	edl_max_pio_alloc_count;
1238} efx_drv_limits_t;
1239
1240extern	__checkReturn	efx_rc_t
1241efx_nic_set_drv_limits(
1242	__inout		efx_nic_t *enp,
1243	__in		efx_drv_limits_t *edlp);
1244
1245typedef enum efx_nic_region_e {
1246	EFX_REGION_VI,			/* Memory BAR UC mapping */
1247	EFX_REGION_PIO_WRITE_VI,	/* Memory BAR WC mapping */
1248} efx_nic_region_t;
1249
1250extern	__checkReturn	efx_rc_t
1251efx_nic_get_bar_region(
1252	__in		efx_nic_t *enp,
1253	__in		efx_nic_region_t region,
1254	__out		uint32_t *offsetp,
1255	__out		size_t *sizep);
1256
1257extern	__checkReturn	efx_rc_t
1258efx_nic_get_vi_pool(
1259	__in		efx_nic_t *enp,
1260	__out		uint32_t *evq_countp,
1261	__out		uint32_t *rxq_countp,
1262	__out		uint32_t *txq_countp);
1263
1264
1265#if EFSYS_OPT_VPD
1266
1267typedef enum efx_vpd_tag_e {
1268	EFX_VPD_ID = 0x02,
1269	EFX_VPD_END = 0x0f,
1270	EFX_VPD_RO = 0x10,
1271	EFX_VPD_RW = 0x11,
1272} efx_vpd_tag_t;
1273
1274typedef uint16_t efx_vpd_keyword_t;
1275
1276typedef struct efx_vpd_value_s {
1277	efx_vpd_tag_t		evv_tag;
1278	efx_vpd_keyword_t	evv_keyword;
1279	uint8_t			evv_length;
1280	uint8_t			evv_value[0x100];
1281} efx_vpd_value_t;
1282
1283
1284#define	EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8))
1285
1286extern	__checkReturn		efx_rc_t
1287efx_vpd_init(
1288	__in			efx_nic_t *enp);
1289
1290extern	__checkReturn		efx_rc_t
1291efx_vpd_size(
1292	__in			efx_nic_t *enp,
1293	__out			size_t *sizep);
1294
1295extern	__checkReturn		efx_rc_t
1296efx_vpd_read(
1297	__in			efx_nic_t *enp,
1298	__out_bcount(size)	caddr_t data,
1299	__in			size_t size);
1300
1301extern	__checkReturn		efx_rc_t
1302efx_vpd_verify(
1303	__in			efx_nic_t *enp,
1304	__in_bcount(size)	caddr_t data,
1305	__in			size_t size);
1306
1307extern	__checkReturn		efx_rc_t
1308efx_vpd_reinit(
1309	__in			efx_nic_t *enp,
1310	__in_bcount(size)	caddr_t data,
1311	__in			size_t size);
1312
1313extern	__checkReturn		efx_rc_t
1314efx_vpd_get(
1315	__in			efx_nic_t *enp,
1316	__in_bcount(size)	caddr_t data,
1317	__in			size_t size,
1318	__inout			efx_vpd_value_t *evvp);
1319
1320extern	__checkReturn		efx_rc_t
1321efx_vpd_set(
1322	__in			efx_nic_t *enp,
1323	__inout_bcount(size)	caddr_t data,
1324	__in			size_t size,
1325	__in			efx_vpd_value_t *evvp);
1326
1327extern	__checkReturn		efx_rc_t
1328efx_vpd_next(
1329	__in			efx_nic_t *enp,
1330	__inout_bcount(size)	caddr_t data,
1331	__in			size_t size,
1332	__out			efx_vpd_value_t *evvp,
1333	__inout			unsigned int *contp);
1334
1335extern	__checkReturn		efx_rc_t
1336efx_vpd_write(
1337	__in			efx_nic_t *enp,
1338	__in_bcount(size)	caddr_t data,
1339	__in			size_t size);
1340
1341extern				void
1342efx_vpd_fini(
1343	__in			efx_nic_t *enp);
1344
1345#endif	/* EFSYS_OPT_VPD */
1346
1347/* NVRAM */
1348
1349#if EFSYS_OPT_NVRAM
1350
1351typedef enum efx_nvram_type_e {
1352	EFX_NVRAM_INVALID = 0,
1353	EFX_NVRAM_BOOTROM,
1354	EFX_NVRAM_BOOTROM_CFG,
1355	EFX_NVRAM_MC_FIRMWARE,
1356	EFX_NVRAM_MC_GOLDEN,
1357	EFX_NVRAM_PHY,
1358	EFX_NVRAM_NULLPHY,
1359	EFX_NVRAM_FPGA,
1360	EFX_NVRAM_FCFW,
1361	EFX_NVRAM_CPLD,
1362	EFX_NVRAM_FPGA_BACKUP,
1363	EFX_NVRAM_DYNAMIC_CFG,
1364	EFX_NVRAM_LICENSE,
1365	EFX_NVRAM_UEFIROM,
1366	EFX_NVRAM_NTYPES,
1367} efx_nvram_type_t;
1368
1369extern	__checkReturn		efx_rc_t
1370efx_nvram_init(
1371	__in			efx_nic_t *enp);
1372
1373#if EFSYS_OPT_DIAG
1374
1375extern	__checkReturn		efx_rc_t
1376efx_nvram_test(
1377	__in			efx_nic_t *enp);
1378
1379#endif	/* EFSYS_OPT_DIAG */
1380
1381extern	__checkReturn		efx_rc_t
1382efx_nvram_size(
1383	__in			efx_nic_t *enp,
1384	__in			efx_nvram_type_t type,
1385	__out			size_t *sizep);
1386
1387extern	__checkReturn		efx_rc_t
1388efx_nvram_rw_start(
1389	__in			efx_nic_t *enp,
1390	__in			efx_nvram_type_t type,
1391	__out_opt		size_t *pref_chunkp);
1392
1393extern	__checkReturn		efx_rc_t
1394efx_nvram_rw_finish(
1395	__in			efx_nic_t *enp,
1396	__in			efx_nvram_type_t type);
1397
1398extern	__checkReturn		efx_rc_t
1399efx_nvram_get_version(
1400	__in			efx_nic_t *enp,
1401	__in			efx_nvram_type_t type,
1402	__out			uint32_t *subtypep,
1403	__out_ecount(4)		uint16_t version[4]);
1404
1405extern	__checkReturn		efx_rc_t
1406efx_nvram_read_chunk(
1407	__in			efx_nic_t *enp,
1408	__in			efx_nvram_type_t type,
1409	__in			unsigned int offset,
1410	__out_bcount(size)	caddr_t data,
1411	__in			size_t size);
1412
1413extern	__checkReturn		efx_rc_t
1414efx_nvram_set_version(
1415	__in			efx_nic_t *enp,
1416	__in			efx_nvram_type_t type,
1417	__in_ecount(4)		uint16_t version[4]);
1418
1419extern	__checkReturn		efx_rc_t
1420efx_nvram_validate(
1421	__in			efx_nic_t *enp,
1422	__in			efx_nvram_type_t type,
1423	__in_bcount(partn_size)	caddr_t partn_data,
1424	__in			size_t partn_size);
1425
1426extern	 __checkReturn		efx_rc_t
1427efx_nvram_erase(
1428	__in			efx_nic_t *enp,
1429	__in			efx_nvram_type_t type);
1430
1431extern	__checkReturn		efx_rc_t
1432efx_nvram_write_chunk(
1433	__in			efx_nic_t *enp,
1434	__in			efx_nvram_type_t type,
1435	__in			unsigned int offset,
1436	__in_bcount(size)	caddr_t data,
1437	__in			size_t size);
1438
1439extern				void
1440efx_nvram_fini(
1441	__in			efx_nic_t *enp);
1442
1443#endif	/* EFSYS_OPT_NVRAM */
1444
1445#if EFSYS_OPT_BOOTCFG
1446
1447/* Report size and offset of bootcfg sector in NVRAM partition. */
1448extern	__checkReturn		efx_rc_t
1449efx_bootcfg_sector_info(
1450	__in			efx_nic_t *enp,
1451	__in			uint32_t pf,
1452	__out_opt		uint32_t *sector_countp,
1453	__out			size_t *offsetp,
1454	__out			size_t *max_sizep);
1455
1456/*
1457 * Copy bootcfg sector data to a target buffer which may differ in size.
1458 * Optionally corrects format errors in source buffer.
1459 */
1460extern				efx_rc_t
1461efx_bootcfg_copy_sector(
1462	__in			efx_nic_t *enp,
1463	__inout_bcount(sector_length)
1464				uint8_t *sector,
1465	__in			size_t sector_length,
1466	__out_bcount(data_size)	uint8_t *data,
1467	__in			size_t data_size,
1468	__in			boolean_t handle_format_errors);
1469
1470extern				efx_rc_t
1471efx_bootcfg_read(
1472	__in			efx_nic_t *enp,
1473	__out_bcount(size)	uint8_t *data,
1474	__in			size_t size);
1475
1476extern				efx_rc_t
1477efx_bootcfg_write(
1478	__in			efx_nic_t *enp,
1479	__in_bcount(size)	uint8_t *data,
1480	__in			size_t size);
1481
1482#endif	/* EFSYS_OPT_BOOTCFG */
1483
1484#if EFSYS_OPT_DIAG
1485
1486typedef enum efx_pattern_type_t {
1487	EFX_PATTERN_BYTE_INCREMENT = 0,
1488	EFX_PATTERN_ALL_THE_SAME,
1489	EFX_PATTERN_BIT_ALTERNATE,
1490	EFX_PATTERN_BYTE_ALTERNATE,
1491	EFX_PATTERN_BYTE_CHANGING,
1492	EFX_PATTERN_BIT_SWEEP,
1493	EFX_PATTERN_NTYPES
1494} efx_pattern_type_t;
1495
1496typedef			void
1497(*efx_sram_pattern_fn_t)(
1498	__in		size_t row,
1499	__in		boolean_t negate,
1500	__out		efx_qword_t *eqp);
1501
1502extern	__checkReturn	efx_rc_t
1503efx_sram_test(
1504	__in		efx_nic_t *enp,
1505	__in		efx_pattern_type_t type);
1506
1507#endif	/* EFSYS_OPT_DIAG */
1508
1509extern	__checkReturn	efx_rc_t
1510efx_sram_buf_tbl_set(
1511	__in		efx_nic_t *enp,
1512	__in		uint32_t id,
1513	__in		efsys_mem_t *esmp,
1514	__in		size_t n);
1515
1516extern		void
1517efx_sram_buf_tbl_clear(
1518	__in	efx_nic_t *enp,
1519	__in	uint32_t id,
1520	__in	size_t n);
1521
1522#define	EFX_BUF_TBL_SIZE	0x20000
1523
1524#define	EFX_BUF_SIZE		4096
1525
1526/* EV */
1527
1528typedef struct efx_evq_s	efx_evq_t;
1529
1530#if EFSYS_OPT_QSTATS
1531
1532/* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 6f3843f5fe7cc843 */
1533typedef enum efx_ev_qstat_e {
1534	EV_ALL,
1535	EV_RX,
1536	EV_RX_OK,
1537	EV_RX_FRM_TRUNC,
1538	EV_RX_TOBE_DISC,
1539	EV_RX_PAUSE_FRM_ERR,
1540	EV_RX_BUF_OWNER_ID_ERR,
1541	EV_RX_IPV4_HDR_CHKSUM_ERR,
1542	EV_RX_TCP_UDP_CHKSUM_ERR,
1543	EV_RX_ETH_CRC_ERR,
1544	EV_RX_IP_FRAG_ERR,
1545	EV_RX_MCAST_PKT,
1546	EV_RX_MCAST_HASH_MATCH,
1547	EV_RX_TCP_IPV4,
1548	EV_RX_TCP_IPV6,
1549	EV_RX_UDP_IPV4,
1550	EV_RX_UDP_IPV6,
1551	EV_RX_OTHER_IPV4,
1552	EV_RX_OTHER_IPV6,
1553	EV_RX_NON_IP,
1554	EV_RX_BATCH,
1555	EV_TX,
1556	EV_TX_WQ_FF_FULL,
1557	EV_TX_PKT_ERR,
1558	EV_TX_PKT_TOO_BIG,
1559	EV_TX_UNEXPECTED,
1560	EV_GLOBAL,
1561	EV_GLOBAL_MNT,
1562	EV_DRIVER,
1563	EV_DRIVER_SRM_UPD_DONE,
1564	EV_DRIVER_TX_DESCQ_FLS_DONE,
1565	EV_DRIVER_RX_DESCQ_FLS_DONE,
1566	EV_DRIVER_RX_DESCQ_FLS_FAILED,
1567	EV_DRIVER_RX_DSC_ERROR,
1568	EV_DRIVER_TX_DSC_ERROR,
1569	EV_DRV_GEN,
1570	EV_MCDI_RESPONSE,
1571	EV_NQSTATS
1572} efx_ev_qstat_t;
1573
1574/* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */
1575
1576#endif	/* EFSYS_OPT_QSTATS */
1577
1578extern	__checkReturn	efx_rc_t
1579efx_ev_init(
1580	__in		efx_nic_t *enp);
1581
1582extern		void
1583efx_ev_fini(
1584	__in		efx_nic_t *enp);
1585
1586#define	EFX_EVQ_MAXNEVS		32768
1587#define	EFX_EVQ_MINNEVS		512
1588
1589#define	EFX_EVQ_SIZE(_nevs)	((_nevs) * sizeof (efx_qword_t))
1590#define	EFX_EVQ_NBUFS(_nevs)	(EFX_EVQ_SIZE(_nevs) / EFX_BUF_SIZE)
1591
1592#define	EFX_EVQ_FLAGS_TYPE_MASK		(0x3)
1593#define	EFX_EVQ_FLAGS_TYPE_AUTO		(0x0)
1594#define	EFX_EVQ_FLAGS_TYPE_THROUGHPUT	(0x1)
1595#define	EFX_EVQ_FLAGS_TYPE_LOW_LATENCY	(0x2)
1596
1597#define	EFX_EVQ_FLAGS_NOTIFY_MASK	(0xC)
1598#define	EFX_EVQ_FLAGS_NOTIFY_INTERRUPT	(0x0)	/* Interrupting (default) */
1599#define	EFX_EVQ_FLAGS_NOTIFY_DISABLED	(0x4)	/* Non-interrupting */
1600
1601extern	__checkReturn	efx_rc_t
1602efx_ev_qcreate(
1603	__in		efx_nic_t *enp,
1604	__in		unsigned int index,
1605	__in		efsys_mem_t *esmp,
1606	__in		size_t n,
1607	__in		uint32_t id,
1608	__in		uint32_t us,
1609	__in		uint32_t flags,
1610	__deref_out	efx_evq_t **eepp);
1611
1612extern		void
1613efx_ev_qpost(
1614	__in		efx_evq_t *eep,
1615	__in		uint16_t data);
1616
1617typedef __checkReturn	boolean_t
1618(*efx_initialized_ev_t)(
1619	__in_opt	void *arg);
1620
1621#define	EFX_PKT_UNICAST		0x0004
1622#define	EFX_PKT_START		0x0008
1623
1624#define	EFX_PKT_VLAN_TAGGED	0x0010
1625#define	EFX_CKSUM_TCPUDP	0x0020
1626#define	EFX_CKSUM_IPV4		0x0040
1627#define	EFX_PKT_CONT		0x0080
1628
1629#define	EFX_CHECK_VLAN		0x0100
1630#define	EFX_PKT_TCP		0x0200
1631#define	EFX_PKT_UDP		0x0400
1632#define	EFX_PKT_IPV4		0x0800
1633
1634#define	EFX_PKT_IPV6		0x1000
1635#define	EFX_PKT_PREFIX_LEN	0x2000
1636#define	EFX_ADDR_MISMATCH	0x4000
1637#define	EFX_DISCARD		0x8000
1638
1639#define	EFX_EV_RX_NLABELS	32
1640#define	EFX_EV_TX_NLABELS	32
1641
1642typedef	__checkReturn	boolean_t
1643(*efx_rx_ev_t)(
1644	__in_opt	void *arg,
1645	__in		uint32_t label,
1646	__in		uint32_t id,
1647	__in		uint32_t size,
1648	__in		uint16_t flags);
1649
1650typedef	__checkReturn	boolean_t
1651(*efx_tx_ev_t)(
1652	__in_opt	void *arg,
1653	__in		uint32_t label,
1654	__in		uint32_t id);
1655
1656#define	EFX_EXCEPTION_RX_RECOVERY	0x00000001
1657#define	EFX_EXCEPTION_RX_DSC_ERROR	0x00000002
1658#define	EFX_EXCEPTION_TX_DSC_ERROR	0x00000003
1659#define	EFX_EXCEPTION_UNKNOWN_SENSOREVT	0x00000004
1660#define	EFX_EXCEPTION_FWALERT_SRAM	0x00000005
1661#define	EFX_EXCEPTION_UNKNOWN_FWALERT	0x00000006
1662#define	EFX_EXCEPTION_RX_ERROR		0x00000007
1663#define	EFX_EXCEPTION_TX_ERROR		0x00000008
1664#define	EFX_EXCEPTION_EV_ERROR		0x00000009
1665
1666typedef	__checkReturn	boolean_t
1667(*efx_exception_ev_t)(
1668	__in_opt	void *arg,
1669	__in		uint32_t label,
1670	__in		uint32_t data);
1671
1672typedef	__checkReturn	boolean_t
1673(*efx_rxq_flush_done_ev_t)(
1674	__in_opt	void *arg,
1675	__in		uint32_t rxq_index);
1676
1677typedef	__checkReturn	boolean_t
1678(*efx_rxq_flush_failed_ev_t)(
1679	__in_opt	void *arg,
1680	__in		uint32_t rxq_index);
1681
1682typedef	__checkReturn	boolean_t
1683(*efx_txq_flush_done_ev_t)(
1684	__in_opt	void *arg,
1685	__in		uint32_t txq_index);
1686
1687typedef	__checkReturn	boolean_t
1688(*efx_software_ev_t)(
1689	__in_opt	void *arg,
1690	__in		uint16_t magic);
1691
1692typedef	__checkReturn	boolean_t
1693(*efx_sram_ev_t)(
1694	__in_opt	void *arg,
1695	__in		uint32_t code);
1696
1697#define	EFX_SRAM_CLEAR		0
1698#define	EFX_SRAM_UPDATE		1
1699#define	EFX_SRAM_ILLEGAL_CLEAR	2
1700
1701typedef	__checkReturn	boolean_t
1702(*efx_wake_up_ev_t)(
1703	__in_opt	void *arg,
1704	__in		uint32_t label);
1705
1706typedef	__checkReturn	boolean_t
1707(*efx_timer_ev_t)(
1708	__in_opt	void *arg,
1709	__in		uint32_t label);
1710
1711typedef __checkReturn	boolean_t
1712(*efx_link_change_ev_t)(
1713	__in_opt	void *arg,
1714	__in		efx_link_mode_t	link_mode);
1715
1716#if EFSYS_OPT_MON_STATS
1717
1718typedef __checkReturn	boolean_t
1719(*efx_monitor_ev_t)(
1720	__in_opt	void *arg,
1721	__in		efx_mon_stat_t id,
1722	__in		efx_mon_stat_value_t value);
1723
1724#endif	/* EFSYS_OPT_MON_STATS */
1725
1726#if EFSYS_OPT_MAC_STATS
1727
1728typedef __checkReturn	boolean_t
1729(*efx_mac_stats_ev_t)(
1730	__in_opt	void *arg,
1731	__in		uint32_t generation
1732	);
1733
1734#endif	/* EFSYS_OPT_MAC_STATS */
1735
1736typedef struct efx_ev_callbacks_s {
1737	efx_initialized_ev_t		eec_initialized;
1738	efx_rx_ev_t			eec_rx;
1739	efx_tx_ev_t			eec_tx;
1740	efx_exception_ev_t		eec_exception;
1741	efx_rxq_flush_done_ev_t		eec_rxq_flush_done;
1742	efx_rxq_flush_failed_ev_t	eec_rxq_flush_failed;
1743	efx_txq_flush_done_ev_t		eec_txq_flush_done;
1744	efx_software_ev_t		eec_software;
1745	efx_sram_ev_t			eec_sram;
1746	efx_wake_up_ev_t		eec_wake_up;
1747	efx_timer_ev_t			eec_timer;
1748	efx_link_change_ev_t		eec_link_change;
1749#if EFSYS_OPT_MON_STATS
1750	efx_monitor_ev_t		eec_monitor;
1751#endif	/* EFSYS_OPT_MON_STATS */
1752#if EFSYS_OPT_MAC_STATS
1753	efx_mac_stats_ev_t		eec_mac_stats;
1754#endif	/* EFSYS_OPT_MAC_STATS */
1755} efx_ev_callbacks_t;
1756
1757extern	__checkReturn	boolean_t
1758efx_ev_qpending(
1759	__in		efx_evq_t *eep,
1760	__in		unsigned int count);
1761
1762#if EFSYS_OPT_EV_PREFETCH
1763
1764extern			void
1765efx_ev_qprefetch(
1766	__in		efx_evq_t *eep,
1767	__in		unsigned int count);
1768
1769#endif	/* EFSYS_OPT_EV_PREFETCH */
1770
1771extern			void
1772efx_ev_qpoll(
1773	__in		efx_evq_t *eep,
1774	__inout		unsigned int *countp,
1775	__in		const efx_ev_callbacks_t *eecp,
1776	__in_opt	void *arg);
1777
1778extern	__checkReturn	efx_rc_t
1779efx_ev_usecs_to_ticks(
1780	__in		efx_nic_t *enp,
1781	__in		unsigned int usecs,
1782	__out		unsigned int *ticksp);
1783
1784extern	__checkReturn	efx_rc_t
1785efx_ev_qmoderate(
1786	__in		efx_evq_t *eep,
1787	__in		unsigned int us);
1788
1789extern	__checkReturn	efx_rc_t
1790efx_ev_qprime(
1791	__in		efx_evq_t *eep,
1792	__in		unsigned int count);
1793
1794#if EFSYS_OPT_QSTATS
1795
1796#if EFSYS_OPT_NAMES
1797
1798extern		const char *
1799efx_ev_qstat_name(
1800	__in	efx_nic_t *enp,
1801	__in	unsigned int id);
1802
1803#endif	/* EFSYS_OPT_NAMES */
1804
1805extern					void
1806efx_ev_qstats_update(
1807	__in				efx_evq_t *eep,
1808	__inout_ecount(EV_NQSTATS)	efsys_stat_t *stat);
1809
1810#endif	/* EFSYS_OPT_QSTATS */
1811
1812extern		void
1813efx_ev_qdestroy(
1814	__in	efx_evq_t *eep);
1815
1816/* RX */
1817
1818extern	__checkReturn	efx_rc_t
1819efx_rx_init(
1820	__inout		efx_nic_t *enp);
1821
1822extern		void
1823efx_rx_fini(
1824	__in		efx_nic_t *enp);
1825
1826#if EFSYS_OPT_RX_SCATTER
1827	__checkReturn	efx_rc_t
1828efx_rx_scatter_enable(
1829	__in		efx_nic_t *enp,
1830	__in		unsigned int buf_size);
1831#endif	/* EFSYS_OPT_RX_SCATTER */
1832
1833/* Handle to represent use of the default RSS context. */
1834#define	EFX_RSS_CONTEXT_DEFAULT	0xffffffff
1835
1836#if EFSYS_OPT_RX_SCALE
1837
1838typedef enum efx_rx_hash_alg_e {
1839	EFX_RX_HASHALG_LFSR = 0,
1840	EFX_RX_HASHALG_TOEPLITZ
1841} efx_rx_hash_alg_t;
1842
1843#define	EFX_RX_HASH_IPV4	(1U << 0)
1844#define	EFX_RX_HASH_TCPIPV4	(1U << 1)
1845#define	EFX_RX_HASH_IPV6	(1U << 2)
1846#define	EFX_RX_HASH_TCPIPV6	(1U << 3)
1847
1848typedef unsigned int efx_rx_hash_type_t;
1849
1850typedef enum efx_rx_hash_support_e {
1851	EFX_RX_HASH_UNAVAILABLE = 0,	/* Hardware hash not inserted */
1852	EFX_RX_HASH_AVAILABLE		/* Insert hash with/without RSS */
1853} efx_rx_hash_support_t;
1854
1855#define	EFX_RSS_TBL_SIZE	128	/* Rows in RX indirection table */
1856#define	EFX_MAXRSS		64	/* RX indirection entry range */
1857#define	EFX_MAXRSS_LEGACY	16	/* See bug16611 and bug17213 */
1858
1859typedef enum efx_rx_scale_support_e {
1860	EFX_RX_SCALE_UNAVAILABLE = 0,	/* Not supported */
1861	EFX_RX_SCALE_EXCLUSIVE,		/* Writable key/indirection table */
1862	EFX_RX_SCALE_SHARED		/* Read-only key/indirection table */
1863} efx_rx_scale_support_t;
1864
1865extern	__checkReturn	efx_rc_t
1866efx_rx_hash_support_get(
1867	__in		efx_nic_t *enp,
1868	__out		efx_rx_hash_support_t *supportp);
1869
1870
1871extern	__checkReturn	efx_rc_t
1872efx_rx_scale_support_get(
1873	__in		efx_nic_t *enp,
1874	__out		efx_rx_scale_support_t *supportp);
1875
1876extern	__checkReturn	efx_rc_t
1877efx_rx_scale_mode_set(
1878	__in	efx_nic_t *enp,
1879	__in	efx_rx_hash_alg_t alg,
1880	__in	efx_rx_hash_type_t type,
1881	__in	boolean_t insert);
1882
1883extern	__checkReturn	efx_rc_t
1884efx_rx_scale_tbl_set(
1885	__in		efx_nic_t *enp,
1886	__in_ecount(n)	unsigned int *table,
1887	__in		size_t n);
1888
1889extern	__checkReturn	efx_rc_t
1890efx_rx_scale_key_set(
1891	__in		efx_nic_t *enp,
1892	__in_ecount(n)	uint8_t *key,
1893	__in		size_t n);
1894
1895extern	__checkReturn	uint32_t
1896efx_pseudo_hdr_hash_get(
1897	__in		efx_rxq_t *erp,
1898	__in		efx_rx_hash_alg_t func,
1899	__in		uint8_t *buffer);
1900
1901#endif	/* EFSYS_OPT_RX_SCALE */
1902
1903extern	__checkReturn	efx_rc_t
1904efx_pseudo_hdr_pkt_length_get(
1905	__in		efx_rxq_t *erp,
1906	__in		uint8_t *buffer,
1907	__out		uint16_t *pkt_lengthp);
1908
1909#define	EFX_RXQ_MAXNDESCS		4096
1910#define	EFX_RXQ_MINNDESCS		512
1911
1912#define	EFX_RXQ_SIZE(_ndescs)		((_ndescs) * sizeof (efx_qword_t))
1913#define	EFX_RXQ_NBUFS(_ndescs)		(EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
1914#define	EFX_RXQ_LIMIT(_ndescs)		((_ndescs) - 16)
1915#define	EFX_RXQ_DC_NDESCS(_dcsize)	(8 << _dcsize)
1916
1917typedef enum efx_rxq_type_e {
1918	EFX_RXQ_TYPE_DEFAULT,
1919	EFX_RXQ_TYPE_SCATTER,
1920	EFX_RXQ_NTYPES
1921} efx_rxq_type_t;
1922
1923extern	__checkReturn	efx_rc_t
1924efx_rx_qcreate(
1925	__in		efx_nic_t *enp,
1926	__in		unsigned int index,
1927	__in		unsigned int label,
1928	__in		efx_rxq_type_t type,
1929	__in		efsys_mem_t *esmp,
1930	__in		size_t n,
1931	__in		uint32_t id,
1932	__in		efx_evq_t *eep,
1933	__deref_out	efx_rxq_t **erpp);
1934
1935typedef struct efx_buffer_s {
1936	efsys_dma_addr_t	eb_addr;
1937	size_t			eb_size;
1938	boolean_t		eb_eop;
1939} efx_buffer_t;
1940
1941typedef struct efx_desc_s {
1942	efx_qword_t ed_eq;
1943} efx_desc_t;
1944
1945extern			void
1946efx_rx_qpost(
1947	__in		efx_rxq_t *erp,
1948	__in_ecount(n)	efsys_dma_addr_t *addrp,
1949	__in		size_t size,
1950	__in		unsigned int n,
1951	__in		unsigned int completed,
1952	__in		unsigned int added);
1953
1954extern		void
1955efx_rx_qpush(
1956	__in	efx_rxq_t *erp,
1957	__in	unsigned int added,
1958	__inout	unsigned int *pushedp);
1959
1960extern	__checkReturn	efx_rc_t
1961efx_rx_qflush(
1962	__in	efx_rxq_t *erp);
1963
1964extern		void
1965efx_rx_qenable(
1966	__in	efx_rxq_t *erp);
1967
1968extern		void
1969efx_rx_qdestroy(
1970	__in	efx_rxq_t *erp);
1971
1972/* TX */
1973
1974typedef struct efx_txq_s	efx_txq_t;
1975
1976#if EFSYS_OPT_QSTATS
1977
1978/* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */
1979typedef enum efx_tx_qstat_e {
1980	TX_POST,
1981	TX_POST_PIO,
1982	TX_NQSTATS
1983} efx_tx_qstat_t;
1984
1985/* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */
1986
1987#endif	/* EFSYS_OPT_QSTATS */
1988
1989extern	__checkReturn	efx_rc_t
1990efx_tx_init(
1991	__in		efx_nic_t *enp);
1992
1993extern		void
1994efx_tx_fini(
1995	__in	efx_nic_t *enp);
1996
1997#define	EFX_TXQ_MINNDESCS		512
1998
1999#define	EFX_TXQ_SIZE(_ndescs)		((_ndescs) * sizeof (efx_qword_t))
2000#define	EFX_TXQ_NBUFS(_ndescs)		(EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
2001#define	EFX_TXQ_LIMIT(_ndescs)		((_ndescs) - 16)
2002#define	EFX_TXQ_DC_NDESCS(_dcsize)	(8 << _dcsize)
2003
2004#define	EFX_TXQ_MAX_BUFS 8 /* Maximum independent of EFX_BUG35388_WORKAROUND. */
2005
2006#define	EFX_TXQ_CKSUM_IPV4		0x0001
2007#define	EFX_TXQ_CKSUM_TCPUDP		0x0002
2008#define	EFX_TXQ_FATSOV2			0x0004
2009#define	EFX_TXQ_CKSUM_INNER_IPV4	0x0008
2010#define	EFX_TXQ_CKSUM_INNER_TCPUDP	0x0010
2011
2012extern	__checkReturn	efx_rc_t
2013efx_tx_qcreate(
2014	__in		efx_nic_t *enp,
2015	__in		unsigned int index,
2016	__in		unsigned int label,
2017	__in		efsys_mem_t *esmp,
2018	__in		size_t n,
2019	__in		uint32_t id,
2020	__in		uint16_t flags,
2021	__in		efx_evq_t *eep,
2022	__deref_out	efx_txq_t **etpp,
2023	__out		unsigned int *addedp);
2024
2025extern	__checkReturn	efx_rc_t
2026efx_tx_qpost(
2027	__in		efx_txq_t *etp,
2028	__in_ecount(n)	efx_buffer_t *eb,
2029	__in		unsigned int n,
2030	__in		unsigned int completed,
2031	__inout		unsigned int *addedp);
2032
2033extern	__checkReturn	efx_rc_t
2034efx_tx_qpace(
2035	__in		efx_txq_t *etp,
2036	__in		unsigned int ns);
2037
2038extern			void
2039efx_tx_qpush(
2040	__in		efx_txq_t *etp,
2041	__in		unsigned int added,
2042	__in		unsigned int pushed);
2043
2044extern	__checkReturn	efx_rc_t
2045efx_tx_qflush(
2046	__in		efx_txq_t *etp);
2047
2048extern			void
2049efx_tx_qenable(
2050	__in		efx_txq_t *etp);
2051
2052extern	__checkReturn	efx_rc_t
2053efx_tx_qpio_enable(
2054	__in		efx_txq_t *etp);
2055
2056extern			void
2057efx_tx_qpio_disable(
2058	__in		efx_txq_t *etp);
2059
2060extern	__checkReturn	efx_rc_t
2061efx_tx_qpio_write(
2062	__in			efx_txq_t *etp,
2063	__in_ecount(buf_length)	uint8_t *buffer,
2064	__in			size_t buf_length,
2065	__in			size_t pio_buf_offset);
2066
2067extern	__checkReturn	efx_rc_t
2068efx_tx_qpio_post(
2069	__in			efx_txq_t *etp,
2070	__in			size_t pkt_length,
2071	__in			unsigned int completed,
2072	__inout			unsigned int *addedp);
2073
2074extern	__checkReturn	efx_rc_t
2075efx_tx_qdesc_post(
2076	__in		efx_txq_t *etp,
2077	__in_ecount(n)	efx_desc_t *ed,
2078	__in		unsigned int n,
2079	__in		unsigned int completed,
2080	__inout		unsigned int *addedp);
2081
2082extern	void
2083efx_tx_qdesc_dma_create(
2084	__in	efx_txq_t *etp,
2085	__in	efsys_dma_addr_t addr,
2086	__in	size_t size,
2087	__in	boolean_t eop,
2088	__out	efx_desc_t *edp);
2089
2090extern	void
2091efx_tx_qdesc_tso_create(
2092	__in	efx_txq_t *etp,
2093	__in	uint16_t ipv4_id,
2094	__in	uint32_t tcp_seq,
2095	__in	uint8_t  tcp_flags,
2096	__out	efx_desc_t *edp);
2097
2098/* Number of FATSOv2 option descriptors */
2099#define	EFX_TX_FATSOV2_OPT_NDESCS		2
2100
2101/* Maximum number of DMA segments per TSO packet (not superframe) */
2102#define	EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX	24
2103
2104extern	void
2105efx_tx_qdesc_tso2_create(
2106	__in			efx_txq_t *etp,
2107	__in			uint16_t ipv4_id,
2108	__in			uint32_t tcp_seq,
2109	__in			uint16_t tcp_mss,
2110	__out_ecount(count)	efx_desc_t *edp,
2111	__in			int count);
2112
2113extern	void
2114efx_tx_qdesc_vlantci_create(
2115	__in	efx_txq_t *etp,
2116	__in	uint16_t tci,
2117	__out	efx_desc_t *edp);
2118
2119extern	void
2120efx_tx_qdesc_checksum_create(
2121	__in	efx_txq_t *etp,
2122	__in	uint16_t flags,
2123	__out	efx_desc_t *edp);
2124
2125#if EFSYS_OPT_QSTATS
2126
2127#if EFSYS_OPT_NAMES
2128
2129extern		const char *
2130efx_tx_qstat_name(
2131	__in	efx_nic_t *etp,
2132	__in	unsigned int id);
2133
2134#endif	/* EFSYS_OPT_NAMES */
2135
2136extern					void
2137efx_tx_qstats_update(
2138	__in				efx_txq_t *etp,
2139	__inout_ecount(TX_NQSTATS)	efsys_stat_t *stat);
2140
2141#endif	/* EFSYS_OPT_QSTATS */
2142
2143extern		void
2144efx_tx_qdestroy(
2145	__in	efx_txq_t *etp);
2146
2147
2148/* FILTER */
2149
2150#if EFSYS_OPT_FILTER
2151
2152#define	EFX_ETHER_TYPE_IPV4 0x0800
2153#define	EFX_ETHER_TYPE_IPV6 0x86DD
2154
2155#define	EFX_IPPROTO_TCP 6
2156#define	EFX_IPPROTO_UDP 17
2157#define	EFX_IPPROTO_GRE	47
2158
2159/* Use RSS to spread across multiple queues */
2160#define	EFX_FILTER_FLAG_RX_RSS		0x01
2161/* Enable RX scatter */
2162#define	EFX_FILTER_FLAG_RX_SCATTER	0x02
2163/*
2164 * Override an automatic filter (priority EFX_FILTER_PRI_AUTO).
2165 * May only be set by the filter implementation for each type.
2166 * A removal request will restore the automatic filter in its place.
2167 */
2168#define	EFX_FILTER_FLAG_RX_OVER_AUTO	0x04
2169/* Filter is for RX */
2170#define	EFX_FILTER_FLAG_RX		0x08
2171/* Filter is for TX */
2172#define	EFX_FILTER_FLAG_TX		0x10
2173
2174typedef uint8_t efx_filter_flags_t;
2175
2176/*
2177 * Flags which specify the fields to match on. The values are the same as in the
2178 * MC_CMD_FILTER_OP/MC_CMD_FILTER_OP_EXT commands.
2179 */
2180
2181/* Match by remote IP host address */
2182#define	EFX_FILTER_MATCH_REM_HOST		0x00000001
2183/* Match by local IP host address */
2184#define	EFX_FILTER_MATCH_LOC_HOST		0x00000002
2185/* Match by remote MAC address */
2186#define	EFX_FILTER_MATCH_REM_MAC		0x00000004
2187/* Match by remote TCP/UDP port */
2188#define	EFX_FILTER_MATCH_REM_PORT		0x00000008
2189/* Match by remote TCP/UDP port */
2190#define	EFX_FILTER_MATCH_LOC_MAC		0x00000010
2191/* Match by local TCP/UDP port */
2192#define	EFX_FILTER_MATCH_LOC_PORT		0x00000020
2193/* Match by Ether-type */
2194#define	EFX_FILTER_MATCH_ETHER_TYPE		0x00000040
2195/* Match by inner VLAN ID */
2196#define	EFX_FILTER_MATCH_INNER_VID		0x00000080
2197/* Match by outer VLAN ID */
2198#define	EFX_FILTER_MATCH_OUTER_VID		0x00000100
2199/* Match by IP transport protocol */
2200#define	EFX_FILTER_MATCH_IP_PROTO		0x00000200
2201/* For encapsulated packets, match all multicast inner frames */
2202#define	EFX_FILTER_MATCH_IFRM_UNKNOWN_MCAST_DST	0x01000000
2203/* For encapsulated packets, match all unicast inner frames */
2204#define	EFX_FILTER_MATCH_IFRM_UNKNOWN_UCAST_DST	0x02000000
2205/* Match otherwise-unmatched multicast and broadcast packets */
2206#define	EFX_FILTER_MATCH_UNKNOWN_MCAST_DST	0x40000000
2207/* Match otherwise-unmatched unicast packets */
2208#define	EFX_FILTER_MATCH_UNKNOWN_UCAST_DST	0x80000000
2209
2210typedef uint32_t efx_filter_match_flags_t;
2211
2212typedef enum efx_filter_priority_s {
2213	EFX_FILTER_PRI_HINT = 0,	/* Performance hint */
2214	EFX_FILTER_PRI_AUTO,		/* Automatic filter based on device
2215					 * address list or hardware
2216					 * requirements. This may only be used
2217					 * by the filter implementation for
2218					 * each NIC type. */
2219	EFX_FILTER_PRI_MANUAL,		/* Manually configured filter */
2220	EFX_FILTER_PRI_REQUIRED,	/* Required for correct behaviour of the
2221					 * client (e.g. SR-IOV, HyperV VMQ etc.)
2222					 */
2223} efx_filter_priority_t;
2224
2225/*
2226 * FIXME: All these fields are assumed to be in little-endian byte order.
2227 * It may be better for some to be big-endian. See bug42804.
2228 */
2229
2230typedef struct efx_filter_spec_s {
2231	efx_filter_match_flags_t	efs_match_flags;
2232	uint8_t				efs_priority;
2233	efx_filter_flags_t		efs_flags;
2234	uint16_t			efs_dmaq_id;
2235	uint32_t			efs_rss_context;
2236	uint16_t			efs_outer_vid;
2237	uint16_t			efs_inner_vid;
2238	uint8_t				efs_loc_mac[EFX_MAC_ADDR_LEN];
2239	uint8_t				efs_rem_mac[EFX_MAC_ADDR_LEN];
2240	uint16_t			efs_ether_type;
2241	uint8_t				efs_ip_proto;
2242	efx_tunnel_protocol_t		efs_encap_type;
2243	uint16_t			efs_loc_port;
2244	uint16_t			efs_rem_port;
2245	efx_oword_t			efs_rem_host;
2246	efx_oword_t			efs_loc_host;
2247} efx_filter_spec_t;
2248
2249
2250/* Default values for use in filter specifications */
2251#define	EFX_FILTER_SPEC_RX_DMAQ_ID_DROP		0xfff
2252#define	EFX_FILTER_SPEC_VID_UNSPEC		0xffff
2253
2254extern	__checkReturn	efx_rc_t
2255efx_filter_init(
2256	__in		efx_nic_t *enp);
2257
2258extern			void
2259efx_filter_fini(
2260	__in		efx_nic_t *enp);
2261
2262extern	__checkReturn	efx_rc_t
2263efx_filter_insert(
2264	__in		efx_nic_t *enp,
2265	__inout		efx_filter_spec_t *spec);
2266
2267extern	__checkReturn	efx_rc_t
2268efx_filter_remove(
2269	__in		efx_nic_t *enp,
2270	__inout		efx_filter_spec_t *spec);
2271
2272extern	__checkReturn	efx_rc_t
2273efx_filter_restore(
2274	__in		efx_nic_t *enp);
2275
2276extern	__checkReturn	efx_rc_t
2277efx_filter_supported_filters(
2278	__in				efx_nic_t *enp,
2279	__out_ecount(buffer_length)	uint32_t *buffer,
2280	__in				size_t buffer_length,
2281	__out				size_t *list_lengthp);
2282
2283extern			void
2284efx_filter_spec_init_rx(
2285	__out		efx_filter_spec_t *spec,
2286	__in		efx_filter_priority_t priority,
2287	__in		efx_filter_flags_t flags,
2288	__in		efx_rxq_t *erp);
2289
2290extern			void
2291efx_filter_spec_init_tx(
2292	__out		efx_filter_spec_t *spec,
2293	__in		efx_txq_t *etp);
2294
2295extern	__checkReturn	efx_rc_t
2296efx_filter_spec_set_ipv4_local(
2297	__inout		efx_filter_spec_t *spec,
2298	__in		uint8_t proto,
2299	__in		uint32_t host,
2300	__in		uint16_t port);
2301
2302extern	__checkReturn	efx_rc_t
2303efx_filter_spec_set_ipv4_full(
2304	__inout		efx_filter_spec_t *spec,
2305	__in		uint8_t proto,
2306	__in		uint32_t lhost,
2307	__in		uint16_t lport,
2308	__in		uint32_t rhost,
2309	__in		uint16_t rport);
2310
2311extern	__checkReturn	efx_rc_t
2312efx_filter_spec_set_eth_local(
2313	__inout		efx_filter_spec_t *spec,
2314	__in		uint16_t vid,
2315	__in		const uint8_t *addr);
2316
2317extern			void
2318efx_filter_spec_set_ether_type(
2319	__inout		efx_filter_spec_t *spec,
2320	__in		uint16_t ether_type);
2321
2322extern	__checkReturn	efx_rc_t
2323efx_filter_spec_set_uc_def(
2324	__inout		efx_filter_spec_t *spec);
2325
2326extern	__checkReturn	efx_rc_t
2327efx_filter_spec_set_mc_def(
2328	__inout		efx_filter_spec_t *spec);
2329
2330typedef enum efx_filter_inner_frame_match_e {
2331	EFX_FILTER_INNER_FRAME_MATCH_OTHER = 0,
2332	EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_MCAST_DST,
2333	EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_UCAST_DST
2334} efx_filter_inner_frame_match_t;
2335
2336extern	__checkReturn	efx_rc_t
2337efx_filter_spec_set_encap_type(
2338	__inout		efx_filter_spec_t *spec,
2339	__in		efx_tunnel_protocol_t encap_type,
2340	__in		efx_filter_inner_frame_match_t inner_frame_match);
2341
2342
2343#endif	/* EFSYS_OPT_FILTER */
2344
2345/* HASH */
2346
2347extern	__checkReturn		uint32_t
2348efx_hash_dwords(
2349	__in_ecount(count)	uint32_t const *input,
2350	__in			size_t count,
2351	__in			uint32_t init);
2352
2353extern	__checkReturn		uint32_t
2354efx_hash_bytes(
2355	__in_ecount(length)	uint8_t const *input,
2356	__in			size_t length,
2357	__in			uint32_t init);
2358
2359#if EFSYS_OPT_LICENSING
2360
2361/* LICENSING */
2362
2363typedef struct efx_key_stats_s {
2364	uint32_t	eks_valid;
2365	uint32_t	eks_invalid;
2366	uint32_t	eks_blacklisted;
2367	uint32_t	eks_unverifiable;
2368	uint32_t	eks_wrong_node;
2369	uint32_t	eks_licensed_apps_lo;
2370	uint32_t	eks_licensed_apps_hi;
2371	uint32_t	eks_licensed_features_lo;
2372	uint32_t	eks_licensed_features_hi;
2373} efx_key_stats_t;
2374
2375extern	__checkReturn		efx_rc_t
2376efx_lic_init(
2377	__in			efx_nic_t *enp);
2378
2379extern				void
2380efx_lic_fini(
2381	__in			efx_nic_t *enp);
2382
2383extern	__checkReturn	boolean_t
2384efx_lic_check_support(
2385	__in			efx_nic_t *enp);
2386
2387extern	__checkReturn	efx_rc_t
2388efx_lic_update_licenses(
2389	__in		efx_nic_t *enp);
2390
2391extern	__checkReturn	efx_rc_t
2392efx_lic_get_key_stats(
2393	__in		efx_nic_t *enp,
2394	__out		efx_key_stats_t *ksp);
2395
2396extern	__checkReturn	efx_rc_t
2397efx_lic_app_state(
2398	__in		efx_nic_t *enp,
2399	__in		uint64_t app_id,
2400	__out		boolean_t *licensedp);
2401
2402extern	__checkReturn	efx_rc_t
2403efx_lic_get_id(
2404	__in		efx_nic_t *enp,
2405	__in		size_t buffer_size,
2406	__out		uint32_t *typep,
2407	__out		size_t *lengthp,
2408	__out_opt	uint8_t *bufferp);
2409
2410
2411extern	__checkReturn		efx_rc_t
2412efx_lic_find_start(
2413	__in			efx_nic_t *enp,
2414	__in_bcount(buffer_size)
2415				caddr_t bufferp,
2416	__in			size_t buffer_size,
2417	__out			uint32_t *startp
2418	);
2419
2420extern	__checkReturn		efx_rc_t
2421efx_lic_find_end(
2422	__in			efx_nic_t *enp,
2423	__in_bcount(buffer_size)
2424				caddr_t bufferp,
2425	__in			size_t buffer_size,
2426	__in			uint32_t offset,
2427	__out			uint32_t *endp
2428	);
2429
2430extern	__checkReturn	__success(return != B_FALSE)	boolean_t
2431efx_lic_find_key(
2432	__in			efx_nic_t *enp,
2433	__in_bcount(buffer_size)
2434				caddr_t bufferp,
2435	__in			size_t buffer_size,
2436	__in			uint32_t offset,
2437	__out			uint32_t *startp,
2438	__out			uint32_t *lengthp
2439	);
2440
2441extern	__checkReturn	__success(return != B_FALSE)	boolean_t
2442efx_lic_validate_key(
2443	__in			efx_nic_t *enp,
2444	__in_bcount(length)	caddr_t keyp,
2445	__in			uint32_t length
2446	);
2447
2448extern	__checkReturn		efx_rc_t
2449efx_lic_read_key(
2450	__in			efx_nic_t *enp,
2451	__in_bcount(buffer_size)
2452				caddr_t bufferp,
2453	__in			size_t buffer_size,
2454	__in			uint32_t offset,
2455	__in			uint32_t length,
2456	__out_bcount_part(key_max_size, *lengthp)
2457				caddr_t keyp,
2458	__in			size_t key_max_size,
2459	__out			uint32_t *lengthp
2460	);
2461
2462extern	__checkReturn		efx_rc_t
2463efx_lic_write_key(
2464	__in			efx_nic_t *enp,
2465	__in_bcount(buffer_size)
2466				caddr_t bufferp,
2467	__in			size_t buffer_size,
2468	__in			uint32_t offset,
2469	__in_bcount(length)	caddr_t keyp,
2470	__in			uint32_t length,
2471	__out			uint32_t *lengthp
2472	);
2473
2474	__checkReturn		efx_rc_t
2475efx_lic_delete_key(
2476	__in			efx_nic_t *enp,
2477	__in_bcount(buffer_size)
2478				caddr_t bufferp,
2479	__in			size_t buffer_size,
2480	__in			uint32_t offset,
2481	__in			uint32_t length,
2482	__in			uint32_t end,
2483	__out			uint32_t *deltap
2484	);
2485
2486extern	__checkReturn		efx_rc_t
2487efx_lic_create_partition(
2488	__in			efx_nic_t *enp,
2489	__in_bcount(buffer_size)
2490				caddr_t bufferp,
2491	__in			size_t buffer_size
2492	);
2493
2494extern	__checkReturn		efx_rc_t
2495efx_lic_finish_partition(
2496	__in			efx_nic_t *enp,
2497	__in_bcount(buffer_size)
2498				caddr_t bufferp,
2499	__in			size_t buffer_size
2500	);
2501
2502#endif	/* EFSYS_OPT_LICENSING */
2503
2504
2505
2506#ifdef	__cplusplus
2507}
2508#endif
2509
2510#endif	/* _SYS_EFX_H */
2511