1/*-
2 * Copyright (c) 2006-2016 Solarflare Communications Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,
9 *    this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 *    this list of conditions and the following disclaimer in the documentation
12 *    and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
29 *
30 * $FreeBSD: stable/11/sys/dev/sfxge/common/efx.h 350412 2019-07-29 10:44:04Z arybchik $
31 */
32
33#ifndef	_SYS_EFX_H
34#define	_SYS_EFX_H
35
36#include "efsys.h"
37#include "efx_check.h"
38#include "efx_phy_ids.h"
39
40#ifdef	__cplusplus
41extern "C" {
42#endif
43
44#define	EFX_STATIC_ASSERT(_cond)		\
45	((void)sizeof(char[(_cond) ? 1 : -1]))
46
47#define	EFX_ARRAY_SIZE(_array)			\
48	(sizeof(_array) / sizeof((_array)[0]))
49
50#define	EFX_FIELD_OFFSET(_type, _field)		\
51	((size_t) &(((_type *)0)->_field))
52
53/* Round value up to the nearest power of two. */
54#define	EFX_P2ROUNDUP(_type, _value, _align)	\
55	(-(-(_type)(_value) & -(_type)(_align)))
56
57/* Align value down to the nearest power of two. */
58#define	EFX_P2ALIGN(_type, _value, _align)	\
59	((_type)(_value) & -(_type)(_align))
60
61/* Test if value is power of 2 aligned. */
62#define	EFX_IS_P2ALIGNED(_type, _value, _align)	\
63	((((_type)(_value)) & ((_type)(_align) - 1)) == 0)
64
65/* Return codes */
66
67typedef __success(return == 0) int efx_rc_t;
68
69
70/* Chip families */
71
72typedef enum efx_family_e {
73	EFX_FAMILY_INVALID,
74	EFX_FAMILY_FALCON,	/* Obsolete and not supported */
75	EFX_FAMILY_SIENA,
76	EFX_FAMILY_HUNTINGTON,
77	EFX_FAMILY_MEDFORD,
78	EFX_FAMILY_NTYPES
79} efx_family_t;
80
81extern	__checkReturn	efx_rc_t
82efx_family(
83	__in		uint16_t venid,
84	__in		uint16_t devid,
85	__out		efx_family_t *efp);
86
87
88#define	EFX_PCI_VENID_SFC			0x1924
89
90#define	EFX_PCI_DEVID_FALCON			0x0710	/* SFC4000 */
91
92#define	EFX_PCI_DEVID_BETHPAGE			0x0803	/* SFC9020 */
93#define	EFX_PCI_DEVID_SIENA			0x0813	/* SFL9021 */
94#define	EFX_PCI_DEVID_SIENA_F1_UNINIT		0x0810
95
96#define	EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT	0x0901
97#define	EFX_PCI_DEVID_FARMINGDALE		0x0903	/* SFC9120 PF */
98#define	EFX_PCI_DEVID_GREENPORT			0x0923	/* SFC9140 PF */
99
100#define	EFX_PCI_DEVID_FARMINGDALE_VF		0x1903	/* SFC9120 VF */
101#define	EFX_PCI_DEVID_GREENPORT_VF		0x1923	/* SFC9140 VF */
102
103#define	EFX_PCI_DEVID_MEDFORD_PF_UNINIT		0x0913
104#define	EFX_PCI_DEVID_MEDFORD			0x0A03	/* SFC9240 PF */
105#define	EFX_PCI_DEVID_MEDFORD_VF		0x1A03	/* SFC9240 VF */
106
107#define	EFX_MEM_BAR	2
108
109/* Error codes */
110
111enum {
112	EFX_ERR_INVALID,
113	EFX_ERR_SRAM_OOB,
114	EFX_ERR_BUFID_DC_OOB,
115	EFX_ERR_MEM_PERR,
116	EFX_ERR_RBUF_OWN,
117	EFX_ERR_TBUF_OWN,
118	EFX_ERR_RDESQ_OWN,
119	EFX_ERR_TDESQ_OWN,
120	EFX_ERR_EVQ_OWN,
121	EFX_ERR_EVFF_OFLO,
122	EFX_ERR_ILL_ADDR,
123	EFX_ERR_SRAM_PERR,
124	EFX_ERR_NCODES
125};
126
127/* Calculate the IEEE 802.3 CRC32 of a MAC addr */
128extern	__checkReturn		uint32_t
129efx_crc32_calculate(
130	__in			uint32_t crc_init,
131	__in_ecount(length)	uint8_t const *input,
132	__in			int length);
133
134
135/* Type prototypes */
136
137typedef struct efx_rxq_s	efx_rxq_t;
138
139/* NIC */
140
141typedef struct efx_nic_s	efx_nic_t;
142
143extern	__checkReturn	efx_rc_t
144efx_nic_create(
145	__in		efx_family_t family,
146	__in		efsys_identifier_t *esip,
147	__in		efsys_bar_t *esbp,
148	__in		efsys_lock_t *eslp,
149	__deref_out	efx_nic_t **enpp);
150
151extern	__checkReturn	efx_rc_t
152efx_nic_probe(
153	__in		efx_nic_t *enp);
154
155extern	__checkReturn	efx_rc_t
156efx_nic_init(
157	__in		efx_nic_t *enp);
158
159extern	__checkReturn	efx_rc_t
160efx_nic_reset(
161	__in		efx_nic_t *enp);
162
163#if EFSYS_OPT_DIAG
164
165extern	__checkReturn	efx_rc_t
166efx_nic_register_test(
167	__in		efx_nic_t *enp);
168
169#endif	/* EFSYS_OPT_DIAG */
170
171extern		void
172efx_nic_fini(
173	__in		efx_nic_t *enp);
174
175extern		void
176efx_nic_unprobe(
177	__in		efx_nic_t *enp);
178
179extern		void
180efx_nic_destroy(
181	__in	efx_nic_t *enp);
182
183#define	EFX_PCIE_LINK_SPEED_GEN1		1
184#define	EFX_PCIE_LINK_SPEED_GEN2		2
185#define	EFX_PCIE_LINK_SPEED_GEN3		3
186
187typedef enum efx_pcie_link_performance_e {
188	EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH,
189	EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH,
190	EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY,
191	EFX_PCIE_LINK_PERFORMANCE_OPTIMAL
192} efx_pcie_link_performance_t;
193
194extern	__checkReturn	efx_rc_t
195efx_nic_calculate_pcie_link_bandwidth(
196	__in		uint32_t pcie_link_width,
197	__in		uint32_t pcie_link_gen,
198	__out		uint32_t *bandwidth_mbpsp);
199
200extern	__checkReturn	efx_rc_t
201efx_nic_check_pcie_link_speed(
202	__in		efx_nic_t *enp,
203	__in		uint32_t pcie_link_width,
204	__in		uint32_t pcie_link_gen,
205	__out		efx_pcie_link_performance_t *resultp);
206
207#if EFSYS_OPT_MCDI
208
209#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
210/* Huntington and Medford require MCDIv2 commands */
211#define	WITH_MCDI_V2 1
212#endif
213
214typedef struct efx_mcdi_req_s efx_mcdi_req_t;
215
216typedef enum efx_mcdi_exception_e {
217	EFX_MCDI_EXCEPTION_MC_REBOOT,
218	EFX_MCDI_EXCEPTION_MC_BADASSERT,
219} efx_mcdi_exception_t;
220
221#if EFSYS_OPT_MCDI_LOGGING
222typedef enum efx_log_msg_e {
223	EFX_LOG_INVALID,
224	EFX_LOG_MCDI_REQUEST,
225	EFX_LOG_MCDI_RESPONSE,
226} efx_log_msg_t;
227#endif /* EFSYS_OPT_MCDI_LOGGING */
228
229typedef struct efx_mcdi_transport_s {
230	void		*emt_context;
231	efsys_mem_t	*emt_dma_mem;
232	void		(*emt_execute)(void *, efx_mcdi_req_t *);
233	void		(*emt_ev_cpl)(void *);
234	void		(*emt_exception)(void *, efx_mcdi_exception_t);
235#if EFSYS_OPT_MCDI_LOGGING
236	void		(*emt_logger)(void *, efx_log_msg_t,
237					void *, size_t, void *, size_t);
238#endif /* EFSYS_OPT_MCDI_LOGGING */
239#if EFSYS_OPT_MCDI_PROXY_AUTH
240	void		(*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t);
241#endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
242} efx_mcdi_transport_t;
243
244extern	__checkReturn	efx_rc_t
245efx_mcdi_init(
246	__in		efx_nic_t *enp,
247	__in		const efx_mcdi_transport_t *mtp);
248
249extern	__checkReturn	efx_rc_t
250efx_mcdi_reboot(
251	__in		efx_nic_t *enp);
252
253			void
254efx_mcdi_new_epoch(
255	__in		efx_nic_t *enp);
256
257extern			void
258efx_mcdi_get_timeout(
259	__in		efx_nic_t *enp,
260	__in		efx_mcdi_req_t *emrp,
261	__out		uint32_t *usec_timeoutp);
262
263extern			void
264efx_mcdi_request_start(
265	__in		efx_nic_t *enp,
266	__in		efx_mcdi_req_t *emrp,
267	__in		boolean_t ev_cpl);
268
269extern	__checkReturn	boolean_t
270efx_mcdi_request_poll(
271	__in		efx_nic_t *enp);
272
273extern	__checkReturn	boolean_t
274efx_mcdi_request_abort(
275	__in		efx_nic_t *enp);
276
277extern			void
278efx_mcdi_fini(
279	__in		efx_nic_t *enp);
280
281#endif	/* EFSYS_OPT_MCDI */
282
283/* INTR */
284
285#define	EFX_NINTR_SIENA 1024
286
287typedef enum efx_intr_type_e {
288	EFX_INTR_INVALID = 0,
289	EFX_INTR_LINE,
290	EFX_INTR_MESSAGE,
291	EFX_INTR_NTYPES
292} efx_intr_type_t;
293
294#define	EFX_INTR_SIZE	(sizeof (efx_oword_t))
295
296extern	__checkReturn	efx_rc_t
297efx_intr_init(
298	__in		efx_nic_t *enp,
299	__in		efx_intr_type_t type,
300	__in		efsys_mem_t *esmp);
301
302extern			void
303efx_intr_enable(
304	__in		efx_nic_t *enp);
305
306extern			void
307efx_intr_disable(
308	__in		efx_nic_t *enp);
309
310extern			void
311efx_intr_disable_unlocked(
312	__in		efx_nic_t *enp);
313
314#define	EFX_INTR_NEVQS	32
315
316extern	__checkReturn	efx_rc_t
317efx_intr_trigger(
318	__in		efx_nic_t *enp,
319	__in		unsigned int level);
320
321extern			void
322efx_intr_status_line(
323	__in		efx_nic_t *enp,
324	__out		boolean_t *fatalp,
325	__out		uint32_t *maskp);
326
327extern			void
328efx_intr_status_message(
329	__in		efx_nic_t *enp,
330	__in		unsigned int message,
331	__out		boolean_t *fatalp);
332
333extern			void
334efx_intr_fatal(
335	__in		efx_nic_t *enp);
336
337extern			void
338efx_intr_fini(
339	__in		efx_nic_t *enp);
340
341/* MAC */
342
343#if EFSYS_OPT_MAC_STATS
344
345/* START MKCONFIG GENERATED EfxHeaderMacBlock e323546097fd7c65 */
346typedef enum efx_mac_stat_e {
347	EFX_MAC_RX_OCTETS,
348	EFX_MAC_RX_PKTS,
349	EFX_MAC_RX_UNICST_PKTS,
350	EFX_MAC_RX_MULTICST_PKTS,
351	EFX_MAC_RX_BRDCST_PKTS,
352	EFX_MAC_RX_PAUSE_PKTS,
353	EFX_MAC_RX_LE_64_PKTS,
354	EFX_MAC_RX_65_TO_127_PKTS,
355	EFX_MAC_RX_128_TO_255_PKTS,
356	EFX_MAC_RX_256_TO_511_PKTS,
357	EFX_MAC_RX_512_TO_1023_PKTS,
358	EFX_MAC_RX_1024_TO_15XX_PKTS,
359	EFX_MAC_RX_GE_15XX_PKTS,
360	EFX_MAC_RX_ERRORS,
361	EFX_MAC_RX_FCS_ERRORS,
362	EFX_MAC_RX_DROP_EVENTS,
363	EFX_MAC_RX_FALSE_CARRIER_ERRORS,
364	EFX_MAC_RX_SYMBOL_ERRORS,
365	EFX_MAC_RX_ALIGN_ERRORS,
366	EFX_MAC_RX_INTERNAL_ERRORS,
367	EFX_MAC_RX_JABBER_PKTS,
368	EFX_MAC_RX_LANE0_CHAR_ERR,
369	EFX_MAC_RX_LANE1_CHAR_ERR,
370	EFX_MAC_RX_LANE2_CHAR_ERR,
371	EFX_MAC_RX_LANE3_CHAR_ERR,
372	EFX_MAC_RX_LANE0_DISP_ERR,
373	EFX_MAC_RX_LANE1_DISP_ERR,
374	EFX_MAC_RX_LANE2_DISP_ERR,
375	EFX_MAC_RX_LANE3_DISP_ERR,
376	EFX_MAC_RX_MATCH_FAULT,
377	EFX_MAC_RX_NODESC_DROP_CNT,
378	EFX_MAC_TX_OCTETS,
379	EFX_MAC_TX_PKTS,
380	EFX_MAC_TX_UNICST_PKTS,
381	EFX_MAC_TX_MULTICST_PKTS,
382	EFX_MAC_TX_BRDCST_PKTS,
383	EFX_MAC_TX_PAUSE_PKTS,
384	EFX_MAC_TX_LE_64_PKTS,
385	EFX_MAC_TX_65_TO_127_PKTS,
386	EFX_MAC_TX_128_TO_255_PKTS,
387	EFX_MAC_TX_256_TO_511_PKTS,
388	EFX_MAC_TX_512_TO_1023_PKTS,
389	EFX_MAC_TX_1024_TO_15XX_PKTS,
390	EFX_MAC_TX_GE_15XX_PKTS,
391	EFX_MAC_TX_ERRORS,
392	EFX_MAC_TX_SGL_COL_PKTS,
393	EFX_MAC_TX_MULT_COL_PKTS,
394	EFX_MAC_TX_EX_COL_PKTS,
395	EFX_MAC_TX_LATE_COL_PKTS,
396	EFX_MAC_TX_DEF_PKTS,
397	EFX_MAC_TX_EX_DEF_PKTS,
398	EFX_MAC_PM_TRUNC_BB_OVERFLOW,
399	EFX_MAC_PM_DISCARD_BB_OVERFLOW,
400	EFX_MAC_PM_TRUNC_VFIFO_FULL,
401	EFX_MAC_PM_DISCARD_VFIFO_FULL,
402	EFX_MAC_PM_TRUNC_QBB,
403	EFX_MAC_PM_DISCARD_QBB,
404	EFX_MAC_PM_DISCARD_MAPPING,
405	EFX_MAC_RXDP_Q_DISABLED_PKTS,
406	EFX_MAC_RXDP_DI_DROPPED_PKTS,
407	EFX_MAC_RXDP_STREAMING_PKTS,
408	EFX_MAC_RXDP_HLB_FETCH,
409	EFX_MAC_RXDP_HLB_WAIT,
410	EFX_MAC_VADAPTER_RX_UNICAST_PACKETS,
411	EFX_MAC_VADAPTER_RX_UNICAST_BYTES,
412	EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS,
413	EFX_MAC_VADAPTER_RX_MULTICAST_BYTES,
414	EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS,
415	EFX_MAC_VADAPTER_RX_BROADCAST_BYTES,
416	EFX_MAC_VADAPTER_RX_BAD_PACKETS,
417	EFX_MAC_VADAPTER_RX_BAD_BYTES,
418	EFX_MAC_VADAPTER_RX_OVERFLOW,
419	EFX_MAC_VADAPTER_TX_UNICAST_PACKETS,
420	EFX_MAC_VADAPTER_TX_UNICAST_BYTES,
421	EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS,
422	EFX_MAC_VADAPTER_TX_MULTICAST_BYTES,
423	EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS,
424	EFX_MAC_VADAPTER_TX_BROADCAST_BYTES,
425	EFX_MAC_VADAPTER_TX_BAD_PACKETS,
426	EFX_MAC_VADAPTER_TX_BAD_BYTES,
427	EFX_MAC_VADAPTER_TX_OVERFLOW,
428	EFX_MAC_NSTATS
429} efx_mac_stat_t;
430
431/* END MKCONFIG GENERATED EfxHeaderMacBlock */
432
433#endif	/* EFSYS_OPT_MAC_STATS */
434
435typedef enum efx_link_mode_e {
436	EFX_LINK_UNKNOWN = 0,
437	EFX_LINK_DOWN,
438	EFX_LINK_10HDX,
439	EFX_LINK_10FDX,
440	EFX_LINK_100HDX,
441	EFX_LINK_100FDX,
442	EFX_LINK_1000HDX,
443	EFX_LINK_1000FDX,
444	EFX_LINK_10000FDX,
445	EFX_LINK_40000FDX,
446	EFX_LINK_NMODES
447} efx_link_mode_t;
448
449#define	EFX_MAC_ADDR_LEN 6
450
451#define	EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t *)_address)[0] & 0x01)
452
453#define	EFX_MAC_MULTICAST_LIST_MAX	256
454
455#define	EFX_MAC_SDU_MAX	9202
456
457#define	EFX_MAC_PDU_ADJUSTMENT					\
458	(/* EtherII */ 14					\
459	    + /* VLAN */ 4					\
460	    + /* CRC */ 4					\
461	    + /* bug16011 */ 16)				\
462
463#define	EFX_MAC_PDU(_sdu)					\
464	EFX_P2ROUNDUP(size_t, (_sdu) + EFX_MAC_PDU_ADJUSTMENT, 8)
465
466/*
467 * Due to the EFX_P2ROUNDUP in EFX_MAC_PDU(), EFX_MAC_SDU_FROM_PDU() may give
468 * the SDU rounded up slightly.
469 */
470#define	EFX_MAC_SDU_FROM_PDU(_pdu)	((_pdu) - EFX_MAC_PDU_ADJUSTMENT)
471
472#define	EFX_MAC_PDU_MIN	60
473#define	EFX_MAC_PDU_MAX	EFX_MAC_PDU(EFX_MAC_SDU_MAX)
474
475extern	__checkReturn	efx_rc_t
476efx_mac_pdu_get(
477	__in		efx_nic_t *enp,
478	__out		size_t *pdu);
479
480extern	__checkReturn	efx_rc_t
481efx_mac_pdu_set(
482	__in		efx_nic_t *enp,
483	__in		size_t pdu);
484
485extern	__checkReturn	efx_rc_t
486efx_mac_addr_set(
487	__in		efx_nic_t *enp,
488	__in		uint8_t *addr);
489
490extern	__checkReturn			efx_rc_t
491efx_mac_filter_set(
492	__in				efx_nic_t *enp,
493	__in				boolean_t all_unicst,
494	__in				boolean_t mulcst,
495	__in				boolean_t all_mulcst,
496	__in				boolean_t brdcst);
497
498extern	__checkReturn	efx_rc_t
499efx_mac_multicast_list_set(
500	__in				efx_nic_t *enp,
501	__in_ecount(6*count)		uint8_t const *addrs,
502	__in				int count);
503
504extern	__checkReturn	efx_rc_t
505efx_mac_filter_default_rxq_set(
506	__in		efx_nic_t *enp,
507	__in		efx_rxq_t *erp,
508	__in		boolean_t using_rss);
509
510extern			void
511efx_mac_filter_default_rxq_clear(
512	__in		efx_nic_t *enp);
513
514extern	__checkReturn	efx_rc_t
515efx_mac_drain(
516	__in		efx_nic_t *enp,
517	__in		boolean_t enabled);
518
519extern	__checkReturn	efx_rc_t
520efx_mac_up(
521	__in		efx_nic_t *enp,
522	__out		boolean_t *mac_upp);
523
524#define	EFX_FCNTL_RESPOND	0x00000001
525#define	EFX_FCNTL_GENERATE	0x00000002
526
527extern	__checkReturn	efx_rc_t
528efx_mac_fcntl_set(
529	__in		efx_nic_t *enp,
530	__in		unsigned int fcntl,
531	__in		boolean_t autoneg);
532
533extern			void
534efx_mac_fcntl_get(
535	__in		efx_nic_t *enp,
536	__out		unsigned int *fcntl_wantedp,
537	__out		unsigned int *fcntl_linkp);
538
539
540#if EFSYS_OPT_MAC_STATS
541
542#if EFSYS_OPT_NAMES
543
544extern	__checkReturn			const char *
545efx_mac_stat_name(
546	__in				efx_nic_t *enp,
547	__in				unsigned int id);
548
549#endif	/* EFSYS_OPT_NAMES */
550
551#define	EFX_MAC_STATS_MASK_BITS_PER_PAGE	(8 * sizeof (uint32_t))
552
553#define	EFX_MAC_STATS_MASK_NPAGES				\
554	(EFX_P2ROUNDUP(uint32_t, EFX_MAC_NSTATS,		\
555		       EFX_MAC_STATS_MASK_BITS_PER_PAGE) /	\
556	    EFX_MAC_STATS_MASK_BITS_PER_PAGE)
557
558/*
559 * Get mask of MAC statistics supported by the hardware.
560 *
561 * If mask_size is insufficient to return the mask, EINVAL error is
562 * returned. EFX_MAC_STATS_MASK_NPAGES multiplied by size of the page
563 * (which is sizeof (uint32_t)) is sufficient.
564 */
565extern	__checkReturn			efx_rc_t
566efx_mac_stats_get_mask(
567	__in				efx_nic_t *enp,
568	__out_bcount(mask_size)		uint32_t *maskp,
569	__in				size_t mask_size);
570
571#define	EFX_MAC_STAT_SUPPORTED(_mask, _stat)	\
572	((_mask)[(_stat) / EFX_MAC_STATS_MASK_BITS_PER_PAGE] &	\
573	 (1ULL << ((_stat) & (EFX_MAC_STATS_MASK_BITS_PER_PAGE - 1))))
574
575#define	EFX_MAC_STATS_SIZE 0x400
576
577/*
578 * Upload mac statistics supported by the hardware into the given buffer.
579 *
580 * The reference buffer must be at least %EFX_MAC_STATS_SIZE bytes,
581 * and page aligned.
582 *
583 * The hardware will only DMA statistics that it understands (of course).
584 * Drivers should not make any assumptions about which statistics are
585 * supported, especially when the statistics are generated by firmware.
586 *
587 * Thus, drivers should zero this buffer before use, so that not-understood
588 * statistics read back as zero.
589 */
590extern	__checkReturn			efx_rc_t
591efx_mac_stats_upload(
592	__in				efx_nic_t *enp,
593	__in				efsys_mem_t *esmp);
594
595extern	__checkReturn			efx_rc_t
596efx_mac_stats_periodic(
597	__in				efx_nic_t *enp,
598	__in				efsys_mem_t *esmp,
599	__in				uint16_t period_ms,
600	__in				boolean_t events);
601
602extern	__checkReturn			efx_rc_t
603efx_mac_stats_update(
604	__in				efx_nic_t *enp,
605	__in				efsys_mem_t *esmp,
606	__inout_ecount(EFX_MAC_NSTATS)	efsys_stat_t *stat,
607	__inout_opt			uint32_t *generationp);
608
609#endif	/* EFSYS_OPT_MAC_STATS */
610
611/* MON */
612
613typedef enum efx_mon_type_e {
614	EFX_MON_INVALID = 0,
615	EFX_MON_SFC90X0,
616	EFX_MON_SFC91X0,
617	EFX_MON_SFC92X0,
618	EFX_MON_NTYPES
619} efx_mon_type_t;
620
621#if EFSYS_OPT_NAMES
622
623extern		const char *
624efx_mon_name(
625	__in	efx_nic_t *enp);
626
627#endif	/* EFSYS_OPT_NAMES */
628
629extern	__checkReturn	efx_rc_t
630efx_mon_init(
631	__in		efx_nic_t *enp);
632
633#if EFSYS_OPT_MON_STATS
634
635#define	EFX_MON_STATS_PAGE_SIZE 0x100
636#define	EFX_MON_MASK_ELEMENT_SIZE 32
637
638/* START MKCONFIG GENERATED MonitorHeaderStatsBlock 5d4ee5185e419abe */
639typedef enum efx_mon_stat_e {
640	EFX_MON_STAT_2_5V,
641	EFX_MON_STAT_VCCP1,
642	EFX_MON_STAT_VCC,
643	EFX_MON_STAT_5V,
644	EFX_MON_STAT_12V,
645	EFX_MON_STAT_VCCP2,
646	EFX_MON_STAT_EXT_TEMP,
647	EFX_MON_STAT_INT_TEMP,
648	EFX_MON_STAT_AIN1,
649	EFX_MON_STAT_AIN2,
650	EFX_MON_STAT_INT_COOLING,
651	EFX_MON_STAT_EXT_COOLING,
652	EFX_MON_STAT_1V,
653	EFX_MON_STAT_1_2V,
654	EFX_MON_STAT_1_8V,
655	EFX_MON_STAT_3_3V,
656	EFX_MON_STAT_1_2VA,
657	EFX_MON_STAT_VREF,
658	EFX_MON_STAT_VAOE,
659	EFX_MON_STAT_AOE_TEMP,
660	EFX_MON_STAT_PSU_AOE_TEMP,
661	EFX_MON_STAT_PSU_TEMP,
662	EFX_MON_STAT_FAN0,
663	EFX_MON_STAT_FAN1,
664	EFX_MON_STAT_FAN2,
665	EFX_MON_STAT_FAN3,
666	EFX_MON_STAT_FAN4,
667	EFX_MON_STAT_VAOE_IN,
668	EFX_MON_STAT_IAOE,
669	EFX_MON_STAT_IAOE_IN,
670	EFX_MON_STAT_NIC_POWER,
671	EFX_MON_STAT_0_9V,
672	EFX_MON_STAT_I0_9V,
673	EFX_MON_STAT_I1_2V,
674	EFX_MON_STAT_0_9V_ADC,
675	EFX_MON_STAT_INT_TEMP2,
676	EFX_MON_STAT_VREG_TEMP,
677	EFX_MON_STAT_VREG_0_9V_TEMP,
678	EFX_MON_STAT_VREG_1_2V_TEMP,
679	EFX_MON_STAT_INT_VPTAT,
680	EFX_MON_STAT_INT_ADC_TEMP,
681	EFX_MON_STAT_EXT_VPTAT,
682	EFX_MON_STAT_EXT_ADC_TEMP,
683	EFX_MON_STAT_AMBIENT_TEMP,
684	EFX_MON_STAT_AIRFLOW,
685	EFX_MON_STAT_VDD08D_VSS08D_CSR,
686	EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC,
687	EFX_MON_STAT_HOTPOINT_TEMP,
688	EFX_MON_STAT_PHY_POWER_SWITCH_PORT0,
689	EFX_MON_STAT_PHY_POWER_SWITCH_PORT1,
690	EFX_MON_STAT_MUM_VCC,
691	EFX_MON_STAT_0V9_A,
692	EFX_MON_STAT_I0V9_A,
693	EFX_MON_STAT_0V9_A_TEMP,
694	EFX_MON_STAT_0V9_B,
695	EFX_MON_STAT_I0V9_B,
696	EFX_MON_STAT_0V9_B_TEMP,
697	EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY,
698	EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXT_ADC,
699	EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY,
700	EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXT_ADC,
701	EFX_MON_STAT_CONTROLLER_MASTER_VPTAT,
702	EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP,
703	EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXT_ADC,
704	EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXT_ADC,
705	EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT,
706	EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP,
707	EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXT_ADC,
708	EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXT_ADC,
709	EFX_MON_STAT_SODIMM_VOUT,
710	EFX_MON_STAT_SODIMM_0_TEMP,
711	EFX_MON_STAT_SODIMM_1_TEMP,
712	EFX_MON_STAT_PHY0_VCC,
713	EFX_MON_STAT_PHY1_VCC,
714	EFX_MON_STAT_CONTROLLER_TDIODE_TEMP,
715	EFX_MON_STAT_BOARD_FRONT_TEMP,
716	EFX_MON_STAT_BOARD_BACK_TEMP,
717	EFX_MON_NSTATS
718} efx_mon_stat_t;
719
720/* END MKCONFIG GENERATED MonitorHeaderStatsBlock */
721
722typedef enum efx_mon_stat_state_e {
723	EFX_MON_STAT_STATE_OK = 0,
724	EFX_MON_STAT_STATE_WARNING = 1,
725	EFX_MON_STAT_STATE_FATAL = 2,
726	EFX_MON_STAT_STATE_BROKEN = 3,
727	EFX_MON_STAT_STATE_NO_READING = 4,
728} efx_mon_stat_state_t;
729
730typedef struct efx_mon_stat_value_s {
731	uint16_t	emsv_value;
732	uint16_t	emsv_state;
733} efx_mon_stat_value_t;
734
735#if EFSYS_OPT_NAMES
736
737extern					const char *
738efx_mon_stat_name(
739	__in				efx_nic_t *enp,
740	__in				efx_mon_stat_t id);
741
742#endif	/* EFSYS_OPT_NAMES */
743
744extern	__checkReturn			efx_rc_t
745efx_mon_stats_update(
746	__in				efx_nic_t *enp,
747	__in				efsys_mem_t *esmp,
748	__inout_ecount(EFX_MON_NSTATS)	efx_mon_stat_value_t *values);
749
750#endif	/* EFSYS_OPT_MON_STATS */
751
752extern		void
753efx_mon_fini(
754	__in	efx_nic_t *enp);
755
756/* PHY */
757
758extern	__checkReturn	efx_rc_t
759efx_phy_verify(
760	__in		efx_nic_t *enp);
761
762#if EFSYS_OPT_PHY_LED_CONTROL
763
764typedef enum efx_phy_led_mode_e {
765	EFX_PHY_LED_DEFAULT = 0,
766	EFX_PHY_LED_OFF,
767	EFX_PHY_LED_ON,
768	EFX_PHY_LED_FLASH,
769	EFX_PHY_LED_NMODES
770} efx_phy_led_mode_t;
771
772extern	__checkReturn	efx_rc_t
773efx_phy_led_set(
774	__in	efx_nic_t *enp,
775	__in	efx_phy_led_mode_t mode);
776
777#endif	/* EFSYS_OPT_PHY_LED_CONTROL */
778
779extern	__checkReturn	efx_rc_t
780efx_port_init(
781	__in		efx_nic_t *enp);
782
783#if EFSYS_OPT_LOOPBACK
784
785typedef enum efx_loopback_type_e {
786	EFX_LOOPBACK_OFF = 0,
787	EFX_LOOPBACK_DATA = 1,
788	EFX_LOOPBACK_GMAC = 2,
789	EFX_LOOPBACK_XGMII = 3,
790	EFX_LOOPBACK_XGXS = 4,
791	EFX_LOOPBACK_XAUI = 5,
792	EFX_LOOPBACK_GMII = 6,
793	EFX_LOOPBACK_SGMII = 7,
794	EFX_LOOPBACK_XGBR = 8,
795	EFX_LOOPBACK_XFI = 9,
796	EFX_LOOPBACK_XAUI_FAR = 10,
797	EFX_LOOPBACK_GMII_FAR = 11,
798	EFX_LOOPBACK_SGMII_FAR = 12,
799	EFX_LOOPBACK_XFI_FAR = 13,
800	EFX_LOOPBACK_GPHY = 14,
801	EFX_LOOPBACK_PHY_XS = 15,
802	EFX_LOOPBACK_PCS = 16,
803	EFX_LOOPBACK_PMA_PMD = 17,
804	EFX_LOOPBACK_XPORT = 18,
805	EFX_LOOPBACK_XGMII_WS = 19,
806	EFX_LOOPBACK_XAUI_WS = 20,
807	EFX_LOOPBACK_XAUI_WS_FAR = 21,
808	EFX_LOOPBACK_XAUI_WS_NEAR = 22,
809	EFX_LOOPBACK_GMII_WS = 23,
810	EFX_LOOPBACK_XFI_WS = 24,
811	EFX_LOOPBACK_XFI_WS_FAR = 25,
812	EFX_LOOPBACK_PHYXS_WS = 26,
813	EFX_LOOPBACK_PMA_INT = 27,
814	EFX_LOOPBACK_SD_NEAR = 28,
815	EFX_LOOPBACK_SD_FAR = 29,
816	EFX_LOOPBACK_PMA_INT_WS = 30,
817	EFX_LOOPBACK_SD_FEP2_WS = 31,
818	EFX_LOOPBACK_SD_FEP1_5_WS = 32,
819	EFX_LOOPBACK_SD_FEP_WS = 33,
820	EFX_LOOPBACK_SD_FES_WS = 34,
821	EFX_LOOPBACK_NTYPES
822} efx_loopback_type_t;
823
824typedef enum efx_loopback_kind_e {
825	EFX_LOOPBACK_KIND_OFF = 0,
826	EFX_LOOPBACK_KIND_ALL,
827	EFX_LOOPBACK_KIND_MAC,
828	EFX_LOOPBACK_KIND_PHY,
829	EFX_LOOPBACK_NKINDS
830} efx_loopback_kind_t;
831
832extern			void
833efx_loopback_mask(
834	__in	efx_loopback_kind_t loopback_kind,
835	__out	efx_qword_t *maskp);
836
837extern	__checkReturn	efx_rc_t
838efx_port_loopback_set(
839	__in	efx_nic_t *enp,
840	__in	efx_link_mode_t link_mode,
841	__in	efx_loopback_type_t type);
842
843#if EFSYS_OPT_NAMES
844
845extern	__checkReturn	const char *
846efx_loopback_type_name(
847	__in		efx_nic_t *enp,
848	__in		efx_loopback_type_t type);
849
850#endif	/* EFSYS_OPT_NAMES */
851
852#endif	/* EFSYS_OPT_LOOPBACK */
853
854extern	__checkReturn	efx_rc_t
855efx_port_poll(
856	__in		efx_nic_t *enp,
857	__out_opt	efx_link_mode_t	*link_modep);
858
859extern		void
860efx_port_fini(
861	__in	efx_nic_t *enp);
862
863typedef enum efx_phy_cap_type_e {
864	EFX_PHY_CAP_INVALID = 0,
865	EFX_PHY_CAP_10HDX,
866	EFX_PHY_CAP_10FDX,
867	EFX_PHY_CAP_100HDX,
868	EFX_PHY_CAP_100FDX,
869	EFX_PHY_CAP_1000HDX,
870	EFX_PHY_CAP_1000FDX,
871	EFX_PHY_CAP_10000FDX,
872	EFX_PHY_CAP_PAUSE,
873	EFX_PHY_CAP_ASYM,
874	EFX_PHY_CAP_AN,
875	EFX_PHY_CAP_40000FDX,
876	EFX_PHY_CAP_NTYPES
877} efx_phy_cap_type_t;
878
879
880#define	EFX_PHY_CAP_CURRENT	0x00000000
881#define	EFX_PHY_CAP_DEFAULT	0x00000001
882#define	EFX_PHY_CAP_PERM	0x00000002
883
884extern		void
885efx_phy_adv_cap_get(
886	__in		efx_nic_t *enp,
887	__in		uint32_t flag,
888	__out		uint32_t *maskp);
889
890extern	__checkReturn	efx_rc_t
891efx_phy_adv_cap_set(
892	__in		efx_nic_t *enp,
893	__in		uint32_t mask);
894
895extern			void
896efx_phy_lp_cap_get(
897	__in		efx_nic_t *enp,
898	__out		uint32_t *maskp);
899
900extern	__checkReturn	efx_rc_t
901efx_phy_oui_get(
902	__in		efx_nic_t *enp,
903	__out		uint32_t *ouip);
904
905typedef enum efx_phy_media_type_e {
906	EFX_PHY_MEDIA_INVALID = 0,
907	EFX_PHY_MEDIA_XAUI,
908	EFX_PHY_MEDIA_CX4,
909	EFX_PHY_MEDIA_KX4,
910	EFX_PHY_MEDIA_XFP,
911	EFX_PHY_MEDIA_SFP_PLUS,
912	EFX_PHY_MEDIA_BASE_T,
913	EFX_PHY_MEDIA_QSFP_PLUS,
914	EFX_PHY_MEDIA_NTYPES
915} efx_phy_media_type_t;
916
917/* Get the type of medium currently used.  If the board has ports for
918 * modules, a module is present, and we recognise the media type of
919 * the module, then this will be the media type of the module.
920 * Otherwise it will be the media type of the port.
921 */
922extern			void
923efx_phy_media_type_get(
924	__in		efx_nic_t *enp,
925	__out		efx_phy_media_type_t *typep);
926
927extern	__checkReturn		efx_rc_t
928efx_phy_module_get_info(
929	__in			efx_nic_t *enp,
930	__in			uint8_t dev_addr,
931	__in			uint8_t offset,
932	__in			uint8_t len,
933	__out_bcount(len)	uint8_t *data);
934
935#if EFSYS_OPT_PHY_STATS
936
937/* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */
938typedef enum efx_phy_stat_e {
939	EFX_PHY_STAT_OUI,
940	EFX_PHY_STAT_PMA_PMD_LINK_UP,
941	EFX_PHY_STAT_PMA_PMD_RX_FAULT,
942	EFX_PHY_STAT_PMA_PMD_TX_FAULT,
943	EFX_PHY_STAT_PMA_PMD_REV_A,
944	EFX_PHY_STAT_PMA_PMD_REV_B,
945	EFX_PHY_STAT_PMA_PMD_REV_C,
946	EFX_PHY_STAT_PMA_PMD_REV_D,
947	EFX_PHY_STAT_PCS_LINK_UP,
948	EFX_PHY_STAT_PCS_RX_FAULT,
949	EFX_PHY_STAT_PCS_TX_FAULT,
950	EFX_PHY_STAT_PCS_BER,
951	EFX_PHY_STAT_PCS_BLOCK_ERRORS,
952	EFX_PHY_STAT_PHY_XS_LINK_UP,
953	EFX_PHY_STAT_PHY_XS_RX_FAULT,
954	EFX_PHY_STAT_PHY_XS_TX_FAULT,
955	EFX_PHY_STAT_PHY_XS_ALIGN,
956	EFX_PHY_STAT_PHY_XS_SYNC_A,
957	EFX_PHY_STAT_PHY_XS_SYNC_B,
958	EFX_PHY_STAT_PHY_XS_SYNC_C,
959	EFX_PHY_STAT_PHY_XS_SYNC_D,
960	EFX_PHY_STAT_AN_LINK_UP,
961	EFX_PHY_STAT_AN_MASTER,
962	EFX_PHY_STAT_AN_LOCAL_RX_OK,
963	EFX_PHY_STAT_AN_REMOTE_RX_OK,
964	EFX_PHY_STAT_CL22EXT_LINK_UP,
965	EFX_PHY_STAT_SNR_A,
966	EFX_PHY_STAT_SNR_B,
967	EFX_PHY_STAT_SNR_C,
968	EFX_PHY_STAT_SNR_D,
969	EFX_PHY_STAT_PMA_PMD_SIGNAL_A,
970	EFX_PHY_STAT_PMA_PMD_SIGNAL_B,
971	EFX_PHY_STAT_PMA_PMD_SIGNAL_C,
972	EFX_PHY_STAT_PMA_PMD_SIGNAL_D,
973	EFX_PHY_STAT_AN_COMPLETE,
974	EFX_PHY_STAT_PMA_PMD_REV_MAJOR,
975	EFX_PHY_STAT_PMA_PMD_REV_MINOR,
976	EFX_PHY_STAT_PMA_PMD_REV_MICRO,
977	EFX_PHY_STAT_PCS_FW_VERSION_0,
978	EFX_PHY_STAT_PCS_FW_VERSION_1,
979	EFX_PHY_STAT_PCS_FW_VERSION_2,
980	EFX_PHY_STAT_PCS_FW_VERSION_3,
981	EFX_PHY_STAT_PCS_FW_BUILD_YY,
982	EFX_PHY_STAT_PCS_FW_BUILD_MM,
983	EFX_PHY_STAT_PCS_FW_BUILD_DD,
984	EFX_PHY_STAT_PCS_OP_MODE,
985	EFX_PHY_NSTATS
986} efx_phy_stat_t;
987
988/* END MKCONFIG GENERATED PhyHeaderStatsBlock */
989
990#if EFSYS_OPT_NAMES
991
992extern					const char *
993efx_phy_stat_name(
994	__in				efx_nic_t *enp,
995	__in				efx_phy_stat_t stat);
996
997#endif	/* EFSYS_OPT_NAMES */
998
999#define	EFX_PHY_STATS_SIZE 0x100
1000
1001extern	__checkReturn			efx_rc_t
1002efx_phy_stats_update(
1003	__in				efx_nic_t *enp,
1004	__in				efsys_mem_t *esmp,
1005	__inout_ecount(EFX_PHY_NSTATS)	uint32_t *stat);
1006
1007#endif	/* EFSYS_OPT_PHY_STATS */
1008
1009
1010#if EFSYS_OPT_BIST
1011
1012typedef enum efx_bist_type_e {
1013	EFX_BIST_TYPE_UNKNOWN,
1014	EFX_BIST_TYPE_PHY_NORMAL,
1015	EFX_BIST_TYPE_PHY_CABLE_SHORT,
1016	EFX_BIST_TYPE_PHY_CABLE_LONG,
1017	EFX_BIST_TYPE_MC_MEM,	/* Test the MC DMEM and IMEM */
1018	EFX_BIST_TYPE_SAT_MEM,	/* Test the DMEM and IMEM of satellite cpus*/
1019	EFX_BIST_TYPE_REG,	/* Test the register memories */
1020	EFX_BIST_TYPE_NTYPES,
1021} efx_bist_type_t;
1022
1023typedef enum efx_bist_result_e {
1024	EFX_BIST_RESULT_UNKNOWN,
1025	EFX_BIST_RESULT_RUNNING,
1026	EFX_BIST_RESULT_PASSED,
1027	EFX_BIST_RESULT_FAILED,
1028} efx_bist_result_t;
1029
1030typedef enum efx_phy_cable_status_e {
1031	EFX_PHY_CABLE_STATUS_OK,
1032	EFX_PHY_CABLE_STATUS_INVALID,
1033	EFX_PHY_CABLE_STATUS_OPEN,
1034	EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT,
1035	EFX_PHY_CABLE_STATUS_INTERPAIRSHORT,
1036	EFX_PHY_CABLE_STATUS_BUSY,
1037} efx_phy_cable_status_t;
1038
1039typedef enum efx_bist_value_e {
1040	EFX_BIST_PHY_CABLE_LENGTH_A,
1041	EFX_BIST_PHY_CABLE_LENGTH_B,
1042	EFX_BIST_PHY_CABLE_LENGTH_C,
1043	EFX_BIST_PHY_CABLE_LENGTH_D,
1044	EFX_BIST_PHY_CABLE_STATUS_A,
1045	EFX_BIST_PHY_CABLE_STATUS_B,
1046	EFX_BIST_PHY_CABLE_STATUS_C,
1047	EFX_BIST_PHY_CABLE_STATUS_D,
1048	EFX_BIST_FAULT_CODE,
1049	/* Memory BIST specific values. These match to the MC_CMD_BIST_POLL
1050	 * response. */
1051	EFX_BIST_MEM_TEST,
1052	EFX_BIST_MEM_ADDR,
1053	EFX_BIST_MEM_BUS,
1054	EFX_BIST_MEM_EXPECT,
1055	EFX_BIST_MEM_ACTUAL,
1056	EFX_BIST_MEM_ECC,
1057	EFX_BIST_MEM_ECC_PARITY,
1058	EFX_BIST_MEM_ECC_FATAL,
1059	EFX_BIST_NVALUES,
1060} efx_bist_value_t;
1061
1062extern	__checkReturn		efx_rc_t
1063efx_bist_enable_offline(
1064	__in			efx_nic_t *enp);
1065
1066extern	__checkReturn		efx_rc_t
1067efx_bist_start(
1068	__in			efx_nic_t *enp,
1069	__in			efx_bist_type_t type);
1070
1071extern	__checkReturn		efx_rc_t
1072efx_bist_poll(
1073	__in			efx_nic_t *enp,
1074	__in			efx_bist_type_t type,
1075	__out			efx_bist_result_t *resultp,
1076	__out_opt		uint32_t *value_maskp,
1077	__out_ecount_opt(count)	unsigned long *valuesp,
1078	__in			size_t count);
1079
1080extern				void
1081efx_bist_stop(
1082	__in			efx_nic_t *enp,
1083	__in			efx_bist_type_t type);
1084
1085#endif	/* EFSYS_OPT_BIST */
1086
1087#define	EFX_FEATURE_IPV6		0x00000001
1088#define	EFX_FEATURE_LFSR_HASH_INSERT	0x00000002
1089#define	EFX_FEATURE_LINK_EVENTS		0x00000004
1090#define	EFX_FEATURE_PERIODIC_MAC_STATS	0x00000008
1091#define	EFX_FEATURE_MCDI		0x00000020
1092#define	EFX_FEATURE_LOOKAHEAD_SPLIT	0x00000040
1093#define	EFX_FEATURE_MAC_HEADER_FILTERS	0x00000080
1094#define	EFX_FEATURE_TURBO		0x00000100
1095#define	EFX_FEATURE_MCDI_DMA		0x00000200
1096#define	EFX_FEATURE_TX_SRC_FILTERS	0x00000400
1097#define	EFX_FEATURE_PIO_BUFFERS		0x00000800
1098#define	EFX_FEATURE_FW_ASSISTED_TSO	0x00001000
1099#define	EFX_FEATURE_FW_ASSISTED_TSO_V2	0x00002000
1100#define	EFX_FEATURE_TXQ_CKSUM_OP_DESC	0x00008000
1101
1102typedef enum efx_tunnel_protocol_e {
1103	EFX_TUNNEL_PROTOCOL_NONE = 0,
1104	EFX_TUNNEL_PROTOCOL_VXLAN,
1105	EFX_TUNNEL_PROTOCOL_GENEVE,
1106	EFX_TUNNEL_PROTOCOL_NVGRE,
1107	EFX_TUNNEL_NPROTOS
1108} efx_tunnel_protocol_t;
1109
1110typedef struct efx_nic_cfg_s {
1111	uint32_t		enc_board_type;
1112	uint32_t		enc_phy_type;
1113#if EFSYS_OPT_NAMES
1114	char			enc_phy_name[21];
1115#endif
1116	char			enc_phy_revision[21];
1117	efx_mon_type_t		enc_mon_type;
1118#if EFSYS_OPT_MON_STATS
1119	uint32_t		enc_mon_stat_dma_buf_size;
1120	uint32_t		enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32];
1121#endif
1122	unsigned int		enc_features;
1123	uint8_t			enc_mac_addr[6];
1124	uint8_t			enc_port;	/* PHY port number */
1125	uint32_t		enc_intr_vec_base;
1126	uint32_t		enc_intr_limit;
1127	uint32_t		enc_evq_limit;
1128	uint32_t		enc_txq_limit;
1129	uint32_t		enc_rxq_limit;
1130	uint32_t		enc_txq_max_ndescs;
1131	uint32_t		enc_buftbl_limit;
1132	uint32_t		enc_piobuf_limit;
1133	uint32_t		enc_piobuf_size;
1134	uint32_t		enc_piobuf_min_alloc_size;
1135	uint32_t		enc_evq_timer_quantum_ns;
1136	uint32_t		enc_evq_timer_max_us;
1137	uint32_t		enc_clk_mult;
1138	uint32_t		enc_rx_prefix_size;
1139	uint32_t		enc_rx_buf_align_start;
1140	uint32_t		enc_rx_buf_align_end;
1141#if EFSYS_OPT_LOOPBACK
1142	efx_qword_t		enc_loopback_types[EFX_LINK_NMODES];
1143#endif	/* EFSYS_OPT_LOOPBACK */
1144#if EFSYS_OPT_PHY_FLAGS
1145	uint32_t		enc_phy_flags_mask;
1146#endif	/* EFSYS_OPT_PHY_FLAGS */
1147#if EFSYS_OPT_PHY_LED_CONTROL
1148	uint32_t		enc_led_mask;
1149#endif	/* EFSYS_OPT_PHY_LED_CONTROL */
1150#if EFSYS_OPT_PHY_STATS
1151	uint64_t		enc_phy_stat_mask;
1152#endif	/* EFSYS_OPT_PHY_STATS */
1153#if EFSYS_OPT_MCDI
1154	uint8_t			enc_mcdi_mdio_channel;
1155#if EFSYS_OPT_PHY_STATS
1156	uint32_t		enc_mcdi_phy_stat_mask;
1157#endif	/* EFSYS_OPT_PHY_STATS */
1158#if EFSYS_OPT_MON_STATS
1159	uint32_t		*enc_mcdi_sensor_maskp;
1160	uint32_t		enc_mcdi_sensor_mask_size;
1161#endif	/* EFSYS_OPT_MON_STATS */
1162#endif	/* EFSYS_OPT_MCDI */
1163#if EFSYS_OPT_BIST
1164	uint32_t		enc_bist_mask;
1165#endif	/* EFSYS_OPT_BIST */
1166#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
1167	uint32_t		enc_pf;
1168	uint32_t		enc_vf;
1169	uint32_t		enc_privilege_mask;
1170#endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
1171	boolean_t		enc_bug26807_workaround;
1172	boolean_t		enc_bug35388_workaround;
1173	boolean_t		enc_bug41750_workaround;
1174	boolean_t		enc_bug61265_workaround;
1175	boolean_t		enc_rx_batching_enabled;
1176	/* Maximum number of descriptors completed in an rx event. */
1177	uint32_t		enc_rx_batch_max;
1178	/* Number of rx descriptors the hardware requires for a push. */
1179	uint32_t		enc_rx_push_align;
1180	/* Maximum amount of data in DMA descriptor */
1181	uint32_t		enc_tx_dma_desc_size_max;
1182	/*
1183	 * Boundary which DMA descriptor data must not cross or 0 if no
1184	 * limitation.
1185	 */
1186	uint32_t		enc_tx_dma_desc_boundary;
1187	/*
1188	 * Maximum number of bytes into the packet the TCP header can start for
1189	 * the hardware to apply TSO packet edits.
1190	 */
1191	uint32_t		enc_tx_tso_tcp_header_offset_limit;
1192	boolean_t		enc_fw_assisted_tso_enabled;
1193	boolean_t		enc_fw_assisted_tso_v2_enabled;
1194	/* Number of TSO contexts on the NIC (FATSOv2) */
1195	uint32_t		enc_fw_assisted_tso_v2_n_contexts;
1196	boolean_t		enc_hw_tx_insert_vlan_enabled;
1197	/* Number of PFs on the NIC */
1198	uint32_t		enc_hw_pf_count;
1199	/* Datapath firmware vadapter/vport/vswitch support */
1200	boolean_t		enc_datapath_cap_evb;
1201	boolean_t		enc_rx_disable_scatter_supported;
1202	boolean_t		enc_allow_set_mac_with_installed_filters;
1203	boolean_t		enc_enhanced_set_mac_supported;
1204	boolean_t		enc_init_evq_v2_supported;
1205	boolean_t		enc_pm_and_rxdp_counters;
1206	boolean_t		enc_mac_stats_40g_tx_size_bins;
1207	uint32_t		enc_tunnel_encapsulations_supported;
1208	/* External port identifier */
1209	uint8_t			enc_external_port;
1210	uint32_t		enc_mcdi_max_payload_length;
1211	/* VPD may be per-PF or global */
1212	boolean_t		enc_vpd_is_global;
1213	/* Minimum unidirectional bandwidth in Mb/s to max out all ports */
1214	uint32_t		enc_required_pcie_bandwidth_mbps;
1215	uint32_t		enc_max_pcie_link_gen;
1216	/* Firmware verifies integrity of NVRAM updates */
1217	uint32_t		enc_fw_verified_nvram_update_required;
1218} efx_nic_cfg_t;
1219
1220#define	EFX_PCI_FUNCTION_IS_PF(_encp)	((_encp)->enc_vf == 0xffff)
1221#define	EFX_PCI_FUNCTION_IS_VF(_encp)	((_encp)->enc_vf != 0xffff)
1222
1223#define	EFX_PCI_FUNCTION(_encp)	\
1224	(EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf)
1225
1226#define	EFX_PCI_VF_PARENT(_encp)	((_encp)->enc_pf)
1227
1228extern			const efx_nic_cfg_t *
1229efx_nic_cfg_get(
1230	__in		efx_nic_t *enp);
1231
1232/* Driver resource limits (minimum required/maximum usable). */
1233typedef struct efx_drv_limits_s {
1234	uint32_t	edl_min_evq_count;
1235	uint32_t	edl_max_evq_count;
1236
1237	uint32_t	edl_min_rxq_count;
1238	uint32_t	edl_max_rxq_count;
1239
1240	uint32_t	edl_min_txq_count;
1241	uint32_t	edl_max_txq_count;
1242
1243	/* PIO blocks (sub-allocated from piobuf) */
1244	uint32_t	edl_min_pio_alloc_size;
1245	uint32_t	edl_max_pio_alloc_count;
1246} efx_drv_limits_t;
1247
1248extern	__checkReturn	efx_rc_t
1249efx_nic_set_drv_limits(
1250	__inout		efx_nic_t *enp,
1251	__in		efx_drv_limits_t *edlp);
1252
1253typedef enum efx_nic_region_e {
1254	EFX_REGION_VI,			/* Memory BAR UC mapping */
1255	EFX_REGION_PIO_WRITE_VI,	/* Memory BAR WC mapping */
1256} efx_nic_region_t;
1257
1258extern	__checkReturn	efx_rc_t
1259efx_nic_get_bar_region(
1260	__in		efx_nic_t *enp,
1261	__in		efx_nic_region_t region,
1262	__out		uint32_t *offsetp,
1263	__out		size_t *sizep);
1264
1265extern	__checkReturn	efx_rc_t
1266efx_nic_get_vi_pool(
1267	__in		efx_nic_t *enp,
1268	__out		uint32_t *evq_countp,
1269	__out		uint32_t *rxq_countp,
1270	__out		uint32_t *txq_countp);
1271
1272
1273#if EFSYS_OPT_VPD
1274
1275typedef enum efx_vpd_tag_e {
1276	EFX_VPD_ID = 0x02,
1277	EFX_VPD_END = 0x0f,
1278	EFX_VPD_RO = 0x10,
1279	EFX_VPD_RW = 0x11,
1280} efx_vpd_tag_t;
1281
1282typedef uint16_t efx_vpd_keyword_t;
1283
1284typedef struct efx_vpd_value_s {
1285	efx_vpd_tag_t		evv_tag;
1286	efx_vpd_keyword_t	evv_keyword;
1287	uint8_t			evv_length;
1288	uint8_t			evv_value[0x100];
1289} efx_vpd_value_t;
1290
1291
1292#define	EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8))
1293
1294extern	__checkReturn		efx_rc_t
1295efx_vpd_init(
1296	__in			efx_nic_t *enp);
1297
1298extern	__checkReturn		efx_rc_t
1299efx_vpd_size(
1300	__in			efx_nic_t *enp,
1301	__out			size_t *sizep);
1302
1303extern	__checkReturn		efx_rc_t
1304efx_vpd_read(
1305	__in			efx_nic_t *enp,
1306	__out_bcount(size)	caddr_t data,
1307	__in			size_t size);
1308
1309extern	__checkReturn		efx_rc_t
1310efx_vpd_verify(
1311	__in			efx_nic_t *enp,
1312	__in_bcount(size)	caddr_t data,
1313	__in			size_t size);
1314
1315extern	__checkReturn		efx_rc_t
1316efx_vpd_reinit(
1317	__in			efx_nic_t *enp,
1318	__in_bcount(size)	caddr_t data,
1319	__in			size_t size);
1320
1321extern	__checkReturn		efx_rc_t
1322efx_vpd_get(
1323	__in			efx_nic_t *enp,
1324	__in_bcount(size)	caddr_t data,
1325	__in			size_t size,
1326	__inout			efx_vpd_value_t *evvp);
1327
1328extern	__checkReturn		efx_rc_t
1329efx_vpd_set(
1330	__in			efx_nic_t *enp,
1331	__inout_bcount(size)	caddr_t data,
1332	__in			size_t size,
1333	__in			efx_vpd_value_t *evvp);
1334
1335extern	__checkReturn		efx_rc_t
1336efx_vpd_next(
1337	__in			efx_nic_t *enp,
1338	__inout_bcount(size)	caddr_t data,
1339	__in			size_t size,
1340	__out			efx_vpd_value_t *evvp,
1341	__inout			unsigned int *contp);
1342
1343extern	__checkReturn		efx_rc_t
1344efx_vpd_write(
1345	__in			efx_nic_t *enp,
1346	__in_bcount(size)	caddr_t data,
1347	__in			size_t size);
1348
1349extern				void
1350efx_vpd_fini(
1351	__in			efx_nic_t *enp);
1352
1353#endif	/* EFSYS_OPT_VPD */
1354
1355/* NVRAM */
1356
1357#if EFSYS_OPT_NVRAM
1358
1359typedef enum efx_nvram_type_e {
1360	EFX_NVRAM_INVALID = 0,
1361	EFX_NVRAM_BOOTROM,
1362	EFX_NVRAM_BOOTROM_CFG,
1363	EFX_NVRAM_MC_FIRMWARE,
1364	EFX_NVRAM_MC_GOLDEN,
1365	EFX_NVRAM_PHY,
1366	EFX_NVRAM_NULLPHY,
1367	EFX_NVRAM_FPGA,
1368	EFX_NVRAM_FCFW,
1369	EFX_NVRAM_CPLD,
1370	EFX_NVRAM_FPGA_BACKUP,
1371	EFX_NVRAM_DYNAMIC_CFG,
1372	EFX_NVRAM_LICENSE,
1373	EFX_NVRAM_UEFIROM,
1374	EFX_NVRAM_NTYPES,
1375} efx_nvram_type_t;
1376
1377extern	__checkReturn		efx_rc_t
1378efx_nvram_init(
1379	__in			efx_nic_t *enp);
1380
1381#if EFSYS_OPT_DIAG
1382
1383extern	__checkReturn		efx_rc_t
1384efx_nvram_test(
1385	__in			efx_nic_t *enp);
1386
1387#endif	/* EFSYS_OPT_DIAG */
1388
1389extern	__checkReturn		efx_rc_t
1390efx_nvram_size(
1391	__in			efx_nic_t *enp,
1392	__in			efx_nvram_type_t type,
1393	__out			size_t *sizep);
1394
1395extern	__checkReturn		efx_rc_t
1396efx_nvram_rw_start(
1397	__in			efx_nic_t *enp,
1398	__in			efx_nvram_type_t type,
1399	__out_opt		size_t *pref_chunkp);
1400
1401extern	__checkReturn		efx_rc_t
1402efx_nvram_rw_finish(
1403	__in			efx_nic_t *enp,
1404	__in			efx_nvram_type_t type);
1405
1406extern	__checkReturn		efx_rc_t
1407efx_nvram_get_version(
1408	__in			efx_nic_t *enp,
1409	__in			efx_nvram_type_t type,
1410	__out			uint32_t *subtypep,
1411	__out_ecount(4)		uint16_t version[4]);
1412
1413extern	__checkReturn		efx_rc_t
1414efx_nvram_read_chunk(
1415	__in			efx_nic_t *enp,
1416	__in			efx_nvram_type_t type,
1417	__in			unsigned int offset,
1418	__out_bcount(size)	caddr_t data,
1419	__in			size_t size);
1420
1421extern	__checkReturn		efx_rc_t
1422efx_nvram_set_version(
1423	__in			efx_nic_t *enp,
1424	__in			efx_nvram_type_t type,
1425	__in_ecount(4)		uint16_t version[4]);
1426
1427extern	__checkReturn		efx_rc_t
1428efx_nvram_validate(
1429	__in			efx_nic_t *enp,
1430	__in			efx_nvram_type_t type,
1431	__in_bcount(partn_size)	caddr_t partn_data,
1432	__in			size_t partn_size);
1433
1434extern	 __checkReturn		efx_rc_t
1435efx_nvram_erase(
1436	__in			efx_nic_t *enp,
1437	__in			efx_nvram_type_t type);
1438
1439extern	__checkReturn		efx_rc_t
1440efx_nvram_write_chunk(
1441	__in			efx_nic_t *enp,
1442	__in			efx_nvram_type_t type,
1443	__in			unsigned int offset,
1444	__in_bcount(size)	caddr_t data,
1445	__in			size_t size);
1446
1447extern				void
1448efx_nvram_fini(
1449	__in			efx_nic_t *enp);
1450
1451#endif	/* EFSYS_OPT_NVRAM */
1452
1453#if EFSYS_OPT_BOOTCFG
1454
1455/* Report size and offset of bootcfg sector in NVRAM partition. */
1456extern	__checkReturn		efx_rc_t
1457efx_bootcfg_sector_info(
1458	__in			efx_nic_t *enp,
1459	__in			uint32_t pf,
1460	__out_opt		uint32_t *sector_countp,
1461	__out			size_t *offsetp,
1462	__out			size_t *max_sizep);
1463
1464/*
1465 * Copy bootcfg sector data to a target buffer which may differ in size.
1466 * Optionally corrects format errors in source buffer.
1467 */
1468extern				efx_rc_t
1469efx_bootcfg_copy_sector(
1470	__in			efx_nic_t *enp,
1471	__inout_bcount(sector_length)
1472				uint8_t *sector,
1473	__in			size_t sector_length,
1474	__out_bcount(data_size)	uint8_t *data,
1475	__in			size_t data_size,
1476	__in			boolean_t handle_format_errors);
1477
1478extern				efx_rc_t
1479efx_bootcfg_read(
1480	__in			efx_nic_t *enp,
1481	__out_bcount(size)	uint8_t *data,
1482	__in			size_t size);
1483
1484extern				efx_rc_t
1485efx_bootcfg_write(
1486	__in			efx_nic_t *enp,
1487	__in_bcount(size)	uint8_t *data,
1488	__in			size_t size);
1489
1490#endif	/* EFSYS_OPT_BOOTCFG */
1491
1492#if EFSYS_OPT_DIAG
1493
1494typedef enum efx_pattern_type_t {
1495	EFX_PATTERN_BYTE_INCREMENT = 0,
1496	EFX_PATTERN_ALL_THE_SAME,
1497	EFX_PATTERN_BIT_ALTERNATE,
1498	EFX_PATTERN_BYTE_ALTERNATE,
1499	EFX_PATTERN_BYTE_CHANGING,
1500	EFX_PATTERN_BIT_SWEEP,
1501	EFX_PATTERN_NTYPES
1502} efx_pattern_type_t;
1503
1504typedef			void
1505(*efx_sram_pattern_fn_t)(
1506	__in		size_t row,
1507	__in		boolean_t negate,
1508	__out		efx_qword_t *eqp);
1509
1510extern	__checkReturn	efx_rc_t
1511efx_sram_test(
1512	__in		efx_nic_t *enp,
1513	__in		efx_pattern_type_t type);
1514
1515#endif	/* EFSYS_OPT_DIAG */
1516
1517extern	__checkReturn	efx_rc_t
1518efx_sram_buf_tbl_set(
1519	__in		efx_nic_t *enp,
1520	__in		uint32_t id,
1521	__in		efsys_mem_t *esmp,
1522	__in		size_t n);
1523
1524extern		void
1525efx_sram_buf_tbl_clear(
1526	__in	efx_nic_t *enp,
1527	__in	uint32_t id,
1528	__in	size_t n);
1529
1530#define	EFX_BUF_TBL_SIZE	0x20000
1531
1532#define	EFX_BUF_SIZE		4096
1533
1534/* EV */
1535
1536typedef struct efx_evq_s	efx_evq_t;
1537
1538#if EFSYS_OPT_QSTATS
1539
1540/* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 6f3843f5fe7cc843 */
1541typedef enum efx_ev_qstat_e {
1542	EV_ALL,
1543	EV_RX,
1544	EV_RX_OK,
1545	EV_RX_FRM_TRUNC,
1546	EV_RX_TOBE_DISC,
1547	EV_RX_PAUSE_FRM_ERR,
1548	EV_RX_BUF_OWNER_ID_ERR,
1549	EV_RX_IPV4_HDR_CHKSUM_ERR,
1550	EV_RX_TCP_UDP_CHKSUM_ERR,
1551	EV_RX_ETH_CRC_ERR,
1552	EV_RX_IP_FRAG_ERR,
1553	EV_RX_MCAST_PKT,
1554	EV_RX_MCAST_HASH_MATCH,
1555	EV_RX_TCP_IPV4,
1556	EV_RX_TCP_IPV6,
1557	EV_RX_UDP_IPV4,
1558	EV_RX_UDP_IPV6,
1559	EV_RX_OTHER_IPV4,
1560	EV_RX_OTHER_IPV6,
1561	EV_RX_NON_IP,
1562	EV_RX_BATCH,
1563	EV_TX,
1564	EV_TX_WQ_FF_FULL,
1565	EV_TX_PKT_ERR,
1566	EV_TX_PKT_TOO_BIG,
1567	EV_TX_UNEXPECTED,
1568	EV_GLOBAL,
1569	EV_GLOBAL_MNT,
1570	EV_DRIVER,
1571	EV_DRIVER_SRM_UPD_DONE,
1572	EV_DRIVER_TX_DESCQ_FLS_DONE,
1573	EV_DRIVER_RX_DESCQ_FLS_DONE,
1574	EV_DRIVER_RX_DESCQ_FLS_FAILED,
1575	EV_DRIVER_RX_DSC_ERROR,
1576	EV_DRIVER_TX_DSC_ERROR,
1577	EV_DRV_GEN,
1578	EV_MCDI_RESPONSE,
1579	EV_NQSTATS
1580} efx_ev_qstat_t;
1581
1582/* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */
1583
1584#endif	/* EFSYS_OPT_QSTATS */
1585
1586extern	__checkReturn	efx_rc_t
1587efx_ev_init(
1588	__in		efx_nic_t *enp);
1589
1590extern		void
1591efx_ev_fini(
1592	__in		efx_nic_t *enp);
1593
1594#define	EFX_EVQ_MAXNEVS		32768
1595#define	EFX_EVQ_MINNEVS		512
1596
1597#define	EFX_EVQ_SIZE(_nevs)	((_nevs) * sizeof (efx_qword_t))
1598#define	EFX_EVQ_NBUFS(_nevs)	(EFX_EVQ_SIZE(_nevs) / EFX_BUF_SIZE)
1599
1600#define	EFX_EVQ_FLAGS_TYPE_MASK		(0x3)
1601#define	EFX_EVQ_FLAGS_TYPE_AUTO		(0x0)
1602#define	EFX_EVQ_FLAGS_TYPE_THROUGHPUT	(0x1)
1603#define	EFX_EVQ_FLAGS_TYPE_LOW_LATENCY	(0x2)
1604
1605#define	EFX_EVQ_FLAGS_NOTIFY_MASK	(0xC)
1606#define	EFX_EVQ_FLAGS_NOTIFY_INTERRUPT	(0x0)	/* Interrupting (default) */
1607#define	EFX_EVQ_FLAGS_NOTIFY_DISABLED	(0x4)	/* Non-interrupting */
1608
1609extern	__checkReturn	efx_rc_t
1610efx_ev_qcreate(
1611	__in		efx_nic_t *enp,
1612	__in		unsigned int index,
1613	__in		efsys_mem_t *esmp,
1614	__in		size_t n,
1615	__in		uint32_t id,
1616	__in		uint32_t us,
1617	__in		uint32_t flags,
1618	__deref_out	efx_evq_t **eepp);
1619
1620extern		void
1621efx_ev_qpost(
1622	__in		efx_evq_t *eep,
1623	__in		uint16_t data);
1624
1625typedef __checkReturn	boolean_t
1626(*efx_initialized_ev_t)(
1627	__in_opt	void *arg);
1628
1629#define	EFX_PKT_UNICAST		0x0004
1630#define	EFX_PKT_START		0x0008
1631
1632#define	EFX_PKT_VLAN_TAGGED	0x0010
1633#define	EFX_CKSUM_TCPUDP	0x0020
1634#define	EFX_CKSUM_IPV4		0x0040
1635#define	EFX_PKT_CONT		0x0080
1636
1637#define	EFX_CHECK_VLAN		0x0100
1638#define	EFX_PKT_TCP		0x0200
1639#define	EFX_PKT_UDP		0x0400
1640#define	EFX_PKT_IPV4		0x0800
1641
1642#define	EFX_PKT_IPV6		0x1000
1643#define	EFX_PKT_PREFIX_LEN	0x2000
1644#define	EFX_ADDR_MISMATCH	0x4000
1645#define	EFX_DISCARD		0x8000
1646
1647#define	EFX_EV_RX_NLABELS	32
1648#define	EFX_EV_TX_NLABELS	32
1649
1650typedef	__checkReturn	boolean_t
1651(*efx_rx_ev_t)(
1652	__in_opt	void *arg,
1653	__in		uint32_t label,
1654	__in		uint32_t id,
1655	__in		uint32_t size,
1656	__in		uint16_t flags);
1657
1658typedef	__checkReturn	boolean_t
1659(*efx_tx_ev_t)(
1660	__in_opt	void *arg,
1661	__in		uint32_t label,
1662	__in		uint32_t id);
1663
1664#define	EFX_EXCEPTION_RX_RECOVERY	0x00000001
1665#define	EFX_EXCEPTION_RX_DSC_ERROR	0x00000002
1666#define	EFX_EXCEPTION_TX_DSC_ERROR	0x00000003
1667#define	EFX_EXCEPTION_UNKNOWN_SENSOREVT	0x00000004
1668#define	EFX_EXCEPTION_FWALERT_SRAM	0x00000005
1669#define	EFX_EXCEPTION_UNKNOWN_FWALERT	0x00000006
1670#define	EFX_EXCEPTION_RX_ERROR		0x00000007
1671#define	EFX_EXCEPTION_TX_ERROR		0x00000008
1672#define	EFX_EXCEPTION_EV_ERROR		0x00000009
1673
1674typedef	__checkReturn	boolean_t
1675(*efx_exception_ev_t)(
1676	__in_opt	void *arg,
1677	__in		uint32_t label,
1678	__in		uint32_t data);
1679
1680typedef	__checkReturn	boolean_t
1681(*efx_rxq_flush_done_ev_t)(
1682	__in_opt	void *arg,
1683	__in		uint32_t rxq_index);
1684
1685typedef	__checkReturn	boolean_t
1686(*efx_rxq_flush_failed_ev_t)(
1687	__in_opt	void *arg,
1688	__in		uint32_t rxq_index);
1689
1690typedef	__checkReturn	boolean_t
1691(*efx_txq_flush_done_ev_t)(
1692	__in_opt	void *arg,
1693	__in		uint32_t txq_index);
1694
1695typedef	__checkReturn	boolean_t
1696(*efx_software_ev_t)(
1697	__in_opt	void *arg,
1698	__in		uint16_t magic);
1699
1700typedef	__checkReturn	boolean_t
1701(*efx_sram_ev_t)(
1702	__in_opt	void *arg,
1703	__in		uint32_t code);
1704
1705#define	EFX_SRAM_CLEAR		0
1706#define	EFX_SRAM_UPDATE		1
1707#define	EFX_SRAM_ILLEGAL_CLEAR	2
1708
1709typedef	__checkReturn	boolean_t
1710(*efx_wake_up_ev_t)(
1711	__in_opt	void *arg,
1712	__in		uint32_t label);
1713
1714typedef	__checkReturn	boolean_t
1715(*efx_timer_ev_t)(
1716	__in_opt	void *arg,
1717	__in		uint32_t label);
1718
1719typedef __checkReturn	boolean_t
1720(*efx_link_change_ev_t)(
1721	__in_opt	void *arg,
1722	__in		efx_link_mode_t	link_mode);
1723
1724#if EFSYS_OPT_MON_STATS
1725
1726typedef __checkReturn	boolean_t
1727(*efx_monitor_ev_t)(
1728	__in_opt	void *arg,
1729	__in		efx_mon_stat_t id,
1730	__in		efx_mon_stat_value_t value);
1731
1732#endif	/* EFSYS_OPT_MON_STATS */
1733
1734#if EFSYS_OPT_MAC_STATS
1735
1736typedef __checkReturn	boolean_t
1737(*efx_mac_stats_ev_t)(
1738	__in_opt	void *arg,
1739	__in		uint32_t generation
1740	);
1741
1742#endif	/* EFSYS_OPT_MAC_STATS */
1743
1744typedef struct efx_ev_callbacks_s {
1745	efx_initialized_ev_t		eec_initialized;
1746	efx_rx_ev_t			eec_rx;
1747	efx_tx_ev_t			eec_tx;
1748	efx_exception_ev_t		eec_exception;
1749	efx_rxq_flush_done_ev_t		eec_rxq_flush_done;
1750	efx_rxq_flush_failed_ev_t	eec_rxq_flush_failed;
1751	efx_txq_flush_done_ev_t		eec_txq_flush_done;
1752	efx_software_ev_t		eec_software;
1753	efx_sram_ev_t			eec_sram;
1754	efx_wake_up_ev_t		eec_wake_up;
1755	efx_timer_ev_t			eec_timer;
1756	efx_link_change_ev_t		eec_link_change;
1757#if EFSYS_OPT_MON_STATS
1758	efx_monitor_ev_t		eec_monitor;
1759#endif	/* EFSYS_OPT_MON_STATS */
1760#if EFSYS_OPT_MAC_STATS
1761	efx_mac_stats_ev_t		eec_mac_stats;
1762#endif	/* EFSYS_OPT_MAC_STATS */
1763} efx_ev_callbacks_t;
1764
1765extern	__checkReturn	boolean_t
1766efx_ev_qpending(
1767	__in		efx_evq_t *eep,
1768	__in		unsigned int count);
1769
1770#if EFSYS_OPT_EV_PREFETCH
1771
1772extern			void
1773efx_ev_qprefetch(
1774	__in		efx_evq_t *eep,
1775	__in		unsigned int count);
1776
1777#endif	/* EFSYS_OPT_EV_PREFETCH */
1778
1779extern			void
1780efx_ev_qpoll(
1781	__in		efx_evq_t *eep,
1782	__inout		unsigned int *countp,
1783	__in		const efx_ev_callbacks_t *eecp,
1784	__in_opt	void *arg);
1785
1786extern	__checkReturn	efx_rc_t
1787efx_ev_usecs_to_ticks(
1788	__in		efx_nic_t *enp,
1789	__in		unsigned int usecs,
1790	__out		unsigned int *ticksp);
1791
1792extern	__checkReturn	efx_rc_t
1793efx_ev_qmoderate(
1794	__in		efx_evq_t *eep,
1795	__in		unsigned int us);
1796
1797extern	__checkReturn	efx_rc_t
1798efx_ev_qprime(
1799	__in		efx_evq_t *eep,
1800	__in		unsigned int count);
1801
1802#if EFSYS_OPT_QSTATS
1803
1804#if EFSYS_OPT_NAMES
1805
1806extern		const char *
1807efx_ev_qstat_name(
1808	__in	efx_nic_t *enp,
1809	__in	unsigned int id);
1810
1811#endif	/* EFSYS_OPT_NAMES */
1812
1813extern					void
1814efx_ev_qstats_update(
1815	__in				efx_evq_t *eep,
1816	__inout_ecount(EV_NQSTATS)	efsys_stat_t *stat);
1817
1818#endif	/* EFSYS_OPT_QSTATS */
1819
1820extern		void
1821efx_ev_qdestroy(
1822	__in	efx_evq_t *eep);
1823
1824/* RX */
1825
1826extern	__checkReturn	efx_rc_t
1827efx_rx_init(
1828	__inout		efx_nic_t *enp);
1829
1830extern		void
1831efx_rx_fini(
1832	__in		efx_nic_t *enp);
1833
1834#if EFSYS_OPT_RX_SCATTER
1835	__checkReturn	efx_rc_t
1836efx_rx_scatter_enable(
1837	__in		efx_nic_t *enp,
1838	__in		unsigned int buf_size);
1839#endif	/* EFSYS_OPT_RX_SCATTER */
1840
1841/* Handle to represent use of the default RSS context. */
1842#define	EFX_RSS_CONTEXT_DEFAULT	0xffffffff
1843
1844#if EFSYS_OPT_RX_SCALE
1845
1846typedef enum efx_rx_hash_alg_e {
1847	EFX_RX_HASHALG_LFSR = 0,
1848	EFX_RX_HASHALG_TOEPLITZ
1849} efx_rx_hash_alg_t;
1850
1851#define	EFX_RX_HASH_IPV4	(1U << 0)
1852#define	EFX_RX_HASH_TCPIPV4	(1U << 1)
1853#define	EFX_RX_HASH_IPV6	(1U << 2)
1854#define	EFX_RX_HASH_TCPIPV6	(1U << 3)
1855
1856typedef unsigned int efx_rx_hash_type_t;
1857
1858typedef enum efx_rx_hash_support_e {
1859	EFX_RX_HASH_UNAVAILABLE = 0,	/* Hardware hash not inserted */
1860	EFX_RX_HASH_AVAILABLE		/* Insert hash with/without RSS */
1861} efx_rx_hash_support_t;
1862
1863#define	EFX_RSS_TBL_SIZE	128	/* Rows in RX indirection table */
1864#define	EFX_MAXRSS		64	/* RX indirection entry range */
1865#define	EFX_MAXRSS_LEGACY	16	/* See bug16611 and bug17213 */
1866
1867typedef enum efx_rx_scale_support_e {
1868	EFX_RX_SCALE_UNAVAILABLE = 0,	/* Not supported */
1869	EFX_RX_SCALE_EXCLUSIVE,		/* Writable key/indirection table */
1870	EFX_RX_SCALE_SHARED		/* Read-only key/indirection table */
1871} efx_rx_scale_support_t;
1872
1873extern	__checkReturn	efx_rc_t
1874efx_rx_hash_support_get(
1875	__in		efx_nic_t *enp,
1876	__out		efx_rx_hash_support_t *supportp);
1877
1878
1879extern	__checkReturn	efx_rc_t
1880efx_rx_scale_support_get(
1881	__in		efx_nic_t *enp,
1882	__out		efx_rx_scale_support_t *supportp);
1883
1884extern	__checkReturn	efx_rc_t
1885efx_rx_scale_mode_set(
1886	__in	efx_nic_t *enp,
1887	__in	efx_rx_hash_alg_t alg,
1888	__in	efx_rx_hash_type_t type,
1889	__in	boolean_t insert);
1890
1891extern	__checkReturn	efx_rc_t
1892efx_rx_scale_tbl_set(
1893	__in		efx_nic_t *enp,
1894	__in_ecount(n)	unsigned int *table,
1895	__in		size_t n);
1896
1897extern	__checkReturn	efx_rc_t
1898efx_rx_scale_key_set(
1899	__in		efx_nic_t *enp,
1900	__in_ecount(n)	uint8_t *key,
1901	__in		size_t n);
1902
1903extern	__checkReturn	uint32_t
1904efx_pseudo_hdr_hash_get(
1905	__in		efx_rxq_t *erp,
1906	__in		efx_rx_hash_alg_t func,
1907	__in		uint8_t *buffer);
1908
1909#endif	/* EFSYS_OPT_RX_SCALE */
1910
1911extern	__checkReturn	efx_rc_t
1912efx_pseudo_hdr_pkt_length_get(
1913	__in		efx_rxq_t *erp,
1914	__in		uint8_t *buffer,
1915	__out		uint16_t *pkt_lengthp);
1916
1917#define	EFX_RXQ_MAXNDESCS		4096
1918#define	EFX_RXQ_MINNDESCS		512
1919
1920#define	EFX_RXQ_SIZE(_ndescs)		((_ndescs) * sizeof (efx_qword_t))
1921#define	EFX_RXQ_NBUFS(_ndescs)		(EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
1922#define	EFX_RXQ_LIMIT(_ndescs)		((_ndescs) - 16)
1923#define	EFX_RXQ_DC_NDESCS(_dcsize)	(8 << _dcsize)
1924
1925typedef enum efx_rxq_type_e {
1926	EFX_RXQ_TYPE_DEFAULT,
1927	EFX_RXQ_TYPE_SCATTER,
1928	EFX_RXQ_NTYPES
1929} efx_rxq_type_t;
1930
1931extern	__checkReturn	efx_rc_t
1932efx_rx_qcreate(
1933	__in		efx_nic_t *enp,
1934	__in		unsigned int index,
1935	__in		unsigned int label,
1936	__in		efx_rxq_type_t type,
1937	__in		efsys_mem_t *esmp,
1938	__in		size_t n,
1939	__in		uint32_t id,
1940	__in		efx_evq_t *eep,
1941	__deref_out	efx_rxq_t **erpp);
1942
1943typedef struct efx_buffer_s {
1944	efsys_dma_addr_t	eb_addr;
1945	size_t			eb_size;
1946	boolean_t		eb_eop;
1947} efx_buffer_t;
1948
1949typedef struct efx_desc_s {
1950	efx_qword_t ed_eq;
1951} efx_desc_t;
1952
1953extern			void
1954efx_rx_qpost(
1955	__in		efx_rxq_t *erp,
1956	__in_ecount(n)	efsys_dma_addr_t *addrp,
1957	__in		size_t size,
1958	__in		unsigned int n,
1959	__in		unsigned int completed,
1960	__in		unsigned int added);
1961
1962extern		void
1963efx_rx_qpush(
1964	__in	efx_rxq_t *erp,
1965	__in	unsigned int added,
1966	__inout	unsigned int *pushedp);
1967
1968extern	__checkReturn	efx_rc_t
1969efx_rx_qflush(
1970	__in	efx_rxq_t *erp);
1971
1972extern		void
1973efx_rx_qenable(
1974	__in	efx_rxq_t *erp);
1975
1976extern		void
1977efx_rx_qdestroy(
1978	__in	efx_rxq_t *erp);
1979
1980/* TX */
1981
1982typedef struct efx_txq_s	efx_txq_t;
1983
1984#if EFSYS_OPT_QSTATS
1985
1986/* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */
1987typedef enum efx_tx_qstat_e {
1988	TX_POST,
1989	TX_POST_PIO,
1990	TX_NQSTATS
1991} efx_tx_qstat_t;
1992
1993/* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */
1994
1995#endif	/* EFSYS_OPT_QSTATS */
1996
1997extern	__checkReturn	efx_rc_t
1998efx_tx_init(
1999	__in		efx_nic_t *enp);
2000
2001extern		void
2002efx_tx_fini(
2003	__in	efx_nic_t *enp);
2004
2005#define	EFX_TXQ_MINNDESCS		512
2006
2007#define	EFX_TXQ_SIZE(_ndescs)		((_ndescs) * sizeof (efx_qword_t))
2008#define	EFX_TXQ_NBUFS(_ndescs)		(EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
2009#define	EFX_TXQ_LIMIT(_ndescs)		((_ndescs) - 16)
2010#define	EFX_TXQ_DC_NDESCS(_dcsize)	(8 << _dcsize)
2011
2012#define	EFX_TXQ_MAX_BUFS 8 /* Maximum independent of EFX_BUG35388_WORKAROUND. */
2013
2014#define	EFX_TXQ_CKSUM_IPV4		0x0001
2015#define	EFX_TXQ_CKSUM_TCPUDP		0x0002
2016#define	EFX_TXQ_FATSOV2			0x0004
2017#define	EFX_TXQ_CKSUM_INNER_IPV4	0x0008
2018#define	EFX_TXQ_CKSUM_INNER_TCPUDP	0x0010
2019
2020extern	__checkReturn	efx_rc_t
2021efx_tx_qcreate(
2022	__in		efx_nic_t *enp,
2023	__in		unsigned int index,
2024	__in		unsigned int label,
2025	__in		efsys_mem_t *esmp,
2026	__in		size_t n,
2027	__in		uint32_t id,
2028	__in		uint16_t flags,
2029	__in		efx_evq_t *eep,
2030	__deref_out	efx_txq_t **etpp,
2031	__out		unsigned int *addedp);
2032
2033extern	__checkReturn	efx_rc_t
2034efx_tx_qpost(
2035	__in		efx_txq_t *etp,
2036	__in_ecount(n)	efx_buffer_t *eb,
2037	__in		unsigned int n,
2038	__in		unsigned int completed,
2039	__inout		unsigned int *addedp);
2040
2041extern	__checkReturn	efx_rc_t
2042efx_tx_qpace(
2043	__in		efx_txq_t *etp,
2044	__in		unsigned int ns);
2045
2046extern			void
2047efx_tx_qpush(
2048	__in		efx_txq_t *etp,
2049	__in		unsigned int added,
2050	__in		unsigned int pushed);
2051
2052extern	__checkReturn	efx_rc_t
2053efx_tx_qflush(
2054	__in		efx_txq_t *etp);
2055
2056extern			void
2057efx_tx_qenable(
2058	__in		efx_txq_t *etp);
2059
2060extern	__checkReturn	efx_rc_t
2061efx_tx_qpio_enable(
2062	__in		efx_txq_t *etp);
2063
2064extern			void
2065efx_tx_qpio_disable(
2066	__in		efx_txq_t *etp);
2067
2068extern	__checkReturn	efx_rc_t
2069efx_tx_qpio_write(
2070	__in			efx_txq_t *etp,
2071	__in_ecount(buf_length)	uint8_t *buffer,
2072	__in			size_t buf_length,
2073	__in			size_t pio_buf_offset);
2074
2075extern	__checkReturn	efx_rc_t
2076efx_tx_qpio_post(
2077	__in			efx_txq_t *etp,
2078	__in			size_t pkt_length,
2079	__in			unsigned int completed,
2080	__inout			unsigned int *addedp);
2081
2082extern	__checkReturn	efx_rc_t
2083efx_tx_qdesc_post(
2084	__in		efx_txq_t *etp,
2085	__in_ecount(n)	efx_desc_t *ed,
2086	__in		unsigned int n,
2087	__in		unsigned int completed,
2088	__inout		unsigned int *addedp);
2089
2090extern	void
2091efx_tx_qdesc_dma_create(
2092	__in	efx_txq_t *etp,
2093	__in	efsys_dma_addr_t addr,
2094	__in	size_t size,
2095	__in	boolean_t eop,
2096	__out	efx_desc_t *edp);
2097
2098extern	void
2099efx_tx_qdesc_tso_create(
2100	__in	efx_txq_t *etp,
2101	__in	uint16_t ipv4_id,
2102	__in	uint32_t tcp_seq,
2103	__in	uint8_t  tcp_flags,
2104	__out	efx_desc_t *edp);
2105
2106/* Number of FATSOv2 option descriptors */
2107#define	EFX_TX_FATSOV2_OPT_NDESCS		2
2108
2109/* Maximum number of DMA segments per TSO packet (not superframe) */
2110#define	EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX	24
2111
2112extern	void
2113efx_tx_qdesc_tso2_create(
2114	__in			efx_txq_t *etp,
2115	__in			uint16_t ipv4_id,
2116	__in			uint32_t tcp_seq,
2117	__in			uint16_t tcp_mss,
2118	__out_ecount(count)	efx_desc_t *edp,
2119	__in			int count);
2120
2121extern	void
2122efx_tx_qdesc_vlantci_create(
2123	__in	efx_txq_t *etp,
2124	__in	uint16_t tci,
2125	__out	efx_desc_t *edp);
2126
2127extern	void
2128efx_tx_qdesc_checksum_create(
2129	__in	efx_txq_t *etp,
2130	__in	uint16_t flags,
2131	__out	efx_desc_t *edp);
2132
2133#if EFSYS_OPT_QSTATS
2134
2135#if EFSYS_OPT_NAMES
2136
2137extern		const char *
2138efx_tx_qstat_name(
2139	__in	efx_nic_t *etp,
2140	__in	unsigned int id);
2141
2142#endif	/* EFSYS_OPT_NAMES */
2143
2144extern					void
2145efx_tx_qstats_update(
2146	__in				efx_txq_t *etp,
2147	__inout_ecount(TX_NQSTATS)	efsys_stat_t *stat);
2148
2149#endif	/* EFSYS_OPT_QSTATS */
2150
2151extern		void
2152efx_tx_qdestroy(
2153	__in	efx_txq_t *etp);
2154
2155
2156/* FILTER */
2157
2158#if EFSYS_OPT_FILTER
2159
2160#define	EFX_ETHER_TYPE_IPV4 0x0800
2161#define	EFX_ETHER_TYPE_IPV6 0x86DD
2162
2163#define	EFX_IPPROTO_TCP 6
2164#define	EFX_IPPROTO_UDP 17
2165#define	EFX_IPPROTO_GRE	47
2166
2167/* Use RSS to spread across multiple queues */
2168#define	EFX_FILTER_FLAG_RX_RSS		0x01
2169/* Enable RX scatter */
2170#define	EFX_FILTER_FLAG_RX_SCATTER	0x02
2171/*
2172 * Override an automatic filter (priority EFX_FILTER_PRI_AUTO).
2173 * May only be set by the filter implementation for each type.
2174 * A removal request will restore the automatic filter in its place.
2175 */
2176#define	EFX_FILTER_FLAG_RX_OVER_AUTO	0x04
2177/* Filter is for RX */
2178#define	EFX_FILTER_FLAG_RX		0x08
2179/* Filter is for TX */
2180#define	EFX_FILTER_FLAG_TX		0x10
2181
2182typedef uint8_t efx_filter_flags_t;
2183
2184/*
2185 * Flags which specify the fields to match on. The values are the same as in the
2186 * MC_CMD_FILTER_OP/MC_CMD_FILTER_OP_EXT commands.
2187 */
2188
2189/* Match by remote IP host address */
2190#define	EFX_FILTER_MATCH_REM_HOST		0x00000001
2191/* Match by local IP host address */
2192#define	EFX_FILTER_MATCH_LOC_HOST		0x00000002
2193/* Match by remote MAC address */
2194#define	EFX_FILTER_MATCH_REM_MAC		0x00000004
2195/* Match by remote TCP/UDP port */
2196#define	EFX_FILTER_MATCH_REM_PORT		0x00000008
2197/* Match by remote TCP/UDP port */
2198#define	EFX_FILTER_MATCH_LOC_MAC		0x00000010
2199/* Match by local TCP/UDP port */
2200#define	EFX_FILTER_MATCH_LOC_PORT		0x00000020
2201/* Match by Ether-type */
2202#define	EFX_FILTER_MATCH_ETHER_TYPE		0x00000040
2203/* Match by inner VLAN ID */
2204#define	EFX_FILTER_MATCH_INNER_VID		0x00000080
2205/* Match by outer VLAN ID */
2206#define	EFX_FILTER_MATCH_OUTER_VID		0x00000100
2207/* Match by IP transport protocol */
2208#define	EFX_FILTER_MATCH_IP_PROTO		0x00000200
2209/* For encapsulated packets, match all multicast inner frames */
2210#define	EFX_FILTER_MATCH_IFRM_UNKNOWN_MCAST_DST	0x01000000
2211/* For encapsulated packets, match all unicast inner frames */
2212#define	EFX_FILTER_MATCH_IFRM_UNKNOWN_UCAST_DST	0x02000000
2213/* Match otherwise-unmatched multicast and broadcast packets */
2214#define	EFX_FILTER_MATCH_UNKNOWN_MCAST_DST	0x40000000
2215/* Match otherwise-unmatched unicast packets */
2216#define	EFX_FILTER_MATCH_UNKNOWN_UCAST_DST	0x80000000
2217
2218typedef uint32_t efx_filter_match_flags_t;
2219
2220typedef enum efx_filter_priority_s {
2221	EFX_FILTER_PRI_HINT = 0,	/* Performance hint */
2222	EFX_FILTER_PRI_AUTO,		/* Automatic filter based on device
2223					 * address list or hardware
2224					 * requirements. This may only be used
2225					 * by the filter implementation for
2226					 * each NIC type. */
2227	EFX_FILTER_PRI_MANUAL,		/* Manually configured filter */
2228	EFX_FILTER_PRI_REQUIRED,	/* Required for correct behaviour of the
2229					 * client (e.g. SR-IOV, HyperV VMQ etc.)
2230					 */
2231} efx_filter_priority_t;
2232
2233/*
2234 * FIXME: All these fields are assumed to be in little-endian byte order.
2235 * It may be better for some to be big-endian. See bug42804.
2236 */
2237
2238typedef struct efx_filter_spec_s {
2239	efx_filter_match_flags_t	efs_match_flags;
2240	uint8_t				efs_priority;
2241	efx_filter_flags_t		efs_flags;
2242	uint16_t			efs_dmaq_id;
2243	uint32_t			efs_rss_context;
2244	uint16_t			efs_outer_vid;
2245	uint16_t			efs_inner_vid;
2246	uint8_t				efs_loc_mac[EFX_MAC_ADDR_LEN];
2247	uint8_t				efs_rem_mac[EFX_MAC_ADDR_LEN];
2248	uint16_t			efs_ether_type;
2249	uint8_t				efs_ip_proto;
2250	efx_tunnel_protocol_t		efs_encap_type;
2251	uint16_t			efs_loc_port;
2252	uint16_t			efs_rem_port;
2253	efx_oword_t			efs_rem_host;
2254	efx_oword_t			efs_loc_host;
2255} efx_filter_spec_t;
2256
2257
2258/* Default values for use in filter specifications */
2259#define	EFX_FILTER_SPEC_RX_DMAQ_ID_DROP		0xfff
2260#define	EFX_FILTER_SPEC_VID_UNSPEC		0xffff
2261
2262extern	__checkReturn	efx_rc_t
2263efx_filter_init(
2264	__in		efx_nic_t *enp);
2265
2266extern			void
2267efx_filter_fini(
2268	__in		efx_nic_t *enp);
2269
2270extern	__checkReturn	efx_rc_t
2271efx_filter_insert(
2272	__in		efx_nic_t *enp,
2273	__inout		efx_filter_spec_t *spec);
2274
2275extern	__checkReturn	efx_rc_t
2276efx_filter_remove(
2277	__in		efx_nic_t *enp,
2278	__inout		efx_filter_spec_t *spec);
2279
2280extern	__checkReturn	efx_rc_t
2281efx_filter_restore(
2282	__in		efx_nic_t *enp);
2283
2284extern	__checkReturn	efx_rc_t
2285efx_filter_supported_filters(
2286	__in				efx_nic_t *enp,
2287	__out_ecount(buffer_length)	uint32_t *buffer,
2288	__in				size_t buffer_length,
2289	__out				size_t *list_lengthp);
2290
2291extern			void
2292efx_filter_spec_init_rx(
2293	__out		efx_filter_spec_t *spec,
2294	__in		efx_filter_priority_t priority,
2295	__in		efx_filter_flags_t flags,
2296	__in		efx_rxq_t *erp);
2297
2298extern			void
2299efx_filter_spec_init_tx(
2300	__out		efx_filter_spec_t *spec,
2301	__in		efx_txq_t *etp);
2302
2303extern	__checkReturn	efx_rc_t
2304efx_filter_spec_set_ipv4_local(
2305	__inout		efx_filter_spec_t *spec,
2306	__in		uint8_t proto,
2307	__in		uint32_t host,
2308	__in		uint16_t port);
2309
2310extern	__checkReturn	efx_rc_t
2311efx_filter_spec_set_ipv4_full(
2312	__inout		efx_filter_spec_t *spec,
2313	__in		uint8_t proto,
2314	__in		uint32_t lhost,
2315	__in		uint16_t lport,
2316	__in		uint32_t rhost,
2317	__in		uint16_t rport);
2318
2319extern	__checkReturn	efx_rc_t
2320efx_filter_spec_set_eth_local(
2321	__inout		efx_filter_spec_t *spec,
2322	__in		uint16_t vid,
2323	__in		const uint8_t *addr);
2324
2325extern			void
2326efx_filter_spec_set_ether_type(
2327	__inout		efx_filter_spec_t *spec,
2328	__in		uint16_t ether_type);
2329
2330extern	__checkReturn	efx_rc_t
2331efx_filter_spec_set_uc_def(
2332	__inout		efx_filter_spec_t *spec);
2333
2334extern	__checkReturn	efx_rc_t
2335efx_filter_spec_set_mc_def(
2336	__inout		efx_filter_spec_t *spec);
2337
2338typedef enum efx_filter_inner_frame_match_e {
2339	EFX_FILTER_INNER_FRAME_MATCH_OTHER = 0,
2340	EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_MCAST_DST,
2341	EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_UCAST_DST
2342} efx_filter_inner_frame_match_t;
2343
2344extern	__checkReturn	efx_rc_t
2345efx_filter_spec_set_encap_type(
2346	__inout		efx_filter_spec_t *spec,
2347	__in		efx_tunnel_protocol_t encap_type,
2348	__in		efx_filter_inner_frame_match_t inner_frame_match);
2349
2350
2351#endif	/* EFSYS_OPT_FILTER */
2352
2353/* HASH */
2354
2355extern	__checkReturn		uint32_t
2356efx_hash_dwords(
2357	__in_ecount(count)	uint32_t const *input,
2358	__in			size_t count,
2359	__in			uint32_t init);
2360
2361extern	__checkReturn		uint32_t
2362efx_hash_bytes(
2363	__in_ecount(length)	uint8_t const *input,
2364	__in			size_t length,
2365	__in			uint32_t init);
2366
2367#if EFSYS_OPT_LICENSING
2368
2369/* LICENSING */
2370
2371typedef struct efx_key_stats_s {
2372	uint32_t	eks_valid;
2373	uint32_t	eks_invalid;
2374	uint32_t	eks_blacklisted;
2375	uint32_t	eks_unverifiable;
2376	uint32_t	eks_wrong_node;
2377	uint32_t	eks_licensed_apps_lo;
2378	uint32_t	eks_licensed_apps_hi;
2379	uint32_t	eks_licensed_features_lo;
2380	uint32_t	eks_licensed_features_hi;
2381} efx_key_stats_t;
2382
2383extern	__checkReturn		efx_rc_t
2384efx_lic_init(
2385	__in			efx_nic_t *enp);
2386
2387extern				void
2388efx_lic_fini(
2389	__in			efx_nic_t *enp);
2390
2391extern	__checkReturn	boolean_t
2392efx_lic_check_support(
2393	__in			efx_nic_t *enp);
2394
2395extern	__checkReturn	efx_rc_t
2396efx_lic_update_licenses(
2397	__in		efx_nic_t *enp);
2398
2399extern	__checkReturn	efx_rc_t
2400efx_lic_get_key_stats(
2401	__in		efx_nic_t *enp,
2402	__out		efx_key_stats_t *ksp);
2403
2404extern	__checkReturn	efx_rc_t
2405efx_lic_app_state(
2406	__in		efx_nic_t *enp,
2407	__in		uint64_t app_id,
2408	__out		boolean_t *licensedp);
2409
2410extern	__checkReturn	efx_rc_t
2411efx_lic_get_id(
2412	__in		efx_nic_t *enp,
2413	__in		size_t buffer_size,
2414	__out		uint32_t *typep,
2415	__out		size_t *lengthp,
2416	__out_opt	uint8_t *bufferp);
2417
2418
2419extern	__checkReturn		efx_rc_t
2420efx_lic_find_start(
2421	__in			efx_nic_t *enp,
2422	__in_bcount(buffer_size)
2423				caddr_t bufferp,
2424	__in			size_t buffer_size,
2425	__out			uint32_t *startp
2426	);
2427
2428extern	__checkReturn		efx_rc_t
2429efx_lic_find_end(
2430	__in			efx_nic_t *enp,
2431	__in_bcount(buffer_size)
2432				caddr_t bufferp,
2433	__in			size_t buffer_size,
2434	__in			uint32_t offset,
2435	__out			uint32_t *endp
2436	);
2437
2438extern	__checkReturn	__success(return != B_FALSE)	boolean_t
2439efx_lic_find_key(
2440	__in			efx_nic_t *enp,
2441	__in_bcount(buffer_size)
2442				caddr_t bufferp,
2443	__in			size_t buffer_size,
2444	__in			uint32_t offset,
2445	__out			uint32_t *startp,
2446	__out			uint32_t *lengthp
2447	);
2448
2449extern	__checkReturn	__success(return != B_FALSE)	boolean_t
2450efx_lic_validate_key(
2451	__in			efx_nic_t *enp,
2452	__in_bcount(length)	caddr_t keyp,
2453	__in			uint32_t length
2454	);
2455
2456extern	__checkReturn		efx_rc_t
2457efx_lic_read_key(
2458	__in			efx_nic_t *enp,
2459	__in_bcount(buffer_size)
2460				caddr_t bufferp,
2461	__in			size_t buffer_size,
2462	__in			uint32_t offset,
2463	__in			uint32_t length,
2464	__out_bcount_part(key_max_size, *lengthp)
2465				caddr_t keyp,
2466	__in			size_t key_max_size,
2467	__out			uint32_t *lengthp
2468	);
2469
2470extern	__checkReturn		efx_rc_t
2471efx_lic_write_key(
2472	__in			efx_nic_t *enp,
2473	__in_bcount(buffer_size)
2474				caddr_t bufferp,
2475	__in			size_t buffer_size,
2476	__in			uint32_t offset,
2477	__in_bcount(length)	caddr_t keyp,
2478	__in			uint32_t length,
2479	__out			uint32_t *lengthp
2480	);
2481
2482	__checkReturn		efx_rc_t
2483efx_lic_delete_key(
2484	__in			efx_nic_t *enp,
2485	__in_bcount(buffer_size)
2486				caddr_t bufferp,
2487	__in			size_t buffer_size,
2488	__in			uint32_t offset,
2489	__in			uint32_t length,
2490	__in			uint32_t end,
2491	__out			uint32_t *deltap
2492	);
2493
2494extern	__checkReturn		efx_rc_t
2495efx_lic_create_partition(
2496	__in			efx_nic_t *enp,
2497	__in_bcount(buffer_size)
2498				caddr_t bufferp,
2499	__in			size_t buffer_size
2500	);
2501
2502extern	__checkReturn		efx_rc_t
2503efx_lic_finish_partition(
2504	__in			efx_nic_t *enp,
2505	__in_bcount(buffer_size)
2506				caddr_t bufferp,
2507	__in			size_t buffer_size
2508	);
2509
2510#endif	/* EFSYS_OPT_LICENSING */
2511
2512
2513
2514#ifdef	__cplusplus
2515}
2516#endif
2517
2518#endif	/* _SYS_EFX_H */
2519