efx.h revision 342433 
1/*-
2 * Copyright (c) 2006-2016 Solarflare Communications Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,
9 *    this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 *    this list of conditions and the following disclaimer in the documentation
12 *    and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
29 *
30 * $FreeBSD: stable/11/sys/dev/sfxge/common/efx.h 342433 2018-12-25 07:12:49Z arybchik $
31 */
32
33#ifndef	_SYS_EFX_H
34#define	_SYS_EFX_H
35
36#include "efsys.h"
37#include "efx_check.h"
38#include "efx_phy_ids.h"
39
40#ifdef	__cplusplus
41extern "C" {
42#endif
43
44#define	EFX_STATIC_ASSERT(_cond)		\
45	((void)sizeof(char[(_cond) ? 1 : -1]))
46
47#define	EFX_ARRAY_SIZE(_array)			\
48	(sizeof(_array) / sizeof((_array)[0]))
49
50#define	EFX_FIELD_OFFSET(_type, _field)		\
51	((size_t) &(((_type *)0)->_field))
52
53/* Return codes */
54
55typedef __success(return == 0) int efx_rc_t;
56
57
58/* Chip families */
59
60typedef enum efx_family_e {
61	EFX_FAMILY_INVALID,
62	EFX_FAMILY_FALCON,	/* Obsolete and not supported */
63	EFX_FAMILY_SIENA,
64	EFX_FAMILY_HUNTINGTON,
65	EFX_FAMILY_MEDFORD,
66	EFX_FAMILY_NTYPES
67} efx_family_t;
68
69extern	__checkReturn	efx_rc_t
70efx_family(
71	__in		uint16_t venid,
72	__in		uint16_t devid,
73	__out		efx_family_t *efp);
74
75
76#define	EFX_PCI_VENID_SFC			0x1924
77
78#define	EFX_PCI_DEVID_FALCON			0x0710	/* SFC4000 */
79
80#define	EFX_PCI_DEVID_BETHPAGE			0x0803	/* SFC9020 */
81#define	EFX_PCI_DEVID_SIENA			0x0813	/* SFL9021 */
82#define	EFX_PCI_DEVID_SIENA_F1_UNINIT		0x0810
83
84#define	EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT	0x0901
85#define	EFX_PCI_DEVID_FARMINGDALE		0x0903	/* SFC9120 PF */
86#define	EFX_PCI_DEVID_GREENPORT			0x0923	/* SFC9140 PF */
87
88#define	EFX_PCI_DEVID_FARMINGDALE_VF		0x1903	/* SFC9120 VF */
89#define	EFX_PCI_DEVID_GREENPORT_VF		0x1923	/* SFC9140 VF */
90
91#define	EFX_PCI_DEVID_MEDFORD_PF_UNINIT		0x0913
92#define	EFX_PCI_DEVID_MEDFORD			0x0A03	/* SFC9240 PF */
93#define	EFX_PCI_DEVID_MEDFORD_VF		0x1A03	/* SFC9240 VF */
94
95#define	EFX_MEM_BAR	2
96
97/* Error codes */
98
99enum {
100	EFX_ERR_INVALID,
101	EFX_ERR_SRAM_OOB,
102	EFX_ERR_BUFID_DC_OOB,
103	EFX_ERR_MEM_PERR,
104	EFX_ERR_RBUF_OWN,
105	EFX_ERR_TBUF_OWN,
106	EFX_ERR_RDESQ_OWN,
107	EFX_ERR_TDESQ_OWN,
108	EFX_ERR_EVQ_OWN,
109	EFX_ERR_EVFF_OFLO,
110	EFX_ERR_ILL_ADDR,
111	EFX_ERR_SRAM_PERR,
112	EFX_ERR_NCODES
113};
114
115/* Calculate the IEEE 802.3 CRC32 of a MAC addr */
116extern	__checkReturn		uint32_t
117efx_crc32_calculate(
118	__in			uint32_t crc_init,
119	__in_ecount(length)	uint8_t const *input,
120	__in			int length);
121
122
123/* Type prototypes */
124
125typedef struct efx_rxq_s	efx_rxq_t;
126
127/* NIC */
128
129typedef struct efx_nic_s	efx_nic_t;
130
131extern	__checkReturn	efx_rc_t
132efx_nic_create(
133	__in		efx_family_t family,
134	__in		efsys_identifier_t *esip,
135	__in		efsys_bar_t *esbp,
136	__in		efsys_lock_t *eslp,
137	__deref_out	efx_nic_t **enpp);
138
139extern	__checkReturn	efx_rc_t
140efx_nic_probe(
141	__in		efx_nic_t *enp);
142
143extern	__checkReturn	efx_rc_t
144efx_nic_init(
145	__in		efx_nic_t *enp);
146
147extern	__checkReturn	efx_rc_t
148efx_nic_reset(
149	__in		efx_nic_t *enp);
150
151#if EFSYS_OPT_DIAG
152
153extern	__checkReturn	efx_rc_t
154efx_nic_register_test(
155	__in		efx_nic_t *enp);
156
157#endif	/* EFSYS_OPT_DIAG */
158
159extern		void
160efx_nic_fini(
161	__in		efx_nic_t *enp);
162
163extern		void
164efx_nic_unprobe(
165	__in		efx_nic_t *enp);
166
167extern		void
168efx_nic_destroy(
169	__in	efx_nic_t *enp);
170
171#define	EFX_PCIE_LINK_SPEED_GEN1		1
172#define	EFX_PCIE_LINK_SPEED_GEN2		2
173#define	EFX_PCIE_LINK_SPEED_GEN3		3
174
175typedef enum efx_pcie_link_performance_e {
176	EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH,
177	EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH,
178	EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY,
179	EFX_PCIE_LINK_PERFORMANCE_OPTIMAL
180} efx_pcie_link_performance_t;
181
182extern	__checkReturn	efx_rc_t
183efx_nic_calculate_pcie_link_bandwidth(
184	__in		uint32_t pcie_link_width,
185	__in		uint32_t pcie_link_gen,
186	__out		uint32_t *bandwidth_mbpsp);
187
188extern	__checkReturn	efx_rc_t
189efx_nic_check_pcie_link_speed(
190	__in		efx_nic_t *enp,
191	__in		uint32_t pcie_link_width,
192	__in		uint32_t pcie_link_gen,
193	__out		efx_pcie_link_performance_t *resultp);
194
195#if EFSYS_OPT_MCDI
196
197#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
198/* Huntington and Medford require MCDIv2 commands */
199#define	WITH_MCDI_V2 1
200#endif
201
202typedef struct efx_mcdi_req_s efx_mcdi_req_t;
203
204typedef enum efx_mcdi_exception_e {
205	EFX_MCDI_EXCEPTION_MC_REBOOT,
206	EFX_MCDI_EXCEPTION_MC_BADASSERT,
207} efx_mcdi_exception_t;
208
209#if EFSYS_OPT_MCDI_LOGGING
210typedef enum efx_log_msg_e {
211	EFX_LOG_INVALID,
212	EFX_LOG_MCDI_REQUEST,
213	EFX_LOG_MCDI_RESPONSE,
214} efx_log_msg_t;
215#endif /* EFSYS_OPT_MCDI_LOGGING */
216
217typedef struct efx_mcdi_transport_s {
218	void		*emt_context;
219	efsys_mem_t	*emt_dma_mem;
220	void		(*emt_execute)(void *, efx_mcdi_req_t *);
221	void		(*emt_ev_cpl)(void *);
222	void		(*emt_exception)(void *, efx_mcdi_exception_t);
223#if EFSYS_OPT_MCDI_LOGGING
224	void		(*emt_logger)(void *, efx_log_msg_t,
225					void *, size_t, void *, size_t);
226#endif /* EFSYS_OPT_MCDI_LOGGING */
227#if EFSYS_OPT_MCDI_PROXY_AUTH
228	void		(*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t);
229#endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
230} efx_mcdi_transport_t;
231
232extern	__checkReturn	efx_rc_t
233efx_mcdi_init(
234	__in		efx_nic_t *enp,
235	__in		const efx_mcdi_transport_t *mtp);
236
237extern	__checkReturn	efx_rc_t
238efx_mcdi_reboot(
239	__in		efx_nic_t *enp);
240
241			void
242efx_mcdi_new_epoch(
243	__in		efx_nic_t *enp);
244
245extern			void
246efx_mcdi_get_timeout(
247	__in		efx_nic_t *enp,
248	__in		efx_mcdi_req_t *emrp,
249	__out		uint32_t *usec_timeoutp);
250
251extern			void
252efx_mcdi_request_start(
253	__in		efx_nic_t *enp,
254	__in		efx_mcdi_req_t *emrp,
255	__in		boolean_t ev_cpl);
256
257extern	__checkReturn	boolean_t
258efx_mcdi_request_poll(
259	__in		efx_nic_t *enp);
260
261extern	__checkReturn	boolean_t
262efx_mcdi_request_abort(
263	__in		efx_nic_t *enp);
264
265extern			void
266efx_mcdi_fini(
267	__in		efx_nic_t *enp);
268
269#endif	/* EFSYS_OPT_MCDI */
270
271/* INTR */
272
273#define	EFX_NINTR_SIENA 1024
274
275typedef enum efx_intr_type_e {
276	EFX_INTR_INVALID = 0,
277	EFX_INTR_LINE,
278	EFX_INTR_MESSAGE,
279	EFX_INTR_NTYPES
280} efx_intr_type_t;
281
282#define	EFX_INTR_SIZE	(sizeof (efx_oword_t))
283
284extern	__checkReturn	efx_rc_t
285efx_intr_init(
286	__in		efx_nic_t *enp,
287	__in		efx_intr_type_t type,
288	__in		efsys_mem_t *esmp);
289
290extern			void
291efx_intr_enable(
292	__in		efx_nic_t *enp);
293
294extern			void
295efx_intr_disable(
296	__in		efx_nic_t *enp);
297
298extern			void
299efx_intr_disable_unlocked(
300	__in		efx_nic_t *enp);
301
302#define	EFX_INTR_NEVQS	32
303
304extern	__checkReturn	efx_rc_t
305efx_intr_trigger(
306	__in		efx_nic_t *enp,
307	__in		unsigned int level);
308
309extern			void
310efx_intr_status_line(
311	__in		efx_nic_t *enp,
312	__out		boolean_t *fatalp,
313	__out		uint32_t *maskp);
314
315extern			void
316efx_intr_status_message(
317	__in		efx_nic_t *enp,
318	__in		unsigned int message,
319	__out		boolean_t *fatalp);
320
321extern			void
322efx_intr_fatal(
323	__in		efx_nic_t *enp);
324
325extern			void
326efx_intr_fini(
327	__in		efx_nic_t *enp);
328
329/* MAC */
330
331#if EFSYS_OPT_MAC_STATS
332
333/* START MKCONFIG GENERATED EfxHeaderMacBlock e323546097fd7c65 */
334typedef enum efx_mac_stat_e {
335	EFX_MAC_RX_OCTETS,
336	EFX_MAC_RX_PKTS,
337	EFX_MAC_RX_UNICST_PKTS,
338	EFX_MAC_RX_MULTICST_PKTS,
339	EFX_MAC_RX_BRDCST_PKTS,
340	EFX_MAC_RX_PAUSE_PKTS,
341	EFX_MAC_RX_LE_64_PKTS,
342	EFX_MAC_RX_65_TO_127_PKTS,
343	EFX_MAC_RX_128_TO_255_PKTS,
344	EFX_MAC_RX_256_TO_511_PKTS,
345	EFX_MAC_RX_512_TO_1023_PKTS,
346	EFX_MAC_RX_1024_TO_15XX_PKTS,
347	EFX_MAC_RX_GE_15XX_PKTS,
348	EFX_MAC_RX_ERRORS,
349	EFX_MAC_RX_FCS_ERRORS,
350	EFX_MAC_RX_DROP_EVENTS,
351	EFX_MAC_RX_FALSE_CARRIER_ERRORS,
352	EFX_MAC_RX_SYMBOL_ERRORS,
353	EFX_MAC_RX_ALIGN_ERRORS,
354	EFX_MAC_RX_INTERNAL_ERRORS,
355	EFX_MAC_RX_JABBER_PKTS,
356	EFX_MAC_RX_LANE0_CHAR_ERR,
357	EFX_MAC_RX_LANE1_CHAR_ERR,
358	EFX_MAC_RX_LANE2_CHAR_ERR,
359	EFX_MAC_RX_LANE3_CHAR_ERR,
360	EFX_MAC_RX_LANE0_DISP_ERR,
361	EFX_MAC_RX_LANE1_DISP_ERR,
362	EFX_MAC_RX_LANE2_DISP_ERR,
363	EFX_MAC_RX_LANE3_DISP_ERR,
364	EFX_MAC_RX_MATCH_FAULT,
365	EFX_MAC_RX_NODESC_DROP_CNT,
366	EFX_MAC_TX_OCTETS,
367	EFX_MAC_TX_PKTS,
368	EFX_MAC_TX_UNICST_PKTS,
369	EFX_MAC_TX_MULTICST_PKTS,
370	EFX_MAC_TX_BRDCST_PKTS,
371	EFX_MAC_TX_PAUSE_PKTS,
372	EFX_MAC_TX_LE_64_PKTS,
373	EFX_MAC_TX_65_TO_127_PKTS,
374	EFX_MAC_TX_128_TO_255_PKTS,
375	EFX_MAC_TX_256_TO_511_PKTS,
376	EFX_MAC_TX_512_TO_1023_PKTS,
377	EFX_MAC_TX_1024_TO_15XX_PKTS,
378	EFX_MAC_TX_GE_15XX_PKTS,
379	EFX_MAC_TX_ERRORS,
380	EFX_MAC_TX_SGL_COL_PKTS,
381	EFX_MAC_TX_MULT_COL_PKTS,
382	EFX_MAC_TX_EX_COL_PKTS,
383	EFX_MAC_TX_LATE_COL_PKTS,
384	EFX_MAC_TX_DEF_PKTS,
385	EFX_MAC_TX_EX_DEF_PKTS,
386	EFX_MAC_PM_TRUNC_BB_OVERFLOW,
387	EFX_MAC_PM_DISCARD_BB_OVERFLOW,
388	EFX_MAC_PM_TRUNC_VFIFO_FULL,
389	EFX_MAC_PM_DISCARD_VFIFO_FULL,
390	EFX_MAC_PM_TRUNC_QBB,
391	EFX_MAC_PM_DISCARD_QBB,
392	EFX_MAC_PM_DISCARD_MAPPING,
393	EFX_MAC_RXDP_Q_DISABLED_PKTS,
394	EFX_MAC_RXDP_DI_DROPPED_PKTS,
395	EFX_MAC_RXDP_STREAMING_PKTS,
396	EFX_MAC_RXDP_HLB_FETCH,
397	EFX_MAC_RXDP_HLB_WAIT,
398	EFX_MAC_VADAPTER_RX_UNICAST_PACKETS,
399	EFX_MAC_VADAPTER_RX_UNICAST_BYTES,
400	EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS,
401	EFX_MAC_VADAPTER_RX_MULTICAST_BYTES,
402	EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS,
403	EFX_MAC_VADAPTER_RX_BROADCAST_BYTES,
404	EFX_MAC_VADAPTER_RX_BAD_PACKETS,
405	EFX_MAC_VADAPTER_RX_BAD_BYTES,
406	EFX_MAC_VADAPTER_RX_OVERFLOW,
407	EFX_MAC_VADAPTER_TX_UNICAST_PACKETS,
408	EFX_MAC_VADAPTER_TX_UNICAST_BYTES,
409	EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS,
410	EFX_MAC_VADAPTER_TX_MULTICAST_BYTES,
411	EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS,
412	EFX_MAC_VADAPTER_TX_BROADCAST_BYTES,
413	EFX_MAC_VADAPTER_TX_BAD_PACKETS,
414	EFX_MAC_VADAPTER_TX_BAD_BYTES,
415	EFX_MAC_VADAPTER_TX_OVERFLOW,
416	EFX_MAC_NSTATS
417} efx_mac_stat_t;
418
419/* END MKCONFIG GENERATED EfxHeaderMacBlock */
420
421#endif	/* EFSYS_OPT_MAC_STATS */
422
423typedef enum efx_link_mode_e {
424	EFX_LINK_UNKNOWN = 0,
425	EFX_LINK_DOWN,
426	EFX_LINK_10HDX,
427	EFX_LINK_10FDX,
428	EFX_LINK_100HDX,
429	EFX_LINK_100FDX,
430	EFX_LINK_1000HDX,
431	EFX_LINK_1000FDX,
432	EFX_LINK_10000FDX,
433	EFX_LINK_40000FDX,
434	EFX_LINK_NMODES
435} efx_link_mode_t;
436
437#define	EFX_MAC_ADDR_LEN 6
438
439#define	EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t *)_address)[0] & 0x01)
440
441#define	EFX_MAC_MULTICAST_LIST_MAX	256
442
443#define	EFX_MAC_SDU_MAX	9202
444
445#define	EFX_MAC_PDU_ADJUSTMENT					\
446	(/* EtherII */ 14					\
447	    + /* VLAN */ 4					\
448	    + /* CRC */ 4					\
449	    + /* bug16011 */ 16)				\
450
451#define	EFX_MAC_PDU(_sdu)					\
452	P2ROUNDUP((_sdu) + EFX_MAC_PDU_ADJUSTMENT, 8)
453
454/*
455 * Due to the P2ROUNDUP in EFX_MAC_PDU(), EFX_MAC_SDU_FROM_PDU() may give
456 * the SDU rounded up slightly.
457 */
458#define	EFX_MAC_SDU_FROM_PDU(_pdu)	((_pdu) - EFX_MAC_PDU_ADJUSTMENT)
459
460#define	EFX_MAC_PDU_MIN	60
461#define	EFX_MAC_PDU_MAX	EFX_MAC_PDU(EFX_MAC_SDU_MAX)
462
463extern	__checkReturn	efx_rc_t
464efx_mac_pdu_get(
465	__in		efx_nic_t *enp,
466	__out		size_t *pdu);
467
468extern	__checkReturn	efx_rc_t
469efx_mac_pdu_set(
470	__in		efx_nic_t *enp,
471	__in		size_t pdu);
472
473extern	__checkReturn	efx_rc_t
474efx_mac_addr_set(
475	__in		efx_nic_t *enp,
476	__in		uint8_t *addr);
477
478extern	__checkReturn			efx_rc_t
479efx_mac_filter_set(
480	__in				efx_nic_t *enp,
481	__in				boolean_t all_unicst,
482	__in				boolean_t mulcst,
483	__in				boolean_t all_mulcst,
484	__in				boolean_t brdcst);
485
486extern	__checkReturn	efx_rc_t
487efx_mac_multicast_list_set(
488	__in				efx_nic_t *enp,
489	__in_ecount(6*count)		uint8_t const *addrs,
490	__in				int count);
491
492extern	__checkReturn	efx_rc_t
493efx_mac_filter_default_rxq_set(
494	__in		efx_nic_t *enp,
495	__in		efx_rxq_t *erp,
496	__in		boolean_t using_rss);
497
498extern			void
499efx_mac_filter_default_rxq_clear(
500	__in		efx_nic_t *enp);
501
502extern	__checkReturn	efx_rc_t
503efx_mac_drain(
504	__in		efx_nic_t *enp,
505	__in		boolean_t enabled);
506
507extern	__checkReturn	efx_rc_t
508efx_mac_up(
509	__in		efx_nic_t *enp,
510	__out		boolean_t *mac_upp);
511
512#define	EFX_FCNTL_RESPOND	0x00000001
513#define	EFX_FCNTL_GENERATE	0x00000002
514
515extern	__checkReturn	efx_rc_t
516efx_mac_fcntl_set(
517	__in		efx_nic_t *enp,
518	__in		unsigned int fcntl,
519	__in		boolean_t autoneg);
520
521extern			void
522efx_mac_fcntl_get(
523	__in		efx_nic_t *enp,
524	__out		unsigned int *fcntl_wantedp,
525	__out		unsigned int *fcntl_linkp);
526
527
528#if EFSYS_OPT_MAC_STATS
529
530#if EFSYS_OPT_NAMES
531
532extern	__checkReturn			const char *
533efx_mac_stat_name(
534	__in				efx_nic_t *enp,
535	__in				unsigned int id);
536
537#endif	/* EFSYS_OPT_NAMES */
538
539#define	EFX_MAC_STATS_MASK_BITS_PER_PAGE	(8 * sizeof (uint32_t))
540
541#define	EFX_MAC_STATS_MASK_NPAGES	\
542	(P2ROUNDUP(EFX_MAC_NSTATS, EFX_MAC_STATS_MASK_BITS_PER_PAGE) / \
543	    EFX_MAC_STATS_MASK_BITS_PER_PAGE)
544
545/*
546 * Get mask of MAC statistics supported by the hardware.
547 *
548 * If mask_size is insufficient to return the mask, EINVAL error is
549 * returned. EFX_MAC_STATS_MASK_NPAGES multiplied by size of the page
550 * (which is sizeof (uint32_t)) is sufficient.
551 */
552extern	__checkReturn			efx_rc_t
553efx_mac_stats_get_mask(
554	__in				efx_nic_t *enp,
555	__out_bcount(mask_size)		uint32_t *maskp,
556	__in				size_t mask_size);
557
558#define	EFX_MAC_STAT_SUPPORTED(_mask, _stat)	\
559	((_mask)[(_stat) / EFX_MAC_STATS_MASK_BITS_PER_PAGE] &	\
560	 (1ULL << ((_stat) & (EFX_MAC_STATS_MASK_BITS_PER_PAGE - 1))))
561
562#define	EFX_MAC_STATS_SIZE 0x400
563
564/*
565 * Upload mac statistics supported by the hardware into the given buffer.
566 *
567 * The reference buffer must be at least %EFX_MAC_STATS_SIZE bytes,
568 * and page aligned.
569 *
570 * The hardware will only DMA statistics that it understands (of course).
571 * Drivers should not make any assumptions about which statistics are
572 * supported, especially when the statistics are generated by firmware.
573 *
574 * Thus, drivers should zero this buffer before use, so that not-understood
575 * statistics read back as zero.
576 */
577extern	__checkReturn			efx_rc_t
578efx_mac_stats_upload(
579	__in				efx_nic_t *enp,
580	__in				efsys_mem_t *esmp);
581
582extern	__checkReturn			efx_rc_t
583efx_mac_stats_periodic(
584	__in				efx_nic_t *enp,
585	__in				efsys_mem_t *esmp,
586	__in				uint16_t period_ms,
587	__in				boolean_t events);
588
589extern	__checkReturn			efx_rc_t
590efx_mac_stats_update(
591	__in				efx_nic_t *enp,
592	__in				efsys_mem_t *esmp,
593	__inout_ecount(EFX_MAC_NSTATS)	efsys_stat_t *stat,
594	__inout_opt			uint32_t *generationp);
595
596#endif	/* EFSYS_OPT_MAC_STATS */
597
598/* MON */
599
600typedef enum efx_mon_type_e {
601	EFX_MON_INVALID = 0,
602	EFX_MON_SFC90X0,
603	EFX_MON_SFC91X0,
604	EFX_MON_SFC92X0,
605	EFX_MON_NTYPES
606} efx_mon_type_t;
607
608#if EFSYS_OPT_NAMES
609
610extern		const char *
611efx_mon_name(
612	__in	efx_nic_t *enp);
613
614#endif	/* EFSYS_OPT_NAMES */
615
616extern	__checkReturn	efx_rc_t
617efx_mon_init(
618	__in		efx_nic_t *enp);
619
620#if EFSYS_OPT_MON_STATS
621
622#define	EFX_MON_STATS_PAGE_SIZE 0x100
623#define	EFX_MON_MASK_ELEMENT_SIZE 32
624
625/* START MKCONFIG GENERATED MonitorHeaderStatsBlock 5d4ee5185e419abe */
626typedef enum efx_mon_stat_e {
627	EFX_MON_STAT_2_5V,
628	EFX_MON_STAT_VCCP1,
629	EFX_MON_STAT_VCC,
630	EFX_MON_STAT_5V,
631	EFX_MON_STAT_12V,
632	EFX_MON_STAT_VCCP2,
633	EFX_MON_STAT_EXT_TEMP,
634	EFX_MON_STAT_INT_TEMP,
635	EFX_MON_STAT_AIN1,
636	EFX_MON_STAT_AIN2,
637	EFX_MON_STAT_INT_COOLING,
638	EFX_MON_STAT_EXT_COOLING,
639	EFX_MON_STAT_1V,
640	EFX_MON_STAT_1_2V,
641	EFX_MON_STAT_1_8V,
642	EFX_MON_STAT_3_3V,
643	EFX_MON_STAT_1_2VA,
644	EFX_MON_STAT_VREF,
645	EFX_MON_STAT_VAOE,
646	EFX_MON_STAT_AOE_TEMP,
647	EFX_MON_STAT_PSU_AOE_TEMP,
648	EFX_MON_STAT_PSU_TEMP,
649	EFX_MON_STAT_FAN0,
650	EFX_MON_STAT_FAN1,
651	EFX_MON_STAT_FAN2,
652	EFX_MON_STAT_FAN3,
653	EFX_MON_STAT_FAN4,
654	EFX_MON_STAT_VAOE_IN,
655	EFX_MON_STAT_IAOE,
656	EFX_MON_STAT_IAOE_IN,
657	EFX_MON_STAT_NIC_POWER,
658	EFX_MON_STAT_0_9V,
659	EFX_MON_STAT_I0_9V,
660	EFX_MON_STAT_I1_2V,
661	EFX_MON_STAT_0_9V_ADC,
662	EFX_MON_STAT_INT_TEMP2,
663	EFX_MON_STAT_VREG_TEMP,
664	EFX_MON_STAT_VREG_0_9V_TEMP,
665	EFX_MON_STAT_VREG_1_2V_TEMP,
666	EFX_MON_STAT_INT_VPTAT,
667	EFX_MON_STAT_INT_ADC_TEMP,
668	EFX_MON_STAT_EXT_VPTAT,
669	EFX_MON_STAT_EXT_ADC_TEMP,
670	EFX_MON_STAT_AMBIENT_TEMP,
671	EFX_MON_STAT_AIRFLOW,
672	EFX_MON_STAT_VDD08D_VSS08D_CSR,
673	EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC,
674	EFX_MON_STAT_HOTPOINT_TEMP,
675	EFX_MON_STAT_PHY_POWER_SWITCH_PORT0,
676	EFX_MON_STAT_PHY_POWER_SWITCH_PORT1,
677	EFX_MON_STAT_MUM_VCC,
678	EFX_MON_STAT_0V9_A,
679	EFX_MON_STAT_I0V9_A,
680	EFX_MON_STAT_0V9_A_TEMP,
681	EFX_MON_STAT_0V9_B,
682	EFX_MON_STAT_I0V9_B,
683	EFX_MON_STAT_0V9_B_TEMP,
684	EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY,
685	EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXT_ADC,
686	EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY,
687	EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXT_ADC,
688	EFX_MON_STAT_CONTROLLER_MASTER_VPTAT,
689	EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP,
690	EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXT_ADC,
691	EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXT_ADC,
692	EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT,
693	EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP,
694	EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXT_ADC,
695	EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXT_ADC,
696	EFX_MON_STAT_SODIMM_VOUT,
697	EFX_MON_STAT_SODIMM_0_TEMP,
698	EFX_MON_STAT_SODIMM_1_TEMP,
699	EFX_MON_STAT_PHY0_VCC,
700	EFX_MON_STAT_PHY1_VCC,
701	EFX_MON_STAT_CONTROLLER_TDIODE_TEMP,
702	EFX_MON_STAT_BOARD_FRONT_TEMP,
703	EFX_MON_STAT_BOARD_BACK_TEMP,
704	EFX_MON_NSTATS
705} efx_mon_stat_t;
706
707/* END MKCONFIG GENERATED MonitorHeaderStatsBlock */
708
709typedef enum efx_mon_stat_state_e {
710	EFX_MON_STAT_STATE_OK = 0,
711	EFX_MON_STAT_STATE_WARNING = 1,
712	EFX_MON_STAT_STATE_FATAL = 2,
713	EFX_MON_STAT_STATE_BROKEN = 3,
714	EFX_MON_STAT_STATE_NO_READING = 4,
715} efx_mon_stat_state_t;
716
717typedef struct efx_mon_stat_value_s {
718	uint16_t	emsv_value;
719	uint16_t	emsv_state;
720} efx_mon_stat_value_t;
721
722#if EFSYS_OPT_NAMES
723
724extern					const char *
725efx_mon_stat_name(
726	__in				efx_nic_t *enp,
727	__in				efx_mon_stat_t id);
728
729#endif	/* EFSYS_OPT_NAMES */
730
731extern	__checkReturn			efx_rc_t
732efx_mon_stats_update(
733	__in				efx_nic_t *enp,
734	__in				efsys_mem_t *esmp,
735	__inout_ecount(EFX_MON_NSTATS)	efx_mon_stat_value_t *values);
736
737#endif	/* EFSYS_OPT_MON_STATS */
738
739extern		void
740efx_mon_fini(
741	__in	efx_nic_t *enp);
742
743/* PHY */
744
745extern	__checkReturn	efx_rc_t
746efx_phy_verify(
747	__in		efx_nic_t *enp);
748
749#if EFSYS_OPT_PHY_LED_CONTROL
750
751typedef enum efx_phy_led_mode_e {
752	EFX_PHY_LED_DEFAULT = 0,
753	EFX_PHY_LED_OFF,
754	EFX_PHY_LED_ON,
755	EFX_PHY_LED_FLASH,
756	EFX_PHY_LED_NMODES
757} efx_phy_led_mode_t;
758
759extern	__checkReturn	efx_rc_t
760efx_phy_led_set(
761	__in	efx_nic_t *enp,
762	__in	efx_phy_led_mode_t mode);
763
764#endif	/* EFSYS_OPT_PHY_LED_CONTROL */
765
766extern	__checkReturn	efx_rc_t
767efx_port_init(
768	__in		efx_nic_t *enp);
769
770#if EFSYS_OPT_LOOPBACK
771
772typedef enum efx_loopback_type_e {
773	EFX_LOOPBACK_OFF = 0,
774	EFX_LOOPBACK_DATA = 1,
775	EFX_LOOPBACK_GMAC = 2,
776	EFX_LOOPBACK_XGMII = 3,
777	EFX_LOOPBACK_XGXS = 4,
778	EFX_LOOPBACK_XAUI = 5,
779	EFX_LOOPBACK_GMII = 6,
780	EFX_LOOPBACK_SGMII = 7,
781	EFX_LOOPBACK_XGBR = 8,
782	EFX_LOOPBACK_XFI = 9,
783	EFX_LOOPBACK_XAUI_FAR = 10,
784	EFX_LOOPBACK_GMII_FAR = 11,
785	EFX_LOOPBACK_SGMII_FAR = 12,
786	EFX_LOOPBACK_XFI_FAR = 13,
787	EFX_LOOPBACK_GPHY = 14,
788	EFX_LOOPBACK_PHY_XS = 15,
789	EFX_LOOPBACK_PCS = 16,
790	EFX_LOOPBACK_PMA_PMD = 17,
791	EFX_LOOPBACK_XPORT = 18,
792	EFX_LOOPBACK_XGMII_WS = 19,
793	EFX_LOOPBACK_XAUI_WS = 20,
794	EFX_LOOPBACK_XAUI_WS_FAR = 21,
795	EFX_LOOPBACK_XAUI_WS_NEAR = 22,
796	EFX_LOOPBACK_GMII_WS = 23,
797	EFX_LOOPBACK_XFI_WS = 24,
798	EFX_LOOPBACK_XFI_WS_FAR = 25,
799	EFX_LOOPBACK_PHYXS_WS = 26,
800	EFX_LOOPBACK_PMA_INT = 27,
801	EFX_LOOPBACK_SD_NEAR = 28,
802	EFX_LOOPBACK_SD_FAR = 29,
803	EFX_LOOPBACK_PMA_INT_WS = 30,
804	EFX_LOOPBACK_SD_FEP2_WS = 31,
805	EFX_LOOPBACK_SD_FEP1_5_WS = 32,
806	EFX_LOOPBACK_SD_FEP_WS = 33,
807	EFX_LOOPBACK_SD_FES_WS = 34,
808	EFX_LOOPBACK_NTYPES
809} efx_loopback_type_t;
810
811typedef enum efx_loopback_kind_e {
812	EFX_LOOPBACK_KIND_OFF = 0,
813	EFX_LOOPBACK_KIND_ALL,
814	EFX_LOOPBACK_KIND_MAC,
815	EFX_LOOPBACK_KIND_PHY,
816	EFX_LOOPBACK_NKINDS
817} efx_loopback_kind_t;
818
819extern			void
820efx_loopback_mask(
821	__in	efx_loopback_kind_t loopback_kind,
822	__out	efx_qword_t *maskp);
823
824extern	__checkReturn	efx_rc_t
825efx_port_loopback_set(
826	__in	efx_nic_t *enp,
827	__in	efx_link_mode_t link_mode,
828	__in	efx_loopback_type_t type);
829
830#if EFSYS_OPT_NAMES
831
832extern	__checkReturn	const char *
833efx_loopback_type_name(
834	__in		efx_nic_t *enp,
835	__in		efx_loopback_type_t type);
836
837#endif	/* EFSYS_OPT_NAMES */
838
839#endif	/* EFSYS_OPT_LOOPBACK */
840
841extern	__checkReturn	efx_rc_t
842efx_port_poll(
843	__in		efx_nic_t *enp,
844	__out_opt	efx_link_mode_t	*link_modep);
845
846extern		void
847efx_port_fini(
848	__in	efx_nic_t *enp);
849
850typedef enum efx_phy_cap_type_e {
851	EFX_PHY_CAP_INVALID = 0,
852	EFX_PHY_CAP_10HDX,
853	EFX_PHY_CAP_10FDX,
854	EFX_PHY_CAP_100HDX,
855	EFX_PHY_CAP_100FDX,
856	EFX_PHY_CAP_1000HDX,
857	EFX_PHY_CAP_1000FDX,
858	EFX_PHY_CAP_10000FDX,
859	EFX_PHY_CAP_PAUSE,
860	EFX_PHY_CAP_ASYM,
861	EFX_PHY_CAP_AN,
862	EFX_PHY_CAP_40000FDX,
863	EFX_PHY_CAP_NTYPES
864} efx_phy_cap_type_t;
865
866
867#define	EFX_PHY_CAP_CURRENT	0x00000000
868#define	EFX_PHY_CAP_DEFAULT	0x00000001
869#define	EFX_PHY_CAP_PERM	0x00000002
870
871extern		void
872efx_phy_adv_cap_get(
873	__in		efx_nic_t *enp,
874	__in		uint32_t flag,
875	__out		uint32_t *maskp);
876
877extern	__checkReturn	efx_rc_t
878efx_phy_adv_cap_set(
879	__in		efx_nic_t *enp,
880	__in		uint32_t mask);
881
882extern			void
883efx_phy_lp_cap_get(
884	__in		efx_nic_t *enp,
885	__out		uint32_t *maskp);
886
887extern	__checkReturn	efx_rc_t
888efx_phy_oui_get(
889	__in		efx_nic_t *enp,
890	__out		uint32_t *ouip);
891
892typedef enum efx_phy_media_type_e {
893	EFX_PHY_MEDIA_INVALID = 0,
894	EFX_PHY_MEDIA_XAUI,
895	EFX_PHY_MEDIA_CX4,
896	EFX_PHY_MEDIA_KX4,
897	EFX_PHY_MEDIA_XFP,
898	EFX_PHY_MEDIA_SFP_PLUS,
899	EFX_PHY_MEDIA_BASE_T,
900	EFX_PHY_MEDIA_QSFP_PLUS,
901	EFX_PHY_MEDIA_NTYPES
902} efx_phy_media_type_t;
903
904/* Get the type of medium currently used.  If the board has ports for
905 * modules, a module is present, and we recognise the media type of
906 * the module, then this will be the media type of the module.
907 * Otherwise it will be the media type of the port.
908 */
909extern			void
910efx_phy_media_type_get(
911	__in		efx_nic_t *enp,
912	__out		efx_phy_media_type_t *typep);
913
914extern	__checkReturn		efx_rc_t
915efx_phy_module_get_info(
916	__in			efx_nic_t *enp,
917	__in			uint8_t dev_addr,
918	__in			uint8_t offset,
919	__in			uint8_t len,
920	__out_bcount(len)	uint8_t *data);
921
922#if EFSYS_OPT_PHY_STATS
923
924/* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */
925typedef enum efx_phy_stat_e {
926	EFX_PHY_STAT_OUI,
927	EFX_PHY_STAT_PMA_PMD_LINK_UP,
928	EFX_PHY_STAT_PMA_PMD_RX_FAULT,
929	EFX_PHY_STAT_PMA_PMD_TX_FAULT,
930	EFX_PHY_STAT_PMA_PMD_REV_A,
931	EFX_PHY_STAT_PMA_PMD_REV_B,
932	EFX_PHY_STAT_PMA_PMD_REV_C,
933	EFX_PHY_STAT_PMA_PMD_REV_D,
934	EFX_PHY_STAT_PCS_LINK_UP,
935	EFX_PHY_STAT_PCS_RX_FAULT,
936	EFX_PHY_STAT_PCS_TX_FAULT,
937	EFX_PHY_STAT_PCS_BER,
938	EFX_PHY_STAT_PCS_BLOCK_ERRORS,
939	EFX_PHY_STAT_PHY_XS_LINK_UP,
940	EFX_PHY_STAT_PHY_XS_RX_FAULT,
941	EFX_PHY_STAT_PHY_XS_TX_FAULT,
942	EFX_PHY_STAT_PHY_XS_ALIGN,
943	EFX_PHY_STAT_PHY_XS_SYNC_A,
944	EFX_PHY_STAT_PHY_XS_SYNC_B,
945	EFX_PHY_STAT_PHY_XS_SYNC_C,
946	EFX_PHY_STAT_PHY_XS_SYNC_D,
947	EFX_PHY_STAT_AN_LINK_UP,
948	EFX_PHY_STAT_AN_MASTER,
949	EFX_PHY_STAT_AN_LOCAL_RX_OK,
950	EFX_PHY_STAT_AN_REMOTE_RX_OK,
951	EFX_PHY_STAT_CL22EXT_LINK_UP,
952	EFX_PHY_STAT_SNR_A,
953	EFX_PHY_STAT_SNR_B,
954	EFX_PHY_STAT_SNR_C,
955	EFX_PHY_STAT_SNR_D,
956	EFX_PHY_STAT_PMA_PMD_SIGNAL_A,
957	EFX_PHY_STAT_PMA_PMD_SIGNAL_B,
958	EFX_PHY_STAT_PMA_PMD_SIGNAL_C,
959	EFX_PHY_STAT_PMA_PMD_SIGNAL_D,
960	EFX_PHY_STAT_AN_COMPLETE,
961	EFX_PHY_STAT_PMA_PMD_REV_MAJOR,
962	EFX_PHY_STAT_PMA_PMD_REV_MINOR,
963	EFX_PHY_STAT_PMA_PMD_REV_MICRO,
964	EFX_PHY_STAT_PCS_FW_VERSION_0,
965	EFX_PHY_STAT_PCS_FW_VERSION_1,
966	EFX_PHY_STAT_PCS_FW_VERSION_2,
967	EFX_PHY_STAT_PCS_FW_VERSION_3,
968	EFX_PHY_STAT_PCS_FW_BUILD_YY,
969	EFX_PHY_STAT_PCS_FW_BUILD_MM,
970	EFX_PHY_STAT_PCS_FW_BUILD_DD,
971	EFX_PHY_STAT_PCS_OP_MODE,
972	EFX_PHY_NSTATS
973} efx_phy_stat_t;
974
975/* END MKCONFIG GENERATED PhyHeaderStatsBlock */
976
977#if EFSYS_OPT_NAMES
978
979extern					const char *
980efx_phy_stat_name(
981	__in				efx_nic_t *enp,
982	__in				efx_phy_stat_t stat);
983
984#endif	/* EFSYS_OPT_NAMES */
985
986#define	EFX_PHY_STATS_SIZE 0x100
987
988extern	__checkReturn			efx_rc_t
989efx_phy_stats_update(
990	__in				efx_nic_t *enp,
991	__in				efsys_mem_t *esmp,
992	__inout_ecount(EFX_PHY_NSTATS)	uint32_t *stat);
993
994#endif	/* EFSYS_OPT_PHY_STATS */
995
996
997#if EFSYS_OPT_BIST
998
999typedef enum efx_bist_type_e {
1000	EFX_BIST_TYPE_UNKNOWN,
1001	EFX_BIST_TYPE_PHY_NORMAL,
1002	EFX_BIST_TYPE_PHY_CABLE_SHORT,
1003	EFX_BIST_TYPE_PHY_CABLE_LONG,
1004	EFX_BIST_TYPE_MC_MEM,	/* Test the MC DMEM and IMEM */
1005	EFX_BIST_TYPE_SAT_MEM,	/* Test the DMEM and IMEM of satellite cpus*/
1006	EFX_BIST_TYPE_REG,	/* Test the register memories */
1007	EFX_BIST_TYPE_NTYPES,
1008} efx_bist_type_t;
1009
1010typedef enum efx_bist_result_e {
1011	EFX_BIST_RESULT_UNKNOWN,
1012	EFX_BIST_RESULT_RUNNING,
1013	EFX_BIST_RESULT_PASSED,
1014	EFX_BIST_RESULT_FAILED,
1015} efx_bist_result_t;
1016
1017typedef enum efx_phy_cable_status_e {
1018	EFX_PHY_CABLE_STATUS_OK,
1019	EFX_PHY_CABLE_STATUS_INVALID,
1020	EFX_PHY_CABLE_STATUS_OPEN,
1021	EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT,
1022	EFX_PHY_CABLE_STATUS_INTERPAIRSHORT,
1023	EFX_PHY_CABLE_STATUS_BUSY,
1024} efx_phy_cable_status_t;
1025
1026typedef enum efx_bist_value_e {
1027	EFX_BIST_PHY_CABLE_LENGTH_A,
1028	EFX_BIST_PHY_CABLE_LENGTH_B,
1029	EFX_BIST_PHY_CABLE_LENGTH_C,
1030	EFX_BIST_PHY_CABLE_LENGTH_D,
1031	EFX_BIST_PHY_CABLE_STATUS_A,
1032	EFX_BIST_PHY_CABLE_STATUS_B,
1033	EFX_BIST_PHY_CABLE_STATUS_C,
1034	EFX_BIST_PHY_CABLE_STATUS_D,
1035	EFX_BIST_FAULT_CODE,
1036	/* Memory BIST specific values. These match to the MC_CMD_BIST_POLL
1037	 * response. */
1038	EFX_BIST_MEM_TEST,
1039	EFX_BIST_MEM_ADDR,
1040	EFX_BIST_MEM_BUS,
1041	EFX_BIST_MEM_EXPECT,
1042	EFX_BIST_MEM_ACTUAL,
1043	EFX_BIST_MEM_ECC,
1044	EFX_BIST_MEM_ECC_PARITY,
1045	EFX_BIST_MEM_ECC_FATAL,
1046	EFX_BIST_NVALUES,
1047} efx_bist_value_t;
1048
1049extern	__checkReturn		efx_rc_t
1050efx_bist_enable_offline(
1051	__in			efx_nic_t *enp);
1052
1053extern	__checkReturn		efx_rc_t
1054efx_bist_start(
1055	__in			efx_nic_t *enp,
1056	__in			efx_bist_type_t type);
1057
1058extern	__checkReturn		efx_rc_t
1059efx_bist_poll(
1060	__in			efx_nic_t *enp,
1061	__in			efx_bist_type_t type,
1062	__out			efx_bist_result_t *resultp,
1063	__out_opt		uint32_t *value_maskp,
1064	__out_ecount_opt(count)	unsigned long *valuesp,
1065	__in			size_t count);
1066
1067extern				void
1068efx_bist_stop(
1069	__in			efx_nic_t *enp,
1070	__in			efx_bist_type_t type);
1071
1072#endif	/* EFSYS_OPT_BIST */
1073
1074#define	EFX_FEATURE_IPV6		0x00000001
1075#define	EFX_FEATURE_LFSR_HASH_INSERT	0x00000002
1076#define	EFX_FEATURE_LINK_EVENTS		0x00000004
1077#define	EFX_FEATURE_PERIODIC_MAC_STATS	0x00000008
1078#define	EFX_FEATURE_MCDI		0x00000020
1079#define	EFX_FEATURE_LOOKAHEAD_SPLIT	0x00000040
1080#define	EFX_FEATURE_MAC_HEADER_FILTERS	0x00000080
1081#define	EFX_FEATURE_TURBO		0x00000100
1082#define	EFX_FEATURE_MCDI_DMA		0x00000200
1083#define	EFX_FEATURE_TX_SRC_FILTERS	0x00000400
1084#define	EFX_FEATURE_PIO_BUFFERS		0x00000800
1085#define	EFX_FEATURE_FW_ASSISTED_TSO	0x00001000
1086#define	EFX_FEATURE_FW_ASSISTED_TSO_V2	0x00002000
1087
1088typedef enum efx_tunnel_protocol_e {
1089	EFX_TUNNEL_PROTOCOL_NONE = 0,
1090	EFX_TUNNEL_PROTOCOL_VXLAN,
1091	EFX_TUNNEL_PROTOCOL_GENEVE,
1092	EFX_TUNNEL_PROTOCOL_NVGRE,
1093	EFX_TUNNEL_NPROTOS
1094} efx_tunnel_protocol_t;
1095
1096typedef struct efx_nic_cfg_s {
1097	uint32_t		enc_board_type;
1098	uint32_t		enc_phy_type;
1099#if EFSYS_OPT_NAMES
1100	char			enc_phy_name[21];
1101#endif
1102	char			enc_phy_revision[21];
1103	efx_mon_type_t		enc_mon_type;
1104#if EFSYS_OPT_MON_STATS
1105	uint32_t		enc_mon_stat_dma_buf_size;
1106	uint32_t		enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32];
1107#endif
1108	unsigned int		enc_features;
1109	uint8_t			enc_mac_addr[6];
1110	uint8_t			enc_port;	/* PHY port number */
1111	uint32_t		enc_intr_vec_base;
1112	uint32_t		enc_intr_limit;
1113	uint32_t		enc_evq_limit;
1114	uint32_t		enc_txq_limit;
1115	uint32_t		enc_rxq_limit;
1116	uint32_t		enc_txq_max_ndescs;
1117	uint32_t		enc_buftbl_limit;
1118	uint32_t		enc_piobuf_limit;
1119	uint32_t		enc_piobuf_size;
1120	uint32_t		enc_piobuf_min_alloc_size;
1121	uint32_t		enc_evq_timer_quantum_ns;
1122	uint32_t		enc_evq_timer_max_us;
1123	uint32_t		enc_clk_mult;
1124	uint32_t		enc_rx_prefix_size;
1125	uint32_t		enc_rx_buf_align_start;
1126	uint32_t		enc_rx_buf_align_end;
1127#if EFSYS_OPT_LOOPBACK
1128	efx_qword_t		enc_loopback_types[EFX_LINK_NMODES];
1129#endif	/* EFSYS_OPT_LOOPBACK */
1130#if EFSYS_OPT_PHY_FLAGS
1131	uint32_t		enc_phy_flags_mask;
1132#endif	/* EFSYS_OPT_PHY_FLAGS */
1133#if EFSYS_OPT_PHY_LED_CONTROL
1134	uint32_t		enc_led_mask;
1135#endif	/* EFSYS_OPT_PHY_LED_CONTROL */
1136#if EFSYS_OPT_PHY_STATS
1137	uint64_t		enc_phy_stat_mask;
1138#endif	/* EFSYS_OPT_PHY_STATS */
1139#if EFSYS_OPT_MCDI
1140	uint8_t			enc_mcdi_mdio_channel;
1141#if EFSYS_OPT_PHY_STATS
1142	uint32_t		enc_mcdi_phy_stat_mask;
1143#endif	/* EFSYS_OPT_PHY_STATS */
1144#if EFSYS_OPT_MON_STATS
1145	uint32_t		*enc_mcdi_sensor_maskp;
1146	uint32_t		enc_mcdi_sensor_mask_size;
1147#endif	/* EFSYS_OPT_MON_STATS */
1148#endif	/* EFSYS_OPT_MCDI */
1149#if EFSYS_OPT_BIST
1150	uint32_t		enc_bist_mask;
1151#endif	/* EFSYS_OPT_BIST */
1152#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
1153	uint32_t		enc_pf;
1154	uint32_t		enc_vf;
1155	uint32_t		enc_privilege_mask;
1156#endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
1157	boolean_t		enc_bug26807_workaround;
1158	boolean_t		enc_bug35388_workaround;
1159	boolean_t		enc_bug41750_workaround;
1160	boolean_t		enc_bug61265_workaround;
1161	boolean_t		enc_rx_batching_enabled;
1162	/* Maximum number of descriptors completed in an rx event. */
1163	uint32_t		enc_rx_batch_max;
1164	/* Number of rx descriptors the hardware requires for a push. */
1165	uint32_t		enc_rx_push_align;
1166	/* Maximum amount of data in DMA descriptor */
1167	uint32_t		enc_tx_dma_desc_size_max;
1168	/*
1169	 * Boundary which DMA descriptor data must not cross or 0 if no
1170	 * limitation.
1171	 */
1172	uint32_t		enc_tx_dma_desc_boundary;
1173	/*
1174	 * Maximum number of bytes into the packet the TCP header can start for
1175	 * the hardware to apply TSO packet edits.
1176	 */
1177	uint32_t		enc_tx_tso_tcp_header_offset_limit;
1178	boolean_t		enc_fw_assisted_tso_enabled;
1179	boolean_t		enc_fw_assisted_tso_v2_enabled;
1180	/* Number of TSO contexts on the NIC (FATSOv2) */
1181	uint32_t		enc_fw_assisted_tso_v2_n_contexts;
1182	boolean_t		enc_hw_tx_insert_vlan_enabled;
1183	/* Number of PFs on the NIC */
1184	uint32_t		enc_hw_pf_count;
1185	/* Datapath firmware vadapter/vport/vswitch support */
1186	boolean_t		enc_datapath_cap_evb;
1187	boolean_t		enc_rx_disable_scatter_supported;
1188	boolean_t		enc_allow_set_mac_with_installed_filters;
1189	boolean_t		enc_enhanced_set_mac_supported;
1190	boolean_t		enc_init_evq_v2_supported;
1191	boolean_t		enc_pm_and_rxdp_counters;
1192	boolean_t		enc_mac_stats_40g_tx_size_bins;
1193	uint32_t		enc_tunnel_encapsulations_supported;
1194	/* External port identifier */
1195	uint8_t			enc_external_port;
1196	uint32_t		enc_mcdi_max_payload_length;
1197	/* VPD may be per-PF or global */
1198	boolean_t		enc_vpd_is_global;
1199	/* Minimum unidirectional bandwidth in Mb/s to max out all ports */
1200	uint32_t		enc_required_pcie_bandwidth_mbps;
1201	uint32_t		enc_max_pcie_link_gen;
1202	/* Firmware verifies integrity of NVRAM updates */
1203	uint32_t		enc_fw_verified_nvram_update_required;
1204} efx_nic_cfg_t;
1205
1206#define	EFX_PCI_FUNCTION_IS_PF(_encp)	((_encp)->enc_vf == 0xffff)
1207#define	EFX_PCI_FUNCTION_IS_VF(_encp)	((_encp)->enc_vf != 0xffff)
1208
1209#define	EFX_PCI_FUNCTION(_encp)	\
1210	(EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf)
1211
1212#define	EFX_PCI_VF_PARENT(_encp)	((_encp)->enc_pf)
1213
1214extern			const efx_nic_cfg_t *
1215efx_nic_cfg_get(
1216	__in		efx_nic_t *enp);
1217
1218/* Driver resource limits (minimum required/maximum usable). */
1219typedef struct efx_drv_limits_s {
1220	uint32_t	edl_min_evq_count;
1221	uint32_t	edl_max_evq_count;
1222
1223	uint32_t	edl_min_rxq_count;
1224	uint32_t	edl_max_rxq_count;
1225
1226	uint32_t	edl_min_txq_count;
1227	uint32_t	edl_max_txq_count;
1228
1229	/* PIO blocks (sub-allocated from piobuf) */
1230	uint32_t	edl_min_pio_alloc_size;
1231	uint32_t	edl_max_pio_alloc_count;
1232} efx_drv_limits_t;
1233
1234extern	__checkReturn	efx_rc_t
1235efx_nic_set_drv_limits(
1236	__inout		efx_nic_t *enp,
1237	__in		efx_drv_limits_t *edlp);
1238
1239typedef enum efx_nic_region_e {
1240	EFX_REGION_VI,			/* Memory BAR UC mapping */
1241	EFX_REGION_PIO_WRITE_VI,	/* Memory BAR WC mapping */
1242} efx_nic_region_t;
1243
1244extern	__checkReturn	efx_rc_t
1245efx_nic_get_bar_region(
1246	__in		efx_nic_t *enp,
1247	__in		efx_nic_region_t region,
1248	__out		uint32_t *offsetp,
1249	__out		size_t *sizep);
1250
1251extern	__checkReturn	efx_rc_t
1252efx_nic_get_vi_pool(
1253	__in		efx_nic_t *enp,
1254	__out		uint32_t *evq_countp,
1255	__out		uint32_t *rxq_countp,
1256	__out		uint32_t *txq_countp);
1257
1258
1259#if EFSYS_OPT_VPD
1260
1261typedef enum efx_vpd_tag_e {
1262	EFX_VPD_ID = 0x02,
1263	EFX_VPD_END = 0x0f,
1264	EFX_VPD_RO = 0x10,
1265	EFX_VPD_RW = 0x11,
1266} efx_vpd_tag_t;
1267
1268typedef uint16_t efx_vpd_keyword_t;
1269
1270typedef struct efx_vpd_value_s {
1271	efx_vpd_tag_t		evv_tag;
1272	efx_vpd_keyword_t	evv_keyword;
1273	uint8_t			evv_length;
1274	uint8_t			evv_value[0x100];
1275} efx_vpd_value_t;
1276
1277
1278#define	EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8))
1279
1280extern	__checkReturn		efx_rc_t
1281efx_vpd_init(
1282	__in			efx_nic_t *enp);
1283
1284extern	__checkReturn		efx_rc_t
1285efx_vpd_size(
1286	__in			efx_nic_t *enp,
1287	__out			size_t *sizep);
1288
1289extern	__checkReturn		efx_rc_t
1290efx_vpd_read(
1291	__in			efx_nic_t *enp,
1292	__out_bcount(size)	caddr_t data,
1293	__in			size_t size);
1294
1295extern	__checkReturn		efx_rc_t
1296efx_vpd_verify(
1297	__in			efx_nic_t *enp,
1298	__in_bcount(size)	caddr_t data,
1299	__in			size_t size);
1300
1301extern	__checkReturn		efx_rc_t
1302efx_vpd_reinit(
1303	__in			efx_nic_t *enp,
1304	__in_bcount(size)	caddr_t data,
1305	__in			size_t size);
1306
1307extern	__checkReturn		efx_rc_t
1308efx_vpd_get(
1309	__in			efx_nic_t *enp,
1310	__in_bcount(size)	caddr_t data,
1311	__in			size_t size,
1312	__inout			efx_vpd_value_t *evvp);
1313
1314extern	__checkReturn		efx_rc_t
1315efx_vpd_set(
1316	__in			efx_nic_t *enp,
1317	__inout_bcount(size)	caddr_t data,
1318	__in			size_t size,
1319	__in			efx_vpd_value_t *evvp);
1320
1321extern	__checkReturn		efx_rc_t
1322efx_vpd_next(
1323	__in			efx_nic_t *enp,
1324	__inout_bcount(size)	caddr_t data,
1325	__in			size_t size,
1326	__out			efx_vpd_value_t *evvp,
1327	__inout			unsigned int *contp);
1328
1329extern	__checkReturn		efx_rc_t
1330efx_vpd_write(
1331	__in			efx_nic_t *enp,
1332	__in_bcount(size)	caddr_t data,
1333	__in			size_t size);
1334
1335extern				void
1336efx_vpd_fini(
1337	__in			efx_nic_t *enp);
1338
1339#endif	/* EFSYS_OPT_VPD */
1340
1341/* NVRAM */
1342
1343#if EFSYS_OPT_NVRAM
1344
1345typedef enum efx_nvram_type_e {
1346	EFX_NVRAM_INVALID = 0,
1347	EFX_NVRAM_BOOTROM,
1348	EFX_NVRAM_BOOTROM_CFG,
1349	EFX_NVRAM_MC_FIRMWARE,
1350	EFX_NVRAM_MC_GOLDEN,
1351	EFX_NVRAM_PHY,
1352	EFX_NVRAM_NULLPHY,
1353	EFX_NVRAM_FPGA,
1354	EFX_NVRAM_FCFW,
1355	EFX_NVRAM_CPLD,
1356	EFX_NVRAM_FPGA_BACKUP,
1357	EFX_NVRAM_DYNAMIC_CFG,
1358	EFX_NVRAM_LICENSE,
1359	EFX_NVRAM_UEFIROM,
1360	EFX_NVRAM_NTYPES,
1361} efx_nvram_type_t;
1362
1363extern	__checkReturn		efx_rc_t
1364efx_nvram_init(
1365	__in			efx_nic_t *enp);
1366
1367#if EFSYS_OPT_DIAG
1368
1369extern	__checkReturn		efx_rc_t
1370efx_nvram_test(
1371	__in			efx_nic_t *enp);
1372
1373#endif	/* EFSYS_OPT_DIAG */
1374
1375extern	__checkReturn		efx_rc_t
1376efx_nvram_size(
1377	__in			efx_nic_t *enp,
1378	__in			efx_nvram_type_t type,
1379	__out			size_t *sizep);
1380
1381extern	__checkReturn		efx_rc_t
1382efx_nvram_rw_start(
1383	__in			efx_nic_t *enp,
1384	__in			efx_nvram_type_t type,
1385	__out_opt		size_t *pref_chunkp);
1386
1387extern	__checkReturn		efx_rc_t
1388efx_nvram_rw_finish(
1389	__in			efx_nic_t *enp,
1390	__in			efx_nvram_type_t type);
1391
1392extern	__checkReturn		efx_rc_t
1393efx_nvram_get_version(
1394	__in			efx_nic_t *enp,
1395	__in			efx_nvram_type_t type,
1396	__out			uint32_t *subtypep,
1397	__out_ecount(4)		uint16_t version[4]);
1398
1399extern	__checkReturn		efx_rc_t
1400efx_nvram_read_chunk(
1401	__in			efx_nic_t *enp,
1402	__in			efx_nvram_type_t type,
1403	__in			unsigned int offset,
1404	__out_bcount(size)	caddr_t data,
1405	__in			size_t size);
1406
1407extern	__checkReturn		efx_rc_t
1408efx_nvram_set_version(
1409	__in			efx_nic_t *enp,
1410	__in			efx_nvram_type_t type,
1411	__in_ecount(4)		uint16_t version[4]);
1412
1413extern	__checkReturn		efx_rc_t
1414efx_nvram_validate(
1415	__in			efx_nic_t *enp,
1416	__in			efx_nvram_type_t type,
1417	__in_bcount(partn_size)	caddr_t partn_data,
1418	__in			size_t partn_size);
1419
1420extern	 __checkReturn		efx_rc_t
1421efx_nvram_erase(
1422	__in			efx_nic_t *enp,
1423	__in			efx_nvram_type_t type);
1424
1425extern	__checkReturn		efx_rc_t
1426efx_nvram_write_chunk(
1427	__in			efx_nic_t *enp,
1428	__in			efx_nvram_type_t type,
1429	__in			unsigned int offset,
1430	__in_bcount(size)	caddr_t data,
1431	__in			size_t size);
1432
1433extern				void
1434efx_nvram_fini(
1435	__in			efx_nic_t *enp);
1436
1437#endif	/* EFSYS_OPT_NVRAM */
1438
1439#if EFSYS_OPT_BOOTCFG
1440
1441/* Report size and offset of bootcfg sector in NVRAM partition. */
1442extern	__checkReturn		efx_rc_t
1443efx_bootcfg_sector_info(
1444	__in			efx_nic_t *enp,
1445	__in			uint32_t pf,
1446	__out_opt		uint32_t *sector_countp,
1447	__out			size_t *offsetp,
1448	__out			size_t *max_sizep);
1449
1450/*
1451 * Copy bootcfg sector data to a target buffer which may differ in size.
1452 * Optionally corrects format errors in source buffer.
1453 */
1454extern				efx_rc_t
1455efx_bootcfg_copy_sector(
1456	__in			efx_nic_t *enp,
1457	__inout_bcount(sector_length)
1458				uint8_t *sector,
1459	__in			size_t sector_length,
1460	__out_bcount(data_size)	uint8_t *data,
1461	__in			size_t data_size,
1462	__in			boolean_t handle_format_errors);
1463
1464extern				efx_rc_t
1465efx_bootcfg_read(
1466	__in			efx_nic_t *enp,
1467	__out_bcount(size)	uint8_t *data,
1468	__in			size_t size);
1469
1470extern				efx_rc_t
1471efx_bootcfg_write(
1472	__in			efx_nic_t *enp,
1473	__in_bcount(size)	uint8_t *data,
1474	__in			size_t size);
1475
1476#endif	/* EFSYS_OPT_BOOTCFG */
1477
1478#if EFSYS_OPT_DIAG
1479
1480typedef enum efx_pattern_type_t {
1481	EFX_PATTERN_BYTE_INCREMENT = 0,
1482	EFX_PATTERN_ALL_THE_SAME,
1483	EFX_PATTERN_BIT_ALTERNATE,
1484	EFX_PATTERN_BYTE_ALTERNATE,
1485	EFX_PATTERN_BYTE_CHANGING,
1486	EFX_PATTERN_BIT_SWEEP,
1487	EFX_PATTERN_NTYPES
1488} efx_pattern_type_t;
1489
1490typedef			void
1491(*efx_sram_pattern_fn_t)(
1492	__in		size_t row,
1493	__in		boolean_t negate,
1494	__out		efx_qword_t *eqp);
1495
1496extern	__checkReturn	efx_rc_t
1497efx_sram_test(
1498	__in		efx_nic_t *enp,
1499	__in		efx_pattern_type_t type);
1500
1501#endif	/* EFSYS_OPT_DIAG */
1502
1503extern	__checkReturn	efx_rc_t
1504efx_sram_buf_tbl_set(
1505	__in		efx_nic_t *enp,
1506	__in		uint32_t id,
1507	__in		efsys_mem_t *esmp,
1508	__in		size_t n);
1509
1510extern		void
1511efx_sram_buf_tbl_clear(
1512	__in	efx_nic_t *enp,
1513	__in	uint32_t id,
1514	__in	size_t n);
1515
1516#define	EFX_BUF_TBL_SIZE	0x20000
1517
1518#define	EFX_BUF_SIZE		4096
1519
1520/* EV */
1521
1522typedef struct efx_evq_s	efx_evq_t;
1523
1524#if EFSYS_OPT_QSTATS
1525
1526/* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 6f3843f5fe7cc843 */
1527typedef enum efx_ev_qstat_e {
1528	EV_ALL,
1529	EV_RX,
1530	EV_RX_OK,
1531	EV_RX_FRM_TRUNC,
1532	EV_RX_TOBE_DISC,
1533	EV_RX_PAUSE_FRM_ERR,
1534	EV_RX_BUF_OWNER_ID_ERR,
1535	EV_RX_IPV4_HDR_CHKSUM_ERR,
1536	EV_RX_TCP_UDP_CHKSUM_ERR,
1537	EV_RX_ETH_CRC_ERR,
1538	EV_RX_IP_FRAG_ERR,
1539	EV_RX_MCAST_PKT,
1540	EV_RX_MCAST_HASH_MATCH,
1541	EV_RX_TCP_IPV4,
1542	EV_RX_TCP_IPV6,
1543	EV_RX_UDP_IPV4,
1544	EV_RX_UDP_IPV6,
1545	EV_RX_OTHER_IPV4,
1546	EV_RX_OTHER_IPV6,
1547	EV_RX_NON_IP,
1548	EV_RX_BATCH,
1549	EV_TX,
1550	EV_TX_WQ_FF_FULL,
1551	EV_TX_PKT_ERR,
1552	EV_TX_PKT_TOO_BIG,
1553	EV_TX_UNEXPECTED,
1554	EV_GLOBAL,
1555	EV_GLOBAL_MNT,
1556	EV_DRIVER,
1557	EV_DRIVER_SRM_UPD_DONE,
1558	EV_DRIVER_TX_DESCQ_FLS_DONE,
1559	EV_DRIVER_RX_DESCQ_FLS_DONE,
1560	EV_DRIVER_RX_DESCQ_FLS_FAILED,
1561	EV_DRIVER_RX_DSC_ERROR,
1562	EV_DRIVER_TX_DSC_ERROR,
1563	EV_DRV_GEN,
1564	EV_MCDI_RESPONSE,
1565	EV_NQSTATS
1566} efx_ev_qstat_t;
1567
1568/* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */
1569
1570#endif	/* EFSYS_OPT_QSTATS */
1571
1572extern	__checkReturn	efx_rc_t
1573efx_ev_init(
1574	__in		efx_nic_t *enp);
1575
1576extern		void
1577efx_ev_fini(
1578	__in		efx_nic_t *enp);
1579
1580#define	EFX_EVQ_MAXNEVS		32768
1581#define	EFX_EVQ_MINNEVS		512
1582
1583#define	EFX_EVQ_SIZE(_nevs)	((_nevs) * sizeof (efx_qword_t))
1584#define	EFX_EVQ_NBUFS(_nevs)	(EFX_EVQ_SIZE(_nevs) / EFX_BUF_SIZE)
1585
1586#define	EFX_EVQ_FLAGS_TYPE_MASK		(0x3)
1587#define	EFX_EVQ_FLAGS_TYPE_AUTO		(0x0)
1588#define	EFX_EVQ_FLAGS_TYPE_THROUGHPUT	(0x1)
1589#define	EFX_EVQ_FLAGS_TYPE_LOW_LATENCY	(0x2)
1590
1591#define	EFX_EVQ_FLAGS_NOTIFY_MASK	(0xC)
1592#define	EFX_EVQ_FLAGS_NOTIFY_INTERRUPT	(0x0)	/* Interrupting (default) */
1593#define	EFX_EVQ_FLAGS_NOTIFY_DISABLED	(0x4)	/* Non-interrupting */
1594
1595extern	__checkReturn	efx_rc_t
1596efx_ev_qcreate(
1597	__in		efx_nic_t *enp,
1598	__in		unsigned int index,
1599	__in		efsys_mem_t *esmp,
1600	__in		size_t n,
1601	__in		uint32_t id,
1602	__in		uint32_t us,
1603	__in		uint32_t flags,
1604	__deref_out	efx_evq_t **eepp);
1605
1606extern		void
1607efx_ev_qpost(
1608	__in		efx_evq_t *eep,
1609	__in		uint16_t data);
1610
1611typedef __checkReturn	boolean_t
1612(*efx_initialized_ev_t)(
1613	__in_opt	void *arg);
1614
1615#define	EFX_PKT_UNICAST		0x0004
1616#define	EFX_PKT_START		0x0008
1617
1618#define	EFX_PKT_VLAN_TAGGED	0x0010
1619#define	EFX_CKSUM_TCPUDP	0x0020
1620#define	EFX_CKSUM_IPV4		0x0040
1621#define	EFX_PKT_CONT		0x0080
1622
1623#define	EFX_CHECK_VLAN		0x0100
1624#define	EFX_PKT_TCP		0x0200
1625#define	EFX_PKT_UDP		0x0400
1626#define	EFX_PKT_IPV4		0x0800
1627
1628#define	EFX_PKT_IPV6		0x1000
1629#define	EFX_PKT_PREFIX_LEN	0x2000
1630#define	EFX_ADDR_MISMATCH	0x4000
1631#define	EFX_DISCARD		0x8000
1632
1633#define	EFX_EV_RX_NLABELS	32
1634#define	EFX_EV_TX_NLABELS	32
1635
1636typedef	__checkReturn	boolean_t
1637(*efx_rx_ev_t)(
1638	__in_opt	void *arg,
1639	__in		uint32_t label,
1640	__in		uint32_t id,
1641	__in		uint32_t size,
1642	__in		uint16_t flags);
1643
1644typedef	__checkReturn	boolean_t
1645(*efx_tx_ev_t)(
1646	__in_opt	void *arg,
1647	__in		uint32_t label,
1648	__in		uint32_t id);
1649
1650#define	EFX_EXCEPTION_RX_RECOVERY	0x00000001
1651#define	EFX_EXCEPTION_RX_DSC_ERROR	0x00000002
1652#define	EFX_EXCEPTION_TX_DSC_ERROR	0x00000003
1653#define	EFX_EXCEPTION_UNKNOWN_SENSOREVT	0x00000004
1654#define	EFX_EXCEPTION_FWALERT_SRAM	0x00000005
1655#define	EFX_EXCEPTION_UNKNOWN_FWALERT	0x00000006
1656#define	EFX_EXCEPTION_RX_ERROR		0x00000007
1657#define	EFX_EXCEPTION_TX_ERROR		0x00000008
1658#define	EFX_EXCEPTION_EV_ERROR		0x00000009
1659
1660typedef	__checkReturn	boolean_t
1661(*efx_exception_ev_t)(
1662	__in_opt	void *arg,
1663	__in		uint32_t label,
1664	__in		uint32_t data);
1665
1666typedef	__checkReturn	boolean_t
1667(*efx_rxq_flush_done_ev_t)(
1668	__in_opt	void *arg,
1669	__in		uint32_t rxq_index);
1670
1671typedef	__checkReturn	boolean_t
1672(*efx_rxq_flush_failed_ev_t)(
1673	__in_opt	void *arg,
1674	__in		uint32_t rxq_index);
1675
1676typedef	__checkReturn	boolean_t
1677(*efx_txq_flush_done_ev_t)(
1678	__in_opt	void *arg,
1679	__in		uint32_t txq_index);
1680
1681typedef	__checkReturn	boolean_t
1682(*efx_software_ev_t)(
1683	__in_opt	void *arg,
1684	__in		uint16_t magic);
1685
1686typedef	__checkReturn	boolean_t
1687(*efx_sram_ev_t)(
1688	__in_opt	void *arg,
1689	__in		uint32_t code);
1690
1691#define	EFX_SRAM_CLEAR		0
1692#define	EFX_SRAM_UPDATE		1
1693#define	EFX_SRAM_ILLEGAL_CLEAR	2
1694
1695typedef	__checkReturn	boolean_t
1696(*efx_wake_up_ev_t)(
1697	__in_opt	void *arg,
1698	__in		uint32_t label);
1699
1700typedef	__checkReturn	boolean_t
1701(*efx_timer_ev_t)(
1702	__in_opt	void *arg,
1703	__in		uint32_t label);
1704
1705typedef __checkReturn	boolean_t
1706(*efx_link_change_ev_t)(
1707	__in_opt	void *arg,
1708	__in		efx_link_mode_t	link_mode);
1709
1710#if EFSYS_OPT_MON_STATS
1711
1712typedef __checkReturn	boolean_t
1713(*efx_monitor_ev_t)(
1714	__in_opt	void *arg,
1715	__in		efx_mon_stat_t id,
1716	__in		efx_mon_stat_value_t value);
1717
1718#endif	/* EFSYS_OPT_MON_STATS */
1719
1720#if EFSYS_OPT_MAC_STATS
1721
1722typedef __checkReturn	boolean_t
1723(*efx_mac_stats_ev_t)(
1724	__in_opt	void *arg,
1725	__in		uint32_t generation
1726	);
1727
1728#endif	/* EFSYS_OPT_MAC_STATS */
1729
1730typedef struct efx_ev_callbacks_s {
1731	efx_initialized_ev_t		eec_initialized;
1732	efx_rx_ev_t			eec_rx;
1733	efx_tx_ev_t			eec_tx;
1734	efx_exception_ev_t		eec_exception;
1735	efx_rxq_flush_done_ev_t		eec_rxq_flush_done;
1736	efx_rxq_flush_failed_ev_t	eec_rxq_flush_failed;
1737	efx_txq_flush_done_ev_t		eec_txq_flush_done;
1738	efx_software_ev_t		eec_software;
1739	efx_sram_ev_t			eec_sram;
1740	efx_wake_up_ev_t		eec_wake_up;
1741	efx_timer_ev_t			eec_timer;
1742	efx_link_change_ev_t		eec_link_change;
1743#if EFSYS_OPT_MON_STATS
1744	efx_monitor_ev_t		eec_monitor;
1745#endif	/* EFSYS_OPT_MON_STATS */
1746#if EFSYS_OPT_MAC_STATS
1747	efx_mac_stats_ev_t		eec_mac_stats;
1748#endif	/* EFSYS_OPT_MAC_STATS */
1749} efx_ev_callbacks_t;
1750
1751extern	__checkReturn	boolean_t
1752efx_ev_qpending(
1753	__in		efx_evq_t *eep,
1754	__in		unsigned int count);
1755
1756#if EFSYS_OPT_EV_PREFETCH
1757
1758extern			void
1759efx_ev_qprefetch(
1760	__in		efx_evq_t *eep,
1761	__in		unsigned int count);
1762
1763#endif	/* EFSYS_OPT_EV_PREFETCH */
1764
1765extern			void
1766efx_ev_qpoll(
1767	__in		efx_evq_t *eep,
1768	__inout		unsigned int *countp,
1769	__in		const efx_ev_callbacks_t *eecp,
1770	__in_opt	void *arg);
1771
1772extern	__checkReturn	efx_rc_t
1773efx_ev_usecs_to_ticks(
1774	__in		efx_nic_t *enp,
1775	__in		unsigned int usecs,
1776	__out		unsigned int *ticksp);
1777
1778extern	__checkReturn	efx_rc_t
1779efx_ev_qmoderate(
1780	__in		efx_evq_t *eep,
1781	__in		unsigned int us);
1782
1783extern	__checkReturn	efx_rc_t
1784efx_ev_qprime(
1785	__in		efx_evq_t *eep,
1786	__in		unsigned int count);
1787
1788#if EFSYS_OPT_QSTATS
1789
1790#if EFSYS_OPT_NAMES
1791
1792extern		const char *
1793efx_ev_qstat_name(
1794	__in	efx_nic_t *enp,
1795	__in	unsigned int id);
1796
1797#endif	/* EFSYS_OPT_NAMES */
1798
1799extern					void
1800efx_ev_qstats_update(
1801	__in				efx_evq_t *eep,
1802	__inout_ecount(EV_NQSTATS)	efsys_stat_t *stat);
1803
1804#endif	/* EFSYS_OPT_QSTATS */
1805
1806extern		void
1807efx_ev_qdestroy(
1808	__in	efx_evq_t *eep);
1809
1810/* RX */
1811
1812extern	__checkReturn	efx_rc_t
1813efx_rx_init(
1814	__inout		efx_nic_t *enp);
1815
1816extern		void
1817efx_rx_fini(
1818	__in		efx_nic_t *enp);
1819
1820#if EFSYS_OPT_RX_SCATTER
1821	__checkReturn	efx_rc_t
1822efx_rx_scatter_enable(
1823	__in		efx_nic_t *enp,
1824	__in		unsigned int buf_size);
1825#endif	/* EFSYS_OPT_RX_SCATTER */
1826
1827/* Handle to represent use of the default RSS context. */
1828#define	EFX_RSS_CONTEXT_DEFAULT	0xffffffff
1829
1830#if EFSYS_OPT_RX_SCALE
1831
1832typedef enum efx_rx_hash_alg_e {
1833	EFX_RX_HASHALG_LFSR = 0,
1834	EFX_RX_HASHALG_TOEPLITZ
1835} efx_rx_hash_alg_t;
1836
1837#define	EFX_RX_HASH_IPV4	(1U << 0)
1838#define	EFX_RX_HASH_TCPIPV4	(1U << 1)
1839#define	EFX_RX_HASH_IPV6	(1U << 2)
1840#define	EFX_RX_HASH_TCPIPV6	(1U << 3)
1841
1842typedef unsigned int efx_rx_hash_type_t;
1843
1844typedef enum efx_rx_hash_support_e {
1845	EFX_RX_HASH_UNAVAILABLE = 0,	/* Hardware hash not inserted */
1846	EFX_RX_HASH_AVAILABLE		/* Insert hash with/without RSS */
1847} efx_rx_hash_support_t;
1848
1849#define	EFX_RSS_TBL_SIZE	128	/* Rows in RX indirection table */
1850#define	EFX_MAXRSS		64	/* RX indirection entry range */
1851#define	EFX_MAXRSS_LEGACY	16	/* See bug16611 and bug17213 */
1852
1853typedef enum efx_rx_scale_support_e {
1854	EFX_RX_SCALE_UNAVAILABLE = 0,	/* Not supported */
1855	EFX_RX_SCALE_EXCLUSIVE,		/* Writable key/indirection table */
1856	EFX_RX_SCALE_SHARED		/* Read-only key/indirection table */
1857} efx_rx_scale_support_t;
1858
1859extern	__checkReturn	efx_rc_t
1860efx_rx_hash_support_get(
1861	__in		efx_nic_t *enp,
1862	__out		efx_rx_hash_support_t *supportp);
1863
1864
1865extern	__checkReturn	efx_rc_t
1866efx_rx_scale_support_get(
1867	__in		efx_nic_t *enp,
1868	__out		efx_rx_scale_support_t *supportp);
1869
1870extern	__checkReturn	efx_rc_t
1871efx_rx_scale_mode_set(
1872	__in	efx_nic_t *enp,
1873	__in	efx_rx_hash_alg_t alg,
1874	__in	efx_rx_hash_type_t type,
1875	__in	boolean_t insert);
1876
1877extern	__checkReturn	efx_rc_t
1878efx_rx_scale_tbl_set(
1879	__in		efx_nic_t *enp,
1880	__in_ecount(n)	unsigned int *table,
1881	__in		size_t n);
1882
1883extern	__checkReturn	efx_rc_t
1884efx_rx_scale_key_set(
1885	__in		efx_nic_t *enp,
1886	__in_ecount(n)	uint8_t *key,
1887	__in		size_t n);
1888
1889extern	__checkReturn	uint32_t
1890efx_pseudo_hdr_hash_get(
1891	__in		efx_rxq_t *erp,
1892	__in		efx_rx_hash_alg_t func,
1893	__in		uint8_t *buffer);
1894
1895#endif	/* EFSYS_OPT_RX_SCALE */
1896
1897extern	__checkReturn	efx_rc_t
1898efx_pseudo_hdr_pkt_length_get(
1899	__in		efx_rxq_t *erp,
1900	__in		uint8_t *buffer,
1901	__out		uint16_t *pkt_lengthp);
1902
1903#define	EFX_RXQ_MAXNDESCS		4096
1904#define	EFX_RXQ_MINNDESCS		512
1905
1906#define	EFX_RXQ_SIZE(_ndescs)		((_ndescs) * sizeof (efx_qword_t))
1907#define	EFX_RXQ_NBUFS(_ndescs)		(EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
1908#define	EFX_RXQ_LIMIT(_ndescs)		((_ndescs) - 16)
1909#define	EFX_RXQ_DC_NDESCS(_dcsize)	(8 << _dcsize)
1910
1911typedef enum efx_rxq_type_e {
1912	EFX_RXQ_TYPE_DEFAULT,
1913	EFX_RXQ_TYPE_SCATTER,
1914	EFX_RXQ_NTYPES
1915} efx_rxq_type_t;
1916
1917extern	__checkReturn	efx_rc_t
1918efx_rx_qcreate(
1919	__in		efx_nic_t *enp,
1920	__in		unsigned int index,
1921	__in		unsigned int label,
1922	__in		efx_rxq_type_t type,
1923	__in		efsys_mem_t *esmp,
1924	__in		size_t n,
1925	__in		uint32_t id,
1926	__in		efx_evq_t *eep,
1927	__deref_out	efx_rxq_t **erpp);
1928
1929typedef struct efx_buffer_s {
1930	efsys_dma_addr_t	eb_addr;
1931	size_t			eb_size;
1932	boolean_t		eb_eop;
1933} efx_buffer_t;
1934
1935typedef struct efx_desc_s {
1936	efx_qword_t ed_eq;
1937} efx_desc_t;
1938
1939extern			void
1940efx_rx_qpost(
1941	__in		efx_rxq_t *erp,
1942	__in_ecount(n)	efsys_dma_addr_t *addrp,
1943	__in		size_t size,
1944	__in		unsigned int n,
1945	__in		unsigned int completed,
1946	__in		unsigned int added);
1947
1948extern		void
1949efx_rx_qpush(
1950	__in	efx_rxq_t *erp,
1951	__in	unsigned int added,
1952	__inout	unsigned int *pushedp);
1953
1954extern	__checkReturn	efx_rc_t
1955efx_rx_qflush(
1956	__in	efx_rxq_t *erp);
1957
1958extern		void
1959efx_rx_qenable(
1960	__in	efx_rxq_t *erp);
1961
1962extern		void
1963efx_rx_qdestroy(
1964	__in	efx_rxq_t *erp);
1965
1966/* TX */
1967
1968typedef struct efx_txq_s	efx_txq_t;
1969
1970#if EFSYS_OPT_QSTATS
1971
1972/* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */
1973typedef enum efx_tx_qstat_e {
1974	TX_POST,
1975	TX_POST_PIO,
1976	TX_NQSTATS
1977} efx_tx_qstat_t;
1978
1979/* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */
1980
1981#endif	/* EFSYS_OPT_QSTATS */
1982
1983extern	__checkReturn	efx_rc_t
1984efx_tx_init(
1985	__in		efx_nic_t *enp);
1986
1987extern		void
1988efx_tx_fini(
1989	__in	efx_nic_t *enp);
1990
1991#define	EFX_TXQ_MINNDESCS		512
1992
1993#define	EFX_TXQ_SIZE(_ndescs)		((_ndescs) * sizeof (efx_qword_t))
1994#define	EFX_TXQ_NBUFS(_ndescs)		(EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
1995#define	EFX_TXQ_LIMIT(_ndescs)		((_ndescs) - 16)
1996#define	EFX_TXQ_DC_NDESCS(_dcsize)	(8 << _dcsize)
1997
1998#define	EFX_TXQ_MAX_BUFS 8 /* Maximum independent of EFX_BUG35388_WORKAROUND. */
1999
2000#define	EFX_TXQ_CKSUM_IPV4		0x0001
2001#define	EFX_TXQ_CKSUM_TCPUDP		0x0002
2002#define	EFX_TXQ_FATSOV2			0x0004
2003#define	EFX_TXQ_CKSUM_INNER_IPV4	0x0008
2004#define	EFX_TXQ_CKSUM_INNER_TCPUDP	0x0010
2005
2006extern	__checkReturn	efx_rc_t
2007efx_tx_qcreate(
2008	__in		efx_nic_t *enp,
2009	__in		unsigned int index,
2010	__in		unsigned int label,
2011	__in		efsys_mem_t *esmp,
2012	__in		size_t n,
2013	__in		uint32_t id,
2014	__in		uint16_t flags,
2015	__in		efx_evq_t *eep,
2016	__deref_out	efx_txq_t **etpp,
2017	__out		unsigned int *addedp);
2018
2019extern	__checkReturn	efx_rc_t
2020efx_tx_qpost(
2021	__in		efx_txq_t *etp,
2022	__in_ecount(n)	efx_buffer_t *eb,
2023	__in		unsigned int n,
2024	__in		unsigned int completed,
2025	__inout		unsigned int *addedp);
2026
2027extern	__checkReturn	efx_rc_t
2028efx_tx_qpace(
2029	__in		efx_txq_t *etp,
2030	__in		unsigned int ns);
2031
2032extern			void
2033efx_tx_qpush(
2034	__in		efx_txq_t *etp,
2035	__in		unsigned int added,
2036	__in		unsigned int pushed);
2037
2038extern	__checkReturn	efx_rc_t
2039efx_tx_qflush(
2040	__in		efx_txq_t *etp);
2041
2042extern			void
2043efx_tx_qenable(
2044	__in		efx_txq_t *etp);
2045
2046extern	__checkReturn	efx_rc_t
2047efx_tx_qpio_enable(
2048	__in		efx_txq_t *etp);
2049
2050extern			void
2051efx_tx_qpio_disable(
2052	__in		efx_txq_t *etp);
2053
2054extern	__checkReturn	efx_rc_t
2055efx_tx_qpio_write(
2056	__in			efx_txq_t *etp,
2057	__in_ecount(buf_length)	uint8_t *buffer,
2058	__in			size_t buf_length,
2059	__in			size_t pio_buf_offset);
2060
2061extern	__checkReturn	efx_rc_t
2062efx_tx_qpio_post(
2063	__in			efx_txq_t *etp,
2064	__in			size_t pkt_length,
2065	__in			unsigned int completed,
2066	__inout			unsigned int *addedp);
2067
2068extern	__checkReturn	efx_rc_t
2069efx_tx_qdesc_post(
2070	__in		efx_txq_t *etp,
2071	__in_ecount(n)	efx_desc_t *ed,
2072	__in		unsigned int n,
2073	__in		unsigned int completed,
2074	__inout		unsigned int *addedp);
2075
2076extern	void
2077efx_tx_qdesc_dma_create(
2078	__in	efx_txq_t *etp,
2079	__in	efsys_dma_addr_t addr,
2080	__in	size_t size,
2081	__in	boolean_t eop,
2082	__out	efx_desc_t *edp);
2083
2084extern	void
2085efx_tx_qdesc_tso_create(
2086	__in	efx_txq_t *etp,
2087	__in	uint16_t ipv4_id,
2088	__in	uint32_t tcp_seq,
2089	__in	uint8_t  tcp_flags,
2090	__out	efx_desc_t *edp);
2091
2092/* Number of FATSOv2 option descriptors */
2093#define	EFX_TX_FATSOV2_OPT_NDESCS		2
2094
2095/* Maximum number of DMA segments per TSO packet (not superframe) */
2096#define	EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX	24
2097
2098extern	void
2099efx_tx_qdesc_tso2_create(
2100	__in			efx_txq_t *etp,
2101	__in			uint16_t ipv4_id,
2102	__in			uint32_t tcp_seq,
2103	__in			uint16_t tcp_mss,
2104	__out_ecount(count)	efx_desc_t *edp,
2105	__in			int count);
2106
2107extern	void
2108efx_tx_qdesc_vlantci_create(
2109	__in	efx_txq_t *etp,
2110	__in	uint16_t tci,
2111	__out	efx_desc_t *edp);
2112
2113#if EFSYS_OPT_QSTATS
2114
2115#if EFSYS_OPT_NAMES
2116
2117extern		const char *
2118efx_tx_qstat_name(
2119	__in	efx_nic_t *etp,
2120	__in	unsigned int id);
2121
2122#endif	/* EFSYS_OPT_NAMES */
2123
2124extern					void
2125efx_tx_qstats_update(
2126	__in				efx_txq_t *etp,
2127	__inout_ecount(TX_NQSTATS)	efsys_stat_t *stat);
2128
2129#endif	/* EFSYS_OPT_QSTATS */
2130
2131extern		void
2132efx_tx_qdestroy(
2133	__in	efx_txq_t *etp);
2134
2135
2136/* FILTER */
2137
2138#if EFSYS_OPT_FILTER
2139
2140#define	EFX_ETHER_TYPE_IPV4 0x0800
2141#define	EFX_ETHER_TYPE_IPV6 0x86DD
2142
2143#define	EFX_IPPROTO_TCP 6
2144#define	EFX_IPPROTO_UDP 17
2145#define	EFX_IPPROTO_GRE	47
2146
2147/* Use RSS to spread across multiple queues */
2148#define	EFX_FILTER_FLAG_RX_RSS		0x01
2149/* Enable RX scatter */
2150#define	EFX_FILTER_FLAG_RX_SCATTER	0x02
2151/*
2152 * Override an automatic filter (priority EFX_FILTER_PRI_AUTO).
2153 * May only be set by the filter implementation for each type.
2154 * A removal request will restore the automatic filter in its place.
2155 */
2156#define	EFX_FILTER_FLAG_RX_OVER_AUTO	0x04
2157/* Filter is for RX */
2158#define	EFX_FILTER_FLAG_RX		0x08
2159/* Filter is for TX */
2160#define	EFX_FILTER_FLAG_TX		0x10
2161
2162typedef uint8_t efx_filter_flags_t;
2163
2164/*
2165 * Flags which specify the fields to match on. The values are the same as in the
2166 * MC_CMD_FILTER_OP/MC_CMD_FILTER_OP_EXT commands.
2167 */
2168
2169/* Match by remote IP host address */
2170#define	EFX_FILTER_MATCH_REM_HOST		0x00000001
2171/* Match by local IP host address */
2172#define	EFX_FILTER_MATCH_LOC_HOST		0x00000002
2173/* Match by remote MAC address */
2174#define	EFX_FILTER_MATCH_REM_MAC		0x00000004
2175/* Match by remote TCP/UDP port */
2176#define	EFX_FILTER_MATCH_REM_PORT		0x00000008
2177/* Match by remote TCP/UDP port */
2178#define	EFX_FILTER_MATCH_LOC_MAC		0x00000010
2179/* Match by local TCP/UDP port */
2180#define	EFX_FILTER_MATCH_LOC_PORT		0x00000020
2181/* Match by Ether-type */
2182#define	EFX_FILTER_MATCH_ETHER_TYPE		0x00000040
2183/* Match by inner VLAN ID */
2184#define	EFX_FILTER_MATCH_INNER_VID		0x00000080
2185/* Match by outer VLAN ID */
2186#define	EFX_FILTER_MATCH_OUTER_VID		0x00000100
2187/* Match by IP transport protocol */
2188#define	EFX_FILTER_MATCH_IP_PROTO		0x00000200
2189/* For encapsulated packets, match all multicast inner frames */
2190#define	EFX_FILTER_MATCH_IFRM_UNKNOWN_MCAST_DST	0x01000000
2191/* For encapsulated packets, match all unicast inner frames */
2192#define	EFX_FILTER_MATCH_IFRM_UNKNOWN_UCAST_DST	0x02000000
2193/* Match otherwise-unmatched multicast and broadcast packets */
2194#define	EFX_FILTER_MATCH_UNKNOWN_MCAST_DST	0x40000000
2195/* Match otherwise-unmatched unicast packets */
2196#define	EFX_FILTER_MATCH_UNKNOWN_UCAST_DST	0x80000000
2197
2198typedef uint32_t efx_filter_match_flags_t;
2199
2200typedef enum efx_filter_priority_s {
2201	EFX_FILTER_PRI_HINT = 0,	/* Performance hint */
2202	EFX_FILTER_PRI_AUTO,		/* Automatic filter based on device
2203					 * address list or hardware
2204					 * requirements. This may only be used
2205					 * by the filter implementation for
2206					 * each NIC type. */
2207	EFX_FILTER_PRI_MANUAL,		/* Manually configured filter */
2208	EFX_FILTER_PRI_REQUIRED,	/* Required for correct behaviour of the
2209					 * client (e.g. SR-IOV, HyperV VMQ etc.)
2210					 */
2211} efx_filter_priority_t;
2212
2213/*
2214 * FIXME: All these fields are assumed to be in little-endian byte order.
2215 * It may be better for some to be big-endian. See bug42804.
2216 */
2217
2218typedef struct efx_filter_spec_s {
2219	efx_filter_match_flags_t	efs_match_flags;
2220	uint8_t				efs_priority;
2221	efx_filter_flags_t		efs_flags;
2222	uint16_t			efs_dmaq_id;
2223	uint32_t			efs_rss_context;
2224	uint16_t			efs_outer_vid;
2225	uint16_t			efs_inner_vid;
2226	uint8_t				efs_loc_mac[EFX_MAC_ADDR_LEN];
2227	uint8_t				efs_rem_mac[EFX_MAC_ADDR_LEN];
2228	uint16_t			efs_ether_type;
2229	uint8_t				efs_ip_proto;
2230	efx_tunnel_protocol_t		efs_encap_type;
2231	uint16_t			efs_loc_port;
2232	uint16_t			efs_rem_port;
2233	efx_oword_t			efs_rem_host;
2234	efx_oword_t			efs_loc_host;
2235} efx_filter_spec_t;
2236
2237
2238/* Default values for use in filter specifications */
2239#define	EFX_FILTER_SPEC_RX_DMAQ_ID_DROP		0xfff
2240#define	EFX_FILTER_SPEC_VID_UNSPEC		0xffff
2241
2242extern	__checkReturn	efx_rc_t
2243efx_filter_init(
2244	__in		efx_nic_t *enp);
2245
2246extern			void
2247efx_filter_fini(
2248	__in		efx_nic_t *enp);
2249
2250extern	__checkReturn	efx_rc_t
2251efx_filter_insert(
2252	__in		efx_nic_t *enp,
2253	__inout		efx_filter_spec_t *spec);
2254
2255extern	__checkReturn	efx_rc_t
2256efx_filter_remove(
2257	__in		efx_nic_t *enp,
2258	__inout		efx_filter_spec_t *spec);
2259
2260extern	__checkReturn	efx_rc_t
2261efx_filter_restore(
2262	__in		efx_nic_t *enp);
2263
2264extern	__checkReturn	efx_rc_t
2265efx_filter_supported_filters(
2266	__in				efx_nic_t *enp,
2267	__out_ecount(buffer_length)	uint32_t *buffer,
2268	__in				size_t buffer_length,
2269	__out				size_t *list_lengthp);
2270
2271extern			void
2272efx_filter_spec_init_rx(
2273	__out		efx_filter_spec_t *spec,
2274	__in		efx_filter_priority_t priority,
2275	__in		efx_filter_flags_t flags,
2276	__in		efx_rxq_t *erp);
2277
2278extern			void
2279efx_filter_spec_init_tx(
2280	__out		efx_filter_spec_t *spec,
2281	__in		efx_txq_t *etp);
2282
2283extern	__checkReturn	efx_rc_t
2284efx_filter_spec_set_ipv4_local(
2285	__inout		efx_filter_spec_t *spec,
2286	__in		uint8_t proto,
2287	__in		uint32_t host,
2288	__in		uint16_t port);
2289
2290extern	__checkReturn	efx_rc_t
2291efx_filter_spec_set_ipv4_full(
2292	__inout		efx_filter_spec_t *spec,
2293	__in		uint8_t proto,
2294	__in		uint32_t lhost,
2295	__in		uint16_t lport,
2296	__in		uint32_t rhost,
2297	__in		uint16_t rport);
2298
2299extern	__checkReturn	efx_rc_t
2300efx_filter_spec_set_eth_local(
2301	__inout		efx_filter_spec_t *spec,
2302	__in		uint16_t vid,
2303	__in		const uint8_t *addr);
2304
2305extern			void
2306efx_filter_spec_set_ether_type(
2307	__inout		efx_filter_spec_t *spec,
2308	__in		uint16_t ether_type);
2309
2310extern	__checkReturn	efx_rc_t
2311efx_filter_spec_set_uc_def(
2312	__inout		efx_filter_spec_t *spec);
2313
2314extern	__checkReturn	efx_rc_t
2315efx_filter_spec_set_mc_def(
2316	__inout		efx_filter_spec_t *spec);
2317
2318typedef enum efx_filter_inner_frame_match_e {
2319	EFX_FILTER_INNER_FRAME_MATCH_OTHER = 0,
2320	EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_MCAST_DST,
2321	EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_UCAST_DST
2322} efx_filter_inner_frame_match_t;
2323
2324extern	__checkReturn	efx_rc_t
2325efx_filter_spec_set_encap_type(
2326	__inout		efx_filter_spec_t *spec,
2327	__in		efx_tunnel_protocol_t encap_type,
2328	__in		efx_filter_inner_frame_match_t inner_frame_match);
2329
2330
2331#endif	/* EFSYS_OPT_FILTER */
2332
2333/* HASH */
2334
2335extern	__checkReturn		uint32_t
2336efx_hash_dwords(
2337	__in_ecount(count)	uint32_t const *input,
2338	__in			size_t count,
2339	__in			uint32_t init);
2340
2341extern	__checkReturn		uint32_t
2342efx_hash_bytes(
2343	__in_ecount(length)	uint8_t const *input,
2344	__in			size_t length,
2345	__in			uint32_t init);
2346
2347#if EFSYS_OPT_LICENSING
2348
2349/* LICENSING */
2350
2351typedef struct efx_key_stats_s {
2352	uint32_t	eks_valid;
2353	uint32_t	eks_invalid;
2354	uint32_t	eks_blacklisted;
2355	uint32_t	eks_unverifiable;
2356	uint32_t	eks_wrong_node;
2357	uint32_t	eks_licensed_apps_lo;
2358	uint32_t	eks_licensed_apps_hi;
2359	uint32_t	eks_licensed_features_lo;
2360	uint32_t	eks_licensed_features_hi;
2361} efx_key_stats_t;
2362
2363extern	__checkReturn		efx_rc_t
2364efx_lic_init(
2365	__in			efx_nic_t *enp);
2366
2367extern				void
2368efx_lic_fini(
2369	__in			efx_nic_t *enp);
2370
2371extern	__checkReturn	boolean_t
2372efx_lic_check_support(
2373	__in			efx_nic_t *enp);
2374
2375extern	__checkReturn	efx_rc_t
2376efx_lic_update_licenses(
2377	__in		efx_nic_t *enp);
2378
2379extern	__checkReturn	efx_rc_t
2380efx_lic_get_key_stats(
2381	__in		efx_nic_t *enp,
2382	__out		efx_key_stats_t *ksp);
2383
2384extern	__checkReturn	efx_rc_t
2385efx_lic_app_state(
2386	__in		efx_nic_t *enp,
2387	__in		uint64_t app_id,
2388	__out		boolean_t *licensedp);
2389
2390extern	__checkReturn	efx_rc_t
2391efx_lic_get_id(
2392	__in		efx_nic_t *enp,
2393	__in		size_t buffer_size,
2394	__out		uint32_t *typep,
2395	__out		size_t *lengthp,
2396	__out_opt	uint8_t *bufferp);
2397
2398
2399extern	__checkReturn		efx_rc_t
2400efx_lic_find_start(
2401	__in			efx_nic_t *enp,
2402	__in_bcount(buffer_size)
2403				caddr_t bufferp,
2404	__in			size_t buffer_size,
2405	__out			uint32_t *startp
2406	);
2407
2408extern	__checkReturn		efx_rc_t
2409efx_lic_find_end(
2410	__in			efx_nic_t *enp,
2411	__in_bcount(buffer_size)
2412				caddr_t bufferp,
2413	__in			size_t buffer_size,
2414	__in			uint32_t offset,
2415	__out			uint32_t *endp
2416	);
2417
2418extern	__checkReturn	__success(return != B_FALSE)	boolean_t
2419efx_lic_find_key(
2420	__in			efx_nic_t *enp,
2421	__in_bcount(buffer_size)
2422				caddr_t bufferp,
2423	__in			size_t buffer_size,
2424	__in			uint32_t offset,
2425	__out			uint32_t *startp,
2426	__out			uint32_t *lengthp
2427	);
2428
2429extern	__checkReturn	__success(return != B_FALSE)	boolean_t
2430efx_lic_validate_key(
2431	__in			efx_nic_t *enp,
2432	__in_bcount(length)	caddr_t keyp,
2433	__in			uint32_t length
2434	);
2435
2436extern	__checkReturn		efx_rc_t
2437efx_lic_read_key(
2438	__in			efx_nic_t *enp,
2439	__in_bcount(buffer_size)
2440				caddr_t bufferp,
2441	__in			size_t buffer_size,
2442	__in			uint32_t offset,
2443	__in			uint32_t length,
2444	__out_bcount_part(key_max_size, *lengthp)
2445				caddr_t keyp,
2446	__in			size_t key_max_size,
2447	__out			uint32_t *lengthp
2448	);
2449
2450extern	__checkReturn		efx_rc_t
2451efx_lic_write_key(
2452	__in			efx_nic_t *enp,
2453	__in_bcount(buffer_size)
2454				caddr_t bufferp,
2455	__in			size_t buffer_size,
2456	__in			uint32_t offset,
2457	__in_bcount(length)	caddr_t keyp,
2458	__in			uint32_t length,
2459	__out			uint32_t *lengthp
2460	);
2461
2462	__checkReturn		efx_rc_t
2463efx_lic_delete_key(
2464	__in			efx_nic_t *enp,
2465	__in_bcount(buffer_size)
2466				caddr_t bufferp,
2467	__in			size_t buffer_size,
2468	__in			uint32_t offset,
2469	__in			uint32_t length,
2470	__in			uint32_t end,
2471	__out			uint32_t *deltap
2472	);
2473
2474extern	__checkReturn		efx_rc_t
2475efx_lic_create_partition(
2476	__in			efx_nic_t *enp,
2477	__in_bcount(buffer_size)
2478				caddr_t bufferp,
2479	__in			size_t buffer_size
2480	);
2481
2482extern	__checkReturn		efx_rc_t
2483efx_lic_finish_partition(
2484	__in			efx_nic_t *enp,
2485	__in_bcount(buffer_size)
2486				caddr_t bufferp,
2487	__in			size_t buffer_size
2488	);
2489
2490#endif	/* EFSYS_OPT_LICENSING */
2491
2492
2493
2494#ifdef	__cplusplus
2495}
2496#endif
2497
2498#endif	/* _SYS_EFX_H */
2499