efx.h revision 311486
111820Sjulian/*- 211820Sjulian * Copyright (c) 2006-2016 Solarflare Communications Inc. 311820Sjulian * All rights reserved. 411820Sjulian * 511820Sjulian * Redistribution and use in source and binary forms, with or without 611820Sjulian * modification, are permitted provided that the following conditions are met: 711820Sjulian * 811820Sjulian * 1. Redistributions of source code must retain the above copyright notice, 911820Sjulian * this list of conditions and the following disclaimer. 1011820Sjulian * 2. Redistributions in binary form must reproduce the above copyright notice, 1111820Sjulian * this list of conditions and the following disclaimer in the documentation 1211820Sjulian * and/or other materials provided with the distribution. 1311820Sjulian * 1411820Sjulian * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 1511820Sjulian * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 1611820Sjulian * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 1711820Sjulian * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 1811820Sjulian * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 1911820Sjulian * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 2011820Sjulian * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 2111820Sjulian * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 2211820Sjulian * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 2311820Sjulian * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 2411820Sjulian * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2511820Sjulian * 2611820Sjulian * The views and conclusions contained in the software and documentation are 2711820Sjulian * those of the authors and should not be interpreted as representing official 2811820Sjulian * policies, either expressed or implied, of the FreeBSD Project. 2911820Sjulian * 3011820Sjulian * $FreeBSD: stable/11/sys/dev/sfxge/common/efx.h 311486 2017-01-06 07:19:03Z arybchik $ 3111820Sjulian */ 3211820Sjulian 3311820Sjulian#ifndef _SYS_EFX_H 3450479Speter#define _SYS_EFX_H 3548791Snik 3669862Sru#include "efsys.h" 3711820Sjulian#include "efx_check.h" 3879537Sru#include "efx_phy_ids.h" 3911820Sjulian 4011820Sjulian#ifdef __cplusplus 4111820Sjulianextern "C" { 4211820Sjulian#endif 4368965Sru 4445988Sjhay#define EFX_STATIC_ASSERT(_cond) \ 4511820Sjulian ((void)sizeof(char[(_cond) ? 1 : -1])) 4611820Sjulian 4711820Sjulian#define EFX_ARRAY_SIZE(_array) \ 4811820Sjulian (sizeof(_array) / sizeof((_array)[0])) 4911820Sjulian 5011820Sjulian#define EFX_FIELD_OFFSET(_type, _field) \ 5199968Scharnier ((size_t) &(((_type *)0)->_field)) 5268965Sru 53122760Strhodes/* Return codes */ 54122760Strhodes 55122760Strhodestypedef __success(return == 0) int efx_rc_t; 56122760Strhodes 57122760Strhodes 58122760Strhodes/* Chip families */ 59122760Strhodes 60122760Strhodestypedef enum efx_family_e { 6111820Sjulian EFX_FAMILY_INVALID, 6211820Sjulian EFX_FAMILY_FALCON, /* Obsolete and not supported */ 6311820Sjulian EFX_FAMILY_SIENA, 6411820Sjulian EFX_FAMILY_HUNTINGTON, 6545988Sjhay EFX_FAMILY_MEDFORD, 66122760Strhodes EFX_FAMILY_NTYPES 67122760Strhodes} efx_family_t; 68122760Strhodes 6911820Sjulianextern __checkReturn efx_rc_t 7011820Sjulianefx_family( 7111820Sjulian __in uint16_t venid, 7211820Sjulian __in uint16_t devid, 7311820Sjulian __out efx_family_t *efp); 7479755Sdd 7568965Sru 7611820Sjulian#define EFX_PCI_VENID_SFC 0x1924 7711820Sjulian 7811820Sjulian#define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */ 79111619Stjr 80130130Sru#define EFX_PCI_DEVID_BETHPAGE 0x0803 /* SFC9020 */ 8157673Ssheldonh#define EFX_PCI_DEVID_SIENA 0x0813 /* SFL9021 */ 8279755Sdd#define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810 83122760Strhodes 8411820Sjulian#define EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT 0x0901 8511820Sjulian#define EFX_PCI_DEVID_FARMINGDALE 0x0903 /* SFC9120 PF */ 8611820Sjulian#define EFX_PCI_DEVID_GREENPORT 0x0923 /* SFC9140 PF */ 87122760Strhodes 88122760Strhodes#define EFX_PCI_DEVID_FARMINGDALE_VF 0x1903 /* SFC9120 VF */ 8968965Sru#define EFX_PCI_DEVID_GREENPORT_VF 0x1923 /* SFC9140 VF */ 9011820Sjulian 9111820Sjulian#define EFX_PCI_DEVID_MEDFORD_PF_UNINIT 0x0913 9211820Sjulian#define EFX_PCI_DEVID_MEDFORD 0x0A03 /* SFC9240 PF */ 9379755Sdd#define EFX_PCI_DEVID_MEDFORD_VF 0x1A03 /* SFC9240 VF */ 9468965Sru 95122760Strhodes#define EFX_MEM_BAR 2 96122760Strhodes 9711820Sjulian/* Error codes */ 9811820Sjulian 9911820Sjulianenum { 10011820Sjulian EFX_ERR_INVALID, 10111820Sjulian EFX_ERR_SRAM_OOB, 10211820Sjulian EFX_ERR_BUFID_DC_OOB, 10368965Sru EFX_ERR_MEM_PERR, 10411820Sjulian EFX_ERR_RBUF_OWN, 105122760Strhodes EFX_ERR_TBUF_OWN, 106122760Strhodes EFX_ERR_RDESQ_OWN, 107122760Strhodes EFX_ERR_TDESQ_OWN, 108122760Strhodes EFX_ERR_EVQ_OWN, 109122760Strhodes EFX_ERR_EVFF_OFLO, 11011820Sjulian EFX_ERR_ILL_ADDR, 11111820Sjulian EFX_ERR_SRAM_PERR, 11211820Sjulian EFX_ERR_NCODES 11311820Sjulian}; 11468965Sru 11511820Sjulian/* Calculate the IEEE 802.3 CRC32 of a MAC addr */ 11611820Sjulianextern __checkReturn uint32_t 11711820Sjulianefx_crc32_calculate( 11811820Sjulian __in uint32_t crc_init, 11911820Sjulian __in_ecount(length) uint8_t const *input, 12011820Sjulian __in int length); 12111820Sjulian 122122760Strhodes 123122760Strhodes/* Type prototypes */ 12411820Sjulian 12511820Sjuliantypedef struct efx_rxq_s efx_rxq_t; 12699968Scharnier 12768965Sru/* NIC */ 12899968Scharnier 12911820Sjuliantypedef struct efx_nic_s efx_nic_t; 13011820Sjulian 13111820Sjulianextern __checkReturn efx_rc_t 13211820Sjulianefx_nic_create( 13311820Sjulian __in efx_family_t family, 13411820Sjulian __in efsys_identifier_t *esip, 13511820Sjulian __in efsys_bar_t *esbp, 13611820Sjulian __in efsys_lock_t *eslp, 13711820Sjulian __deref_out efx_nic_t **enpp); 13811820Sjulian 13911820Sjulianextern __checkReturn efx_rc_t 14079755Sddefx_nic_probe( 14168965Sru __in efx_nic_t *enp); 14211820Sjulian 143122760Strhodesextern __checkReturn efx_rc_t 144122760Strhodesefx_nic_init( 14511820Sjulian __in efx_nic_t *enp); 14611820Sjulian 14711820Sjulianextern __checkReturn efx_rc_t 14811820Sjulianefx_nic_reset( 14911820Sjulian __in efx_nic_t *enp); 15011820Sjulian 15111820Sjulian#if EFSYS_OPT_DIAG 15211820Sjulian 15311820Sjulianextern __checkReturn efx_rc_t 15411820Sjulianefx_nic_register_test( 15511820Sjulian __in efx_nic_t *enp); 15611820Sjulian 15711820Sjulian#endif /* EFSYS_OPT_DIAG */ 15868965Sru 15911820Sjulianextern void 16011820Sjulianefx_nic_fini( 16111820Sjulian __in efx_nic_t *enp); 16211820Sjulian 16311820Sjulianextern void 164122760Strhodesefx_nic_unprobe( 165122760Strhodes __in efx_nic_t *enp); 166131500Sru 16711820Sjulianextern void 16811820Sjulianefx_nic_destroy( 169122760Strhodes __in efx_nic_t *enp); 170122760Strhodes 17111820Sjulian#define EFX_PCIE_LINK_SPEED_GEN1 1 17211820Sjulian#define EFX_PCIE_LINK_SPEED_GEN2 2 17311820Sjulian#define EFX_PCIE_LINK_SPEED_GEN3 3 17411820Sjulian 17511820Sjuliantypedef enum efx_pcie_link_performance_e { 17611820Sjulian EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH, 17711820Sjulian EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH, 17811820Sjulian EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY, 17911820Sjulian EFX_PCIE_LINK_PERFORMANCE_OPTIMAL 18011820Sjulian} efx_pcie_link_performance_t; 18111820Sjulian 18211820Sjulianextern __checkReturn efx_rc_t 18311820Sjulianefx_nic_calculate_pcie_link_bandwidth( 18411820Sjulian __in uint32_t pcie_link_width, 18568965Sru __in uint32_t pcie_link_gen, 18611820Sjulian __out uint32_t *bandwidth_mbpsp); 18711820Sjulian 18811820Sjulianextern __checkReturn efx_rc_t 189116050Scharnierefx_nic_check_pcie_link_speed( 190116050Scharnier __in efx_nic_t *enp, 191116050Scharnier __in uint32_t pcie_link_width, 19211820Sjulian __in uint32_t pcie_link_gen, 19311820Sjulian __out efx_pcie_link_performance_t *resultp); 19411820Sjulian 19511820Sjulian#if EFSYS_OPT_MCDI 19668965Sru 19711820Sjulian#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD 19811820Sjulian/* Huntington and Medford require MCDIv2 commands */ 199122760Strhodes#define WITH_MCDI_V2 1 200122760Strhodes#endif 201211936Sbrucec 20211820Sjuliantypedef struct efx_mcdi_req_s efx_mcdi_req_t; 20311820Sjulian 20411820Sjuliantypedef enum efx_mcdi_exception_e { 20511820Sjulian EFX_MCDI_EXCEPTION_MC_REBOOT, 20611820Sjulian EFX_MCDI_EXCEPTION_MC_BADASSERT, 20715248Sjhay} efx_mcdi_exception_t; 20815248Sjhay 20968965Sru#if EFSYS_OPT_MCDI_LOGGING 210130130Srutypedef enum efx_log_msg_e { 211130130Sru EFX_LOG_INVALID, 212130130Sru EFX_LOG_MCDI_REQUEST, 213122760Strhodes EFX_LOG_MCDI_RESPONSE, 214122760Strhodes} efx_log_msg_t; 215122760Strhodes#endif /* EFSYS_OPT_MCDI_LOGGING */ 216122760Strhodes 217122760Strhodestypedef struct efx_mcdi_transport_s { 21811820Sjulian void *emt_context; 21914038Smpp efsys_mem_t *emt_dma_mem; 22011820Sjulian void (*emt_execute)(void *, efx_mcdi_req_t *); 221122760Strhodes void (*emt_ev_cpl)(void *); 222122760Strhodes void (*emt_exception)(void *, efx_mcdi_exception_t); 223122760Strhodes#if EFSYS_OPT_MCDI_LOGGING 224122760Strhodes void (*emt_logger)(void *, efx_log_msg_t, 225 void *, size_t, void *, size_t); 226#endif /* EFSYS_OPT_MCDI_LOGGING */ 227#if EFSYS_OPT_MCDI_PROXY_AUTH 228 void (*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t); 229#endif /* EFSYS_OPT_MCDI_PROXY_AUTH */ 230} efx_mcdi_transport_t; 231 232extern __checkReturn efx_rc_t 233efx_mcdi_init( 234 __in efx_nic_t *enp, 235 __in const efx_mcdi_transport_t *mtp); 236 237extern __checkReturn efx_rc_t 238efx_mcdi_reboot( 239 __in efx_nic_t *enp); 240 241 void 242efx_mcdi_new_epoch( 243 __in efx_nic_t *enp); 244 245extern void 246efx_mcdi_get_timeout( 247 __in efx_nic_t *enp, 248 __in efx_mcdi_req_t *emrp, 249 __out uint32_t *usec_timeoutp); 250 251extern void 252efx_mcdi_request_start( 253 __in efx_nic_t *enp, 254 __in efx_mcdi_req_t *emrp, 255 __in boolean_t ev_cpl); 256 257extern __checkReturn boolean_t 258efx_mcdi_request_poll( 259 __in efx_nic_t *enp); 260 261extern __checkReturn boolean_t 262efx_mcdi_request_abort( 263 __in efx_nic_t *enp); 264 265extern void 266efx_mcdi_fini( 267 __in efx_nic_t *enp); 268 269#endif /* EFSYS_OPT_MCDI */ 270 271/* INTR */ 272 273#define EFX_NINTR_SIENA 1024 274 275typedef enum efx_intr_type_e { 276 EFX_INTR_INVALID = 0, 277 EFX_INTR_LINE, 278 EFX_INTR_MESSAGE, 279 EFX_INTR_NTYPES 280} efx_intr_type_t; 281 282#define EFX_INTR_SIZE (sizeof (efx_oword_t)) 283 284extern __checkReturn efx_rc_t 285efx_intr_init( 286 __in efx_nic_t *enp, 287 __in efx_intr_type_t type, 288 __in efsys_mem_t *esmp); 289 290extern void 291efx_intr_enable( 292 __in efx_nic_t *enp); 293 294extern void 295efx_intr_disable( 296 __in efx_nic_t *enp); 297 298extern void 299efx_intr_disable_unlocked( 300 __in efx_nic_t *enp); 301 302#define EFX_INTR_NEVQS 32 303 304extern __checkReturn efx_rc_t 305efx_intr_trigger( 306 __in efx_nic_t *enp, 307 __in unsigned int level); 308 309extern void 310efx_intr_status_line( 311 __in efx_nic_t *enp, 312 __out boolean_t *fatalp, 313 __out uint32_t *maskp); 314 315extern void 316efx_intr_status_message( 317 __in efx_nic_t *enp, 318 __in unsigned int message, 319 __out boolean_t *fatalp); 320 321extern void 322efx_intr_fatal( 323 __in efx_nic_t *enp); 324 325extern void 326efx_intr_fini( 327 __in efx_nic_t *enp); 328 329/* MAC */ 330 331#if EFSYS_OPT_MAC_STATS 332 333/* START MKCONFIG GENERATED EfxHeaderMacBlock e323546097fd7c65 */ 334typedef enum efx_mac_stat_e { 335 EFX_MAC_RX_OCTETS, 336 EFX_MAC_RX_PKTS, 337 EFX_MAC_RX_UNICST_PKTS, 338 EFX_MAC_RX_MULTICST_PKTS, 339 EFX_MAC_RX_BRDCST_PKTS, 340 EFX_MAC_RX_PAUSE_PKTS, 341 EFX_MAC_RX_LE_64_PKTS, 342 EFX_MAC_RX_65_TO_127_PKTS, 343 EFX_MAC_RX_128_TO_255_PKTS, 344 EFX_MAC_RX_256_TO_511_PKTS, 345 EFX_MAC_RX_512_TO_1023_PKTS, 346 EFX_MAC_RX_1024_TO_15XX_PKTS, 347 EFX_MAC_RX_GE_15XX_PKTS, 348 EFX_MAC_RX_ERRORS, 349 EFX_MAC_RX_FCS_ERRORS, 350 EFX_MAC_RX_DROP_EVENTS, 351 EFX_MAC_RX_FALSE_CARRIER_ERRORS, 352 EFX_MAC_RX_SYMBOL_ERRORS, 353 EFX_MAC_RX_ALIGN_ERRORS, 354 EFX_MAC_RX_INTERNAL_ERRORS, 355 EFX_MAC_RX_JABBER_PKTS, 356 EFX_MAC_RX_LANE0_CHAR_ERR, 357 EFX_MAC_RX_LANE1_CHAR_ERR, 358 EFX_MAC_RX_LANE2_CHAR_ERR, 359 EFX_MAC_RX_LANE3_CHAR_ERR, 360 EFX_MAC_RX_LANE0_DISP_ERR, 361 EFX_MAC_RX_LANE1_DISP_ERR, 362 EFX_MAC_RX_LANE2_DISP_ERR, 363 EFX_MAC_RX_LANE3_DISP_ERR, 364 EFX_MAC_RX_MATCH_FAULT, 365 EFX_MAC_RX_NODESC_DROP_CNT, 366 EFX_MAC_TX_OCTETS, 367 EFX_MAC_TX_PKTS, 368 EFX_MAC_TX_UNICST_PKTS, 369 EFX_MAC_TX_MULTICST_PKTS, 370 EFX_MAC_TX_BRDCST_PKTS, 371 EFX_MAC_TX_PAUSE_PKTS, 372 EFX_MAC_TX_LE_64_PKTS, 373 EFX_MAC_TX_65_TO_127_PKTS, 374 EFX_MAC_TX_128_TO_255_PKTS, 375 EFX_MAC_TX_256_TO_511_PKTS, 376 EFX_MAC_TX_512_TO_1023_PKTS, 377 EFX_MAC_TX_1024_TO_15XX_PKTS, 378 EFX_MAC_TX_GE_15XX_PKTS, 379 EFX_MAC_TX_ERRORS, 380 EFX_MAC_TX_SGL_COL_PKTS, 381 EFX_MAC_TX_MULT_COL_PKTS, 382 EFX_MAC_TX_EX_COL_PKTS, 383 EFX_MAC_TX_LATE_COL_PKTS, 384 EFX_MAC_TX_DEF_PKTS, 385 EFX_MAC_TX_EX_DEF_PKTS, 386 EFX_MAC_PM_TRUNC_BB_OVERFLOW, 387 EFX_MAC_PM_DISCARD_BB_OVERFLOW, 388 EFX_MAC_PM_TRUNC_VFIFO_FULL, 389 EFX_MAC_PM_DISCARD_VFIFO_FULL, 390 EFX_MAC_PM_TRUNC_QBB, 391 EFX_MAC_PM_DISCARD_QBB, 392 EFX_MAC_PM_DISCARD_MAPPING, 393 EFX_MAC_RXDP_Q_DISABLED_PKTS, 394 EFX_MAC_RXDP_DI_DROPPED_PKTS, 395 EFX_MAC_RXDP_STREAMING_PKTS, 396 EFX_MAC_RXDP_HLB_FETCH, 397 EFX_MAC_RXDP_HLB_WAIT, 398 EFX_MAC_VADAPTER_RX_UNICAST_PACKETS, 399 EFX_MAC_VADAPTER_RX_UNICAST_BYTES, 400 EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS, 401 EFX_MAC_VADAPTER_RX_MULTICAST_BYTES, 402 EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS, 403 EFX_MAC_VADAPTER_RX_BROADCAST_BYTES, 404 EFX_MAC_VADAPTER_RX_BAD_PACKETS, 405 EFX_MAC_VADAPTER_RX_BAD_BYTES, 406 EFX_MAC_VADAPTER_RX_OVERFLOW, 407 EFX_MAC_VADAPTER_TX_UNICAST_PACKETS, 408 EFX_MAC_VADAPTER_TX_UNICAST_BYTES, 409 EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS, 410 EFX_MAC_VADAPTER_TX_MULTICAST_BYTES, 411 EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS, 412 EFX_MAC_VADAPTER_TX_BROADCAST_BYTES, 413 EFX_MAC_VADAPTER_TX_BAD_PACKETS, 414 EFX_MAC_VADAPTER_TX_BAD_BYTES, 415 EFX_MAC_VADAPTER_TX_OVERFLOW, 416 EFX_MAC_NSTATS 417} efx_mac_stat_t; 418 419/* END MKCONFIG GENERATED EfxHeaderMacBlock */ 420 421#endif /* EFSYS_OPT_MAC_STATS */ 422 423typedef enum efx_link_mode_e { 424 EFX_LINK_UNKNOWN = 0, 425 EFX_LINK_DOWN, 426 EFX_LINK_10HDX, 427 EFX_LINK_10FDX, 428 EFX_LINK_100HDX, 429 EFX_LINK_100FDX, 430 EFX_LINK_1000HDX, 431 EFX_LINK_1000FDX, 432 EFX_LINK_10000FDX, 433 EFX_LINK_40000FDX, 434 EFX_LINK_NMODES 435} efx_link_mode_t; 436 437#define EFX_MAC_ADDR_LEN 6 438 439#define EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t *)_address)[0] & 0x01) 440 441#define EFX_MAC_MULTICAST_LIST_MAX 256 442 443#define EFX_MAC_SDU_MAX 9202 444 445#define EFX_MAC_PDU_ADJUSTMENT \ 446 (/* EtherII */ 14 \ 447 + /* VLAN */ 4 \ 448 + /* CRC */ 4 \ 449 + /* bug16011 */ 16) \ 450 451#define EFX_MAC_PDU(_sdu) \ 452 P2ROUNDUP((_sdu) + EFX_MAC_PDU_ADJUSTMENT, 8) 453 454/* 455 * Due to the P2ROUNDUP in EFX_MAC_PDU(), EFX_MAC_SDU_FROM_PDU() may give 456 * the SDU rounded up slightly. 457 */ 458#define EFX_MAC_SDU_FROM_PDU(_pdu) ((_pdu) - EFX_MAC_PDU_ADJUSTMENT) 459 460#define EFX_MAC_PDU_MIN 60 461#define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX) 462 463extern __checkReturn efx_rc_t 464efx_mac_pdu_get( 465 __in efx_nic_t *enp, 466 __out size_t *pdu); 467 468extern __checkReturn efx_rc_t 469efx_mac_pdu_set( 470 __in efx_nic_t *enp, 471 __in size_t pdu); 472 473extern __checkReturn efx_rc_t 474efx_mac_addr_set( 475 __in efx_nic_t *enp, 476 __in uint8_t *addr); 477 478extern __checkReturn efx_rc_t 479efx_mac_filter_set( 480 __in efx_nic_t *enp, 481 __in boolean_t all_unicst, 482 __in boolean_t mulcst, 483 __in boolean_t all_mulcst, 484 __in boolean_t brdcst); 485 486extern __checkReturn efx_rc_t 487efx_mac_multicast_list_set( 488 __in efx_nic_t *enp, 489 __in_ecount(6*count) uint8_t const *addrs, 490 __in int count); 491 492extern __checkReturn efx_rc_t 493efx_mac_filter_default_rxq_set( 494 __in efx_nic_t *enp, 495 __in efx_rxq_t *erp, 496 __in boolean_t using_rss); 497 498extern void 499efx_mac_filter_default_rxq_clear( 500 __in efx_nic_t *enp); 501 502extern __checkReturn efx_rc_t 503efx_mac_drain( 504 __in efx_nic_t *enp, 505 __in boolean_t enabled); 506 507extern __checkReturn efx_rc_t 508efx_mac_up( 509 __in efx_nic_t *enp, 510 __out boolean_t *mac_upp); 511 512#define EFX_FCNTL_RESPOND 0x00000001 513#define EFX_FCNTL_GENERATE 0x00000002 514 515extern __checkReturn efx_rc_t 516efx_mac_fcntl_set( 517 __in efx_nic_t *enp, 518 __in unsigned int fcntl, 519 __in boolean_t autoneg); 520 521extern void 522efx_mac_fcntl_get( 523 __in efx_nic_t *enp, 524 __out unsigned int *fcntl_wantedp, 525 __out unsigned int *fcntl_linkp); 526 527 528#if EFSYS_OPT_MAC_STATS 529 530#if EFSYS_OPT_NAMES 531 532extern __checkReturn const char * 533efx_mac_stat_name( 534 __in efx_nic_t *enp, 535 __in unsigned int id); 536 537#endif /* EFSYS_OPT_NAMES */ 538 539#define EFX_MAC_STATS_MASK_BITS_PER_PAGE (8 * sizeof (uint32_t)) 540 541#define EFX_MAC_STATS_MASK_NPAGES \ 542 (P2ROUNDUP(EFX_MAC_NSTATS, EFX_MAC_STATS_MASK_BITS_PER_PAGE) / \ 543 EFX_MAC_STATS_MASK_BITS_PER_PAGE) 544 545/* 546 * Get mask of MAC statistics supported by the hardware. 547 * 548 * If mask_size is insufficient to return the mask, EINVAL error is 549 * returned. EFX_MAC_STATS_MASK_NPAGES multiplied by size of the page 550 * (which is sizeof (uint32_t)) is sufficient. 551 */ 552extern __checkReturn efx_rc_t 553efx_mac_stats_get_mask( 554 __in efx_nic_t *enp, 555 __out_bcount(mask_size) uint32_t *maskp, 556 __in size_t mask_size); 557 558#define EFX_MAC_STAT_SUPPORTED(_mask, _stat) \ 559 ((_mask)[(_stat) / EFX_MAC_STATS_MASK_BITS_PER_PAGE] & \ 560 (1ULL << ((_stat) & (EFX_MAC_STATS_MASK_BITS_PER_PAGE - 1)))) 561 562#define EFX_MAC_STATS_SIZE 0x400 563 564/* 565 * Upload mac statistics supported by the hardware into the given buffer. 566 * 567 * The reference buffer must be at least %EFX_MAC_STATS_SIZE bytes, 568 * and page aligned. 569 * 570 * The hardware will only DMA statistics that it understands (of course). 571 * Drivers should not make any assumptions about which statistics are 572 * supported, especially when the statistics are generated by firmware. 573 * 574 * Thus, drivers should zero this buffer before use, so that not-understood 575 * statistics read back as zero. 576 */ 577extern __checkReturn efx_rc_t 578efx_mac_stats_upload( 579 __in efx_nic_t *enp, 580 __in efsys_mem_t *esmp); 581 582extern __checkReturn efx_rc_t 583efx_mac_stats_periodic( 584 __in efx_nic_t *enp, 585 __in efsys_mem_t *esmp, 586 __in uint16_t period_ms, 587 __in boolean_t events); 588 589extern __checkReturn efx_rc_t 590efx_mac_stats_update( 591 __in efx_nic_t *enp, 592 __in efsys_mem_t *esmp, 593 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat, 594 __inout_opt uint32_t *generationp); 595 596#endif /* EFSYS_OPT_MAC_STATS */ 597 598/* MON */ 599 600typedef enum efx_mon_type_e { 601 EFX_MON_INVALID = 0, 602 EFX_MON_SFC90X0, 603 EFX_MON_SFC91X0, 604 EFX_MON_SFC92X0, 605 EFX_MON_NTYPES 606} efx_mon_type_t; 607 608#if EFSYS_OPT_NAMES 609 610extern const char * 611efx_mon_name( 612 __in efx_nic_t *enp); 613 614#endif /* EFSYS_OPT_NAMES */ 615 616extern __checkReturn efx_rc_t 617efx_mon_init( 618 __in efx_nic_t *enp); 619 620#if EFSYS_OPT_MON_STATS 621 622#define EFX_MON_STATS_PAGE_SIZE 0x100 623#define EFX_MON_MASK_ELEMENT_SIZE 32 624 625/* START MKCONFIG GENERATED MonitorHeaderStatsBlock 5d4ee5185e419abe */ 626typedef enum efx_mon_stat_e { 627 EFX_MON_STAT_2_5V, 628 EFX_MON_STAT_VCCP1, 629 EFX_MON_STAT_VCC, 630 EFX_MON_STAT_5V, 631 EFX_MON_STAT_12V, 632 EFX_MON_STAT_VCCP2, 633 EFX_MON_STAT_EXT_TEMP, 634 EFX_MON_STAT_INT_TEMP, 635 EFX_MON_STAT_AIN1, 636 EFX_MON_STAT_AIN2, 637 EFX_MON_STAT_INT_COOLING, 638 EFX_MON_STAT_EXT_COOLING, 639 EFX_MON_STAT_1V, 640 EFX_MON_STAT_1_2V, 641 EFX_MON_STAT_1_8V, 642 EFX_MON_STAT_3_3V, 643 EFX_MON_STAT_1_2VA, 644 EFX_MON_STAT_VREF, 645 EFX_MON_STAT_VAOE, 646 EFX_MON_STAT_AOE_TEMP, 647 EFX_MON_STAT_PSU_AOE_TEMP, 648 EFX_MON_STAT_PSU_TEMP, 649 EFX_MON_STAT_FAN0, 650 EFX_MON_STAT_FAN1, 651 EFX_MON_STAT_FAN2, 652 EFX_MON_STAT_FAN3, 653 EFX_MON_STAT_FAN4, 654 EFX_MON_STAT_VAOE_IN, 655 EFX_MON_STAT_IAOE, 656 EFX_MON_STAT_IAOE_IN, 657 EFX_MON_STAT_NIC_POWER, 658 EFX_MON_STAT_0_9V, 659 EFX_MON_STAT_I0_9V, 660 EFX_MON_STAT_I1_2V, 661 EFX_MON_STAT_0_9V_ADC, 662 EFX_MON_STAT_INT_TEMP2, 663 EFX_MON_STAT_VREG_TEMP, 664 EFX_MON_STAT_VREG_0_9V_TEMP, 665 EFX_MON_STAT_VREG_1_2V_TEMP, 666 EFX_MON_STAT_INT_VPTAT, 667 EFX_MON_STAT_INT_ADC_TEMP, 668 EFX_MON_STAT_EXT_VPTAT, 669 EFX_MON_STAT_EXT_ADC_TEMP, 670 EFX_MON_STAT_AMBIENT_TEMP, 671 EFX_MON_STAT_AIRFLOW, 672 EFX_MON_STAT_VDD08D_VSS08D_CSR, 673 EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC, 674 EFX_MON_STAT_HOTPOINT_TEMP, 675 EFX_MON_STAT_PHY_POWER_SWITCH_PORT0, 676 EFX_MON_STAT_PHY_POWER_SWITCH_PORT1, 677 EFX_MON_STAT_MUM_VCC, 678 EFX_MON_STAT_0V9_A, 679 EFX_MON_STAT_I0V9_A, 680 EFX_MON_STAT_0V9_A_TEMP, 681 EFX_MON_STAT_0V9_B, 682 EFX_MON_STAT_I0V9_B, 683 EFX_MON_STAT_0V9_B_TEMP, 684 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY, 685 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXT_ADC, 686 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY, 687 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXT_ADC, 688 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT, 689 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP, 690 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXT_ADC, 691 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXT_ADC, 692 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT, 693 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP, 694 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXT_ADC, 695 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXT_ADC, 696 EFX_MON_STAT_SODIMM_VOUT, 697 EFX_MON_STAT_SODIMM_0_TEMP, 698 EFX_MON_STAT_SODIMM_1_TEMP, 699 EFX_MON_STAT_PHY0_VCC, 700 EFX_MON_STAT_PHY1_VCC, 701 EFX_MON_STAT_CONTROLLER_TDIODE_TEMP, 702 EFX_MON_STAT_BOARD_FRONT_TEMP, 703 EFX_MON_STAT_BOARD_BACK_TEMP, 704 EFX_MON_NSTATS 705} efx_mon_stat_t; 706 707/* END MKCONFIG GENERATED MonitorHeaderStatsBlock */ 708 709typedef enum efx_mon_stat_state_e { 710 EFX_MON_STAT_STATE_OK = 0, 711 EFX_MON_STAT_STATE_WARNING = 1, 712 EFX_MON_STAT_STATE_FATAL = 2, 713 EFX_MON_STAT_STATE_BROKEN = 3, 714 EFX_MON_STAT_STATE_NO_READING = 4, 715} efx_mon_stat_state_t; 716 717typedef struct efx_mon_stat_value_s { 718 uint16_t emsv_value; 719 uint16_t emsv_state; 720} efx_mon_stat_value_t; 721 722#if EFSYS_OPT_NAMES 723 724extern const char * 725efx_mon_stat_name( 726 __in efx_nic_t *enp, 727 __in efx_mon_stat_t id); 728 729#endif /* EFSYS_OPT_NAMES */ 730 731extern __checkReturn efx_rc_t 732efx_mon_stats_update( 733 __in efx_nic_t *enp, 734 __in efsys_mem_t *esmp, 735 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values); 736 737#endif /* EFSYS_OPT_MON_STATS */ 738 739extern void 740efx_mon_fini( 741 __in efx_nic_t *enp); 742 743/* PHY */ 744 745extern __checkReturn efx_rc_t 746efx_phy_verify( 747 __in efx_nic_t *enp); 748 749#if EFSYS_OPT_PHY_LED_CONTROL 750 751typedef enum efx_phy_led_mode_e { 752 EFX_PHY_LED_DEFAULT = 0, 753 EFX_PHY_LED_OFF, 754 EFX_PHY_LED_ON, 755 EFX_PHY_LED_FLASH, 756 EFX_PHY_LED_NMODES 757} efx_phy_led_mode_t; 758 759extern __checkReturn efx_rc_t 760efx_phy_led_set( 761 __in efx_nic_t *enp, 762 __in efx_phy_led_mode_t mode); 763 764#endif /* EFSYS_OPT_PHY_LED_CONTROL */ 765 766extern __checkReturn efx_rc_t 767efx_port_init( 768 __in efx_nic_t *enp); 769 770#if EFSYS_OPT_LOOPBACK 771 772typedef enum efx_loopback_type_e { 773 EFX_LOOPBACK_OFF = 0, 774 EFX_LOOPBACK_DATA = 1, 775 EFX_LOOPBACK_GMAC = 2, 776 EFX_LOOPBACK_XGMII = 3, 777 EFX_LOOPBACK_XGXS = 4, 778 EFX_LOOPBACK_XAUI = 5, 779 EFX_LOOPBACK_GMII = 6, 780 EFX_LOOPBACK_SGMII = 7, 781 EFX_LOOPBACK_XGBR = 8, 782 EFX_LOOPBACK_XFI = 9, 783 EFX_LOOPBACK_XAUI_FAR = 10, 784 EFX_LOOPBACK_GMII_FAR = 11, 785 EFX_LOOPBACK_SGMII_FAR = 12, 786 EFX_LOOPBACK_XFI_FAR = 13, 787 EFX_LOOPBACK_GPHY = 14, 788 EFX_LOOPBACK_PHY_XS = 15, 789 EFX_LOOPBACK_PCS = 16, 790 EFX_LOOPBACK_PMA_PMD = 17, 791 EFX_LOOPBACK_XPORT = 18, 792 EFX_LOOPBACK_XGMII_WS = 19, 793 EFX_LOOPBACK_XAUI_WS = 20, 794 EFX_LOOPBACK_XAUI_WS_FAR = 21, 795 EFX_LOOPBACK_XAUI_WS_NEAR = 22, 796 EFX_LOOPBACK_GMII_WS = 23, 797 EFX_LOOPBACK_XFI_WS = 24, 798 EFX_LOOPBACK_XFI_WS_FAR = 25, 799 EFX_LOOPBACK_PHYXS_WS = 26, 800 EFX_LOOPBACK_PMA_INT = 27, 801 EFX_LOOPBACK_SD_NEAR = 28, 802 EFX_LOOPBACK_SD_FAR = 29, 803 EFX_LOOPBACK_PMA_INT_WS = 30, 804 EFX_LOOPBACK_SD_FEP2_WS = 31, 805 EFX_LOOPBACK_SD_FEP1_5_WS = 32, 806 EFX_LOOPBACK_SD_FEP_WS = 33, 807 EFX_LOOPBACK_SD_FES_WS = 34, 808 EFX_LOOPBACK_NTYPES 809} efx_loopback_type_t; 810 811typedef enum efx_loopback_kind_e { 812 EFX_LOOPBACK_KIND_OFF = 0, 813 EFX_LOOPBACK_KIND_ALL, 814 EFX_LOOPBACK_KIND_MAC, 815 EFX_LOOPBACK_KIND_PHY, 816 EFX_LOOPBACK_NKINDS 817} efx_loopback_kind_t; 818 819extern void 820efx_loopback_mask( 821 __in efx_loopback_kind_t loopback_kind, 822 __out efx_qword_t *maskp); 823 824extern __checkReturn efx_rc_t 825efx_port_loopback_set( 826 __in efx_nic_t *enp, 827 __in efx_link_mode_t link_mode, 828 __in efx_loopback_type_t type); 829 830#if EFSYS_OPT_NAMES 831 832extern __checkReturn const char * 833efx_loopback_type_name( 834 __in efx_nic_t *enp, 835 __in efx_loopback_type_t type); 836 837#endif /* EFSYS_OPT_NAMES */ 838 839#endif /* EFSYS_OPT_LOOPBACK */ 840 841extern __checkReturn efx_rc_t 842efx_port_poll( 843 __in efx_nic_t *enp, 844 __out_opt efx_link_mode_t *link_modep); 845 846extern void 847efx_port_fini( 848 __in efx_nic_t *enp); 849 850typedef enum efx_phy_cap_type_e { 851 EFX_PHY_CAP_INVALID = 0, 852 EFX_PHY_CAP_10HDX, 853 EFX_PHY_CAP_10FDX, 854 EFX_PHY_CAP_100HDX, 855 EFX_PHY_CAP_100FDX, 856 EFX_PHY_CAP_1000HDX, 857 EFX_PHY_CAP_1000FDX, 858 EFX_PHY_CAP_10000FDX, 859 EFX_PHY_CAP_PAUSE, 860 EFX_PHY_CAP_ASYM, 861 EFX_PHY_CAP_AN, 862 EFX_PHY_CAP_40000FDX, 863 EFX_PHY_CAP_NTYPES 864} efx_phy_cap_type_t; 865 866 867#define EFX_PHY_CAP_CURRENT 0x00000000 868#define EFX_PHY_CAP_DEFAULT 0x00000001 869#define EFX_PHY_CAP_PERM 0x00000002 870 871extern void 872efx_phy_adv_cap_get( 873 __in efx_nic_t *enp, 874 __in uint32_t flag, 875 __out uint32_t *maskp); 876 877extern __checkReturn efx_rc_t 878efx_phy_adv_cap_set( 879 __in efx_nic_t *enp, 880 __in uint32_t mask); 881 882extern void 883efx_phy_lp_cap_get( 884 __in efx_nic_t *enp, 885 __out uint32_t *maskp); 886 887extern __checkReturn efx_rc_t 888efx_phy_oui_get( 889 __in efx_nic_t *enp, 890 __out uint32_t *ouip); 891 892typedef enum efx_phy_media_type_e { 893 EFX_PHY_MEDIA_INVALID = 0, 894 EFX_PHY_MEDIA_XAUI, 895 EFX_PHY_MEDIA_CX4, 896 EFX_PHY_MEDIA_KX4, 897 EFX_PHY_MEDIA_XFP, 898 EFX_PHY_MEDIA_SFP_PLUS, 899 EFX_PHY_MEDIA_BASE_T, 900 EFX_PHY_MEDIA_QSFP_PLUS, 901 EFX_PHY_MEDIA_NTYPES 902} efx_phy_media_type_t; 903 904/* Get the type of medium currently used. If the board has ports for 905 * modules, a module is present, and we recognise the media type of 906 * the module, then this will be the media type of the module. 907 * Otherwise it will be the media type of the port. 908 */ 909extern void 910efx_phy_media_type_get( 911 __in efx_nic_t *enp, 912 __out efx_phy_media_type_t *typep); 913 914extern efx_rc_t 915efx_phy_module_get_info( 916 __in efx_nic_t *enp, 917 __in uint8_t dev_addr, 918 __in uint8_t offset, 919 __in uint8_t len, 920 __out_bcount(len) uint8_t *data); 921 922#if EFSYS_OPT_PHY_STATS 923 924/* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */ 925typedef enum efx_phy_stat_e { 926 EFX_PHY_STAT_OUI, 927 EFX_PHY_STAT_PMA_PMD_LINK_UP, 928 EFX_PHY_STAT_PMA_PMD_RX_FAULT, 929 EFX_PHY_STAT_PMA_PMD_TX_FAULT, 930 EFX_PHY_STAT_PMA_PMD_REV_A, 931 EFX_PHY_STAT_PMA_PMD_REV_B, 932 EFX_PHY_STAT_PMA_PMD_REV_C, 933 EFX_PHY_STAT_PMA_PMD_REV_D, 934 EFX_PHY_STAT_PCS_LINK_UP, 935 EFX_PHY_STAT_PCS_RX_FAULT, 936 EFX_PHY_STAT_PCS_TX_FAULT, 937 EFX_PHY_STAT_PCS_BER, 938 EFX_PHY_STAT_PCS_BLOCK_ERRORS, 939 EFX_PHY_STAT_PHY_XS_LINK_UP, 940 EFX_PHY_STAT_PHY_XS_RX_FAULT, 941 EFX_PHY_STAT_PHY_XS_TX_FAULT, 942 EFX_PHY_STAT_PHY_XS_ALIGN, 943 EFX_PHY_STAT_PHY_XS_SYNC_A, 944 EFX_PHY_STAT_PHY_XS_SYNC_B, 945 EFX_PHY_STAT_PHY_XS_SYNC_C, 946 EFX_PHY_STAT_PHY_XS_SYNC_D, 947 EFX_PHY_STAT_AN_LINK_UP, 948 EFX_PHY_STAT_AN_MASTER, 949 EFX_PHY_STAT_AN_LOCAL_RX_OK, 950 EFX_PHY_STAT_AN_REMOTE_RX_OK, 951 EFX_PHY_STAT_CL22EXT_LINK_UP, 952 EFX_PHY_STAT_SNR_A, 953 EFX_PHY_STAT_SNR_B, 954 EFX_PHY_STAT_SNR_C, 955 EFX_PHY_STAT_SNR_D, 956 EFX_PHY_STAT_PMA_PMD_SIGNAL_A, 957 EFX_PHY_STAT_PMA_PMD_SIGNAL_B, 958 EFX_PHY_STAT_PMA_PMD_SIGNAL_C, 959 EFX_PHY_STAT_PMA_PMD_SIGNAL_D, 960 EFX_PHY_STAT_AN_COMPLETE, 961 EFX_PHY_STAT_PMA_PMD_REV_MAJOR, 962 EFX_PHY_STAT_PMA_PMD_REV_MINOR, 963 EFX_PHY_STAT_PMA_PMD_REV_MICRO, 964 EFX_PHY_STAT_PCS_FW_VERSION_0, 965 EFX_PHY_STAT_PCS_FW_VERSION_1, 966 EFX_PHY_STAT_PCS_FW_VERSION_2, 967 EFX_PHY_STAT_PCS_FW_VERSION_3, 968 EFX_PHY_STAT_PCS_FW_BUILD_YY, 969 EFX_PHY_STAT_PCS_FW_BUILD_MM, 970 EFX_PHY_STAT_PCS_FW_BUILD_DD, 971 EFX_PHY_STAT_PCS_OP_MODE, 972 EFX_PHY_NSTATS 973} efx_phy_stat_t; 974 975/* END MKCONFIG GENERATED PhyHeaderStatsBlock */ 976 977#if EFSYS_OPT_NAMES 978 979extern const char * 980efx_phy_stat_name( 981 __in efx_nic_t *enp, 982 __in efx_phy_stat_t stat); 983 984#endif /* EFSYS_OPT_NAMES */ 985 986#define EFX_PHY_STATS_SIZE 0x100 987 988extern __checkReturn efx_rc_t 989efx_phy_stats_update( 990 __in efx_nic_t *enp, 991 __in efsys_mem_t *esmp, 992 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat); 993 994#endif /* EFSYS_OPT_PHY_STATS */ 995 996 997#if EFSYS_OPT_BIST 998 999typedef enum efx_bist_type_e { 1000 EFX_BIST_TYPE_UNKNOWN, 1001 EFX_BIST_TYPE_PHY_NORMAL, 1002 EFX_BIST_TYPE_PHY_CABLE_SHORT, 1003 EFX_BIST_TYPE_PHY_CABLE_LONG, 1004 EFX_BIST_TYPE_MC_MEM, /* Test the MC DMEM and IMEM */ 1005 EFX_BIST_TYPE_SAT_MEM, /* Test the DMEM and IMEM of satellite cpus*/ 1006 EFX_BIST_TYPE_REG, /* Test the register memories */ 1007 EFX_BIST_TYPE_NTYPES, 1008} efx_bist_type_t; 1009 1010typedef enum efx_bist_result_e { 1011 EFX_BIST_RESULT_UNKNOWN, 1012 EFX_BIST_RESULT_RUNNING, 1013 EFX_BIST_RESULT_PASSED, 1014 EFX_BIST_RESULT_FAILED, 1015} efx_bist_result_t; 1016 1017typedef enum efx_phy_cable_status_e { 1018 EFX_PHY_CABLE_STATUS_OK, 1019 EFX_PHY_CABLE_STATUS_INVALID, 1020 EFX_PHY_CABLE_STATUS_OPEN, 1021 EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT, 1022 EFX_PHY_CABLE_STATUS_INTERPAIRSHORT, 1023 EFX_PHY_CABLE_STATUS_BUSY, 1024} efx_phy_cable_status_t; 1025 1026typedef enum efx_bist_value_e { 1027 EFX_BIST_PHY_CABLE_LENGTH_A, 1028 EFX_BIST_PHY_CABLE_LENGTH_B, 1029 EFX_BIST_PHY_CABLE_LENGTH_C, 1030 EFX_BIST_PHY_CABLE_LENGTH_D, 1031 EFX_BIST_PHY_CABLE_STATUS_A, 1032 EFX_BIST_PHY_CABLE_STATUS_B, 1033 EFX_BIST_PHY_CABLE_STATUS_C, 1034 EFX_BIST_PHY_CABLE_STATUS_D, 1035 EFX_BIST_FAULT_CODE, 1036 /* Memory BIST specific values. These match to the MC_CMD_BIST_POLL 1037 * response. */ 1038 EFX_BIST_MEM_TEST, 1039 EFX_BIST_MEM_ADDR, 1040 EFX_BIST_MEM_BUS, 1041 EFX_BIST_MEM_EXPECT, 1042 EFX_BIST_MEM_ACTUAL, 1043 EFX_BIST_MEM_ECC, 1044 EFX_BIST_MEM_ECC_PARITY, 1045 EFX_BIST_MEM_ECC_FATAL, 1046 EFX_BIST_NVALUES, 1047} efx_bist_value_t; 1048 1049extern __checkReturn efx_rc_t 1050efx_bist_enable_offline( 1051 __in efx_nic_t *enp); 1052 1053extern __checkReturn efx_rc_t 1054efx_bist_start( 1055 __in efx_nic_t *enp, 1056 __in efx_bist_type_t type); 1057 1058extern __checkReturn efx_rc_t 1059efx_bist_poll( 1060 __in efx_nic_t *enp, 1061 __in efx_bist_type_t type, 1062 __out efx_bist_result_t *resultp, 1063 __out_opt uint32_t *value_maskp, 1064 __out_ecount_opt(count) unsigned long *valuesp, 1065 __in size_t count); 1066 1067extern void 1068efx_bist_stop( 1069 __in efx_nic_t *enp, 1070 __in efx_bist_type_t type); 1071 1072#endif /* EFSYS_OPT_BIST */ 1073 1074#define EFX_FEATURE_IPV6 0x00000001 1075#define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002 1076#define EFX_FEATURE_LINK_EVENTS 0x00000004 1077#define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008 1078#define EFX_FEATURE_WOL 0x00000010 1079#define EFX_FEATURE_MCDI 0x00000020 1080#define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040 1081#define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080 1082#define EFX_FEATURE_TURBO 0x00000100 1083#define EFX_FEATURE_MCDI_DMA 0x00000200 1084#define EFX_FEATURE_TX_SRC_FILTERS 0x00000400 1085#define EFX_FEATURE_PIO_BUFFERS 0x00000800 1086#define EFX_FEATURE_FW_ASSISTED_TSO 0x00001000 1087#define EFX_FEATURE_FW_ASSISTED_TSO_V2 0x00002000 1088 1089typedef struct efx_nic_cfg_s { 1090 uint32_t enc_board_type; 1091 uint32_t enc_phy_type; 1092#if EFSYS_OPT_NAMES 1093 char enc_phy_name[21]; 1094#endif 1095 char enc_phy_revision[21]; 1096 efx_mon_type_t enc_mon_type; 1097#if EFSYS_OPT_MON_STATS 1098 uint32_t enc_mon_stat_dma_buf_size; 1099 uint32_t enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32]; 1100#endif 1101 unsigned int enc_features; 1102 uint8_t enc_mac_addr[6]; 1103 uint8_t enc_port; /* PHY port number */ 1104 uint32_t enc_intr_vec_base; 1105 uint32_t enc_intr_limit; 1106 uint32_t enc_evq_limit; 1107 uint32_t enc_txq_limit; 1108 uint32_t enc_rxq_limit; 1109 uint32_t enc_buftbl_limit; 1110 uint32_t enc_piobuf_limit; 1111 uint32_t enc_piobuf_size; 1112 uint32_t enc_piobuf_min_alloc_size; 1113 uint32_t enc_evq_timer_quantum_ns; 1114 uint32_t enc_evq_timer_max_us; 1115 uint32_t enc_clk_mult; 1116 uint32_t enc_rx_prefix_size; 1117 uint32_t enc_rx_buf_align_start; 1118 uint32_t enc_rx_buf_align_end; 1119#if EFSYS_OPT_LOOPBACK 1120 efx_qword_t enc_loopback_types[EFX_LINK_NMODES]; 1121#endif /* EFSYS_OPT_LOOPBACK */ 1122#if EFSYS_OPT_PHY_FLAGS 1123 uint32_t enc_phy_flags_mask; 1124#endif /* EFSYS_OPT_PHY_FLAGS */ 1125#if EFSYS_OPT_PHY_LED_CONTROL 1126 uint32_t enc_led_mask; 1127#endif /* EFSYS_OPT_PHY_LED_CONTROL */ 1128#if EFSYS_OPT_PHY_STATS 1129 uint64_t enc_phy_stat_mask; 1130#endif /* EFSYS_OPT_PHY_STATS */ 1131#if EFSYS_OPT_MCDI 1132 uint8_t enc_mcdi_mdio_channel; 1133#if EFSYS_OPT_PHY_STATS 1134 uint32_t enc_mcdi_phy_stat_mask; 1135#endif /* EFSYS_OPT_PHY_STATS */ 1136#if EFSYS_OPT_MON_STATS 1137 uint32_t *enc_mcdi_sensor_maskp; 1138 uint32_t enc_mcdi_sensor_mask_size; 1139#endif /* EFSYS_OPT_MON_STATS */ 1140#endif /* EFSYS_OPT_MCDI */ 1141#if EFSYS_OPT_BIST 1142 uint32_t enc_bist_mask; 1143#endif /* EFSYS_OPT_BIST */ 1144#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD 1145 uint32_t enc_pf; 1146 uint32_t enc_vf; 1147 uint32_t enc_privilege_mask; 1148#endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */ 1149 boolean_t enc_bug26807_workaround; 1150 boolean_t enc_bug35388_workaround; 1151 boolean_t enc_bug41750_workaround; 1152 boolean_t enc_bug61265_workaround; 1153 boolean_t enc_rx_batching_enabled; 1154 /* Maximum number of descriptors completed in an rx event. */ 1155 uint32_t enc_rx_batch_max; 1156 /* Number of rx descriptors the hardware requires for a push. */ 1157 uint32_t enc_rx_push_align; 1158 /* 1159 * Maximum number of bytes into the packet the TCP header can start for 1160 * the hardware to apply TSO packet edits. 1161 */ 1162 uint32_t enc_tx_tso_tcp_header_offset_limit; 1163 boolean_t enc_fw_assisted_tso_enabled; 1164 boolean_t enc_fw_assisted_tso_v2_enabled; 1165 /* Number of TSO contexts on the NIC (FATSOv2) */ 1166 uint32_t enc_fw_assisted_tso_v2_n_contexts; 1167 boolean_t enc_hw_tx_insert_vlan_enabled; 1168 /* Number of PFs on the NIC */ 1169 uint32_t enc_hw_pf_count; 1170 /* Datapath firmware vadapter/vport/vswitch support */ 1171 boolean_t enc_datapath_cap_evb; 1172 boolean_t enc_rx_disable_scatter_supported; 1173 boolean_t enc_allow_set_mac_with_installed_filters; 1174 boolean_t enc_enhanced_set_mac_supported; 1175 boolean_t enc_init_evq_v2_supported; 1176 boolean_t enc_pm_and_rxdp_counters; 1177 boolean_t enc_mac_stats_40g_tx_size_bins; 1178 /* External port identifier */ 1179 uint8_t enc_external_port; 1180 uint32_t enc_mcdi_max_payload_length; 1181 /* VPD may be per-PF or global */ 1182 boolean_t enc_vpd_is_global; 1183 /* Minimum unidirectional bandwidth in Mb/s to max out all ports */ 1184 uint32_t enc_required_pcie_bandwidth_mbps; 1185 uint32_t enc_max_pcie_link_gen; 1186 /* Firmware verifies integrity of NVRAM updates */ 1187 uint32_t enc_fw_verified_nvram_update_required; 1188} efx_nic_cfg_t; 1189 1190#define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == 0xffff) 1191#define EFX_PCI_FUNCTION_IS_VF(_encp) ((_encp)->enc_vf != 0xffff) 1192 1193#define EFX_PCI_FUNCTION(_encp) \ 1194 (EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf) 1195 1196#define EFX_PCI_VF_PARENT(_encp) ((_encp)->enc_pf) 1197 1198extern const efx_nic_cfg_t * 1199efx_nic_cfg_get( 1200 __in efx_nic_t *enp); 1201 1202/* Driver resource limits (minimum required/maximum usable). */ 1203typedef struct efx_drv_limits_s { 1204 uint32_t edl_min_evq_count; 1205 uint32_t edl_max_evq_count; 1206 1207 uint32_t edl_min_rxq_count; 1208 uint32_t edl_max_rxq_count; 1209 1210 uint32_t edl_min_txq_count; 1211 uint32_t edl_max_txq_count; 1212 1213 /* PIO blocks (sub-allocated from piobuf) */ 1214 uint32_t edl_min_pio_alloc_size; 1215 uint32_t edl_max_pio_alloc_count; 1216} efx_drv_limits_t; 1217 1218extern __checkReturn efx_rc_t 1219efx_nic_set_drv_limits( 1220 __inout efx_nic_t *enp, 1221 __in efx_drv_limits_t *edlp); 1222 1223typedef enum efx_nic_region_e { 1224 EFX_REGION_VI, /* Memory BAR UC mapping */ 1225 EFX_REGION_PIO_WRITE_VI, /* Memory BAR WC mapping */ 1226} efx_nic_region_t; 1227 1228extern __checkReturn efx_rc_t 1229efx_nic_get_bar_region( 1230 __in efx_nic_t *enp, 1231 __in efx_nic_region_t region, 1232 __out uint32_t *offsetp, 1233 __out size_t *sizep); 1234 1235extern __checkReturn efx_rc_t 1236efx_nic_get_vi_pool( 1237 __in efx_nic_t *enp, 1238 __out uint32_t *evq_countp, 1239 __out uint32_t *rxq_countp, 1240 __out uint32_t *txq_countp); 1241 1242 1243#if EFSYS_OPT_VPD 1244 1245typedef enum efx_vpd_tag_e { 1246 EFX_VPD_ID = 0x02, 1247 EFX_VPD_END = 0x0f, 1248 EFX_VPD_RO = 0x10, 1249 EFX_VPD_RW = 0x11, 1250} efx_vpd_tag_t; 1251 1252typedef uint16_t efx_vpd_keyword_t; 1253 1254typedef struct efx_vpd_value_s { 1255 efx_vpd_tag_t evv_tag; 1256 efx_vpd_keyword_t evv_keyword; 1257 uint8_t evv_length; 1258 uint8_t evv_value[0x100]; 1259} efx_vpd_value_t; 1260 1261 1262#define EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8)) 1263 1264extern __checkReturn efx_rc_t 1265efx_vpd_init( 1266 __in efx_nic_t *enp); 1267 1268extern __checkReturn efx_rc_t 1269efx_vpd_size( 1270 __in efx_nic_t *enp, 1271 __out size_t *sizep); 1272 1273extern __checkReturn efx_rc_t 1274efx_vpd_read( 1275 __in efx_nic_t *enp, 1276 __out_bcount(size) caddr_t data, 1277 __in size_t size); 1278 1279extern __checkReturn efx_rc_t 1280efx_vpd_verify( 1281 __in efx_nic_t *enp, 1282 __in_bcount(size) caddr_t data, 1283 __in size_t size); 1284 1285extern __checkReturn efx_rc_t 1286efx_vpd_reinit( 1287 __in efx_nic_t *enp, 1288 __in_bcount(size) caddr_t data, 1289 __in size_t size); 1290 1291extern __checkReturn efx_rc_t 1292efx_vpd_get( 1293 __in efx_nic_t *enp, 1294 __in_bcount(size) caddr_t data, 1295 __in size_t size, 1296 __inout efx_vpd_value_t *evvp); 1297 1298extern __checkReturn efx_rc_t 1299efx_vpd_set( 1300 __in efx_nic_t *enp, 1301 __inout_bcount(size) caddr_t data, 1302 __in size_t size, 1303 __in efx_vpd_value_t *evvp); 1304 1305extern __checkReturn efx_rc_t 1306efx_vpd_next( 1307 __in efx_nic_t *enp, 1308 __inout_bcount(size) caddr_t data, 1309 __in size_t size, 1310 __out efx_vpd_value_t *evvp, 1311 __inout unsigned int *contp); 1312 1313extern __checkReturn efx_rc_t 1314efx_vpd_write( 1315 __in efx_nic_t *enp, 1316 __in_bcount(size) caddr_t data, 1317 __in size_t size); 1318 1319extern void 1320efx_vpd_fini( 1321 __in efx_nic_t *enp); 1322 1323#endif /* EFSYS_OPT_VPD */ 1324 1325/* NVRAM */ 1326 1327#if EFSYS_OPT_NVRAM 1328 1329typedef enum efx_nvram_type_e { 1330 EFX_NVRAM_INVALID = 0, 1331 EFX_NVRAM_BOOTROM, 1332 EFX_NVRAM_BOOTROM_CFG, 1333 EFX_NVRAM_MC_FIRMWARE, 1334 EFX_NVRAM_MC_GOLDEN, 1335 EFX_NVRAM_PHY, 1336 EFX_NVRAM_NULLPHY, 1337 EFX_NVRAM_FPGA, 1338 EFX_NVRAM_FCFW, 1339 EFX_NVRAM_CPLD, 1340 EFX_NVRAM_FPGA_BACKUP, 1341 EFX_NVRAM_DYNAMIC_CFG, 1342 EFX_NVRAM_LICENSE, 1343 EFX_NVRAM_UEFIROM, 1344 EFX_NVRAM_NTYPES, 1345} efx_nvram_type_t; 1346 1347extern __checkReturn efx_rc_t 1348efx_nvram_init( 1349 __in efx_nic_t *enp); 1350 1351#if EFSYS_OPT_DIAG 1352 1353extern __checkReturn efx_rc_t 1354efx_nvram_test( 1355 __in efx_nic_t *enp); 1356 1357#endif /* EFSYS_OPT_DIAG */ 1358 1359extern __checkReturn efx_rc_t 1360efx_nvram_size( 1361 __in efx_nic_t *enp, 1362 __in efx_nvram_type_t type, 1363 __out size_t *sizep); 1364 1365extern __checkReturn efx_rc_t 1366efx_nvram_rw_start( 1367 __in efx_nic_t *enp, 1368 __in efx_nvram_type_t type, 1369 __out_opt size_t *pref_chunkp); 1370 1371extern __checkReturn efx_rc_t 1372efx_nvram_rw_finish( 1373 __in efx_nic_t *enp, 1374 __in efx_nvram_type_t type); 1375 1376extern __checkReturn efx_rc_t 1377efx_nvram_get_version( 1378 __in efx_nic_t *enp, 1379 __in efx_nvram_type_t type, 1380 __out uint32_t *subtypep, 1381 __out_ecount(4) uint16_t version[4]); 1382 1383extern __checkReturn efx_rc_t 1384efx_nvram_read_chunk( 1385 __in efx_nic_t *enp, 1386 __in efx_nvram_type_t type, 1387 __in unsigned int offset, 1388 __out_bcount(size) caddr_t data, 1389 __in size_t size); 1390 1391extern __checkReturn efx_rc_t 1392efx_nvram_set_version( 1393 __in efx_nic_t *enp, 1394 __in efx_nvram_type_t type, 1395 __in_ecount(4) uint16_t version[4]); 1396 1397extern __checkReturn efx_rc_t 1398efx_nvram_validate( 1399 __in efx_nic_t *enp, 1400 __in efx_nvram_type_t type, 1401 __in_bcount(partn_size) caddr_t partn_data, 1402 __in size_t partn_size); 1403 1404extern __checkReturn efx_rc_t 1405efx_nvram_erase( 1406 __in efx_nic_t *enp, 1407 __in efx_nvram_type_t type); 1408 1409extern __checkReturn efx_rc_t 1410efx_nvram_write_chunk( 1411 __in efx_nic_t *enp, 1412 __in efx_nvram_type_t type, 1413 __in unsigned int offset, 1414 __in_bcount(size) caddr_t data, 1415 __in size_t size); 1416 1417extern void 1418efx_nvram_fini( 1419 __in efx_nic_t *enp); 1420 1421#endif /* EFSYS_OPT_NVRAM */ 1422 1423#if EFSYS_OPT_BOOTCFG 1424 1425extern efx_rc_t 1426efx_bootcfg_read( 1427 __in efx_nic_t *enp, 1428 __out_bcount(size) caddr_t data, 1429 __in size_t size); 1430 1431extern efx_rc_t 1432efx_bootcfg_write( 1433 __in efx_nic_t *enp, 1434 __in_bcount(size) caddr_t data, 1435 __in size_t size); 1436 1437#endif /* EFSYS_OPT_BOOTCFG */ 1438 1439#if EFSYS_OPT_WOL 1440 1441typedef enum efx_wol_type_e { 1442 EFX_WOL_TYPE_INVALID, 1443 EFX_WOL_TYPE_MAGIC, 1444 EFX_WOL_TYPE_BITMAP, 1445 EFX_WOL_TYPE_LINK, 1446 EFX_WOL_NTYPES, 1447} efx_wol_type_t; 1448 1449typedef enum efx_lightsout_offload_type_e { 1450 EFX_LIGHTSOUT_OFFLOAD_TYPE_INVALID, 1451 EFX_LIGHTSOUT_OFFLOAD_TYPE_ARP, 1452 EFX_LIGHTSOUT_OFFLOAD_TYPE_NS, 1453} efx_lightsout_offload_type_t; 1454 1455#define EFX_WOL_BITMAP_MASK_SIZE (48) 1456#define EFX_WOL_BITMAP_VALUE_SIZE (128) 1457 1458typedef union efx_wol_param_u { 1459 struct { 1460 uint8_t mac_addr[6]; 1461 } ewp_magic; 1462 struct { 1463 uint8_t mask[EFX_WOL_BITMAP_MASK_SIZE]; /* 1 bit per byte */ 1464 uint8_t value[EFX_WOL_BITMAP_VALUE_SIZE]; /* value to match */ 1465 uint8_t value_len; 1466 } ewp_bitmap; 1467} efx_wol_param_t; 1468 1469typedef union efx_lightsout_offload_param_u { 1470 struct { 1471 uint8_t mac_addr[6]; 1472 uint32_t ip; 1473 } elop_arp; 1474 struct { 1475 uint8_t mac_addr[6]; 1476 uint32_t solicited_node[4]; 1477 uint32_t ip[4]; 1478 } elop_ns; 1479} efx_lightsout_offload_param_t; 1480 1481extern __checkReturn efx_rc_t 1482efx_wol_init( 1483 __in efx_nic_t *enp); 1484 1485extern __checkReturn efx_rc_t 1486efx_wol_filter_clear( 1487 __in efx_nic_t *enp); 1488 1489extern __checkReturn efx_rc_t 1490efx_wol_filter_add( 1491 __in efx_nic_t *enp, 1492 __in efx_wol_type_t type, 1493 __in efx_wol_param_t *paramp, 1494 __out uint32_t *filter_idp); 1495 1496extern __checkReturn efx_rc_t 1497efx_wol_filter_remove( 1498 __in efx_nic_t *enp, 1499 __in uint32_t filter_id); 1500 1501extern __checkReturn efx_rc_t 1502efx_lightsout_offload_add( 1503 __in efx_nic_t *enp, 1504 __in efx_lightsout_offload_type_t type, 1505 __in efx_lightsout_offload_param_t *paramp, 1506 __out uint32_t *filter_idp); 1507 1508extern __checkReturn efx_rc_t 1509efx_lightsout_offload_remove( 1510 __in efx_nic_t *enp, 1511 __in efx_lightsout_offload_type_t type, 1512 __in uint32_t filter_id); 1513 1514extern void 1515efx_wol_fini( 1516 __in efx_nic_t *enp); 1517 1518#endif /* EFSYS_OPT_WOL */ 1519 1520#if EFSYS_OPT_DIAG 1521 1522typedef enum efx_pattern_type_t { 1523 EFX_PATTERN_BYTE_INCREMENT = 0, 1524 EFX_PATTERN_ALL_THE_SAME, 1525 EFX_PATTERN_BIT_ALTERNATE, 1526 EFX_PATTERN_BYTE_ALTERNATE, 1527 EFX_PATTERN_BYTE_CHANGING, 1528 EFX_PATTERN_BIT_SWEEP, 1529 EFX_PATTERN_NTYPES 1530} efx_pattern_type_t; 1531 1532typedef void 1533(*efx_sram_pattern_fn_t)( 1534 __in size_t row, 1535 __in boolean_t negate, 1536 __out efx_qword_t *eqp); 1537 1538extern __checkReturn efx_rc_t 1539efx_sram_test( 1540 __in efx_nic_t *enp, 1541 __in efx_pattern_type_t type); 1542 1543#endif /* EFSYS_OPT_DIAG */ 1544 1545extern __checkReturn efx_rc_t 1546efx_sram_buf_tbl_set( 1547 __in efx_nic_t *enp, 1548 __in uint32_t id, 1549 __in efsys_mem_t *esmp, 1550 __in size_t n); 1551 1552extern void 1553efx_sram_buf_tbl_clear( 1554 __in efx_nic_t *enp, 1555 __in uint32_t id, 1556 __in size_t n); 1557 1558#define EFX_BUF_TBL_SIZE 0x20000 1559 1560#define EFX_BUF_SIZE 4096 1561 1562/* EV */ 1563 1564typedef struct efx_evq_s efx_evq_t; 1565 1566#if EFSYS_OPT_QSTATS 1567 1568/* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 6f3843f5fe7cc843 */ 1569typedef enum efx_ev_qstat_e { 1570 EV_ALL, 1571 EV_RX, 1572 EV_RX_OK, 1573 EV_RX_FRM_TRUNC, 1574 EV_RX_TOBE_DISC, 1575 EV_RX_PAUSE_FRM_ERR, 1576 EV_RX_BUF_OWNER_ID_ERR, 1577 EV_RX_IPV4_HDR_CHKSUM_ERR, 1578 EV_RX_TCP_UDP_CHKSUM_ERR, 1579 EV_RX_ETH_CRC_ERR, 1580 EV_RX_IP_FRAG_ERR, 1581 EV_RX_MCAST_PKT, 1582 EV_RX_MCAST_HASH_MATCH, 1583 EV_RX_TCP_IPV4, 1584 EV_RX_TCP_IPV6, 1585 EV_RX_UDP_IPV4, 1586 EV_RX_UDP_IPV6, 1587 EV_RX_OTHER_IPV4, 1588 EV_RX_OTHER_IPV6, 1589 EV_RX_NON_IP, 1590 EV_RX_BATCH, 1591 EV_TX, 1592 EV_TX_WQ_FF_FULL, 1593 EV_TX_PKT_ERR, 1594 EV_TX_PKT_TOO_BIG, 1595 EV_TX_UNEXPECTED, 1596 EV_GLOBAL, 1597 EV_GLOBAL_MNT, 1598 EV_DRIVER, 1599 EV_DRIVER_SRM_UPD_DONE, 1600 EV_DRIVER_TX_DESCQ_FLS_DONE, 1601 EV_DRIVER_RX_DESCQ_FLS_DONE, 1602 EV_DRIVER_RX_DESCQ_FLS_FAILED, 1603 EV_DRIVER_RX_DSC_ERROR, 1604 EV_DRIVER_TX_DSC_ERROR, 1605 EV_DRV_GEN, 1606 EV_MCDI_RESPONSE, 1607 EV_NQSTATS 1608} efx_ev_qstat_t; 1609 1610/* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */ 1611 1612#endif /* EFSYS_OPT_QSTATS */ 1613 1614extern __checkReturn efx_rc_t 1615efx_ev_init( 1616 __in efx_nic_t *enp); 1617 1618extern void 1619efx_ev_fini( 1620 __in efx_nic_t *enp); 1621 1622#define EFX_EVQ_MAXNEVS 32768 1623#define EFX_EVQ_MINNEVS 512 1624 1625#define EFX_EVQ_SIZE(_nevs) ((_nevs) * sizeof (efx_qword_t)) 1626#define EFX_EVQ_NBUFS(_nevs) (EFX_EVQ_SIZE(_nevs) / EFX_BUF_SIZE) 1627 1628#define EFX_EVQ_FLAGS_TYPE_MASK (0x3) 1629#define EFX_EVQ_FLAGS_TYPE_AUTO (0x0) 1630#define EFX_EVQ_FLAGS_TYPE_THROUGHPUT (0x1) 1631#define EFX_EVQ_FLAGS_TYPE_LOW_LATENCY (0x2) 1632 1633#define EFX_EVQ_FLAGS_NOTIFY_MASK (0xC) 1634#define EFX_EVQ_FLAGS_NOTIFY_INTERRUPT (0x0) /* Interrupting (default) */ 1635#define EFX_EVQ_FLAGS_NOTIFY_DISABLED (0x4) /* Non-interrupting */ 1636 1637extern __checkReturn efx_rc_t 1638efx_ev_qcreate( 1639 __in efx_nic_t *enp, 1640 __in unsigned int index, 1641 __in efsys_mem_t *esmp, 1642 __in size_t n, 1643 __in uint32_t id, 1644 __in uint32_t us, 1645 __in uint32_t flags, 1646 __deref_out efx_evq_t **eepp); 1647 1648extern void 1649efx_ev_qpost( 1650 __in efx_evq_t *eep, 1651 __in uint16_t data); 1652 1653typedef __checkReturn boolean_t 1654(*efx_initialized_ev_t)( 1655 __in_opt void *arg); 1656 1657#define EFX_PKT_UNICAST 0x0004 1658#define EFX_PKT_START 0x0008 1659 1660#define EFX_PKT_VLAN_TAGGED 0x0010 1661#define EFX_CKSUM_TCPUDP 0x0020 1662#define EFX_CKSUM_IPV4 0x0040 1663#define EFX_PKT_CONT 0x0080 1664 1665#define EFX_CHECK_VLAN 0x0100 1666#define EFX_PKT_TCP 0x0200 1667#define EFX_PKT_UDP 0x0400 1668#define EFX_PKT_IPV4 0x0800 1669 1670#define EFX_PKT_IPV6 0x1000 1671#define EFX_PKT_PREFIX_LEN 0x2000 1672#define EFX_ADDR_MISMATCH 0x4000 1673#define EFX_DISCARD 0x8000 1674 1675#define EFX_EV_RX_NLABELS 32 1676#define EFX_EV_TX_NLABELS 32 1677 1678typedef __checkReturn boolean_t 1679(*efx_rx_ev_t)( 1680 __in_opt void *arg, 1681 __in uint32_t label, 1682 __in uint32_t id, 1683 __in uint32_t size, 1684 __in uint16_t flags); 1685 1686typedef __checkReturn boolean_t 1687(*efx_tx_ev_t)( 1688 __in_opt void *arg, 1689 __in uint32_t label, 1690 __in uint32_t id); 1691 1692#define EFX_EXCEPTION_RX_RECOVERY 0x00000001 1693#define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002 1694#define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003 1695#define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004 1696#define EFX_EXCEPTION_FWALERT_SRAM 0x00000005 1697#define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006 1698#define EFX_EXCEPTION_RX_ERROR 0x00000007 1699#define EFX_EXCEPTION_TX_ERROR 0x00000008 1700#define EFX_EXCEPTION_EV_ERROR 0x00000009 1701 1702typedef __checkReturn boolean_t 1703(*efx_exception_ev_t)( 1704 __in_opt void *arg, 1705 __in uint32_t label, 1706 __in uint32_t data); 1707 1708typedef __checkReturn boolean_t 1709(*efx_rxq_flush_done_ev_t)( 1710 __in_opt void *arg, 1711 __in uint32_t rxq_index); 1712 1713typedef __checkReturn boolean_t 1714(*efx_rxq_flush_failed_ev_t)( 1715 __in_opt void *arg, 1716 __in uint32_t rxq_index); 1717 1718typedef __checkReturn boolean_t 1719(*efx_txq_flush_done_ev_t)( 1720 __in_opt void *arg, 1721 __in uint32_t txq_index); 1722 1723typedef __checkReturn boolean_t 1724(*efx_software_ev_t)( 1725 __in_opt void *arg, 1726 __in uint16_t magic); 1727 1728typedef __checkReturn boolean_t 1729(*efx_sram_ev_t)( 1730 __in_opt void *arg, 1731 __in uint32_t code); 1732 1733#define EFX_SRAM_CLEAR 0 1734#define EFX_SRAM_UPDATE 1 1735#define EFX_SRAM_ILLEGAL_CLEAR 2 1736 1737typedef __checkReturn boolean_t 1738(*efx_wake_up_ev_t)( 1739 __in_opt void *arg, 1740 __in uint32_t label); 1741 1742typedef __checkReturn boolean_t 1743(*efx_timer_ev_t)( 1744 __in_opt void *arg, 1745 __in uint32_t label); 1746 1747typedef __checkReturn boolean_t 1748(*efx_link_change_ev_t)( 1749 __in_opt void *arg, 1750 __in efx_link_mode_t link_mode); 1751 1752#if EFSYS_OPT_MON_STATS 1753 1754typedef __checkReturn boolean_t 1755(*efx_monitor_ev_t)( 1756 __in_opt void *arg, 1757 __in efx_mon_stat_t id, 1758 __in efx_mon_stat_value_t value); 1759 1760#endif /* EFSYS_OPT_MON_STATS */ 1761 1762#if EFSYS_OPT_MAC_STATS 1763 1764typedef __checkReturn boolean_t 1765(*efx_mac_stats_ev_t)( 1766 __in_opt void *arg, 1767 __in uint32_t generation 1768 ); 1769 1770#endif /* EFSYS_OPT_MAC_STATS */ 1771 1772typedef struct efx_ev_callbacks_s { 1773 efx_initialized_ev_t eec_initialized; 1774 efx_rx_ev_t eec_rx; 1775 efx_tx_ev_t eec_tx; 1776 efx_exception_ev_t eec_exception; 1777 efx_rxq_flush_done_ev_t eec_rxq_flush_done; 1778 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed; 1779 efx_txq_flush_done_ev_t eec_txq_flush_done; 1780 efx_software_ev_t eec_software; 1781 efx_sram_ev_t eec_sram; 1782 efx_wake_up_ev_t eec_wake_up; 1783 efx_timer_ev_t eec_timer; 1784 efx_link_change_ev_t eec_link_change; 1785#if EFSYS_OPT_MON_STATS 1786 efx_monitor_ev_t eec_monitor; 1787#endif /* EFSYS_OPT_MON_STATS */ 1788#if EFSYS_OPT_MAC_STATS 1789 efx_mac_stats_ev_t eec_mac_stats; 1790#endif /* EFSYS_OPT_MAC_STATS */ 1791} efx_ev_callbacks_t; 1792 1793extern __checkReturn boolean_t 1794efx_ev_qpending( 1795 __in efx_evq_t *eep, 1796 __in unsigned int count); 1797 1798#if EFSYS_OPT_EV_PREFETCH 1799 1800extern void 1801efx_ev_qprefetch( 1802 __in efx_evq_t *eep, 1803 __in unsigned int count); 1804 1805#endif /* EFSYS_OPT_EV_PREFETCH */ 1806 1807extern void 1808efx_ev_qpoll( 1809 __in efx_evq_t *eep, 1810 __inout unsigned int *countp, 1811 __in const efx_ev_callbacks_t *eecp, 1812 __in_opt void *arg); 1813 1814extern __checkReturn efx_rc_t 1815efx_ev_usecs_to_ticks( 1816 __in efx_nic_t *enp, 1817 __in unsigned int usecs, 1818 __out unsigned int *ticksp); 1819 1820extern __checkReturn efx_rc_t 1821efx_ev_qmoderate( 1822 __in efx_evq_t *eep, 1823 __in unsigned int us); 1824 1825extern __checkReturn efx_rc_t 1826efx_ev_qprime( 1827 __in efx_evq_t *eep, 1828 __in unsigned int count); 1829 1830#if EFSYS_OPT_QSTATS 1831 1832#if EFSYS_OPT_NAMES 1833 1834extern const char * 1835efx_ev_qstat_name( 1836 __in efx_nic_t *enp, 1837 __in unsigned int id); 1838 1839#endif /* EFSYS_OPT_NAMES */ 1840 1841extern void 1842efx_ev_qstats_update( 1843 __in efx_evq_t *eep, 1844 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat); 1845 1846#endif /* EFSYS_OPT_QSTATS */ 1847 1848extern void 1849efx_ev_qdestroy( 1850 __in efx_evq_t *eep); 1851 1852/* RX */ 1853 1854extern __checkReturn efx_rc_t 1855efx_rx_init( 1856 __inout efx_nic_t *enp); 1857 1858extern void 1859efx_rx_fini( 1860 __in efx_nic_t *enp); 1861 1862#if EFSYS_OPT_RX_SCATTER 1863 __checkReturn efx_rc_t 1864efx_rx_scatter_enable( 1865 __in efx_nic_t *enp, 1866 __in unsigned int buf_size); 1867#endif /* EFSYS_OPT_RX_SCATTER */ 1868 1869#if EFSYS_OPT_RX_SCALE 1870 1871typedef enum efx_rx_hash_alg_e { 1872 EFX_RX_HASHALG_LFSR = 0, 1873 EFX_RX_HASHALG_TOEPLITZ 1874} efx_rx_hash_alg_t; 1875 1876#define EFX_RX_HASH_IPV4 (1U << 0) 1877#define EFX_RX_HASH_TCPIPV4 (1U << 1) 1878#define EFX_RX_HASH_IPV6 (1U << 2) 1879#define EFX_RX_HASH_TCPIPV6 (1U << 3) 1880 1881typedef unsigned int efx_rx_hash_type_t; 1882 1883typedef enum efx_rx_hash_support_e { 1884 EFX_RX_HASH_UNAVAILABLE = 0, /* Hardware hash not inserted */ 1885 EFX_RX_HASH_AVAILABLE /* Insert hash with/without RSS */ 1886} efx_rx_hash_support_t; 1887 1888#define EFX_RSS_TBL_SIZE 128 /* Rows in RX indirection table */ 1889#define EFX_MAXRSS 64 /* RX indirection entry range */ 1890#define EFX_MAXRSS_LEGACY 16 /* See bug16611 and bug17213 */ 1891 1892typedef enum efx_rx_scale_support_e { 1893 EFX_RX_SCALE_UNAVAILABLE = 0, /* Not supported */ 1894 EFX_RX_SCALE_EXCLUSIVE, /* Writable key/indirection table */ 1895 EFX_RX_SCALE_SHARED /* Read-only key/indirection table */ 1896} efx_rx_scale_support_t; 1897 1898extern __checkReturn efx_rc_t 1899efx_rx_hash_support_get( 1900 __in efx_nic_t *enp, 1901 __out efx_rx_hash_support_t *supportp); 1902 1903 1904extern __checkReturn efx_rc_t 1905efx_rx_scale_support_get( 1906 __in efx_nic_t *enp, 1907 __out efx_rx_scale_support_t *supportp); 1908 1909extern __checkReturn efx_rc_t 1910efx_rx_scale_mode_set( 1911 __in efx_nic_t *enp, 1912 __in efx_rx_hash_alg_t alg, 1913 __in efx_rx_hash_type_t type, 1914 __in boolean_t insert); 1915 1916extern __checkReturn efx_rc_t 1917efx_rx_scale_tbl_set( 1918 __in efx_nic_t *enp, 1919 __in_ecount(n) unsigned int *table, 1920 __in size_t n); 1921 1922extern __checkReturn efx_rc_t 1923efx_rx_scale_key_set( 1924 __in efx_nic_t *enp, 1925 __in_ecount(n) uint8_t *key, 1926 __in size_t n); 1927 1928extern __checkReturn uint32_t 1929efx_pseudo_hdr_hash_get( 1930 __in efx_rxq_t *erp, 1931 __in efx_rx_hash_alg_t func, 1932 __in uint8_t *buffer); 1933 1934#endif /* EFSYS_OPT_RX_SCALE */ 1935 1936extern __checkReturn efx_rc_t 1937efx_pseudo_hdr_pkt_length_get( 1938 __in efx_rxq_t *erp, 1939 __in uint8_t *buffer, 1940 __out uint16_t *pkt_lengthp); 1941 1942#define EFX_RXQ_MAXNDESCS 4096 1943#define EFX_RXQ_MINNDESCS 512 1944 1945#define EFX_RXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t)) 1946#define EFX_RXQ_NBUFS(_ndescs) (EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE) 1947#define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16) 1948#define EFX_RXQ_DC_NDESCS(_dcsize) (8 << _dcsize) 1949 1950typedef enum efx_rxq_type_e { 1951 EFX_RXQ_TYPE_DEFAULT, 1952 EFX_RXQ_TYPE_SCATTER, 1953 EFX_RXQ_NTYPES 1954} efx_rxq_type_t; 1955 1956extern __checkReturn efx_rc_t 1957efx_rx_qcreate( 1958 __in efx_nic_t *enp, 1959 __in unsigned int index, 1960 __in unsigned int label, 1961 __in efx_rxq_type_t type, 1962 __in efsys_mem_t *esmp, 1963 __in size_t n, 1964 __in uint32_t id, 1965 __in efx_evq_t *eep, 1966 __deref_out efx_rxq_t **erpp); 1967 1968typedef struct efx_buffer_s { 1969 efsys_dma_addr_t eb_addr; 1970 size_t eb_size; 1971 boolean_t eb_eop; 1972} efx_buffer_t; 1973 1974typedef struct efx_desc_s { 1975 efx_qword_t ed_eq; 1976} efx_desc_t; 1977 1978extern void 1979efx_rx_qpost( 1980 __in efx_rxq_t *erp, 1981 __in_ecount(n) efsys_dma_addr_t *addrp, 1982 __in size_t size, 1983 __in unsigned int n, 1984 __in unsigned int completed, 1985 __in unsigned int added); 1986 1987extern void 1988efx_rx_qpush( 1989 __in efx_rxq_t *erp, 1990 __in unsigned int added, 1991 __inout unsigned int *pushedp); 1992 1993extern __checkReturn efx_rc_t 1994efx_rx_qflush( 1995 __in efx_rxq_t *erp); 1996 1997extern void 1998efx_rx_qenable( 1999 __in efx_rxq_t *erp); 2000 2001extern void 2002efx_rx_qdestroy( 2003 __in efx_rxq_t *erp); 2004 2005/* TX */ 2006 2007typedef struct efx_txq_s efx_txq_t; 2008 2009#if EFSYS_OPT_QSTATS 2010 2011/* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */ 2012typedef enum efx_tx_qstat_e { 2013 TX_POST, 2014 TX_POST_PIO, 2015 TX_NQSTATS 2016} efx_tx_qstat_t; 2017 2018/* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */ 2019 2020#endif /* EFSYS_OPT_QSTATS */ 2021 2022extern __checkReturn efx_rc_t 2023efx_tx_init( 2024 __in efx_nic_t *enp); 2025 2026extern void 2027efx_tx_fini( 2028 __in efx_nic_t *enp); 2029 2030#define EFX_BUG35388_WORKAROUND(_encp) \ 2031 (((_encp) == NULL) ? 1 : ((_encp)->enc_bug35388_workaround != 0)) 2032 2033#define EFX_TXQ_MAXNDESCS(_encp) \ 2034 ((EFX_BUG35388_WORKAROUND(_encp)) ? 2048 : 4096) 2035 2036#define EFX_TXQ_MINNDESCS 512 2037 2038#define EFX_TXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t)) 2039#define EFX_TXQ_NBUFS(_ndescs) (EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE) 2040#define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16) 2041#define EFX_TXQ_DC_NDESCS(_dcsize) (8 << _dcsize) 2042 2043#define EFX_TXQ_MAX_BUFS 8 /* Maximum independent of EFX_BUG35388_WORKAROUND. */ 2044 2045#define EFX_TXQ_CKSUM_IPV4 0x0001 2046#define EFX_TXQ_CKSUM_TCPUDP 0x0002 2047#define EFX_TXQ_FATSOV2 0x0004 2048 2049extern __checkReturn efx_rc_t 2050efx_tx_qcreate( 2051 __in efx_nic_t *enp, 2052 __in unsigned int index, 2053 __in unsigned int label, 2054 __in efsys_mem_t *esmp, 2055 __in size_t n, 2056 __in uint32_t id, 2057 __in uint16_t flags, 2058 __in efx_evq_t *eep, 2059 __deref_out efx_txq_t **etpp, 2060 __out unsigned int *addedp); 2061 2062extern __checkReturn efx_rc_t 2063efx_tx_qpost( 2064 __in efx_txq_t *etp, 2065 __in_ecount(n) efx_buffer_t *eb, 2066 __in unsigned int n, 2067 __in unsigned int completed, 2068 __inout unsigned int *addedp); 2069 2070extern __checkReturn efx_rc_t 2071efx_tx_qpace( 2072 __in efx_txq_t *etp, 2073 __in unsigned int ns); 2074 2075extern void 2076efx_tx_qpush( 2077 __in efx_txq_t *etp, 2078 __in unsigned int added, 2079 __in unsigned int pushed); 2080 2081extern __checkReturn efx_rc_t 2082efx_tx_qflush( 2083 __in efx_txq_t *etp); 2084 2085extern void 2086efx_tx_qenable( 2087 __in efx_txq_t *etp); 2088 2089extern __checkReturn efx_rc_t 2090efx_tx_qpio_enable( 2091 __in efx_txq_t *etp); 2092 2093extern void 2094efx_tx_qpio_disable( 2095 __in efx_txq_t *etp); 2096 2097extern __checkReturn efx_rc_t 2098efx_tx_qpio_write( 2099 __in efx_txq_t *etp, 2100 __in_ecount(buf_length) uint8_t *buffer, 2101 __in size_t buf_length, 2102 __in size_t pio_buf_offset); 2103 2104extern __checkReturn efx_rc_t 2105efx_tx_qpio_post( 2106 __in efx_txq_t *etp, 2107 __in size_t pkt_length, 2108 __in unsigned int completed, 2109 __inout unsigned int *addedp); 2110 2111extern __checkReturn efx_rc_t 2112efx_tx_qdesc_post( 2113 __in efx_txq_t *etp, 2114 __in_ecount(n) efx_desc_t *ed, 2115 __in unsigned int n, 2116 __in unsigned int completed, 2117 __inout unsigned int *addedp); 2118 2119extern void 2120efx_tx_qdesc_dma_create( 2121 __in efx_txq_t *etp, 2122 __in efsys_dma_addr_t addr, 2123 __in size_t size, 2124 __in boolean_t eop, 2125 __out efx_desc_t *edp); 2126 2127extern void 2128efx_tx_qdesc_tso_create( 2129 __in efx_txq_t *etp, 2130 __in uint16_t ipv4_id, 2131 __in uint32_t tcp_seq, 2132 __in uint8_t tcp_flags, 2133 __out efx_desc_t *edp); 2134 2135/* Number of FATSOv2 option descriptors */ 2136#define EFX_TX_FATSOV2_OPT_NDESCS 2 2137 2138/* Maximum number of DMA segments per TSO packet (not superframe) */ 2139#define EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX 24 2140 2141extern void 2142efx_tx_qdesc_tso2_create( 2143 __in efx_txq_t *etp, 2144 __in uint16_t ipv4_id, 2145 __in uint32_t tcp_seq, 2146 __in uint16_t tcp_mss, 2147 __out_ecount(count) efx_desc_t *edp, 2148 __in int count); 2149 2150extern void 2151efx_tx_qdesc_vlantci_create( 2152 __in efx_txq_t *etp, 2153 __in uint16_t tci, 2154 __out efx_desc_t *edp); 2155 2156#if EFSYS_OPT_QSTATS 2157 2158#if EFSYS_OPT_NAMES 2159 2160extern const char * 2161efx_tx_qstat_name( 2162 __in efx_nic_t *etp, 2163 __in unsigned int id); 2164 2165#endif /* EFSYS_OPT_NAMES */ 2166 2167extern void 2168efx_tx_qstats_update( 2169 __in efx_txq_t *etp, 2170 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat); 2171 2172#endif /* EFSYS_OPT_QSTATS */ 2173 2174extern void 2175efx_tx_qdestroy( 2176 __in efx_txq_t *etp); 2177 2178 2179/* FILTER */ 2180 2181#if EFSYS_OPT_FILTER 2182 2183#define EFX_ETHER_TYPE_IPV4 0x0800 2184#define EFX_ETHER_TYPE_IPV6 0x86DD 2185 2186#define EFX_IPPROTO_TCP 6 2187#define EFX_IPPROTO_UDP 17 2188 2189/* Use RSS to spread across multiple queues */ 2190#define EFX_FILTER_FLAG_RX_RSS 0x01 2191/* Enable RX scatter */ 2192#define EFX_FILTER_FLAG_RX_SCATTER 0x02 2193/* 2194 * Override an automatic filter (priority EFX_FILTER_PRI_AUTO). 2195 * May only be set by the filter implementation for each type. 2196 * A removal request will restore the automatic filter in its place. 2197 */ 2198#define EFX_FILTER_FLAG_RX_OVER_AUTO 0x04 2199/* Filter is for RX */ 2200#define EFX_FILTER_FLAG_RX 0x08 2201/* Filter is for TX */ 2202#define EFX_FILTER_FLAG_TX 0x10 2203 2204typedef unsigned int efx_filter_flags_t; 2205 2206typedef enum efx_filter_match_flags_e { 2207 EFX_FILTER_MATCH_REM_HOST = 0x0001, /* Match by remote IP host 2208 * address */ 2209 EFX_FILTER_MATCH_LOC_HOST = 0x0002, /* Match by local IP host 2210 * address */ 2211 EFX_FILTER_MATCH_REM_MAC = 0x0004, /* Match by remote MAC address */ 2212 EFX_FILTER_MATCH_REM_PORT = 0x0008, /* Match by remote TCP/UDP port */ 2213 EFX_FILTER_MATCH_LOC_MAC = 0x0010, /* Match by remote TCP/UDP port */ 2214 EFX_FILTER_MATCH_LOC_PORT = 0x0020, /* Match by local TCP/UDP port */ 2215 EFX_FILTER_MATCH_ETHER_TYPE = 0x0040, /* Match by Ether-type */ 2216 EFX_FILTER_MATCH_INNER_VID = 0x0080, /* Match by inner VLAN ID */ 2217 EFX_FILTER_MATCH_OUTER_VID = 0x0100, /* Match by outer VLAN ID */ 2218 EFX_FILTER_MATCH_IP_PROTO = 0x0200, /* Match by IP transport 2219 * protocol */ 2220 /* Match otherwise-unmatched multicast and broadcast packets */ 2221 EFX_FILTER_MATCH_UNKNOWN_MCAST_DST = 0x40000000, 2222 /* Match otherwise-unmatched unicast packets */ 2223 EFX_FILTER_MATCH_UNKNOWN_UCAST_DST = 0x80000000, 2224} efx_filter_match_flags_t; 2225 2226typedef enum efx_filter_priority_s { 2227 EFX_FILTER_PRI_HINT = 0, /* Performance hint */ 2228 EFX_FILTER_PRI_AUTO, /* Automatic filter based on device 2229 * address list or hardware 2230 * requirements. This may only be used 2231 * by the filter implementation for 2232 * each NIC type. */ 2233 EFX_FILTER_PRI_MANUAL, /* Manually configured filter */ 2234 EFX_FILTER_PRI_REQUIRED, /* Required for correct behaviour of the 2235 * client (e.g. SR-IOV, HyperV VMQ etc.) 2236 */ 2237} efx_filter_priority_t; 2238 2239/* 2240 * FIXME: All these fields are assumed to be in little-endian byte order. 2241 * It may be better for some to be big-endian. See bug42804. 2242 */ 2243 2244typedef struct efx_filter_spec_s { 2245 uint32_t efs_match_flags; 2246 uint32_t efs_priority:2; 2247 uint32_t efs_flags:6; 2248 uint32_t efs_dmaq_id:12; 2249 uint32_t efs_rss_context; 2250 uint16_t efs_outer_vid; 2251 uint16_t efs_inner_vid; 2252 uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN]; 2253 uint8_t efs_rem_mac[EFX_MAC_ADDR_LEN]; 2254 uint16_t efs_ether_type; 2255 uint8_t efs_ip_proto; 2256 uint16_t efs_loc_port; 2257 uint16_t efs_rem_port; 2258 efx_oword_t efs_rem_host; 2259 efx_oword_t efs_loc_host; 2260} efx_filter_spec_t; 2261 2262 2263/* Default values for use in filter specifications */ 2264#define EFX_FILTER_SPEC_RSS_CONTEXT_DEFAULT 0xffffffff 2265#define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP 0xfff 2266#define EFX_FILTER_SPEC_VID_UNSPEC 0xffff 2267 2268extern __checkReturn efx_rc_t 2269efx_filter_init( 2270 __in efx_nic_t *enp); 2271 2272extern void 2273efx_filter_fini( 2274 __in efx_nic_t *enp); 2275 2276extern __checkReturn efx_rc_t 2277efx_filter_insert( 2278 __in efx_nic_t *enp, 2279 __inout efx_filter_spec_t *spec); 2280 2281extern __checkReturn efx_rc_t 2282efx_filter_remove( 2283 __in efx_nic_t *enp, 2284 __inout efx_filter_spec_t *spec); 2285 2286extern __checkReturn efx_rc_t 2287efx_filter_restore( 2288 __in efx_nic_t *enp); 2289 2290extern __checkReturn efx_rc_t 2291efx_filter_supported_filters( 2292 __in efx_nic_t *enp, 2293 __out_ecount(buffer_length) uint32_t *buffer, 2294 __in size_t buffer_length, 2295 __out size_t *list_lengthp); 2296 2297extern void 2298efx_filter_spec_init_rx( 2299 __out efx_filter_spec_t *spec, 2300 __in efx_filter_priority_t priority, 2301 __in efx_filter_flags_t flags, 2302 __in efx_rxq_t *erp); 2303 2304extern void 2305efx_filter_spec_init_tx( 2306 __out efx_filter_spec_t *spec, 2307 __in efx_txq_t *etp); 2308 2309extern __checkReturn efx_rc_t 2310efx_filter_spec_set_ipv4_local( 2311 __inout efx_filter_spec_t *spec, 2312 __in uint8_t proto, 2313 __in uint32_t host, 2314 __in uint16_t port); 2315 2316extern __checkReturn efx_rc_t 2317efx_filter_spec_set_ipv4_full( 2318 __inout efx_filter_spec_t *spec, 2319 __in uint8_t proto, 2320 __in uint32_t lhost, 2321 __in uint16_t lport, 2322 __in uint32_t rhost, 2323 __in uint16_t rport); 2324 2325extern __checkReturn efx_rc_t 2326efx_filter_spec_set_eth_local( 2327 __inout efx_filter_spec_t *spec, 2328 __in uint16_t vid, 2329 __in const uint8_t *addr); 2330 2331extern __checkReturn efx_rc_t 2332efx_filter_spec_set_uc_def( 2333 __inout efx_filter_spec_t *spec); 2334 2335extern __checkReturn efx_rc_t 2336efx_filter_spec_set_mc_def( 2337 __inout efx_filter_spec_t *spec); 2338 2339#endif /* EFSYS_OPT_FILTER */ 2340 2341/* HASH */ 2342 2343extern __checkReturn uint32_t 2344efx_hash_dwords( 2345 __in_ecount(count) uint32_t const *input, 2346 __in size_t count, 2347 __in uint32_t init); 2348 2349extern __checkReturn uint32_t 2350efx_hash_bytes( 2351 __in_ecount(length) uint8_t const *input, 2352 __in size_t length, 2353 __in uint32_t init); 2354 2355#if EFSYS_OPT_LICENSING 2356 2357/* LICENSING */ 2358 2359typedef struct efx_key_stats_s { 2360 uint32_t eks_valid; 2361 uint32_t eks_invalid; 2362 uint32_t eks_blacklisted; 2363 uint32_t eks_unverifiable; 2364 uint32_t eks_wrong_node; 2365 uint32_t eks_licensed_apps_lo; 2366 uint32_t eks_licensed_apps_hi; 2367 uint32_t eks_licensed_features_lo; 2368 uint32_t eks_licensed_features_hi; 2369} efx_key_stats_t; 2370 2371extern __checkReturn efx_rc_t 2372efx_lic_init( 2373 __in efx_nic_t *enp); 2374 2375extern void 2376efx_lic_fini( 2377 __in efx_nic_t *enp); 2378 2379extern __checkReturn boolean_t 2380efx_lic_check_support( 2381 __in efx_nic_t *enp); 2382 2383extern __checkReturn efx_rc_t 2384efx_lic_update_licenses( 2385 __in efx_nic_t *enp); 2386 2387extern __checkReturn efx_rc_t 2388efx_lic_get_key_stats( 2389 __in efx_nic_t *enp, 2390 __out efx_key_stats_t *ksp); 2391 2392extern __checkReturn efx_rc_t 2393efx_lic_app_state( 2394 __in efx_nic_t *enp, 2395 __in uint64_t app_id, 2396 __out boolean_t *licensedp); 2397 2398extern __checkReturn efx_rc_t 2399efx_lic_get_id( 2400 __in efx_nic_t *enp, 2401 __in size_t buffer_size, 2402 __out uint32_t *typep, 2403 __out size_t *lengthp, 2404 __out_opt uint8_t *bufferp); 2405 2406 2407extern __checkReturn efx_rc_t 2408efx_lic_find_start( 2409 __in efx_nic_t *enp, 2410 __in_bcount(buffer_size) 2411 caddr_t bufferp, 2412 __in size_t buffer_size, 2413 __out uint32_t *startp 2414 ); 2415 2416extern __checkReturn efx_rc_t 2417efx_lic_find_end( 2418 __in efx_nic_t *enp, 2419 __in_bcount(buffer_size) 2420 caddr_t bufferp, 2421 __in size_t buffer_size, 2422 __in uint32_t offset, 2423 __out uint32_t *endp 2424 ); 2425 2426extern __checkReturn __success(return != B_FALSE) boolean_t 2427efx_lic_find_key( 2428 __in efx_nic_t *enp, 2429 __in_bcount(buffer_size) 2430 caddr_t bufferp, 2431 __in size_t buffer_size, 2432 __in uint32_t offset, 2433 __out uint32_t *startp, 2434 __out uint32_t *lengthp 2435 ); 2436 2437extern __checkReturn __success(return != B_FALSE) boolean_t 2438efx_lic_validate_key( 2439 __in efx_nic_t *enp, 2440 __in_bcount(length) caddr_t keyp, 2441 __in uint32_t length 2442 ); 2443 2444extern __checkReturn efx_rc_t 2445efx_lic_read_key( 2446 __in efx_nic_t *enp, 2447 __in_bcount(buffer_size) 2448 caddr_t bufferp, 2449 __in size_t buffer_size, 2450 __in uint32_t offset, 2451 __in uint32_t length, 2452 __out_bcount_part(key_max_size, *lengthp) 2453 caddr_t keyp, 2454 __in size_t key_max_size, 2455 __out uint32_t *lengthp 2456 ); 2457 2458extern __checkReturn efx_rc_t 2459efx_lic_write_key( 2460 __in efx_nic_t *enp, 2461 __in_bcount(buffer_size) 2462 caddr_t bufferp, 2463 __in size_t buffer_size, 2464 __in uint32_t offset, 2465 __in_bcount(length) caddr_t keyp, 2466 __in uint32_t length, 2467 __out uint32_t *lengthp 2468 ); 2469 2470 __checkReturn efx_rc_t 2471efx_lic_delete_key( 2472 __in efx_nic_t *enp, 2473 __in_bcount(buffer_size) 2474 caddr_t bufferp, 2475 __in size_t buffer_size, 2476 __in uint32_t offset, 2477 __in uint32_t length, 2478 __in uint32_t end, 2479 __out uint32_t *deltap 2480 ); 2481 2482extern __checkReturn efx_rc_t 2483efx_lic_create_partition( 2484 __in efx_nic_t *enp, 2485 __in_bcount(buffer_size) 2486 caddr_t bufferp, 2487 __in size_t buffer_size 2488 ); 2489 2490extern __checkReturn efx_rc_t 2491efx_lic_finish_partition( 2492 __in efx_nic_t *enp, 2493 __in_bcount(buffer_size) 2494 caddr_t bufferp, 2495 __in size_t buffer_size 2496 ); 2497 2498#endif /* EFSYS_OPT_LICENSING */ 2499 2500 2501 2502#ifdef __cplusplus 2503} 2504#endif 2505 2506#endif /* _SYS_EFX_H */ 2507