efx.h revision 311030 
1/*-
2 * Copyright (c) 2006-2016 Solarflare Communications Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,
9 *    this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 *    this list of conditions and the following disclaimer in the documentation
12 *    and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
29 *
30 * $FreeBSD: stable/11/sys/dev/sfxge/common/efx.h 311030 2017-01-01 19:37:22Z arybchik $
31 */
32
33#ifndef	_SYS_EFX_H
34#define	_SYS_EFX_H
35
36#include "efsys.h"
37#include "efx_check.h"
38#include "efx_phy_ids.h"
39
40#ifdef	__cplusplus
41extern "C" {
42#endif
43
44#define	EFX_STATIC_ASSERT(_cond)		\
45	((void)sizeof(char[(_cond) ? 1 : -1]))
46
47#define	EFX_ARRAY_SIZE(_array)			\
48	(sizeof(_array) / sizeof((_array)[0]))
49
50#define	EFX_FIELD_OFFSET(_type, _field)		\
51	((size_t) &(((_type *)0)->_field))
52
53/* Return codes */
54
55typedef __success(return == 0) int efx_rc_t;
56
57
58/* Chip families */
59
60typedef enum efx_family_e {
61	EFX_FAMILY_INVALID,
62	EFX_FAMILY_FALCON,	/* Obsolete and not supported */
63	EFX_FAMILY_SIENA,
64	EFX_FAMILY_HUNTINGTON,
65	EFX_FAMILY_MEDFORD,
66	EFX_FAMILY_NTYPES
67} efx_family_t;
68
69extern	__checkReturn	efx_rc_t
70efx_family(
71	__in		uint16_t venid,
72	__in		uint16_t devid,
73	__out		efx_family_t *efp);
74
75
76#define	EFX_PCI_VENID_SFC			0x1924
77
78#define	EFX_PCI_DEVID_FALCON			0x0710	/* SFC4000 */
79
80#define	EFX_PCI_DEVID_BETHPAGE			0x0803	/* SFC9020 */
81#define	EFX_PCI_DEVID_SIENA			0x0813	/* SFL9021 */
82#define	EFX_PCI_DEVID_SIENA_F1_UNINIT		0x0810
83
84#define	EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT	0x0901
85#define	EFX_PCI_DEVID_FARMINGDALE		0x0903	/* SFC9120 PF */
86#define	EFX_PCI_DEVID_GREENPORT			0x0923	/* SFC9140 PF */
87
88#define	EFX_PCI_DEVID_FARMINGDALE_VF		0x1903	/* SFC9120 VF */
89#define	EFX_PCI_DEVID_GREENPORT_VF		0x1923	/* SFC9140 VF */
90
91#define	EFX_PCI_DEVID_MEDFORD_PF_UNINIT		0x0913
92#define	EFX_PCI_DEVID_MEDFORD			0x0A03	/* SFC9240 PF */
93#define	EFX_PCI_DEVID_MEDFORD_VF		0x1A03	/* SFC9240 VF */
94
95#define	EFX_MEM_BAR	2
96
97/* Error codes */
98
99enum {
100	EFX_ERR_INVALID,
101	EFX_ERR_SRAM_OOB,
102	EFX_ERR_BUFID_DC_OOB,
103	EFX_ERR_MEM_PERR,
104	EFX_ERR_RBUF_OWN,
105	EFX_ERR_TBUF_OWN,
106	EFX_ERR_RDESQ_OWN,
107	EFX_ERR_TDESQ_OWN,
108	EFX_ERR_EVQ_OWN,
109	EFX_ERR_EVFF_OFLO,
110	EFX_ERR_ILL_ADDR,
111	EFX_ERR_SRAM_PERR,
112	EFX_ERR_NCODES
113};
114
115/* Calculate the IEEE 802.3 CRC32 of a MAC addr */
116extern	__checkReturn		uint32_t
117efx_crc32_calculate(
118	__in			uint32_t crc_init,
119	__in_ecount(length)	uint8_t const *input,
120	__in			int length);
121
122
123/* Type prototypes */
124
125typedef struct efx_rxq_s	efx_rxq_t;
126
127/* NIC */
128
129typedef struct efx_nic_s	efx_nic_t;
130
131extern	__checkReturn	efx_rc_t
132efx_nic_create(
133	__in		efx_family_t family,
134	__in		efsys_identifier_t *esip,
135	__in		efsys_bar_t *esbp,
136	__in		efsys_lock_t *eslp,
137	__deref_out	efx_nic_t **enpp);
138
139extern	__checkReturn	efx_rc_t
140efx_nic_probe(
141	__in		efx_nic_t *enp);
142
143extern	__checkReturn	efx_rc_t
144efx_nic_init(
145	__in		efx_nic_t *enp);
146
147extern	__checkReturn	efx_rc_t
148efx_nic_reset(
149	__in		efx_nic_t *enp);
150
151#if EFSYS_OPT_DIAG
152
153extern	__checkReturn	efx_rc_t
154efx_nic_register_test(
155	__in		efx_nic_t *enp);
156
157#endif	/* EFSYS_OPT_DIAG */
158
159extern		void
160efx_nic_fini(
161	__in		efx_nic_t *enp);
162
163extern		void
164efx_nic_unprobe(
165	__in		efx_nic_t *enp);
166
167extern		void
168efx_nic_destroy(
169	__in	efx_nic_t *enp);
170
171#define	EFX_PCIE_LINK_SPEED_GEN1		1
172#define	EFX_PCIE_LINK_SPEED_GEN2		2
173#define	EFX_PCIE_LINK_SPEED_GEN3		3
174
175typedef enum efx_pcie_link_performance_e {
176	EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH,
177	EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH,
178	EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY,
179	EFX_PCIE_LINK_PERFORMANCE_OPTIMAL
180} efx_pcie_link_performance_t;
181
182extern	__checkReturn	efx_rc_t
183efx_nic_calculate_pcie_link_bandwidth(
184	__in		uint32_t pcie_link_width,
185	__in		uint32_t pcie_link_gen,
186	__out		uint32_t *bandwidth_mbpsp);
187
188extern	__checkReturn	efx_rc_t
189efx_nic_check_pcie_link_speed(
190	__in		efx_nic_t *enp,
191	__in		uint32_t pcie_link_width,
192	__in		uint32_t pcie_link_gen,
193	__out		efx_pcie_link_performance_t *resultp);
194
195#if EFSYS_OPT_MCDI
196
197#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
198/* Huntington and Medford require MCDIv2 commands */
199#define	WITH_MCDI_V2 1
200#endif
201
202typedef struct efx_mcdi_req_s efx_mcdi_req_t;
203
204typedef enum efx_mcdi_exception_e {
205	EFX_MCDI_EXCEPTION_MC_REBOOT,
206	EFX_MCDI_EXCEPTION_MC_BADASSERT,
207} efx_mcdi_exception_t;
208
209#if EFSYS_OPT_MCDI_LOGGING
210typedef enum efx_log_msg_e {
211	EFX_LOG_INVALID,
212	EFX_LOG_MCDI_REQUEST,
213	EFX_LOG_MCDI_RESPONSE,
214} efx_log_msg_t;
215#endif /* EFSYS_OPT_MCDI_LOGGING */
216
217typedef struct efx_mcdi_transport_s {
218	void		*emt_context;
219	efsys_mem_t	*emt_dma_mem;
220	void		(*emt_execute)(void *, efx_mcdi_req_t *);
221	void		(*emt_ev_cpl)(void *);
222	void		(*emt_exception)(void *, efx_mcdi_exception_t);
223#if EFSYS_OPT_MCDI_LOGGING
224	void		(*emt_logger)(void *, efx_log_msg_t,
225					void *, size_t, void *, size_t);
226#endif /* EFSYS_OPT_MCDI_LOGGING */
227#if EFSYS_OPT_MCDI_PROXY_AUTH
228	void		(*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t);
229#endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
230} efx_mcdi_transport_t;
231
232extern	__checkReturn	efx_rc_t
233efx_mcdi_init(
234	__in		efx_nic_t *enp,
235	__in		const efx_mcdi_transport_t *mtp);
236
237extern	__checkReturn	efx_rc_t
238efx_mcdi_reboot(
239	__in		efx_nic_t *enp);
240
241			void
242efx_mcdi_new_epoch(
243	__in		efx_nic_t *enp);
244
245extern			void
246efx_mcdi_request_start(
247	__in		efx_nic_t *enp,
248	__in		efx_mcdi_req_t *emrp,
249	__in		boolean_t ev_cpl);
250
251extern	__checkReturn	boolean_t
252efx_mcdi_request_poll(
253	__in		efx_nic_t *enp);
254
255extern	__checkReturn	boolean_t
256efx_mcdi_request_abort(
257	__in		efx_nic_t *enp);
258
259extern			void
260efx_mcdi_fini(
261	__in		efx_nic_t *enp);
262
263#endif	/* EFSYS_OPT_MCDI */
264
265/* INTR */
266
267#define	EFX_NINTR_SIENA 1024
268
269typedef enum efx_intr_type_e {
270	EFX_INTR_INVALID = 0,
271	EFX_INTR_LINE,
272	EFX_INTR_MESSAGE,
273	EFX_INTR_NTYPES
274} efx_intr_type_t;
275
276#define	EFX_INTR_SIZE	(sizeof (efx_oword_t))
277
278extern	__checkReturn	efx_rc_t
279efx_intr_init(
280	__in		efx_nic_t *enp,
281	__in		efx_intr_type_t type,
282	__in		efsys_mem_t *esmp);
283
284extern			void
285efx_intr_enable(
286	__in		efx_nic_t *enp);
287
288extern			void
289efx_intr_disable(
290	__in		efx_nic_t *enp);
291
292extern			void
293efx_intr_disable_unlocked(
294	__in		efx_nic_t *enp);
295
296#define	EFX_INTR_NEVQS	32
297
298extern	__checkReturn	efx_rc_t
299efx_intr_trigger(
300	__in		efx_nic_t *enp,
301	__in		unsigned int level);
302
303extern			void
304efx_intr_status_line(
305	__in		efx_nic_t *enp,
306	__out		boolean_t *fatalp,
307	__out		uint32_t *maskp);
308
309extern			void
310efx_intr_status_message(
311	__in		efx_nic_t *enp,
312	__in		unsigned int message,
313	__out		boolean_t *fatalp);
314
315extern			void
316efx_intr_fatal(
317	__in		efx_nic_t *enp);
318
319extern			void
320efx_intr_fini(
321	__in		efx_nic_t *enp);
322
323/* MAC */
324
325#if EFSYS_OPT_MAC_STATS
326
327/* START MKCONFIG GENERATED EfxHeaderMacBlock e323546097fd7c65 */
328typedef enum efx_mac_stat_e {
329	EFX_MAC_RX_OCTETS,
330	EFX_MAC_RX_PKTS,
331	EFX_MAC_RX_UNICST_PKTS,
332	EFX_MAC_RX_MULTICST_PKTS,
333	EFX_MAC_RX_BRDCST_PKTS,
334	EFX_MAC_RX_PAUSE_PKTS,
335	EFX_MAC_RX_LE_64_PKTS,
336	EFX_MAC_RX_65_TO_127_PKTS,
337	EFX_MAC_RX_128_TO_255_PKTS,
338	EFX_MAC_RX_256_TO_511_PKTS,
339	EFX_MAC_RX_512_TO_1023_PKTS,
340	EFX_MAC_RX_1024_TO_15XX_PKTS,
341	EFX_MAC_RX_GE_15XX_PKTS,
342	EFX_MAC_RX_ERRORS,
343	EFX_MAC_RX_FCS_ERRORS,
344	EFX_MAC_RX_DROP_EVENTS,
345	EFX_MAC_RX_FALSE_CARRIER_ERRORS,
346	EFX_MAC_RX_SYMBOL_ERRORS,
347	EFX_MAC_RX_ALIGN_ERRORS,
348	EFX_MAC_RX_INTERNAL_ERRORS,
349	EFX_MAC_RX_JABBER_PKTS,
350	EFX_MAC_RX_LANE0_CHAR_ERR,
351	EFX_MAC_RX_LANE1_CHAR_ERR,
352	EFX_MAC_RX_LANE2_CHAR_ERR,
353	EFX_MAC_RX_LANE3_CHAR_ERR,
354	EFX_MAC_RX_LANE0_DISP_ERR,
355	EFX_MAC_RX_LANE1_DISP_ERR,
356	EFX_MAC_RX_LANE2_DISP_ERR,
357	EFX_MAC_RX_LANE3_DISP_ERR,
358	EFX_MAC_RX_MATCH_FAULT,
359	EFX_MAC_RX_NODESC_DROP_CNT,
360	EFX_MAC_TX_OCTETS,
361	EFX_MAC_TX_PKTS,
362	EFX_MAC_TX_UNICST_PKTS,
363	EFX_MAC_TX_MULTICST_PKTS,
364	EFX_MAC_TX_BRDCST_PKTS,
365	EFX_MAC_TX_PAUSE_PKTS,
366	EFX_MAC_TX_LE_64_PKTS,
367	EFX_MAC_TX_65_TO_127_PKTS,
368	EFX_MAC_TX_128_TO_255_PKTS,
369	EFX_MAC_TX_256_TO_511_PKTS,
370	EFX_MAC_TX_512_TO_1023_PKTS,
371	EFX_MAC_TX_1024_TO_15XX_PKTS,
372	EFX_MAC_TX_GE_15XX_PKTS,
373	EFX_MAC_TX_ERRORS,
374	EFX_MAC_TX_SGL_COL_PKTS,
375	EFX_MAC_TX_MULT_COL_PKTS,
376	EFX_MAC_TX_EX_COL_PKTS,
377	EFX_MAC_TX_LATE_COL_PKTS,
378	EFX_MAC_TX_DEF_PKTS,
379	EFX_MAC_TX_EX_DEF_PKTS,
380	EFX_MAC_PM_TRUNC_BB_OVERFLOW,
381	EFX_MAC_PM_DISCARD_BB_OVERFLOW,
382	EFX_MAC_PM_TRUNC_VFIFO_FULL,
383	EFX_MAC_PM_DISCARD_VFIFO_FULL,
384	EFX_MAC_PM_TRUNC_QBB,
385	EFX_MAC_PM_DISCARD_QBB,
386	EFX_MAC_PM_DISCARD_MAPPING,
387	EFX_MAC_RXDP_Q_DISABLED_PKTS,
388	EFX_MAC_RXDP_DI_DROPPED_PKTS,
389	EFX_MAC_RXDP_STREAMING_PKTS,
390	EFX_MAC_RXDP_HLB_FETCH,
391	EFX_MAC_RXDP_HLB_WAIT,
392	EFX_MAC_VADAPTER_RX_UNICAST_PACKETS,
393	EFX_MAC_VADAPTER_RX_UNICAST_BYTES,
394	EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS,
395	EFX_MAC_VADAPTER_RX_MULTICAST_BYTES,
396	EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS,
397	EFX_MAC_VADAPTER_RX_BROADCAST_BYTES,
398	EFX_MAC_VADAPTER_RX_BAD_PACKETS,
399	EFX_MAC_VADAPTER_RX_BAD_BYTES,
400	EFX_MAC_VADAPTER_RX_OVERFLOW,
401	EFX_MAC_VADAPTER_TX_UNICAST_PACKETS,
402	EFX_MAC_VADAPTER_TX_UNICAST_BYTES,
403	EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS,
404	EFX_MAC_VADAPTER_TX_MULTICAST_BYTES,
405	EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS,
406	EFX_MAC_VADAPTER_TX_BROADCAST_BYTES,
407	EFX_MAC_VADAPTER_TX_BAD_PACKETS,
408	EFX_MAC_VADAPTER_TX_BAD_BYTES,
409	EFX_MAC_VADAPTER_TX_OVERFLOW,
410	EFX_MAC_NSTATS
411} efx_mac_stat_t;
412
413/* END MKCONFIG GENERATED EfxHeaderMacBlock */
414
415#endif	/* EFSYS_OPT_MAC_STATS */
416
417typedef enum efx_link_mode_e {
418	EFX_LINK_UNKNOWN = 0,
419	EFX_LINK_DOWN,
420	EFX_LINK_10HDX,
421	EFX_LINK_10FDX,
422	EFX_LINK_100HDX,
423	EFX_LINK_100FDX,
424	EFX_LINK_1000HDX,
425	EFX_LINK_1000FDX,
426	EFX_LINK_10000FDX,
427	EFX_LINK_40000FDX,
428	EFX_LINK_NMODES
429} efx_link_mode_t;
430
431#define	EFX_MAC_ADDR_LEN 6
432
433#define	EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t *)_address)[0] & 0x01)
434
435#define	EFX_MAC_MULTICAST_LIST_MAX	256
436
437#define	EFX_MAC_SDU_MAX	9202
438
439#define	EFX_MAC_PDU_ADJUSTMENT					\
440	(/* EtherII */ 14					\
441	    + /* VLAN */ 4					\
442	    + /* CRC */ 4					\
443	    + /* bug16011 */ 16)				\
444
445#define	EFX_MAC_PDU(_sdu)					\
446	P2ROUNDUP((_sdu) + EFX_MAC_PDU_ADJUSTMENT, 8)
447
448/*
449 * Due to the P2ROUNDUP in EFX_MAC_PDU(), EFX_MAC_SDU_FROM_PDU() may give
450 * the SDU rounded up slightly.
451 */
452#define	EFX_MAC_SDU_FROM_PDU(_pdu)	((_pdu) - EFX_MAC_PDU_ADJUSTMENT)
453
454#define	EFX_MAC_PDU_MIN	60
455#define	EFX_MAC_PDU_MAX	EFX_MAC_PDU(EFX_MAC_SDU_MAX)
456
457extern	__checkReturn	efx_rc_t
458efx_mac_pdu_get(
459	__in		efx_nic_t *enp,
460	__out		size_t *pdu);
461
462extern	__checkReturn	efx_rc_t
463efx_mac_pdu_set(
464	__in		efx_nic_t *enp,
465	__in		size_t pdu);
466
467extern	__checkReturn	efx_rc_t
468efx_mac_addr_set(
469	__in		efx_nic_t *enp,
470	__in		uint8_t *addr);
471
472extern	__checkReturn			efx_rc_t
473efx_mac_filter_set(
474	__in				efx_nic_t *enp,
475	__in				boolean_t all_unicst,
476	__in				boolean_t mulcst,
477	__in				boolean_t all_mulcst,
478	__in				boolean_t brdcst);
479
480extern	__checkReturn	efx_rc_t
481efx_mac_multicast_list_set(
482	__in				efx_nic_t *enp,
483	__in_ecount(6*count)		uint8_t const *addrs,
484	__in				int count);
485
486extern	__checkReturn	efx_rc_t
487efx_mac_filter_default_rxq_set(
488	__in		efx_nic_t *enp,
489	__in		efx_rxq_t *erp,
490	__in		boolean_t using_rss);
491
492extern			void
493efx_mac_filter_default_rxq_clear(
494	__in		efx_nic_t *enp);
495
496extern	__checkReturn	efx_rc_t
497efx_mac_drain(
498	__in		efx_nic_t *enp,
499	__in		boolean_t enabled);
500
501extern	__checkReturn	efx_rc_t
502efx_mac_up(
503	__in		efx_nic_t *enp,
504	__out		boolean_t *mac_upp);
505
506#define	EFX_FCNTL_RESPOND	0x00000001
507#define	EFX_FCNTL_GENERATE	0x00000002
508
509extern	__checkReturn	efx_rc_t
510efx_mac_fcntl_set(
511	__in		efx_nic_t *enp,
512	__in		unsigned int fcntl,
513	__in		boolean_t autoneg);
514
515extern			void
516efx_mac_fcntl_get(
517	__in		efx_nic_t *enp,
518	__out		unsigned int *fcntl_wantedp,
519	__out		unsigned int *fcntl_linkp);
520
521
522#if EFSYS_OPT_MAC_STATS
523
524#if EFSYS_OPT_NAMES
525
526extern	__checkReturn			const char *
527efx_mac_stat_name(
528	__in				efx_nic_t *enp,
529	__in				unsigned int id);
530
531#endif	/* EFSYS_OPT_NAMES */
532
533#define	EFX_MAC_STATS_MASK_BITS_PER_PAGE	(8 * sizeof (uint32_t))
534
535#define	EFX_MAC_STATS_MASK_NPAGES	\
536	(P2ROUNDUP(EFX_MAC_NSTATS, EFX_MAC_STATS_MASK_BITS_PER_PAGE) / \
537	    EFX_MAC_STATS_MASK_BITS_PER_PAGE)
538
539/*
540 * Get mask of MAC statistics supported by the hardware.
541 *
542 * If mask_size is insufficient to return the mask, EINVAL error is
543 * returned. EFX_MAC_STATS_MASK_NPAGES multiplied by size of the page
544 * (which is sizeof (uint32_t)) is sufficient.
545 */
546extern	__checkReturn			efx_rc_t
547efx_mac_stats_get_mask(
548	__in				efx_nic_t *enp,
549	__out_bcount(mask_size)		uint32_t *maskp,
550	__in				size_t mask_size);
551
552#define	EFX_MAC_STAT_SUPPORTED(_mask, _stat)	\
553	((_mask)[(_stat) / EFX_MAC_STATS_MASK_BITS_PER_PAGE] &	\
554	 (1ULL << ((_stat) & (EFX_MAC_STATS_MASK_BITS_PER_PAGE - 1))))
555
556#define	EFX_MAC_STATS_SIZE 0x400
557
558/*
559 * Upload mac statistics supported by the hardware into the given buffer.
560 *
561 * The reference buffer must be at least %EFX_MAC_STATS_SIZE bytes,
562 * and page aligned.
563 *
564 * The hardware will only DMA statistics that it understands (of course).
565 * Drivers should not make any assumptions about which statistics are
566 * supported, especially when the statistics are generated by firmware.
567 *
568 * Thus, drivers should zero this buffer before use, so that not-understood
569 * statistics read back as zero.
570 */
571extern	__checkReturn			efx_rc_t
572efx_mac_stats_upload(
573	__in				efx_nic_t *enp,
574	__in				efsys_mem_t *esmp);
575
576extern	__checkReturn			efx_rc_t
577efx_mac_stats_periodic(
578	__in				efx_nic_t *enp,
579	__in				efsys_mem_t *esmp,
580	__in				uint16_t period_ms,
581	__in				boolean_t events);
582
583extern	__checkReturn			efx_rc_t
584efx_mac_stats_update(
585	__in				efx_nic_t *enp,
586	__in				efsys_mem_t *esmp,
587	__inout_ecount(EFX_MAC_NSTATS)	efsys_stat_t *stat,
588	__inout_opt			uint32_t *generationp);
589
590#endif	/* EFSYS_OPT_MAC_STATS */
591
592/* MON */
593
594typedef enum efx_mon_type_e {
595	EFX_MON_INVALID = 0,
596	EFX_MON_SFC90X0,
597	EFX_MON_SFC91X0,
598	EFX_MON_SFC92X0,
599	EFX_MON_NTYPES
600} efx_mon_type_t;
601
602#if EFSYS_OPT_NAMES
603
604extern		const char *
605efx_mon_name(
606	__in	efx_nic_t *enp);
607
608#endif	/* EFSYS_OPT_NAMES */
609
610extern	__checkReturn	efx_rc_t
611efx_mon_init(
612	__in		efx_nic_t *enp);
613
614#if EFSYS_OPT_MON_STATS
615
616#define	EFX_MON_STATS_PAGE_SIZE 0x100
617#define	EFX_MON_MASK_ELEMENT_SIZE 32
618
619/* START MKCONFIG GENERATED MonitorHeaderStatsBlock 5d4ee5185e419abe */
620typedef enum efx_mon_stat_e {
621	EFX_MON_STAT_2_5V,
622	EFX_MON_STAT_VCCP1,
623	EFX_MON_STAT_VCC,
624	EFX_MON_STAT_5V,
625	EFX_MON_STAT_12V,
626	EFX_MON_STAT_VCCP2,
627	EFX_MON_STAT_EXT_TEMP,
628	EFX_MON_STAT_INT_TEMP,
629	EFX_MON_STAT_AIN1,
630	EFX_MON_STAT_AIN2,
631	EFX_MON_STAT_INT_COOLING,
632	EFX_MON_STAT_EXT_COOLING,
633	EFX_MON_STAT_1V,
634	EFX_MON_STAT_1_2V,
635	EFX_MON_STAT_1_8V,
636	EFX_MON_STAT_3_3V,
637	EFX_MON_STAT_1_2VA,
638	EFX_MON_STAT_VREF,
639	EFX_MON_STAT_VAOE,
640	EFX_MON_STAT_AOE_TEMP,
641	EFX_MON_STAT_PSU_AOE_TEMP,
642	EFX_MON_STAT_PSU_TEMP,
643	EFX_MON_STAT_FAN0,
644	EFX_MON_STAT_FAN1,
645	EFX_MON_STAT_FAN2,
646	EFX_MON_STAT_FAN3,
647	EFX_MON_STAT_FAN4,
648	EFX_MON_STAT_VAOE_IN,
649	EFX_MON_STAT_IAOE,
650	EFX_MON_STAT_IAOE_IN,
651	EFX_MON_STAT_NIC_POWER,
652	EFX_MON_STAT_0_9V,
653	EFX_MON_STAT_I0_9V,
654	EFX_MON_STAT_I1_2V,
655	EFX_MON_STAT_0_9V_ADC,
656	EFX_MON_STAT_INT_TEMP2,
657	EFX_MON_STAT_VREG_TEMP,
658	EFX_MON_STAT_VREG_0_9V_TEMP,
659	EFX_MON_STAT_VREG_1_2V_TEMP,
660	EFX_MON_STAT_INT_VPTAT,
661	EFX_MON_STAT_INT_ADC_TEMP,
662	EFX_MON_STAT_EXT_VPTAT,
663	EFX_MON_STAT_EXT_ADC_TEMP,
664	EFX_MON_STAT_AMBIENT_TEMP,
665	EFX_MON_STAT_AIRFLOW,
666	EFX_MON_STAT_VDD08D_VSS08D_CSR,
667	EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC,
668	EFX_MON_STAT_HOTPOINT_TEMP,
669	EFX_MON_STAT_PHY_POWER_SWITCH_PORT0,
670	EFX_MON_STAT_PHY_POWER_SWITCH_PORT1,
671	EFX_MON_STAT_MUM_VCC,
672	EFX_MON_STAT_0V9_A,
673	EFX_MON_STAT_I0V9_A,
674	EFX_MON_STAT_0V9_A_TEMP,
675	EFX_MON_STAT_0V9_B,
676	EFX_MON_STAT_I0V9_B,
677	EFX_MON_STAT_0V9_B_TEMP,
678	EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY,
679	EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXT_ADC,
680	EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY,
681	EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXT_ADC,
682	EFX_MON_STAT_CONTROLLER_MASTER_VPTAT,
683	EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP,
684	EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXT_ADC,
685	EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXT_ADC,
686	EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT,
687	EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP,
688	EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXT_ADC,
689	EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXT_ADC,
690	EFX_MON_STAT_SODIMM_VOUT,
691	EFX_MON_STAT_SODIMM_0_TEMP,
692	EFX_MON_STAT_SODIMM_1_TEMP,
693	EFX_MON_STAT_PHY0_VCC,
694	EFX_MON_STAT_PHY1_VCC,
695	EFX_MON_STAT_CONTROLLER_TDIODE_TEMP,
696	EFX_MON_STAT_BOARD_FRONT_TEMP,
697	EFX_MON_STAT_BOARD_BACK_TEMP,
698	EFX_MON_NSTATS
699} efx_mon_stat_t;
700
701/* END MKCONFIG GENERATED MonitorHeaderStatsBlock */
702
703typedef enum efx_mon_stat_state_e {
704	EFX_MON_STAT_STATE_OK = 0,
705	EFX_MON_STAT_STATE_WARNING = 1,
706	EFX_MON_STAT_STATE_FATAL = 2,
707	EFX_MON_STAT_STATE_BROKEN = 3,
708	EFX_MON_STAT_STATE_NO_READING = 4,
709} efx_mon_stat_state_t;
710
711typedef struct efx_mon_stat_value_s {
712	uint16_t	emsv_value;
713	uint16_t	emsv_state;
714} efx_mon_stat_value_t;
715
716#if EFSYS_OPT_NAMES
717
718extern					const char *
719efx_mon_stat_name(
720	__in				efx_nic_t *enp,
721	__in				efx_mon_stat_t id);
722
723#endif	/* EFSYS_OPT_NAMES */
724
725extern	__checkReturn			efx_rc_t
726efx_mon_stats_update(
727	__in				efx_nic_t *enp,
728	__in				efsys_mem_t *esmp,
729	__inout_ecount(EFX_MON_NSTATS)	efx_mon_stat_value_t *values);
730
731#endif	/* EFSYS_OPT_MON_STATS */
732
733extern		void
734efx_mon_fini(
735	__in	efx_nic_t *enp);
736
737/* PHY */
738
739extern	__checkReturn	efx_rc_t
740efx_phy_verify(
741	__in		efx_nic_t *enp);
742
743#if EFSYS_OPT_PHY_LED_CONTROL
744
745typedef enum efx_phy_led_mode_e {
746	EFX_PHY_LED_DEFAULT = 0,
747	EFX_PHY_LED_OFF,
748	EFX_PHY_LED_ON,
749	EFX_PHY_LED_FLASH,
750	EFX_PHY_LED_NMODES
751} efx_phy_led_mode_t;
752
753extern	__checkReturn	efx_rc_t
754efx_phy_led_set(
755	__in	efx_nic_t *enp,
756	__in	efx_phy_led_mode_t mode);
757
758#endif	/* EFSYS_OPT_PHY_LED_CONTROL */
759
760extern	__checkReturn	efx_rc_t
761efx_port_init(
762	__in		efx_nic_t *enp);
763
764#if EFSYS_OPT_LOOPBACK
765
766typedef enum efx_loopback_type_e {
767	EFX_LOOPBACK_OFF = 0,
768	EFX_LOOPBACK_DATA = 1,
769	EFX_LOOPBACK_GMAC = 2,
770	EFX_LOOPBACK_XGMII = 3,
771	EFX_LOOPBACK_XGXS = 4,
772	EFX_LOOPBACK_XAUI = 5,
773	EFX_LOOPBACK_GMII = 6,
774	EFX_LOOPBACK_SGMII = 7,
775	EFX_LOOPBACK_XGBR = 8,
776	EFX_LOOPBACK_XFI = 9,
777	EFX_LOOPBACK_XAUI_FAR = 10,
778	EFX_LOOPBACK_GMII_FAR = 11,
779	EFX_LOOPBACK_SGMII_FAR = 12,
780	EFX_LOOPBACK_XFI_FAR = 13,
781	EFX_LOOPBACK_GPHY = 14,
782	EFX_LOOPBACK_PHY_XS = 15,
783	EFX_LOOPBACK_PCS = 16,
784	EFX_LOOPBACK_PMA_PMD = 17,
785	EFX_LOOPBACK_XPORT = 18,
786	EFX_LOOPBACK_XGMII_WS = 19,
787	EFX_LOOPBACK_XAUI_WS = 20,
788	EFX_LOOPBACK_XAUI_WS_FAR = 21,
789	EFX_LOOPBACK_XAUI_WS_NEAR = 22,
790	EFX_LOOPBACK_GMII_WS = 23,
791	EFX_LOOPBACK_XFI_WS = 24,
792	EFX_LOOPBACK_XFI_WS_FAR = 25,
793	EFX_LOOPBACK_PHYXS_WS = 26,
794	EFX_LOOPBACK_PMA_INT = 27,
795	EFX_LOOPBACK_SD_NEAR = 28,
796	EFX_LOOPBACK_SD_FAR = 29,
797	EFX_LOOPBACK_PMA_INT_WS = 30,
798	EFX_LOOPBACK_SD_FEP2_WS = 31,
799	EFX_LOOPBACK_SD_FEP1_5_WS = 32,
800	EFX_LOOPBACK_SD_FEP_WS = 33,
801	EFX_LOOPBACK_SD_FES_WS = 34,
802	EFX_LOOPBACK_NTYPES
803} efx_loopback_type_t;
804
805typedef enum efx_loopback_kind_e {
806	EFX_LOOPBACK_KIND_OFF = 0,
807	EFX_LOOPBACK_KIND_ALL,
808	EFX_LOOPBACK_KIND_MAC,
809	EFX_LOOPBACK_KIND_PHY,
810	EFX_LOOPBACK_NKINDS
811} efx_loopback_kind_t;
812
813extern			void
814efx_loopback_mask(
815	__in	efx_loopback_kind_t loopback_kind,
816	__out	efx_qword_t *maskp);
817
818extern	__checkReturn	efx_rc_t
819efx_port_loopback_set(
820	__in	efx_nic_t *enp,
821	__in	efx_link_mode_t link_mode,
822	__in	efx_loopback_type_t type);
823
824#if EFSYS_OPT_NAMES
825
826extern	__checkReturn	const char *
827efx_loopback_type_name(
828	__in		efx_nic_t *enp,
829	__in		efx_loopback_type_t type);
830
831#endif	/* EFSYS_OPT_NAMES */
832
833#endif	/* EFSYS_OPT_LOOPBACK */
834
835extern	__checkReturn	efx_rc_t
836efx_port_poll(
837	__in		efx_nic_t *enp,
838	__out_opt	efx_link_mode_t	*link_modep);
839
840extern		void
841efx_port_fini(
842	__in	efx_nic_t *enp);
843
844typedef enum efx_phy_cap_type_e {
845	EFX_PHY_CAP_INVALID = 0,
846	EFX_PHY_CAP_10HDX,
847	EFX_PHY_CAP_10FDX,
848	EFX_PHY_CAP_100HDX,
849	EFX_PHY_CAP_100FDX,
850	EFX_PHY_CAP_1000HDX,
851	EFX_PHY_CAP_1000FDX,
852	EFX_PHY_CAP_10000FDX,
853	EFX_PHY_CAP_PAUSE,
854	EFX_PHY_CAP_ASYM,
855	EFX_PHY_CAP_AN,
856	EFX_PHY_CAP_40000FDX,
857	EFX_PHY_CAP_NTYPES
858} efx_phy_cap_type_t;
859
860
861#define	EFX_PHY_CAP_CURRENT	0x00000000
862#define	EFX_PHY_CAP_DEFAULT	0x00000001
863#define	EFX_PHY_CAP_PERM	0x00000002
864
865extern		void
866efx_phy_adv_cap_get(
867	__in		efx_nic_t *enp,
868	__in		uint32_t flag,
869	__out		uint32_t *maskp);
870
871extern	__checkReturn	efx_rc_t
872efx_phy_adv_cap_set(
873	__in		efx_nic_t *enp,
874	__in		uint32_t mask);
875
876extern			void
877efx_phy_lp_cap_get(
878	__in		efx_nic_t *enp,
879	__out		uint32_t *maskp);
880
881extern	__checkReturn	efx_rc_t
882efx_phy_oui_get(
883	__in		efx_nic_t *enp,
884	__out		uint32_t *ouip);
885
886typedef enum efx_phy_media_type_e {
887	EFX_PHY_MEDIA_INVALID = 0,
888	EFX_PHY_MEDIA_XAUI,
889	EFX_PHY_MEDIA_CX4,
890	EFX_PHY_MEDIA_KX4,
891	EFX_PHY_MEDIA_XFP,
892	EFX_PHY_MEDIA_SFP_PLUS,
893	EFX_PHY_MEDIA_BASE_T,
894	EFX_PHY_MEDIA_QSFP_PLUS,
895	EFX_PHY_MEDIA_NTYPES
896} efx_phy_media_type_t;
897
898/* Get the type of medium currently used.  If the board has ports for
899 * modules, a module is present, and we recognise the media type of
900 * the module, then this will be the media type of the module.
901 * Otherwise it will be the media type of the port.
902 */
903extern			void
904efx_phy_media_type_get(
905	__in		efx_nic_t *enp,
906	__out		efx_phy_media_type_t *typep);
907
908extern					efx_rc_t
909efx_phy_module_get_info(
910	__in				efx_nic_t *enp,
911	__in				uint8_t dev_addr,
912	__in				uint8_t offset,
913	__in				uint8_t len,
914	__out_bcount(len)		uint8_t *data);
915
916#if EFSYS_OPT_PHY_STATS
917
918/* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */
919typedef enum efx_phy_stat_e {
920	EFX_PHY_STAT_OUI,
921	EFX_PHY_STAT_PMA_PMD_LINK_UP,
922	EFX_PHY_STAT_PMA_PMD_RX_FAULT,
923	EFX_PHY_STAT_PMA_PMD_TX_FAULT,
924	EFX_PHY_STAT_PMA_PMD_REV_A,
925	EFX_PHY_STAT_PMA_PMD_REV_B,
926	EFX_PHY_STAT_PMA_PMD_REV_C,
927	EFX_PHY_STAT_PMA_PMD_REV_D,
928	EFX_PHY_STAT_PCS_LINK_UP,
929	EFX_PHY_STAT_PCS_RX_FAULT,
930	EFX_PHY_STAT_PCS_TX_FAULT,
931	EFX_PHY_STAT_PCS_BER,
932	EFX_PHY_STAT_PCS_BLOCK_ERRORS,
933	EFX_PHY_STAT_PHY_XS_LINK_UP,
934	EFX_PHY_STAT_PHY_XS_RX_FAULT,
935	EFX_PHY_STAT_PHY_XS_TX_FAULT,
936	EFX_PHY_STAT_PHY_XS_ALIGN,
937	EFX_PHY_STAT_PHY_XS_SYNC_A,
938	EFX_PHY_STAT_PHY_XS_SYNC_B,
939	EFX_PHY_STAT_PHY_XS_SYNC_C,
940	EFX_PHY_STAT_PHY_XS_SYNC_D,
941	EFX_PHY_STAT_AN_LINK_UP,
942	EFX_PHY_STAT_AN_MASTER,
943	EFX_PHY_STAT_AN_LOCAL_RX_OK,
944	EFX_PHY_STAT_AN_REMOTE_RX_OK,
945	EFX_PHY_STAT_CL22EXT_LINK_UP,
946	EFX_PHY_STAT_SNR_A,
947	EFX_PHY_STAT_SNR_B,
948	EFX_PHY_STAT_SNR_C,
949	EFX_PHY_STAT_SNR_D,
950	EFX_PHY_STAT_PMA_PMD_SIGNAL_A,
951	EFX_PHY_STAT_PMA_PMD_SIGNAL_B,
952	EFX_PHY_STAT_PMA_PMD_SIGNAL_C,
953	EFX_PHY_STAT_PMA_PMD_SIGNAL_D,
954	EFX_PHY_STAT_AN_COMPLETE,
955	EFX_PHY_STAT_PMA_PMD_REV_MAJOR,
956	EFX_PHY_STAT_PMA_PMD_REV_MINOR,
957	EFX_PHY_STAT_PMA_PMD_REV_MICRO,
958	EFX_PHY_STAT_PCS_FW_VERSION_0,
959	EFX_PHY_STAT_PCS_FW_VERSION_1,
960	EFX_PHY_STAT_PCS_FW_VERSION_2,
961	EFX_PHY_STAT_PCS_FW_VERSION_3,
962	EFX_PHY_STAT_PCS_FW_BUILD_YY,
963	EFX_PHY_STAT_PCS_FW_BUILD_MM,
964	EFX_PHY_STAT_PCS_FW_BUILD_DD,
965	EFX_PHY_STAT_PCS_OP_MODE,
966	EFX_PHY_NSTATS
967} efx_phy_stat_t;
968
969/* END MKCONFIG GENERATED PhyHeaderStatsBlock */
970
971#if EFSYS_OPT_NAMES
972
973extern					const char *
974efx_phy_stat_name(
975	__in				efx_nic_t *enp,
976	__in				efx_phy_stat_t stat);
977
978#endif	/* EFSYS_OPT_NAMES */
979
980#define	EFX_PHY_STATS_SIZE 0x100
981
982extern	__checkReturn			efx_rc_t
983efx_phy_stats_update(
984	__in				efx_nic_t *enp,
985	__in				efsys_mem_t *esmp,
986	__inout_ecount(EFX_PHY_NSTATS)	uint32_t *stat);
987
988#endif	/* EFSYS_OPT_PHY_STATS */
989
990
991#if EFSYS_OPT_BIST
992
993typedef enum efx_bist_type_e {
994	EFX_BIST_TYPE_UNKNOWN,
995	EFX_BIST_TYPE_PHY_NORMAL,
996	EFX_BIST_TYPE_PHY_CABLE_SHORT,
997	EFX_BIST_TYPE_PHY_CABLE_LONG,
998	EFX_BIST_TYPE_MC_MEM,	/* Test the MC DMEM and IMEM */
999	EFX_BIST_TYPE_SAT_MEM,	/* Test the DMEM and IMEM of satellite cpus*/
1000	EFX_BIST_TYPE_REG,	/* Test the register memories */
1001	EFX_BIST_TYPE_NTYPES,
1002} efx_bist_type_t;
1003
1004typedef enum efx_bist_result_e {
1005	EFX_BIST_RESULT_UNKNOWN,
1006	EFX_BIST_RESULT_RUNNING,
1007	EFX_BIST_RESULT_PASSED,
1008	EFX_BIST_RESULT_FAILED,
1009} efx_bist_result_t;
1010
1011typedef enum efx_phy_cable_status_e {
1012	EFX_PHY_CABLE_STATUS_OK,
1013	EFX_PHY_CABLE_STATUS_INVALID,
1014	EFX_PHY_CABLE_STATUS_OPEN,
1015	EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT,
1016	EFX_PHY_CABLE_STATUS_INTERPAIRSHORT,
1017	EFX_PHY_CABLE_STATUS_BUSY,
1018} efx_phy_cable_status_t;
1019
1020typedef enum efx_bist_value_e {
1021	EFX_BIST_PHY_CABLE_LENGTH_A,
1022	EFX_BIST_PHY_CABLE_LENGTH_B,
1023	EFX_BIST_PHY_CABLE_LENGTH_C,
1024	EFX_BIST_PHY_CABLE_LENGTH_D,
1025	EFX_BIST_PHY_CABLE_STATUS_A,
1026	EFX_BIST_PHY_CABLE_STATUS_B,
1027	EFX_BIST_PHY_CABLE_STATUS_C,
1028	EFX_BIST_PHY_CABLE_STATUS_D,
1029	EFX_BIST_FAULT_CODE,
1030	/* Memory BIST specific values. These match to the MC_CMD_BIST_POLL
1031	 * response. */
1032	EFX_BIST_MEM_TEST,
1033	EFX_BIST_MEM_ADDR,
1034	EFX_BIST_MEM_BUS,
1035	EFX_BIST_MEM_EXPECT,
1036	EFX_BIST_MEM_ACTUAL,
1037	EFX_BIST_MEM_ECC,
1038	EFX_BIST_MEM_ECC_PARITY,
1039	EFX_BIST_MEM_ECC_FATAL,
1040	EFX_BIST_NVALUES,
1041} efx_bist_value_t;
1042
1043extern	__checkReturn		efx_rc_t
1044efx_bist_enable_offline(
1045	__in			efx_nic_t *enp);
1046
1047extern	__checkReturn		efx_rc_t
1048efx_bist_start(
1049	__in			efx_nic_t *enp,
1050	__in			efx_bist_type_t type);
1051
1052extern	__checkReturn		efx_rc_t
1053efx_bist_poll(
1054	__in			efx_nic_t *enp,
1055	__in			efx_bist_type_t type,
1056	__out			efx_bist_result_t *resultp,
1057	__out_opt		uint32_t *value_maskp,
1058	__out_ecount_opt(count)	unsigned long *valuesp,
1059	__in			size_t count);
1060
1061extern				void
1062efx_bist_stop(
1063	__in			efx_nic_t *enp,
1064	__in			efx_bist_type_t type);
1065
1066#endif	/* EFSYS_OPT_BIST */
1067
1068#define	EFX_FEATURE_IPV6		0x00000001
1069#define	EFX_FEATURE_LFSR_HASH_INSERT	0x00000002
1070#define	EFX_FEATURE_LINK_EVENTS		0x00000004
1071#define	EFX_FEATURE_PERIODIC_MAC_STATS	0x00000008
1072#define	EFX_FEATURE_WOL			0x00000010
1073#define	EFX_FEATURE_MCDI		0x00000020
1074#define	EFX_FEATURE_LOOKAHEAD_SPLIT	0x00000040
1075#define	EFX_FEATURE_MAC_HEADER_FILTERS	0x00000080
1076#define	EFX_FEATURE_TURBO		0x00000100
1077#define	EFX_FEATURE_MCDI_DMA		0x00000200
1078#define	EFX_FEATURE_TX_SRC_FILTERS	0x00000400
1079#define	EFX_FEATURE_PIO_BUFFERS		0x00000800
1080#define	EFX_FEATURE_FW_ASSISTED_TSO	0x00001000
1081#define	EFX_FEATURE_FW_ASSISTED_TSO_V2	0x00002000
1082
1083typedef struct efx_nic_cfg_s {
1084	uint32_t		enc_board_type;
1085	uint32_t		enc_phy_type;
1086#if EFSYS_OPT_NAMES
1087	char			enc_phy_name[21];
1088#endif
1089	char			enc_phy_revision[21];
1090	efx_mon_type_t		enc_mon_type;
1091#if EFSYS_OPT_MON_STATS
1092	uint32_t		enc_mon_stat_dma_buf_size;
1093	uint32_t		enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32];
1094#endif
1095	unsigned int		enc_features;
1096	uint8_t			enc_mac_addr[6];
1097	uint8_t			enc_port;	/* PHY port number */
1098	uint32_t		enc_intr_vec_base;
1099	uint32_t		enc_intr_limit;
1100	uint32_t		enc_evq_limit;
1101	uint32_t		enc_txq_limit;
1102	uint32_t		enc_rxq_limit;
1103	uint32_t		enc_buftbl_limit;
1104	uint32_t		enc_piobuf_limit;
1105	uint32_t		enc_piobuf_size;
1106	uint32_t		enc_piobuf_min_alloc_size;
1107	uint32_t		enc_evq_timer_quantum_ns;
1108	uint32_t		enc_evq_timer_max_us;
1109	uint32_t		enc_clk_mult;
1110	uint32_t		enc_rx_prefix_size;
1111	uint32_t		enc_rx_buf_align_start;
1112	uint32_t		enc_rx_buf_align_end;
1113#if EFSYS_OPT_LOOPBACK
1114	efx_qword_t		enc_loopback_types[EFX_LINK_NMODES];
1115#endif	/* EFSYS_OPT_LOOPBACK */
1116#if EFSYS_OPT_PHY_FLAGS
1117	uint32_t		enc_phy_flags_mask;
1118#endif	/* EFSYS_OPT_PHY_FLAGS */
1119#if EFSYS_OPT_PHY_LED_CONTROL
1120	uint32_t		enc_led_mask;
1121#endif	/* EFSYS_OPT_PHY_LED_CONTROL */
1122#if EFSYS_OPT_PHY_STATS
1123	uint64_t		enc_phy_stat_mask;
1124#endif	/* EFSYS_OPT_PHY_STATS */
1125#if EFSYS_OPT_MCDI
1126	uint8_t			enc_mcdi_mdio_channel;
1127#if EFSYS_OPT_PHY_STATS
1128	uint32_t		enc_mcdi_phy_stat_mask;
1129#endif	/* EFSYS_OPT_PHY_STATS */
1130#if EFSYS_OPT_MON_STATS
1131	uint32_t		*enc_mcdi_sensor_maskp;
1132	uint32_t		enc_mcdi_sensor_mask_size;
1133#endif	/* EFSYS_OPT_MON_STATS */
1134#endif	/* EFSYS_OPT_MCDI */
1135#if EFSYS_OPT_BIST
1136	uint32_t		enc_bist_mask;
1137#endif	/* EFSYS_OPT_BIST */
1138#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
1139	uint32_t		enc_pf;
1140	uint32_t		enc_vf;
1141	uint32_t		enc_privilege_mask;
1142#endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
1143	boolean_t		enc_bug26807_workaround;
1144	boolean_t		enc_bug35388_workaround;
1145	boolean_t		enc_bug41750_workaround;
1146	boolean_t		enc_bug61265_workaround;
1147	boolean_t		enc_rx_batching_enabled;
1148	/* Maximum number of descriptors completed in an rx event. */
1149	uint32_t		enc_rx_batch_max;
1150	/* Number of rx descriptors the hardware requires for a push. */
1151	uint32_t		enc_rx_push_align;
1152	/*
1153	 * Maximum number of bytes into the packet the TCP header can start for
1154	 * the hardware to apply TSO packet edits.
1155	 */
1156	uint32_t		enc_tx_tso_tcp_header_offset_limit;
1157	boolean_t		enc_fw_assisted_tso_enabled;
1158	boolean_t		enc_fw_assisted_tso_v2_enabled;
1159	/* Number of TSO contexts on the NIC (FATSOv2) */
1160	uint32_t		enc_fw_assisted_tso_v2_n_contexts;
1161	boolean_t		enc_hw_tx_insert_vlan_enabled;
1162	/* Number of PFs on the NIC */
1163	uint32_t		enc_hw_pf_count;
1164	/* Datapath firmware vadapter/vport/vswitch support */
1165	boolean_t		enc_datapath_cap_evb;
1166	boolean_t		enc_rx_disable_scatter_supported;
1167	boolean_t		enc_allow_set_mac_with_installed_filters;
1168	boolean_t		enc_enhanced_set_mac_supported;
1169	boolean_t		enc_init_evq_v2_supported;
1170	boolean_t		enc_pm_and_rxdp_counters;
1171	boolean_t		enc_mac_stats_40g_tx_size_bins;
1172	/* External port identifier */
1173	uint8_t			enc_external_port;
1174	uint32_t		enc_mcdi_max_payload_length;
1175	/* VPD may be per-PF or global */
1176	boolean_t		enc_vpd_is_global;
1177	/* Minimum unidirectional bandwidth in Mb/s to max out all ports */
1178	uint32_t		enc_required_pcie_bandwidth_mbps;
1179	uint32_t		enc_max_pcie_link_gen;
1180} efx_nic_cfg_t;
1181
1182#define	EFX_PCI_FUNCTION_IS_PF(_encp)	((_encp)->enc_vf == 0xffff)
1183#define	EFX_PCI_FUNCTION_IS_VF(_encp)	((_encp)->enc_vf != 0xffff)
1184
1185#define	EFX_PCI_FUNCTION(_encp)	\
1186	(EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf)
1187
1188#define	EFX_PCI_VF_PARENT(_encp)	((_encp)->enc_pf)
1189
1190extern			const efx_nic_cfg_t *
1191efx_nic_cfg_get(
1192	__in		efx_nic_t *enp);
1193
1194/* Driver resource limits (minimum required/maximum usable). */
1195typedef struct efx_drv_limits_s {
1196	uint32_t	edl_min_evq_count;
1197	uint32_t	edl_max_evq_count;
1198
1199	uint32_t	edl_min_rxq_count;
1200	uint32_t	edl_max_rxq_count;
1201
1202	uint32_t	edl_min_txq_count;
1203	uint32_t	edl_max_txq_count;
1204
1205	/* PIO blocks (sub-allocated from piobuf) */
1206	uint32_t	edl_min_pio_alloc_size;
1207	uint32_t	edl_max_pio_alloc_count;
1208} efx_drv_limits_t;
1209
1210extern	__checkReturn	efx_rc_t
1211efx_nic_set_drv_limits(
1212	__inout		efx_nic_t *enp,
1213	__in		efx_drv_limits_t *edlp);
1214
1215typedef enum efx_nic_region_e {
1216	EFX_REGION_VI,			/* Memory BAR UC mapping */
1217	EFX_REGION_PIO_WRITE_VI,	/* Memory BAR WC mapping */
1218} efx_nic_region_t;
1219
1220extern	__checkReturn	efx_rc_t
1221efx_nic_get_bar_region(
1222	__in		efx_nic_t *enp,
1223	__in		efx_nic_region_t region,
1224	__out		uint32_t *offsetp,
1225	__out		size_t *sizep);
1226
1227extern	__checkReturn	efx_rc_t
1228efx_nic_get_vi_pool(
1229	__in		efx_nic_t *enp,
1230	__out		uint32_t *evq_countp,
1231	__out		uint32_t *rxq_countp,
1232	__out		uint32_t *txq_countp);
1233
1234
1235#if EFSYS_OPT_VPD
1236
1237typedef enum efx_vpd_tag_e {
1238	EFX_VPD_ID = 0x02,
1239	EFX_VPD_END = 0x0f,
1240	EFX_VPD_RO = 0x10,
1241	EFX_VPD_RW = 0x11,
1242} efx_vpd_tag_t;
1243
1244typedef uint16_t efx_vpd_keyword_t;
1245
1246typedef struct efx_vpd_value_s {
1247	efx_vpd_tag_t		evv_tag;
1248	efx_vpd_keyword_t	evv_keyword;
1249	uint8_t			evv_length;
1250	uint8_t			evv_value[0x100];
1251} efx_vpd_value_t;
1252
1253
1254#define	EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8))
1255
1256extern	__checkReturn		efx_rc_t
1257efx_vpd_init(
1258	__in			efx_nic_t *enp);
1259
1260extern	__checkReturn		efx_rc_t
1261efx_vpd_size(
1262	__in			efx_nic_t *enp,
1263	__out			size_t *sizep);
1264
1265extern	__checkReturn		efx_rc_t
1266efx_vpd_read(
1267	__in			efx_nic_t *enp,
1268	__out_bcount(size)	caddr_t data,
1269	__in			size_t size);
1270
1271extern	__checkReturn		efx_rc_t
1272efx_vpd_verify(
1273	__in			efx_nic_t *enp,
1274	__in_bcount(size)	caddr_t data,
1275	__in			size_t size);
1276
1277extern	__checkReturn		efx_rc_t
1278efx_vpd_reinit(
1279	__in			efx_nic_t *enp,
1280	__in_bcount(size)	caddr_t data,
1281	__in			size_t size);
1282
1283extern	__checkReturn		efx_rc_t
1284efx_vpd_get(
1285	__in			efx_nic_t *enp,
1286	__in_bcount(size)	caddr_t data,
1287	__in			size_t size,
1288	__inout			efx_vpd_value_t *evvp);
1289
1290extern	__checkReturn		efx_rc_t
1291efx_vpd_set(
1292	__in			efx_nic_t *enp,
1293	__inout_bcount(size)	caddr_t data,
1294	__in			size_t size,
1295	__in			efx_vpd_value_t *evvp);
1296
1297extern	__checkReturn		efx_rc_t
1298efx_vpd_next(
1299	__in			efx_nic_t *enp,
1300	__inout_bcount(size)	caddr_t data,
1301	__in			size_t size,
1302	__out			efx_vpd_value_t *evvp,
1303	__inout			unsigned int *contp);
1304
1305extern	__checkReturn		efx_rc_t
1306efx_vpd_write(
1307	__in			efx_nic_t *enp,
1308	__in_bcount(size)	caddr_t data,
1309	__in			size_t size);
1310
1311extern				void
1312efx_vpd_fini(
1313	__in			efx_nic_t *enp);
1314
1315#endif	/* EFSYS_OPT_VPD */
1316
1317/* NVRAM */
1318
1319#if EFSYS_OPT_NVRAM
1320
1321typedef enum efx_nvram_type_e {
1322	EFX_NVRAM_INVALID = 0,
1323	EFX_NVRAM_BOOTROM,
1324	EFX_NVRAM_BOOTROM_CFG,
1325	EFX_NVRAM_MC_FIRMWARE,
1326	EFX_NVRAM_MC_GOLDEN,
1327	EFX_NVRAM_PHY,
1328	EFX_NVRAM_NULLPHY,
1329	EFX_NVRAM_FPGA,
1330	EFX_NVRAM_FCFW,
1331	EFX_NVRAM_CPLD,
1332	EFX_NVRAM_FPGA_BACKUP,
1333	EFX_NVRAM_DYNAMIC_CFG,
1334	EFX_NVRAM_LICENSE,
1335	EFX_NVRAM_UEFIROM,
1336	EFX_NVRAM_NTYPES,
1337} efx_nvram_type_t;
1338
1339extern	__checkReturn		efx_rc_t
1340efx_nvram_init(
1341	__in			efx_nic_t *enp);
1342
1343#if EFSYS_OPT_DIAG
1344
1345extern	__checkReturn		efx_rc_t
1346efx_nvram_test(
1347	__in			efx_nic_t *enp);
1348
1349#endif	/* EFSYS_OPT_DIAG */
1350
1351extern	__checkReturn		efx_rc_t
1352efx_nvram_size(
1353	__in			efx_nic_t *enp,
1354	__in			efx_nvram_type_t type,
1355	__out			size_t *sizep);
1356
1357extern	__checkReturn		efx_rc_t
1358efx_nvram_rw_start(
1359	__in			efx_nic_t *enp,
1360	__in			efx_nvram_type_t type,
1361	__out_opt		size_t *pref_chunkp);
1362
1363extern				void
1364efx_nvram_rw_finish(
1365	__in			efx_nic_t *enp,
1366	__in			efx_nvram_type_t type);
1367
1368extern	__checkReturn		efx_rc_t
1369efx_nvram_get_version(
1370	__in			efx_nic_t *enp,
1371	__in			efx_nvram_type_t type,
1372	__out			uint32_t *subtypep,
1373	__out_ecount(4)		uint16_t version[4]);
1374
1375extern	__checkReturn		efx_rc_t
1376efx_nvram_read_chunk(
1377	__in			efx_nic_t *enp,
1378	__in			efx_nvram_type_t type,
1379	__in			unsigned int offset,
1380	__out_bcount(size)	caddr_t data,
1381	__in			size_t size);
1382
1383extern	__checkReturn		efx_rc_t
1384efx_nvram_set_version(
1385	__in			efx_nic_t *enp,
1386	__in			efx_nvram_type_t type,
1387	__in_ecount(4)		uint16_t version[4]);
1388
1389extern	__checkReturn		efx_rc_t
1390efx_nvram_validate(
1391	__in			efx_nic_t *enp,
1392	__in			efx_nvram_type_t type,
1393	__in_bcount(partn_size)	caddr_t partn_data,
1394	__in			size_t partn_size);
1395
1396extern	 __checkReturn		efx_rc_t
1397efx_nvram_erase(
1398	__in			efx_nic_t *enp,
1399	__in			efx_nvram_type_t type);
1400
1401extern	__checkReturn		efx_rc_t
1402efx_nvram_write_chunk(
1403	__in			efx_nic_t *enp,
1404	__in			efx_nvram_type_t type,
1405	__in			unsigned int offset,
1406	__in_bcount(size)	caddr_t data,
1407	__in			size_t size);
1408
1409extern				void
1410efx_nvram_fini(
1411	__in			efx_nic_t *enp);
1412
1413#endif	/* EFSYS_OPT_NVRAM */
1414
1415#if EFSYS_OPT_BOOTCFG
1416
1417extern				efx_rc_t
1418efx_bootcfg_read(
1419	__in			efx_nic_t *enp,
1420	__out_bcount(size)	caddr_t data,
1421	__in			size_t size);
1422
1423extern				efx_rc_t
1424efx_bootcfg_write(
1425	__in			efx_nic_t *enp,
1426	__in_bcount(size)	caddr_t data,
1427	__in			size_t size);
1428
1429#endif	/* EFSYS_OPT_BOOTCFG */
1430
1431#if EFSYS_OPT_WOL
1432
1433typedef enum efx_wol_type_e {
1434	EFX_WOL_TYPE_INVALID,
1435	EFX_WOL_TYPE_MAGIC,
1436	EFX_WOL_TYPE_BITMAP,
1437	EFX_WOL_TYPE_LINK,
1438	EFX_WOL_NTYPES,
1439} efx_wol_type_t;
1440
1441typedef enum efx_lightsout_offload_type_e {
1442	EFX_LIGHTSOUT_OFFLOAD_TYPE_INVALID,
1443	EFX_LIGHTSOUT_OFFLOAD_TYPE_ARP,
1444	EFX_LIGHTSOUT_OFFLOAD_TYPE_NS,
1445} efx_lightsout_offload_type_t;
1446
1447#define	EFX_WOL_BITMAP_MASK_SIZE    (48)
1448#define	EFX_WOL_BITMAP_VALUE_SIZE   (128)
1449
1450typedef union efx_wol_param_u {
1451	struct {
1452		uint8_t mac_addr[6];
1453	} ewp_magic;
1454	struct {
1455		uint8_t mask[EFX_WOL_BITMAP_MASK_SIZE];   /* 1 bit per byte */
1456		uint8_t value[EFX_WOL_BITMAP_VALUE_SIZE]; /* value to match */
1457		uint8_t value_len;
1458	} ewp_bitmap;
1459} efx_wol_param_t;
1460
1461typedef union efx_lightsout_offload_param_u {
1462	struct {
1463		uint8_t mac_addr[6];
1464		uint32_t ip;
1465	} elop_arp;
1466	struct {
1467		uint8_t mac_addr[6];
1468		uint32_t solicited_node[4];
1469		uint32_t ip[4];
1470	} elop_ns;
1471} efx_lightsout_offload_param_t;
1472
1473extern	__checkReturn	efx_rc_t
1474efx_wol_init(
1475	__in		efx_nic_t *enp);
1476
1477extern	__checkReturn	efx_rc_t
1478efx_wol_filter_clear(
1479	__in		efx_nic_t *enp);
1480
1481extern	__checkReturn	efx_rc_t
1482efx_wol_filter_add(
1483	__in		efx_nic_t *enp,
1484	__in		efx_wol_type_t type,
1485	__in		efx_wol_param_t *paramp,
1486	__out		uint32_t *filter_idp);
1487
1488extern	__checkReturn	efx_rc_t
1489efx_wol_filter_remove(
1490	__in		efx_nic_t *enp,
1491	__in		uint32_t filter_id);
1492
1493extern	__checkReturn	efx_rc_t
1494efx_lightsout_offload_add(
1495	__in		efx_nic_t *enp,
1496	__in		efx_lightsout_offload_type_t type,
1497	__in		efx_lightsout_offload_param_t *paramp,
1498	__out		uint32_t *filter_idp);
1499
1500extern	__checkReturn	efx_rc_t
1501efx_lightsout_offload_remove(
1502	__in		efx_nic_t *enp,
1503	__in		efx_lightsout_offload_type_t type,
1504	__in		uint32_t filter_id);
1505
1506extern			void
1507efx_wol_fini(
1508	__in		efx_nic_t *enp);
1509
1510#endif	/* EFSYS_OPT_WOL */
1511
1512#if EFSYS_OPT_DIAG
1513
1514typedef enum efx_pattern_type_t {
1515	EFX_PATTERN_BYTE_INCREMENT = 0,
1516	EFX_PATTERN_ALL_THE_SAME,
1517	EFX_PATTERN_BIT_ALTERNATE,
1518	EFX_PATTERN_BYTE_ALTERNATE,
1519	EFX_PATTERN_BYTE_CHANGING,
1520	EFX_PATTERN_BIT_SWEEP,
1521	EFX_PATTERN_NTYPES
1522} efx_pattern_type_t;
1523
1524typedef			void
1525(*efx_sram_pattern_fn_t)(
1526	__in		size_t row,
1527	__in		boolean_t negate,
1528	__out		efx_qword_t *eqp);
1529
1530extern	__checkReturn	efx_rc_t
1531efx_sram_test(
1532	__in		efx_nic_t *enp,
1533	__in		efx_pattern_type_t type);
1534
1535#endif	/* EFSYS_OPT_DIAG */
1536
1537extern	__checkReturn	efx_rc_t
1538efx_sram_buf_tbl_set(
1539	__in		efx_nic_t *enp,
1540	__in		uint32_t id,
1541	__in		efsys_mem_t *esmp,
1542	__in		size_t n);
1543
1544extern		void
1545efx_sram_buf_tbl_clear(
1546	__in	efx_nic_t *enp,
1547	__in	uint32_t id,
1548	__in	size_t n);
1549
1550#define	EFX_BUF_TBL_SIZE	0x20000
1551
1552#define	EFX_BUF_SIZE		4096
1553
1554/* EV */
1555
1556typedef struct efx_evq_s	efx_evq_t;
1557
1558#if EFSYS_OPT_QSTATS
1559
1560/* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 6f3843f5fe7cc843 */
1561typedef enum efx_ev_qstat_e {
1562	EV_ALL,
1563	EV_RX,
1564	EV_RX_OK,
1565	EV_RX_FRM_TRUNC,
1566	EV_RX_TOBE_DISC,
1567	EV_RX_PAUSE_FRM_ERR,
1568	EV_RX_BUF_OWNER_ID_ERR,
1569	EV_RX_IPV4_HDR_CHKSUM_ERR,
1570	EV_RX_TCP_UDP_CHKSUM_ERR,
1571	EV_RX_ETH_CRC_ERR,
1572	EV_RX_IP_FRAG_ERR,
1573	EV_RX_MCAST_PKT,
1574	EV_RX_MCAST_HASH_MATCH,
1575	EV_RX_TCP_IPV4,
1576	EV_RX_TCP_IPV6,
1577	EV_RX_UDP_IPV4,
1578	EV_RX_UDP_IPV6,
1579	EV_RX_OTHER_IPV4,
1580	EV_RX_OTHER_IPV6,
1581	EV_RX_NON_IP,
1582	EV_RX_BATCH,
1583	EV_TX,
1584	EV_TX_WQ_FF_FULL,
1585	EV_TX_PKT_ERR,
1586	EV_TX_PKT_TOO_BIG,
1587	EV_TX_UNEXPECTED,
1588	EV_GLOBAL,
1589	EV_GLOBAL_MNT,
1590	EV_DRIVER,
1591	EV_DRIVER_SRM_UPD_DONE,
1592	EV_DRIVER_TX_DESCQ_FLS_DONE,
1593	EV_DRIVER_RX_DESCQ_FLS_DONE,
1594	EV_DRIVER_RX_DESCQ_FLS_FAILED,
1595	EV_DRIVER_RX_DSC_ERROR,
1596	EV_DRIVER_TX_DSC_ERROR,
1597	EV_DRV_GEN,
1598	EV_MCDI_RESPONSE,
1599	EV_NQSTATS
1600} efx_ev_qstat_t;
1601
1602/* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */
1603
1604#endif	/* EFSYS_OPT_QSTATS */
1605
1606extern	__checkReturn	efx_rc_t
1607efx_ev_init(
1608	__in		efx_nic_t *enp);
1609
1610extern		void
1611efx_ev_fini(
1612	__in		efx_nic_t *enp);
1613
1614#define	EFX_EVQ_MAXNEVS		32768
1615#define	EFX_EVQ_MINNEVS		512
1616
1617#define	EFX_EVQ_SIZE(_nevs)	((_nevs) * sizeof (efx_qword_t))
1618#define	EFX_EVQ_NBUFS(_nevs)	(EFX_EVQ_SIZE(_nevs) / EFX_BUF_SIZE)
1619
1620#define	EFX_EVQ_FLAGS_TYPE_MASK		(0x3)
1621#define	EFX_EVQ_FLAGS_TYPE_AUTO		(0x0)
1622#define	EFX_EVQ_FLAGS_TYPE_THROUGHPUT	(0x1)
1623#define	EFX_EVQ_FLAGS_TYPE_LOW_LATENCY	(0x2)
1624
1625extern	__checkReturn	efx_rc_t
1626efx_ev_qcreate(
1627	__in		efx_nic_t *enp,
1628	__in		unsigned int index,
1629	__in		efsys_mem_t *esmp,
1630	__in		size_t n,
1631	__in		uint32_t id,
1632	__in		uint32_t us,
1633	__in		uint32_t flags,
1634	__deref_out	efx_evq_t **eepp);
1635
1636extern		void
1637efx_ev_qpost(
1638	__in		efx_evq_t *eep,
1639	__in		uint16_t data);
1640
1641typedef __checkReturn	boolean_t
1642(*efx_initialized_ev_t)(
1643	__in_opt	void *arg);
1644
1645#define	EFX_PKT_UNICAST		0x0004
1646#define	EFX_PKT_START		0x0008
1647
1648#define	EFX_PKT_VLAN_TAGGED	0x0010
1649#define	EFX_CKSUM_TCPUDP	0x0020
1650#define	EFX_CKSUM_IPV4		0x0040
1651#define	EFX_PKT_CONT		0x0080
1652
1653#define	EFX_CHECK_VLAN		0x0100
1654#define	EFX_PKT_TCP		0x0200
1655#define	EFX_PKT_UDP		0x0400
1656#define	EFX_PKT_IPV4		0x0800
1657
1658#define	EFX_PKT_IPV6		0x1000
1659#define	EFX_PKT_PREFIX_LEN	0x2000
1660#define	EFX_ADDR_MISMATCH	0x4000
1661#define	EFX_DISCARD		0x8000
1662
1663#define	EFX_EV_RX_NLABELS	32
1664#define	EFX_EV_TX_NLABELS	32
1665
1666typedef	__checkReturn	boolean_t
1667(*efx_rx_ev_t)(
1668	__in_opt	void *arg,
1669	__in		uint32_t label,
1670	__in		uint32_t id,
1671	__in		uint32_t size,
1672	__in		uint16_t flags);
1673
1674typedef	__checkReturn	boolean_t
1675(*efx_tx_ev_t)(
1676	__in_opt	void *arg,
1677	__in		uint32_t label,
1678	__in		uint32_t id);
1679
1680#define	EFX_EXCEPTION_RX_RECOVERY	0x00000001
1681#define	EFX_EXCEPTION_RX_DSC_ERROR	0x00000002
1682#define	EFX_EXCEPTION_TX_DSC_ERROR	0x00000003
1683#define	EFX_EXCEPTION_UNKNOWN_SENSOREVT	0x00000004
1684#define	EFX_EXCEPTION_FWALERT_SRAM	0x00000005
1685#define	EFX_EXCEPTION_UNKNOWN_FWALERT	0x00000006
1686#define	EFX_EXCEPTION_RX_ERROR		0x00000007
1687#define	EFX_EXCEPTION_TX_ERROR		0x00000008
1688#define	EFX_EXCEPTION_EV_ERROR		0x00000009
1689
1690typedef	__checkReturn	boolean_t
1691(*efx_exception_ev_t)(
1692	__in_opt	void *arg,
1693	__in		uint32_t label,
1694	__in		uint32_t data);
1695
1696typedef	__checkReturn	boolean_t
1697(*efx_rxq_flush_done_ev_t)(
1698	__in_opt	void *arg,
1699	__in		uint32_t rxq_index);
1700
1701typedef	__checkReturn	boolean_t
1702(*efx_rxq_flush_failed_ev_t)(
1703	__in_opt	void *arg,
1704	__in		uint32_t rxq_index);
1705
1706typedef	__checkReturn	boolean_t
1707(*efx_txq_flush_done_ev_t)(
1708	__in_opt	void *arg,
1709	__in		uint32_t txq_index);
1710
1711typedef	__checkReturn	boolean_t
1712(*efx_software_ev_t)(
1713	__in_opt	void *arg,
1714	__in		uint16_t magic);
1715
1716typedef	__checkReturn	boolean_t
1717(*efx_sram_ev_t)(
1718	__in_opt	void *arg,
1719	__in		uint32_t code);
1720
1721#define	EFX_SRAM_CLEAR		0
1722#define	EFX_SRAM_UPDATE		1
1723#define	EFX_SRAM_ILLEGAL_CLEAR	2
1724
1725typedef	__checkReturn	boolean_t
1726(*efx_wake_up_ev_t)(
1727	__in_opt	void *arg,
1728	__in		uint32_t label);
1729
1730typedef	__checkReturn	boolean_t
1731(*efx_timer_ev_t)(
1732	__in_opt	void *arg,
1733	__in		uint32_t label);
1734
1735typedef __checkReturn	boolean_t
1736(*efx_link_change_ev_t)(
1737	__in_opt	void *arg,
1738	__in		efx_link_mode_t	link_mode);
1739
1740#if EFSYS_OPT_MON_STATS
1741
1742typedef __checkReturn	boolean_t
1743(*efx_monitor_ev_t)(
1744	__in_opt	void *arg,
1745	__in		efx_mon_stat_t id,
1746	__in		efx_mon_stat_value_t value);
1747
1748#endif	/* EFSYS_OPT_MON_STATS */
1749
1750#if EFSYS_OPT_MAC_STATS
1751
1752typedef __checkReturn	boolean_t
1753(*efx_mac_stats_ev_t)(
1754	__in_opt	void *arg,
1755	__in		uint32_t generation
1756	);
1757
1758#endif	/* EFSYS_OPT_MAC_STATS */
1759
1760typedef struct efx_ev_callbacks_s {
1761	efx_initialized_ev_t		eec_initialized;
1762	efx_rx_ev_t			eec_rx;
1763	efx_tx_ev_t			eec_tx;
1764	efx_exception_ev_t		eec_exception;
1765	efx_rxq_flush_done_ev_t		eec_rxq_flush_done;
1766	efx_rxq_flush_failed_ev_t	eec_rxq_flush_failed;
1767	efx_txq_flush_done_ev_t		eec_txq_flush_done;
1768	efx_software_ev_t		eec_software;
1769	efx_sram_ev_t			eec_sram;
1770	efx_wake_up_ev_t		eec_wake_up;
1771	efx_timer_ev_t			eec_timer;
1772	efx_link_change_ev_t		eec_link_change;
1773#if EFSYS_OPT_MON_STATS
1774	efx_monitor_ev_t		eec_monitor;
1775#endif	/* EFSYS_OPT_MON_STATS */
1776#if EFSYS_OPT_MAC_STATS
1777	efx_mac_stats_ev_t		eec_mac_stats;
1778#endif	/* EFSYS_OPT_MAC_STATS */
1779} efx_ev_callbacks_t;
1780
1781extern	__checkReturn	boolean_t
1782efx_ev_qpending(
1783	__in		efx_evq_t *eep,
1784	__in		unsigned int count);
1785
1786#if EFSYS_OPT_EV_PREFETCH
1787
1788extern			void
1789efx_ev_qprefetch(
1790	__in		efx_evq_t *eep,
1791	__in		unsigned int count);
1792
1793#endif	/* EFSYS_OPT_EV_PREFETCH */
1794
1795extern			void
1796efx_ev_qpoll(
1797	__in		efx_evq_t *eep,
1798	__inout		unsigned int *countp,
1799	__in		const efx_ev_callbacks_t *eecp,
1800	__in_opt	void *arg);
1801
1802extern	__checkReturn	efx_rc_t
1803efx_ev_usecs_to_ticks(
1804	__in		efx_nic_t *enp,
1805	__in		unsigned int usecs,
1806	__out		unsigned int *ticksp);
1807
1808extern	__checkReturn	efx_rc_t
1809efx_ev_qmoderate(
1810	__in		efx_evq_t *eep,
1811	__in		unsigned int us);
1812
1813extern	__checkReturn	efx_rc_t
1814efx_ev_qprime(
1815	__in		efx_evq_t *eep,
1816	__in		unsigned int count);
1817
1818#if EFSYS_OPT_QSTATS
1819
1820#if EFSYS_OPT_NAMES
1821
1822extern		const char *
1823efx_ev_qstat_name(
1824	__in	efx_nic_t *enp,
1825	__in	unsigned int id);
1826
1827#endif	/* EFSYS_OPT_NAMES */
1828
1829extern					void
1830efx_ev_qstats_update(
1831	__in				efx_evq_t *eep,
1832	__inout_ecount(EV_NQSTATS)	efsys_stat_t *stat);
1833
1834#endif	/* EFSYS_OPT_QSTATS */
1835
1836extern		void
1837efx_ev_qdestroy(
1838	__in	efx_evq_t *eep);
1839
1840/* RX */
1841
1842extern	__checkReturn	efx_rc_t
1843efx_rx_init(
1844	__inout		efx_nic_t *enp);
1845
1846extern		void
1847efx_rx_fini(
1848	__in		efx_nic_t *enp);
1849
1850#if EFSYS_OPT_RX_SCATTER
1851	__checkReturn	efx_rc_t
1852efx_rx_scatter_enable(
1853	__in		efx_nic_t *enp,
1854	__in		unsigned int buf_size);
1855#endif	/* EFSYS_OPT_RX_SCATTER */
1856
1857#if EFSYS_OPT_RX_SCALE
1858
1859typedef enum efx_rx_hash_alg_e {
1860	EFX_RX_HASHALG_LFSR = 0,
1861	EFX_RX_HASHALG_TOEPLITZ
1862} efx_rx_hash_alg_t;
1863
1864#define	EFX_RX_HASH_IPV4	(1U << 0)
1865#define	EFX_RX_HASH_TCPIPV4	(1U << 1)
1866#define	EFX_RX_HASH_IPV6	(1U << 2)
1867#define	EFX_RX_HASH_TCPIPV6	(1U << 3)
1868
1869typedef unsigned int efx_rx_hash_type_t;
1870
1871typedef enum efx_rx_hash_support_e {
1872	EFX_RX_HASH_UNAVAILABLE = 0,	/* Hardware hash not inserted */
1873	EFX_RX_HASH_AVAILABLE		/* Insert hash with/without RSS */
1874} efx_rx_hash_support_t;
1875
1876#define	EFX_RSS_TBL_SIZE	128	/* Rows in RX indirection table */
1877#define	EFX_MAXRSS		64	/* RX indirection entry range */
1878#define	EFX_MAXRSS_LEGACY	16	/* See bug16611 and bug17213 */
1879
1880typedef enum efx_rx_scale_support_e {
1881	EFX_RX_SCALE_UNAVAILABLE = 0,	/* Not supported */
1882	EFX_RX_SCALE_EXCLUSIVE,		/* Writable key/indirection table */
1883	EFX_RX_SCALE_SHARED		/* Read-only key/indirection table */
1884} efx_rx_scale_support_t;
1885
1886extern	__checkReturn	efx_rc_t
1887efx_rx_hash_support_get(
1888	__in		efx_nic_t *enp,
1889	__out		efx_rx_hash_support_t *supportp);
1890
1891
1892extern	__checkReturn	efx_rc_t
1893efx_rx_scale_support_get(
1894	__in		efx_nic_t *enp,
1895	__out		efx_rx_scale_support_t *supportp);
1896
1897extern	__checkReturn	efx_rc_t
1898efx_rx_scale_mode_set(
1899	__in	efx_nic_t *enp,
1900	__in	efx_rx_hash_alg_t alg,
1901	__in	efx_rx_hash_type_t type,
1902	__in	boolean_t insert);
1903
1904extern	__checkReturn	efx_rc_t
1905efx_rx_scale_tbl_set(
1906	__in		efx_nic_t *enp,
1907	__in_ecount(n)	unsigned int *table,
1908	__in		size_t n);
1909
1910extern	__checkReturn	efx_rc_t
1911efx_rx_scale_key_set(
1912	__in		efx_nic_t *enp,
1913	__in_ecount(n)	uint8_t *key,
1914	__in		size_t n);
1915
1916extern	__checkReturn	uint32_t
1917efx_pseudo_hdr_hash_get(
1918	__in		efx_rxq_t *erp,
1919	__in		efx_rx_hash_alg_t func,
1920	__in		uint8_t *buffer);
1921
1922#endif	/* EFSYS_OPT_RX_SCALE */
1923
1924extern	__checkReturn	efx_rc_t
1925efx_pseudo_hdr_pkt_length_get(
1926	__in		efx_rxq_t *erp,
1927	__in		uint8_t *buffer,
1928	__out		uint16_t *pkt_lengthp);
1929
1930#define	EFX_RXQ_MAXNDESCS		4096
1931#define	EFX_RXQ_MINNDESCS		512
1932
1933#define	EFX_RXQ_SIZE(_ndescs)		((_ndescs) * sizeof (efx_qword_t))
1934#define	EFX_RXQ_NBUFS(_ndescs)		(EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
1935#define	EFX_RXQ_LIMIT(_ndescs)		((_ndescs) - 16)
1936#define	EFX_RXQ_DC_NDESCS(_dcsize)	(8 << _dcsize)
1937
1938typedef enum efx_rxq_type_e {
1939	EFX_RXQ_TYPE_DEFAULT,
1940	EFX_RXQ_TYPE_SCATTER,
1941	EFX_RXQ_NTYPES
1942} efx_rxq_type_t;
1943
1944extern	__checkReturn	efx_rc_t
1945efx_rx_qcreate(
1946	__in		efx_nic_t *enp,
1947	__in		unsigned int index,
1948	__in		unsigned int label,
1949	__in		efx_rxq_type_t type,
1950	__in		efsys_mem_t *esmp,
1951	__in		size_t n,
1952	__in		uint32_t id,
1953	__in		efx_evq_t *eep,
1954	__deref_out	efx_rxq_t **erpp);
1955
1956typedef struct efx_buffer_s {
1957	efsys_dma_addr_t	eb_addr;
1958	size_t			eb_size;
1959	boolean_t		eb_eop;
1960} efx_buffer_t;
1961
1962typedef struct efx_desc_s {
1963	efx_qword_t ed_eq;
1964} efx_desc_t;
1965
1966extern			void
1967efx_rx_qpost(
1968	__in		efx_rxq_t *erp,
1969	__in_ecount(n)	efsys_dma_addr_t *addrp,
1970	__in		size_t size,
1971	__in		unsigned int n,
1972	__in		unsigned int completed,
1973	__in		unsigned int added);
1974
1975extern		void
1976efx_rx_qpush(
1977	__in	efx_rxq_t *erp,
1978	__in	unsigned int added,
1979	__inout	unsigned int *pushedp);
1980
1981extern	__checkReturn	efx_rc_t
1982efx_rx_qflush(
1983	__in	efx_rxq_t *erp);
1984
1985extern		void
1986efx_rx_qenable(
1987	__in	efx_rxq_t *erp);
1988
1989extern		void
1990efx_rx_qdestroy(
1991	__in	efx_rxq_t *erp);
1992
1993/* TX */
1994
1995typedef struct efx_txq_s	efx_txq_t;
1996
1997#if EFSYS_OPT_QSTATS
1998
1999/* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */
2000typedef enum efx_tx_qstat_e {
2001	TX_POST,
2002	TX_POST_PIO,
2003	TX_NQSTATS
2004} efx_tx_qstat_t;
2005
2006/* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */
2007
2008#endif	/* EFSYS_OPT_QSTATS */
2009
2010extern	__checkReturn	efx_rc_t
2011efx_tx_init(
2012	__in		efx_nic_t *enp);
2013
2014extern		void
2015efx_tx_fini(
2016	__in	efx_nic_t *enp);
2017
2018#define	EFX_BUG35388_WORKAROUND(_encp)					\
2019	(((_encp) == NULL) ? 1 : ((_encp)->enc_bug35388_workaround != 0))
2020
2021#define	EFX_TXQ_MAXNDESCS(_encp)					\
2022	((EFX_BUG35388_WORKAROUND(_encp)) ? 2048 : 4096)
2023
2024#define	EFX_TXQ_MINNDESCS		512
2025
2026#define	EFX_TXQ_SIZE(_ndescs)		((_ndescs) * sizeof (efx_qword_t))
2027#define	EFX_TXQ_NBUFS(_ndescs)		(EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
2028#define	EFX_TXQ_LIMIT(_ndescs)		((_ndescs) - 16)
2029#define	EFX_TXQ_DC_NDESCS(_dcsize)	(8 << _dcsize)
2030
2031#define	EFX_TXQ_MAX_BUFS 8 /* Maximum independent of EFX_BUG35388_WORKAROUND. */
2032
2033#define	EFX_TXQ_CKSUM_IPV4	0x0001
2034#define	EFX_TXQ_CKSUM_TCPUDP	0x0002
2035#define	EFX_TXQ_FATSOV2		0x0004
2036
2037extern	__checkReturn	efx_rc_t
2038efx_tx_qcreate(
2039	__in		efx_nic_t *enp,
2040	__in		unsigned int index,
2041	__in		unsigned int label,
2042	__in		efsys_mem_t *esmp,
2043	__in		size_t n,
2044	__in		uint32_t id,
2045	__in		uint16_t flags,
2046	__in		efx_evq_t *eep,
2047	__deref_out	efx_txq_t **etpp,
2048	__out		unsigned int *addedp);
2049
2050extern	__checkReturn	efx_rc_t
2051efx_tx_qpost(
2052	__in		efx_txq_t *etp,
2053	__in_ecount(n)	efx_buffer_t *eb,
2054	__in		unsigned int n,
2055	__in		unsigned int completed,
2056	__inout		unsigned int *addedp);
2057
2058extern	__checkReturn	efx_rc_t
2059efx_tx_qpace(
2060	__in		efx_txq_t *etp,
2061	__in		unsigned int ns);
2062
2063extern			void
2064efx_tx_qpush(
2065	__in		efx_txq_t *etp,
2066	__in		unsigned int added,
2067	__in		unsigned int pushed);
2068
2069extern	__checkReturn	efx_rc_t
2070efx_tx_qflush(
2071	__in		efx_txq_t *etp);
2072
2073extern			void
2074efx_tx_qenable(
2075	__in		efx_txq_t *etp);
2076
2077extern	__checkReturn	efx_rc_t
2078efx_tx_qpio_enable(
2079	__in		efx_txq_t *etp);
2080
2081extern			void
2082efx_tx_qpio_disable(
2083	__in		efx_txq_t *etp);
2084
2085extern	__checkReturn	efx_rc_t
2086efx_tx_qpio_write(
2087	__in			efx_txq_t *etp,
2088	__in_ecount(buf_length)	uint8_t *buffer,
2089	__in			size_t buf_length,
2090	__in			size_t pio_buf_offset);
2091
2092extern	__checkReturn	efx_rc_t
2093efx_tx_qpio_post(
2094	__in			efx_txq_t *etp,
2095	__in			size_t pkt_length,
2096	__in			unsigned int completed,
2097	__inout			unsigned int *addedp);
2098
2099extern	__checkReturn	efx_rc_t
2100efx_tx_qdesc_post(
2101	__in		efx_txq_t *etp,
2102	__in_ecount(n)	efx_desc_t *ed,
2103	__in		unsigned int n,
2104	__in		unsigned int completed,
2105	__inout		unsigned int *addedp);
2106
2107extern	void
2108efx_tx_qdesc_dma_create(
2109	__in	efx_txq_t *etp,
2110	__in	efsys_dma_addr_t addr,
2111	__in	size_t size,
2112	__in	boolean_t eop,
2113	__out	efx_desc_t *edp);
2114
2115extern	void
2116efx_tx_qdesc_tso_create(
2117	__in	efx_txq_t *etp,
2118	__in	uint16_t ipv4_id,
2119	__in	uint32_t tcp_seq,
2120	__in	uint8_t  tcp_flags,
2121	__out	efx_desc_t *edp);
2122
2123/* Number of FATSOv2 option descriptors */
2124#define	EFX_TX_FATSOV2_OPT_NDESCS		2
2125
2126/* Maximum number of DMA segments per TSO packet (not superframe) */
2127#define	EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX	24
2128
2129extern	void
2130efx_tx_qdesc_tso2_create(
2131	__in			efx_txq_t *etp,
2132	__in			uint16_t ipv4_id,
2133	__in			uint32_t tcp_seq,
2134	__in			uint16_t tcp_mss,
2135	__out_ecount(count)	efx_desc_t *edp,
2136	__in			int count);
2137
2138extern	void
2139efx_tx_qdesc_vlantci_create(
2140	__in	efx_txq_t *etp,
2141	__in	uint16_t tci,
2142	__out	efx_desc_t *edp);
2143
2144#if EFSYS_OPT_QSTATS
2145
2146#if EFSYS_OPT_NAMES
2147
2148extern		const char *
2149efx_tx_qstat_name(
2150	__in	efx_nic_t *etp,
2151	__in	unsigned int id);
2152
2153#endif	/* EFSYS_OPT_NAMES */
2154
2155extern					void
2156efx_tx_qstats_update(
2157	__in				efx_txq_t *etp,
2158	__inout_ecount(TX_NQSTATS)	efsys_stat_t *stat);
2159
2160#endif	/* EFSYS_OPT_QSTATS */
2161
2162extern		void
2163efx_tx_qdestroy(
2164	__in	efx_txq_t *etp);
2165
2166
2167/* FILTER */
2168
2169#if EFSYS_OPT_FILTER
2170
2171#define	EFX_ETHER_TYPE_IPV4 0x0800
2172#define	EFX_ETHER_TYPE_IPV6 0x86DD
2173
2174#define	EFX_IPPROTO_TCP 6
2175#define	EFX_IPPROTO_UDP 17
2176
2177/* Use RSS to spread across multiple queues */
2178#define	EFX_FILTER_FLAG_RX_RSS		0x01
2179/* Enable RX scatter */
2180#define	EFX_FILTER_FLAG_RX_SCATTER	0x02
2181/*
2182 * Override an automatic filter (priority EFX_FILTER_PRI_AUTO).
2183 * May only be set by the filter implementation for each type.
2184 * A removal request will restore the automatic filter in its place.
2185 */
2186#define	EFX_FILTER_FLAG_RX_OVER_AUTO	0x04
2187/* Filter is for RX */
2188#define	EFX_FILTER_FLAG_RX		0x08
2189/* Filter is for TX */
2190#define	EFX_FILTER_FLAG_TX		0x10
2191
2192typedef unsigned int efx_filter_flags_t;
2193
2194typedef enum efx_filter_match_flags_e {
2195	EFX_FILTER_MATCH_REM_HOST = 0x0001,	/* Match by remote IP host
2196						 * address */
2197	EFX_FILTER_MATCH_LOC_HOST = 0x0002,	/* Match by local IP host
2198						 * address */
2199	EFX_FILTER_MATCH_REM_MAC = 0x0004,	/* Match by remote MAC address */
2200	EFX_FILTER_MATCH_REM_PORT = 0x0008,	/* Match by remote TCP/UDP port */
2201	EFX_FILTER_MATCH_LOC_MAC = 0x0010,	/* Match by remote TCP/UDP port */
2202	EFX_FILTER_MATCH_LOC_PORT = 0x0020,	/* Match by local TCP/UDP port */
2203	EFX_FILTER_MATCH_ETHER_TYPE = 0x0040,	/* Match by Ether-type */
2204	EFX_FILTER_MATCH_INNER_VID = 0x0080,	/* Match by inner VLAN ID */
2205	EFX_FILTER_MATCH_OUTER_VID = 0x0100,	/* Match by outer VLAN ID */
2206	EFX_FILTER_MATCH_IP_PROTO = 0x0200,	/* Match by IP transport
2207						 * protocol */
2208	EFX_FILTER_MATCH_LOC_MAC_IG = 0x0400,	/* Match by local MAC address
2209						 * I/G bit. Used for RX default
2210						 * unicast and multicast/
2211						 * broadcast filters. */
2212} efx_filter_match_flags_t;
2213
2214typedef enum efx_filter_priority_s {
2215	EFX_FILTER_PRI_HINT = 0,	/* Performance hint */
2216	EFX_FILTER_PRI_AUTO,		/* Automatic filter based on device
2217					 * address list or hardware
2218					 * requirements. This may only be used
2219					 * by the filter implementation for
2220					 * each NIC type. */
2221	EFX_FILTER_PRI_MANUAL,		/* Manually configured filter */
2222	EFX_FILTER_PRI_REQUIRED,	/* Required for correct behaviour of the
2223					 * client (e.g. SR-IOV, HyperV VMQ etc.)
2224					 */
2225} efx_filter_priority_t;
2226
2227/*
2228 * FIXME: All these fields are assumed to be in little-endian byte order.
2229 * It may be better for some to be big-endian. See bug42804.
2230 */
2231
2232typedef struct efx_filter_spec_s {
2233	uint32_t	efs_match_flags:12;
2234	uint32_t	efs_priority:2;
2235	uint32_t	efs_flags:6;
2236	uint32_t	efs_dmaq_id:12;
2237	uint32_t	efs_rss_context;
2238	uint16_t	efs_outer_vid;
2239	uint16_t	efs_inner_vid;
2240	uint8_t		efs_loc_mac[EFX_MAC_ADDR_LEN];
2241	uint8_t		efs_rem_mac[EFX_MAC_ADDR_LEN];
2242	uint16_t	efs_ether_type;
2243	uint8_t		efs_ip_proto;
2244	uint16_t	efs_loc_port;
2245	uint16_t	efs_rem_port;
2246	efx_oword_t	efs_rem_host;
2247	efx_oword_t	efs_loc_host;
2248} efx_filter_spec_t;
2249
2250
2251/* Default values for use in filter specifications */
2252#define	EFX_FILTER_SPEC_RSS_CONTEXT_DEFAULT	0xffffffff
2253#define	EFX_FILTER_SPEC_RX_DMAQ_ID_DROP		0xfff
2254#define	EFX_FILTER_SPEC_VID_UNSPEC		0xffff
2255
2256extern	__checkReturn	efx_rc_t
2257efx_filter_init(
2258	__in		efx_nic_t *enp);
2259
2260extern			void
2261efx_filter_fini(
2262	__in		efx_nic_t *enp);
2263
2264extern	__checkReturn	efx_rc_t
2265efx_filter_insert(
2266	__in		efx_nic_t *enp,
2267	__inout		efx_filter_spec_t *spec);
2268
2269extern	__checkReturn	efx_rc_t
2270efx_filter_remove(
2271	__in		efx_nic_t *enp,
2272	__inout		efx_filter_spec_t *spec);
2273
2274extern	__checkReturn	efx_rc_t
2275efx_filter_restore(
2276	__in		efx_nic_t *enp);
2277
2278extern	__checkReturn	efx_rc_t
2279efx_filter_supported_filters(
2280	__in		efx_nic_t *enp,
2281	__out		uint32_t *list,
2282	__out		size_t *length);
2283
2284extern			void
2285efx_filter_spec_init_rx(
2286	__out		efx_filter_spec_t *spec,
2287	__in		efx_filter_priority_t priority,
2288	__in		efx_filter_flags_t flags,
2289	__in		efx_rxq_t *erp);
2290
2291extern			void
2292efx_filter_spec_init_tx(
2293	__out		efx_filter_spec_t *spec,
2294	__in		efx_txq_t *etp);
2295
2296extern	__checkReturn	efx_rc_t
2297efx_filter_spec_set_ipv4_local(
2298	__inout		efx_filter_spec_t *spec,
2299	__in		uint8_t proto,
2300	__in		uint32_t host,
2301	__in		uint16_t port);
2302
2303extern	__checkReturn	efx_rc_t
2304efx_filter_spec_set_ipv4_full(
2305	__inout		efx_filter_spec_t *spec,
2306	__in		uint8_t proto,
2307	__in		uint32_t lhost,
2308	__in		uint16_t lport,
2309	__in		uint32_t rhost,
2310	__in		uint16_t rport);
2311
2312extern	__checkReturn	efx_rc_t
2313efx_filter_spec_set_eth_local(
2314	__inout		efx_filter_spec_t *spec,
2315	__in		uint16_t vid,
2316	__in		const uint8_t *addr);
2317
2318extern	__checkReturn	efx_rc_t
2319efx_filter_spec_set_uc_def(
2320	__inout		efx_filter_spec_t *spec);
2321
2322extern	__checkReturn	efx_rc_t
2323efx_filter_spec_set_mc_def(
2324	__inout		efx_filter_spec_t *spec);
2325
2326#endif	/* EFSYS_OPT_FILTER */
2327
2328/* HASH */
2329
2330extern	__checkReturn		uint32_t
2331efx_hash_dwords(
2332	__in_ecount(count)	uint32_t const *input,
2333	__in			size_t count,
2334	__in			uint32_t init);
2335
2336extern	__checkReturn		uint32_t
2337efx_hash_bytes(
2338	__in_ecount(length)	uint8_t const *input,
2339	__in			size_t length,
2340	__in			uint32_t init);
2341
2342#if EFSYS_OPT_LICENSING
2343
2344/* LICENSING */
2345
2346typedef struct efx_key_stats_s {
2347	uint32_t	eks_valid;
2348	uint32_t	eks_invalid;
2349	uint32_t	eks_blacklisted;
2350	uint32_t	eks_unverifiable;
2351	uint32_t	eks_wrong_node;
2352	uint32_t	eks_licensed_apps_lo;
2353	uint32_t	eks_licensed_apps_hi;
2354	uint32_t	eks_licensed_features_lo;
2355	uint32_t	eks_licensed_features_hi;
2356} efx_key_stats_t;
2357
2358extern	__checkReturn		efx_rc_t
2359efx_lic_init(
2360	__in			efx_nic_t *enp);
2361
2362extern				void
2363efx_lic_fini(
2364	__in			efx_nic_t *enp);
2365
2366extern	__checkReturn	boolean_t
2367efx_lic_check_support(
2368	__in			efx_nic_t *enp);
2369
2370extern	__checkReturn	efx_rc_t
2371efx_lic_update_licenses(
2372	__in		efx_nic_t *enp);
2373
2374extern	__checkReturn	efx_rc_t
2375efx_lic_get_key_stats(
2376	__in		efx_nic_t *enp,
2377	__out		efx_key_stats_t *ksp);
2378
2379extern	__checkReturn	efx_rc_t
2380efx_lic_app_state(
2381	__in		efx_nic_t *enp,
2382	__in		uint64_t app_id,
2383	__out		boolean_t *licensedp);
2384
2385extern	__checkReturn	efx_rc_t
2386efx_lic_get_id(
2387	__in		efx_nic_t *enp,
2388	__in		size_t buffer_size,
2389	__out		uint32_t *typep,
2390	__out		size_t *lengthp,
2391	__out_opt	uint8_t *bufferp);
2392
2393
2394extern	__checkReturn		efx_rc_t
2395efx_lic_find_start(
2396	__in			efx_nic_t *enp,
2397	__in_bcount(buffer_size)
2398				caddr_t bufferp,
2399	__in			size_t buffer_size,
2400	__out			uint32_t *startp
2401	);
2402
2403extern	__checkReturn		efx_rc_t
2404efx_lic_find_end(
2405	__in			efx_nic_t *enp,
2406	__in_bcount(buffer_size)
2407				caddr_t bufferp,
2408	__in			size_t buffer_size,
2409	__in			uint32_t offset,
2410	__out			uint32_t *endp
2411	);
2412
2413extern	__checkReturn	__success(return != B_FALSE)	boolean_t
2414efx_lic_find_key(
2415	__in			efx_nic_t *enp,
2416	__in_bcount(buffer_size)
2417				caddr_t bufferp,
2418	__in			size_t buffer_size,
2419	__in			uint32_t offset,
2420	__out			uint32_t *startp,
2421	__out			uint32_t *lengthp
2422	);
2423
2424extern	__checkReturn	__success(return != B_FALSE)	boolean_t
2425efx_lic_validate_key(
2426	__in			efx_nic_t *enp,
2427	__in_bcount(length)	caddr_t keyp,
2428	__in			uint32_t length
2429	);
2430
2431extern	__checkReturn		efx_rc_t
2432efx_lic_read_key(
2433	__in			efx_nic_t *enp,
2434	__in_bcount(buffer_size)
2435				caddr_t bufferp,
2436	__in			size_t buffer_size,
2437	__in			uint32_t offset,
2438	__in			uint32_t length,
2439	__out_bcount_part(key_max_size, *lengthp)
2440				caddr_t keyp,
2441	__in			size_t key_max_size,
2442	__out			uint32_t *lengthp
2443	);
2444
2445extern	__checkReturn		efx_rc_t
2446efx_lic_write_key(
2447	__in			efx_nic_t *enp,
2448	__in_bcount(buffer_size)
2449				caddr_t bufferp,
2450	__in			size_t buffer_size,
2451	__in			uint32_t offset,
2452	__in_bcount(length)	caddr_t keyp,
2453	__in			uint32_t length,
2454	__out			uint32_t *lengthp
2455	);
2456
2457	__checkReturn		efx_rc_t
2458efx_lic_delete_key(
2459	__in			efx_nic_t *enp,
2460	__in_bcount(buffer_size)
2461				caddr_t bufferp,
2462	__in			size_t buffer_size,
2463	__in			uint32_t offset,
2464	__in			uint32_t length,
2465	__in			uint32_t end,
2466	__out			uint32_t *deltap
2467	);
2468
2469extern	__checkReturn		efx_rc_t
2470efx_lic_create_partition(
2471	__in			efx_nic_t *enp,
2472	__in_bcount(buffer_size)
2473				caddr_t bufferp,
2474	__in			size_t buffer_size
2475	);
2476
2477extern	__checkReturn		efx_rc_t
2478efx_lic_finish_partition(
2479	__in			efx_nic_t *enp,
2480	__in_bcount(buffer_size)
2481				caddr_t bufferp,
2482	__in			size_t buffer_size
2483	);
2484
2485#endif	/* EFSYS_OPT_LICENSING */
2486
2487
2488
2489#ifdef	__cplusplus
2490}
2491#endif
2492
2493#endif	/* _SYS_EFX_H */
2494