efx.h revision 310926 
1/*-
2 * Copyright (c) 2006-2016 Solarflare Communications Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,
9 *    this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 *    this list of conditions and the following disclaimer in the documentation
12 *    and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
29 *
30 * $FreeBSD: stable/11/sys/dev/sfxge/common/efx.h 310926 2016-12-31 11:07:44Z arybchik $
31 */
32
33#ifndef	_SYS_EFX_H
34#define	_SYS_EFX_H
35
36#include "efsys.h"
37#include "efx_check.h"
38#include "efx_phy_ids.h"
39
40#ifdef	__cplusplus
41extern "C" {
42#endif
43
44#define	EFX_STATIC_ASSERT(_cond)		\
45	((void)sizeof(char[(_cond) ? 1 : -1]))
46
47#define	EFX_ARRAY_SIZE(_array)			\
48	(sizeof(_array) / sizeof((_array)[0]))
49
50#define	EFX_FIELD_OFFSET(_type, _field)		\
51	((size_t) &(((_type *)0)->_field))
52
53/* Return codes */
54
55typedef __success(return == 0) int efx_rc_t;
56
57
58/* Chip families */
59
60typedef enum efx_family_e {
61	EFX_FAMILY_INVALID,
62	EFX_FAMILY_FALCON,	/* Obsolete and not supported */
63	EFX_FAMILY_SIENA,
64	EFX_FAMILY_HUNTINGTON,
65	EFX_FAMILY_MEDFORD,
66	EFX_FAMILY_NTYPES
67} efx_family_t;
68
69extern	__checkReturn	efx_rc_t
70efx_family(
71	__in		uint16_t venid,
72	__in		uint16_t devid,
73	__out		efx_family_t *efp);
74
75
76#define	EFX_PCI_VENID_SFC			0x1924
77
78#define	EFX_PCI_DEVID_FALCON			0x0710	/* SFC4000 */
79
80#define	EFX_PCI_DEVID_BETHPAGE			0x0803	/* SFC9020 */
81#define	EFX_PCI_DEVID_SIENA			0x0813	/* SFL9021 */
82#define	EFX_PCI_DEVID_SIENA_F1_UNINIT		0x0810
83
84#define	EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT	0x0901
85#define	EFX_PCI_DEVID_FARMINGDALE		0x0903	/* SFC9120 PF */
86#define	EFX_PCI_DEVID_GREENPORT			0x0923	/* SFC9140 PF */
87
88#define	EFX_PCI_DEVID_FARMINGDALE_VF		0x1903	/* SFC9120 VF */
89#define	EFX_PCI_DEVID_GREENPORT_VF		0x1923	/* SFC9140 VF */
90
91#define	EFX_PCI_DEVID_MEDFORD_PF_UNINIT		0x0913
92#define	EFX_PCI_DEVID_MEDFORD			0x0A03	/* SFC9240 PF */
93#define	EFX_PCI_DEVID_MEDFORD_VF		0x1A03	/* SFC9240 VF */
94
95#define	EFX_MEM_BAR	2
96
97/* Error codes */
98
99enum {
100	EFX_ERR_INVALID,
101	EFX_ERR_SRAM_OOB,
102	EFX_ERR_BUFID_DC_OOB,
103	EFX_ERR_MEM_PERR,
104	EFX_ERR_RBUF_OWN,
105	EFX_ERR_TBUF_OWN,
106	EFX_ERR_RDESQ_OWN,
107	EFX_ERR_TDESQ_OWN,
108	EFX_ERR_EVQ_OWN,
109	EFX_ERR_EVFF_OFLO,
110	EFX_ERR_ILL_ADDR,
111	EFX_ERR_SRAM_PERR,
112	EFX_ERR_NCODES
113};
114
115/* Calculate the IEEE 802.3 CRC32 of a MAC addr */
116extern	__checkReturn		uint32_t
117efx_crc32_calculate(
118	__in			uint32_t crc_init,
119	__in_ecount(length)	uint8_t const *input,
120	__in			int length);
121
122
123/* Type prototypes */
124
125typedef struct efx_rxq_s	efx_rxq_t;
126
127/* NIC */
128
129typedef struct efx_nic_s	efx_nic_t;
130
131#define	EFX_NIC_FUNC_PRIMARY	0x00000001
132#define	EFX_NIC_FUNC_LINKCTRL	0x00000002
133#define	EFX_NIC_FUNC_TRUSTED	0x00000004
134
135
136extern	__checkReturn	efx_rc_t
137efx_nic_create(
138	__in		efx_family_t family,
139	__in		efsys_identifier_t *esip,
140	__in		efsys_bar_t *esbp,
141	__in		efsys_lock_t *eslp,
142	__deref_out	efx_nic_t **enpp);
143
144extern	__checkReturn	efx_rc_t
145efx_nic_probe(
146	__in		efx_nic_t *enp);
147
148extern	__checkReturn	efx_rc_t
149efx_nic_init(
150	__in		efx_nic_t *enp);
151
152extern	__checkReturn	efx_rc_t
153efx_nic_reset(
154	__in		efx_nic_t *enp);
155
156#if EFSYS_OPT_DIAG
157
158extern	__checkReturn	efx_rc_t
159efx_nic_register_test(
160	__in		efx_nic_t *enp);
161
162#endif	/* EFSYS_OPT_DIAG */
163
164extern		void
165efx_nic_fini(
166	__in		efx_nic_t *enp);
167
168extern		void
169efx_nic_unprobe(
170	__in		efx_nic_t *enp);
171
172extern		void
173efx_nic_destroy(
174	__in	efx_nic_t *enp);
175
176#define	EFX_PCIE_LINK_SPEED_GEN1		1
177#define	EFX_PCIE_LINK_SPEED_GEN2		2
178#define	EFX_PCIE_LINK_SPEED_GEN3		3
179
180typedef enum efx_pcie_link_performance_e {
181	EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH,
182	EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH,
183	EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY,
184	EFX_PCIE_LINK_PERFORMANCE_OPTIMAL
185} efx_pcie_link_performance_t;
186
187extern	__checkReturn	efx_rc_t
188efx_nic_calculate_pcie_link_bandwidth(
189	__in		uint32_t pcie_link_width,
190	__in		uint32_t pcie_link_gen,
191	__out		uint32_t *bandwidth_mbpsp);
192
193extern	__checkReturn	efx_rc_t
194efx_nic_check_pcie_link_speed(
195	__in		efx_nic_t *enp,
196	__in		uint32_t pcie_link_width,
197	__in		uint32_t pcie_link_gen,
198	__out		efx_pcie_link_performance_t *resultp);
199
200#if EFSYS_OPT_MCDI
201
202#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
203/* Huntington and Medford require MCDIv2 commands */
204#define	WITH_MCDI_V2 1
205#endif
206
207typedef struct efx_mcdi_req_s efx_mcdi_req_t;
208
209typedef enum efx_mcdi_exception_e {
210	EFX_MCDI_EXCEPTION_MC_REBOOT,
211	EFX_MCDI_EXCEPTION_MC_BADASSERT,
212} efx_mcdi_exception_t;
213
214#if EFSYS_OPT_MCDI_LOGGING
215typedef enum efx_log_msg_e {
216	EFX_LOG_INVALID,
217	EFX_LOG_MCDI_REQUEST,
218	EFX_LOG_MCDI_RESPONSE,
219} efx_log_msg_t;
220#endif /* EFSYS_OPT_MCDI_LOGGING */
221
222typedef struct efx_mcdi_transport_s {
223	void		*emt_context;
224	efsys_mem_t	*emt_dma_mem;
225	void		(*emt_execute)(void *, efx_mcdi_req_t *);
226	void		(*emt_ev_cpl)(void *);
227	void		(*emt_exception)(void *, efx_mcdi_exception_t);
228#if EFSYS_OPT_MCDI_LOGGING
229	void		(*emt_logger)(void *, efx_log_msg_t,
230					void *, size_t, void *, size_t);
231#endif /* EFSYS_OPT_MCDI_LOGGING */
232#if EFSYS_OPT_MCDI_PROXY_AUTH
233	void		(*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t);
234#endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
235} efx_mcdi_transport_t;
236
237extern	__checkReturn	efx_rc_t
238efx_mcdi_init(
239	__in		efx_nic_t *enp,
240	__in		const efx_mcdi_transport_t *mtp);
241
242extern	__checkReturn	efx_rc_t
243efx_mcdi_reboot(
244	__in		efx_nic_t *enp);
245
246			void
247efx_mcdi_new_epoch(
248	__in		efx_nic_t *enp);
249
250extern			void
251efx_mcdi_request_start(
252	__in		efx_nic_t *enp,
253	__in		efx_mcdi_req_t *emrp,
254	__in		boolean_t ev_cpl);
255
256extern	__checkReturn	boolean_t
257efx_mcdi_request_poll(
258	__in		efx_nic_t *enp);
259
260extern	__checkReturn	boolean_t
261efx_mcdi_request_abort(
262	__in		efx_nic_t *enp);
263
264extern			void
265efx_mcdi_fini(
266	__in		efx_nic_t *enp);
267
268#endif	/* EFSYS_OPT_MCDI */
269
270/* INTR */
271
272#define	EFX_NINTR_SIENA 1024
273
274typedef enum efx_intr_type_e {
275	EFX_INTR_INVALID = 0,
276	EFX_INTR_LINE,
277	EFX_INTR_MESSAGE,
278	EFX_INTR_NTYPES
279} efx_intr_type_t;
280
281#define	EFX_INTR_SIZE	(sizeof (efx_oword_t))
282
283extern	__checkReturn	efx_rc_t
284efx_intr_init(
285	__in		efx_nic_t *enp,
286	__in		efx_intr_type_t type,
287	__in		efsys_mem_t *esmp);
288
289extern			void
290efx_intr_enable(
291	__in		efx_nic_t *enp);
292
293extern			void
294efx_intr_disable(
295	__in		efx_nic_t *enp);
296
297extern			void
298efx_intr_disable_unlocked(
299	__in		efx_nic_t *enp);
300
301#define	EFX_INTR_NEVQS	32
302
303extern	__checkReturn	efx_rc_t
304efx_intr_trigger(
305	__in		efx_nic_t *enp,
306	__in		unsigned int level);
307
308extern			void
309efx_intr_status_line(
310	__in		efx_nic_t *enp,
311	__out		boolean_t *fatalp,
312	__out		uint32_t *maskp);
313
314extern			void
315efx_intr_status_message(
316	__in		efx_nic_t *enp,
317	__in		unsigned int message,
318	__out		boolean_t *fatalp);
319
320extern			void
321efx_intr_fatal(
322	__in		efx_nic_t *enp);
323
324extern			void
325efx_intr_fini(
326	__in		efx_nic_t *enp);
327
328/* MAC */
329
330#if EFSYS_OPT_MAC_STATS
331
332/* START MKCONFIG GENERATED EfxHeaderMacBlock e323546097fd7c65 */
333typedef enum efx_mac_stat_e {
334	EFX_MAC_RX_OCTETS,
335	EFX_MAC_RX_PKTS,
336	EFX_MAC_RX_UNICST_PKTS,
337	EFX_MAC_RX_MULTICST_PKTS,
338	EFX_MAC_RX_BRDCST_PKTS,
339	EFX_MAC_RX_PAUSE_PKTS,
340	EFX_MAC_RX_LE_64_PKTS,
341	EFX_MAC_RX_65_TO_127_PKTS,
342	EFX_MAC_RX_128_TO_255_PKTS,
343	EFX_MAC_RX_256_TO_511_PKTS,
344	EFX_MAC_RX_512_TO_1023_PKTS,
345	EFX_MAC_RX_1024_TO_15XX_PKTS,
346	EFX_MAC_RX_GE_15XX_PKTS,
347	EFX_MAC_RX_ERRORS,
348	EFX_MAC_RX_FCS_ERRORS,
349	EFX_MAC_RX_DROP_EVENTS,
350	EFX_MAC_RX_FALSE_CARRIER_ERRORS,
351	EFX_MAC_RX_SYMBOL_ERRORS,
352	EFX_MAC_RX_ALIGN_ERRORS,
353	EFX_MAC_RX_INTERNAL_ERRORS,
354	EFX_MAC_RX_JABBER_PKTS,
355	EFX_MAC_RX_LANE0_CHAR_ERR,
356	EFX_MAC_RX_LANE1_CHAR_ERR,
357	EFX_MAC_RX_LANE2_CHAR_ERR,
358	EFX_MAC_RX_LANE3_CHAR_ERR,
359	EFX_MAC_RX_LANE0_DISP_ERR,
360	EFX_MAC_RX_LANE1_DISP_ERR,
361	EFX_MAC_RX_LANE2_DISP_ERR,
362	EFX_MAC_RX_LANE3_DISP_ERR,
363	EFX_MAC_RX_MATCH_FAULT,
364	EFX_MAC_RX_NODESC_DROP_CNT,
365	EFX_MAC_TX_OCTETS,
366	EFX_MAC_TX_PKTS,
367	EFX_MAC_TX_UNICST_PKTS,
368	EFX_MAC_TX_MULTICST_PKTS,
369	EFX_MAC_TX_BRDCST_PKTS,
370	EFX_MAC_TX_PAUSE_PKTS,
371	EFX_MAC_TX_LE_64_PKTS,
372	EFX_MAC_TX_65_TO_127_PKTS,
373	EFX_MAC_TX_128_TO_255_PKTS,
374	EFX_MAC_TX_256_TO_511_PKTS,
375	EFX_MAC_TX_512_TO_1023_PKTS,
376	EFX_MAC_TX_1024_TO_15XX_PKTS,
377	EFX_MAC_TX_GE_15XX_PKTS,
378	EFX_MAC_TX_ERRORS,
379	EFX_MAC_TX_SGL_COL_PKTS,
380	EFX_MAC_TX_MULT_COL_PKTS,
381	EFX_MAC_TX_EX_COL_PKTS,
382	EFX_MAC_TX_LATE_COL_PKTS,
383	EFX_MAC_TX_DEF_PKTS,
384	EFX_MAC_TX_EX_DEF_PKTS,
385	EFX_MAC_PM_TRUNC_BB_OVERFLOW,
386	EFX_MAC_PM_DISCARD_BB_OVERFLOW,
387	EFX_MAC_PM_TRUNC_VFIFO_FULL,
388	EFX_MAC_PM_DISCARD_VFIFO_FULL,
389	EFX_MAC_PM_TRUNC_QBB,
390	EFX_MAC_PM_DISCARD_QBB,
391	EFX_MAC_PM_DISCARD_MAPPING,
392	EFX_MAC_RXDP_Q_DISABLED_PKTS,
393	EFX_MAC_RXDP_DI_DROPPED_PKTS,
394	EFX_MAC_RXDP_STREAMING_PKTS,
395	EFX_MAC_RXDP_HLB_FETCH,
396	EFX_MAC_RXDP_HLB_WAIT,
397	EFX_MAC_VADAPTER_RX_UNICAST_PACKETS,
398	EFX_MAC_VADAPTER_RX_UNICAST_BYTES,
399	EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS,
400	EFX_MAC_VADAPTER_RX_MULTICAST_BYTES,
401	EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS,
402	EFX_MAC_VADAPTER_RX_BROADCAST_BYTES,
403	EFX_MAC_VADAPTER_RX_BAD_PACKETS,
404	EFX_MAC_VADAPTER_RX_BAD_BYTES,
405	EFX_MAC_VADAPTER_RX_OVERFLOW,
406	EFX_MAC_VADAPTER_TX_UNICAST_PACKETS,
407	EFX_MAC_VADAPTER_TX_UNICAST_BYTES,
408	EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS,
409	EFX_MAC_VADAPTER_TX_MULTICAST_BYTES,
410	EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS,
411	EFX_MAC_VADAPTER_TX_BROADCAST_BYTES,
412	EFX_MAC_VADAPTER_TX_BAD_PACKETS,
413	EFX_MAC_VADAPTER_TX_BAD_BYTES,
414	EFX_MAC_VADAPTER_TX_OVERFLOW,
415	EFX_MAC_NSTATS
416} efx_mac_stat_t;
417
418/* END MKCONFIG GENERATED EfxHeaderMacBlock */
419
420#endif	/* EFSYS_OPT_MAC_STATS */
421
422typedef enum efx_link_mode_e {
423	EFX_LINK_UNKNOWN = 0,
424	EFX_LINK_DOWN,
425	EFX_LINK_10HDX,
426	EFX_LINK_10FDX,
427	EFX_LINK_100HDX,
428	EFX_LINK_100FDX,
429	EFX_LINK_1000HDX,
430	EFX_LINK_1000FDX,
431	EFX_LINK_10000FDX,
432	EFX_LINK_40000FDX,
433	EFX_LINK_NMODES
434} efx_link_mode_t;
435
436#define	EFX_MAC_ADDR_LEN 6
437
438#define	EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t *)_address)[0] & 0x01)
439
440#define	EFX_MAC_MULTICAST_LIST_MAX	256
441
442#define	EFX_MAC_SDU_MAX	9202
443
444#define	EFX_MAC_PDU_ADJUSTMENT					\
445	(/* EtherII */ 14					\
446	    + /* VLAN */ 4					\
447	    + /* CRC */ 4					\
448	    + /* bug16011 */ 16)				\
449
450#define	EFX_MAC_PDU(_sdu)					\
451	P2ROUNDUP((_sdu) + EFX_MAC_PDU_ADJUSTMENT, 8)
452
453/*
454 * Due to the P2ROUNDUP in EFX_MAC_PDU(), EFX_MAC_SDU_FROM_PDU() may give
455 * the SDU rounded up slightly.
456 */
457#define	EFX_MAC_SDU_FROM_PDU(_pdu)	((_pdu) - EFX_MAC_PDU_ADJUSTMENT)
458
459#define	EFX_MAC_PDU_MIN	60
460#define	EFX_MAC_PDU_MAX	EFX_MAC_PDU(EFX_MAC_SDU_MAX)
461
462extern	__checkReturn	efx_rc_t
463efx_mac_pdu_get(
464	__in		efx_nic_t *enp,
465	__out		size_t *pdu);
466
467extern	__checkReturn	efx_rc_t
468efx_mac_pdu_set(
469	__in		efx_nic_t *enp,
470	__in		size_t pdu);
471
472extern	__checkReturn	efx_rc_t
473efx_mac_addr_set(
474	__in		efx_nic_t *enp,
475	__in		uint8_t *addr);
476
477extern	__checkReturn			efx_rc_t
478efx_mac_filter_set(
479	__in				efx_nic_t *enp,
480	__in				boolean_t all_unicst,
481	__in				boolean_t mulcst,
482	__in				boolean_t all_mulcst,
483	__in				boolean_t brdcst);
484
485extern	__checkReturn	efx_rc_t
486efx_mac_multicast_list_set(
487	__in				efx_nic_t *enp,
488	__in_ecount(6*count)		uint8_t const *addrs,
489	__in				int count);
490
491extern	__checkReturn	efx_rc_t
492efx_mac_filter_default_rxq_set(
493	__in		efx_nic_t *enp,
494	__in		efx_rxq_t *erp,
495	__in		boolean_t using_rss);
496
497extern			void
498efx_mac_filter_default_rxq_clear(
499	__in		efx_nic_t *enp);
500
501extern	__checkReturn	efx_rc_t
502efx_mac_drain(
503	__in		efx_nic_t *enp,
504	__in		boolean_t enabled);
505
506extern	__checkReturn	efx_rc_t
507efx_mac_up(
508	__in		efx_nic_t *enp,
509	__out		boolean_t *mac_upp);
510
511#define	EFX_FCNTL_RESPOND	0x00000001
512#define	EFX_FCNTL_GENERATE	0x00000002
513
514extern	__checkReturn	efx_rc_t
515efx_mac_fcntl_set(
516	__in		efx_nic_t *enp,
517	__in		unsigned int fcntl,
518	__in		boolean_t autoneg);
519
520extern			void
521efx_mac_fcntl_get(
522	__in		efx_nic_t *enp,
523	__out		unsigned int *fcntl_wantedp,
524	__out		unsigned int *fcntl_linkp);
525
526
527#if EFSYS_OPT_MAC_STATS
528
529#if EFSYS_OPT_NAMES
530
531extern	__checkReturn			const char *
532efx_mac_stat_name(
533	__in				efx_nic_t *enp,
534	__in				unsigned int id);
535
536#endif	/* EFSYS_OPT_NAMES */
537
538#define	EFX_MAC_STATS_SIZE 0x400
539
540/*
541 * Upload mac statistics supported by the hardware into the given buffer.
542 *
543 * The reference buffer must be at least %EFX_MAC_STATS_SIZE bytes,
544 * and page aligned.
545 *
546 * The hardware will only DMA statistics that it understands (of course).
547 * Drivers should not make any assumptions about which statistics are
548 * supported, especially when the statistics are generated by firmware.
549 *
550 * Thus, drivers should zero this buffer before use, so that not-understood
551 * statistics read back as zero.
552 */
553extern	__checkReturn			efx_rc_t
554efx_mac_stats_upload(
555	__in				efx_nic_t *enp,
556	__in				efsys_mem_t *esmp);
557
558extern	__checkReturn			efx_rc_t
559efx_mac_stats_periodic(
560	__in				efx_nic_t *enp,
561	__in				efsys_mem_t *esmp,
562	__in				uint16_t period_ms,
563	__in				boolean_t events);
564
565extern	__checkReturn			efx_rc_t
566efx_mac_stats_update(
567	__in				efx_nic_t *enp,
568	__in				efsys_mem_t *esmp,
569	__inout_ecount(EFX_MAC_NSTATS)	efsys_stat_t *stat,
570	__inout_opt			uint32_t *generationp);
571
572#endif	/* EFSYS_OPT_MAC_STATS */
573
574/* MON */
575
576typedef enum efx_mon_type_e {
577	EFX_MON_INVALID = 0,
578	EFX_MON_SFC90X0,
579	EFX_MON_SFC91X0,
580	EFX_MON_SFC92X0,
581	EFX_MON_NTYPES
582} efx_mon_type_t;
583
584#if EFSYS_OPT_NAMES
585
586extern		const char *
587efx_mon_name(
588	__in	efx_nic_t *enp);
589
590#endif	/* EFSYS_OPT_NAMES */
591
592extern	__checkReturn	efx_rc_t
593efx_mon_init(
594	__in		efx_nic_t *enp);
595
596#if EFSYS_OPT_MON_STATS
597
598#define	EFX_MON_STATS_PAGE_SIZE 0x100
599#define	EFX_MON_MASK_ELEMENT_SIZE 32
600
601/* START MKCONFIG GENERATED MonitorHeaderStatsBlock 5d4ee5185e419abe */
602typedef enum efx_mon_stat_e {
603	EFX_MON_STAT_2_5V,
604	EFX_MON_STAT_VCCP1,
605	EFX_MON_STAT_VCC,
606	EFX_MON_STAT_5V,
607	EFX_MON_STAT_12V,
608	EFX_MON_STAT_VCCP2,
609	EFX_MON_STAT_EXT_TEMP,
610	EFX_MON_STAT_INT_TEMP,
611	EFX_MON_STAT_AIN1,
612	EFX_MON_STAT_AIN2,
613	EFX_MON_STAT_INT_COOLING,
614	EFX_MON_STAT_EXT_COOLING,
615	EFX_MON_STAT_1V,
616	EFX_MON_STAT_1_2V,
617	EFX_MON_STAT_1_8V,
618	EFX_MON_STAT_3_3V,
619	EFX_MON_STAT_1_2VA,
620	EFX_MON_STAT_VREF,
621	EFX_MON_STAT_VAOE,
622	EFX_MON_STAT_AOE_TEMP,
623	EFX_MON_STAT_PSU_AOE_TEMP,
624	EFX_MON_STAT_PSU_TEMP,
625	EFX_MON_STAT_FAN0,
626	EFX_MON_STAT_FAN1,
627	EFX_MON_STAT_FAN2,
628	EFX_MON_STAT_FAN3,
629	EFX_MON_STAT_FAN4,
630	EFX_MON_STAT_VAOE_IN,
631	EFX_MON_STAT_IAOE,
632	EFX_MON_STAT_IAOE_IN,
633	EFX_MON_STAT_NIC_POWER,
634	EFX_MON_STAT_0_9V,
635	EFX_MON_STAT_I0_9V,
636	EFX_MON_STAT_I1_2V,
637	EFX_MON_STAT_0_9V_ADC,
638	EFX_MON_STAT_INT_TEMP2,
639	EFX_MON_STAT_VREG_TEMP,
640	EFX_MON_STAT_VREG_0_9V_TEMP,
641	EFX_MON_STAT_VREG_1_2V_TEMP,
642	EFX_MON_STAT_INT_VPTAT,
643	EFX_MON_STAT_INT_ADC_TEMP,
644	EFX_MON_STAT_EXT_VPTAT,
645	EFX_MON_STAT_EXT_ADC_TEMP,
646	EFX_MON_STAT_AMBIENT_TEMP,
647	EFX_MON_STAT_AIRFLOW,
648	EFX_MON_STAT_VDD08D_VSS08D_CSR,
649	EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC,
650	EFX_MON_STAT_HOTPOINT_TEMP,
651	EFX_MON_STAT_PHY_POWER_SWITCH_PORT0,
652	EFX_MON_STAT_PHY_POWER_SWITCH_PORT1,
653	EFX_MON_STAT_MUM_VCC,
654	EFX_MON_STAT_0V9_A,
655	EFX_MON_STAT_I0V9_A,
656	EFX_MON_STAT_0V9_A_TEMP,
657	EFX_MON_STAT_0V9_B,
658	EFX_MON_STAT_I0V9_B,
659	EFX_MON_STAT_0V9_B_TEMP,
660	EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY,
661	EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXT_ADC,
662	EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY,
663	EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXT_ADC,
664	EFX_MON_STAT_CONTROLLER_MASTER_VPTAT,
665	EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP,
666	EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXT_ADC,
667	EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXT_ADC,
668	EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT,
669	EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP,
670	EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXT_ADC,
671	EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXT_ADC,
672	EFX_MON_STAT_SODIMM_VOUT,
673	EFX_MON_STAT_SODIMM_0_TEMP,
674	EFX_MON_STAT_SODIMM_1_TEMP,
675	EFX_MON_STAT_PHY0_VCC,
676	EFX_MON_STAT_PHY1_VCC,
677	EFX_MON_STAT_CONTROLLER_TDIODE_TEMP,
678	EFX_MON_STAT_BOARD_FRONT_TEMP,
679	EFX_MON_STAT_BOARD_BACK_TEMP,
680	EFX_MON_NSTATS
681} efx_mon_stat_t;
682
683/* END MKCONFIG GENERATED MonitorHeaderStatsBlock */
684
685typedef enum efx_mon_stat_state_e {
686	EFX_MON_STAT_STATE_OK = 0,
687	EFX_MON_STAT_STATE_WARNING = 1,
688	EFX_MON_STAT_STATE_FATAL = 2,
689	EFX_MON_STAT_STATE_BROKEN = 3,
690	EFX_MON_STAT_STATE_NO_READING = 4,
691} efx_mon_stat_state_t;
692
693typedef struct efx_mon_stat_value_s {
694	uint16_t	emsv_value;
695	uint16_t	emsv_state;
696} efx_mon_stat_value_t;
697
698#if EFSYS_OPT_NAMES
699
700extern					const char *
701efx_mon_stat_name(
702	__in				efx_nic_t *enp,
703	__in				efx_mon_stat_t id);
704
705#endif	/* EFSYS_OPT_NAMES */
706
707extern	__checkReturn			efx_rc_t
708efx_mon_stats_update(
709	__in				efx_nic_t *enp,
710	__in				efsys_mem_t *esmp,
711	__inout_ecount(EFX_MON_NSTATS)	efx_mon_stat_value_t *values);
712
713#endif	/* EFSYS_OPT_MON_STATS */
714
715extern		void
716efx_mon_fini(
717	__in	efx_nic_t *enp);
718
719/* PHY */
720
721extern	__checkReturn	efx_rc_t
722efx_phy_verify(
723	__in		efx_nic_t *enp);
724
725#if EFSYS_OPT_PHY_LED_CONTROL
726
727typedef enum efx_phy_led_mode_e {
728	EFX_PHY_LED_DEFAULT = 0,
729	EFX_PHY_LED_OFF,
730	EFX_PHY_LED_ON,
731	EFX_PHY_LED_FLASH,
732	EFX_PHY_LED_NMODES
733} efx_phy_led_mode_t;
734
735extern	__checkReturn	efx_rc_t
736efx_phy_led_set(
737	__in	efx_nic_t *enp,
738	__in	efx_phy_led_mode_t mode);
739
740#endif	/* EFSYS_OPT_PHY_LED_CONTROL */
741
742extern	__checkReturn	efx_rc_t
743efx_port_init(
744	__in		efx_nic_t *enp);
745
746#if EFSYS_OPT_LOOPBACK
747
748typedef enum efx_loopback_type_e {
749	EFX_LOOPBACK_OFF = 0,
750	EFX_LOOPBACK_DATA = 1,
751	EFX_LOOPBACK_GMAC = 2,
752	EFX_LOOPBACK_XGMII = 3,
753	EFX_LOOPBACK_XGXS = 4,
754	EFX_LOOPBACK_XAUI = 5,
755	EFX_LOOPBACK_GMII = 6,
756	EFX_LOOPBACK_SGMII = 7,
757	EFX_LOOPBACK_XGBR = 8,
758	EFX_LOOPBACK_XFI = 9,
759	EFX_LOOPBACK_XAUI_FAR = 10,
760	EFX_LOOPBACK_GMII_FAR = 11,
761	EFX_LOOPBACK_SGMII_FAR = 12,
762	EFX_LOOPBACK_XFI_FAR = 13,
763	EFX_LOOPBACK_GPHY = 14,
764	EFX_LOOPBACK_PHY_XS = 15,
765	EFX_LOOPBACK_PCS = 16,
766	EFX_LOOPBACK_PMA_PMD = 17,
767	EFX_LOOPBACK_XPORT = 18,
768	EFX_LOOPBACK_XGMII_WS = 19,
769	EFX_LOOPBACK_XAUI_WS = 20,
770	EFX_LOOPBACK_XAUI_WS_FAR = 21,
771	EFX_LOOPBACK_XAUI_WS_NEAR = 22,
772	EFX_LOOPBACK_GMII_WS = 23,
773	EFX_LOOPBACK_XFI_WS = 24,
774	EFX_LOOPBACK_XFI_WS_FAR = 25,
775	EFX_LOOPBACK_PHYXS_WS = 26,
776	EFX_LOOPBACK_PMA_INT = 27,
777	EFX_LOOPBACK_SD_NEAR = 28,
778	EFX_LOOPBACK_SD_FAR = 29,
779	EFX_LOOPBACK_PMA_INT_WS = 30,
780	EFX_LOOPBACK_SD_FEP2_WS = 31,
781	EFX_LOOPBACK_SD_FEP1_5_WS = 32,
782	EFX_LOOPBACK_SD_FEP_WS = 33,
783	EFX_LOOPBACK_SD_FES_WS = 34,
784	EFX_LOOPBACK_NTYPES
785} efx_loopback_type_t;
786
787typedef enum efx_loopback_kind_e {
788	EFX_LOOPBACK_KIND_OFF = 0,
789	EFX_LOOPBACK_KIND_ALL,
790	EFX_LOOPBACK_KIND_MAC,
791	EFX_LOOPBACK_KIND_PHY,
792	EFX_LOOPBACK_NKINDS
793} efx_loopback_kind_t;
794
795extern			void
796efx_loopback_mask(
797	__in	efx_loopback_kind_t loopback_kind,
798	__out	efx_qword_t *maskp);
799
800extern	__checkReturn	efx_rc_t
801efx_port_loopback_set(
802	__in	efx_nic_t *enp,
803	__in	efx_link_mode_t link_mode,
804	__in	efx_loopback_type_t type);
805
806#if EFSYS_OPT_NAMES
807
808extern	__checkReturn	const char *
809efx_loopback_type_name(
810	__in		efx_nic_t *enp,
811	__in		efx_loopback_type_t type);
812
813#endif	/* EFSYS_OPT_NAMES */
814
815#endif	/* EFSYS_OPT_LOOPBACK */
816
817extern	__checkReturn	efx_rc_t
818efx_port_poll(
819	__in		efx_nic_t *enp,
820	__out_opt	efx_link_mode_t	*link_modep);
821
822extern		void
823efx_port_fini(
824	__in	efx_nic_t *enp);
825
826typedef enum efx_phy_cap_type_e {
827	EFX_PHY_CAP_INVALID = 0,
828	EFX_PHY_CAP_10HDX,
829	EFX_PHY_CAP_10FDX,
830	EFX_PHY_CAP_100HDX,
831	EFX_PHY_CAP_100FDX,
832	EFX_PHY_CAP_1000HDX,
833	EFX_PHY_CAP_1000FDX,
834	EFX_PHY_CAP_10000FDX,
835	EFX_PHY_CAP_PAUSE,
836	EFX_PHY_CAP_ASYM,
837	EFX_PHY_CAP_AN,
838	EFX_PHY_CAP_40000FDX,
839	EFX_PHY_CAP_NTYPES
840} efx_phy_cap_type_t;
841
842
843#define	EFX_PHY_CAP_CURRENT	0x00000000
844#define	EFX_PHY_CAP_DEFAULT	0x00000001
845#define	EFX_PHY_CAP_PERM	0x00000002
846
847extern		void
848efx_phy_adv_cap_get(
849	__in		efx_nic_t *enp,
850	__in		uint32_t flag,
851	__out		uint32_t *maskp);
852
853extern	__checkReturn	efx_rc_t
854efx_phy_adv_cap_set(
855	__in		efx_nic_t *enp,
856	__in		uint32_t mask);
857
858extern			void
859efx_phy_lp_cap_get(
860	__in		efx_nic_t *enp,
861	__out		uint32_t *maskp);
862
863extern	__checkReturn	efx_rc_t
864efx_phy_oui_get(
865	__in		efx_nic_t *enp,
866	__out		uint32_t *ouip);
867
868typedef enum efx_phy_media_type_e {
869	EFX_PHY_MEDIA_INVALID = 0,
870	EFX_PHY_MEDIA_XAUI,
871	EFX_PHY_MEDIA_CX4,
872	EFX_PHY_MEDIA_KX4,
873	EFX_PHY_MEDIA_XFP,
874	EFX_PHY_MEDIA_SFP_PLUS,
875	EFX_PHY_MEDIA_BASE_T,
876	EFX_PHY_MEDIA_QSFP_PLUS,
877	EFX_PHY_MEDIA_NTYPES
878} efx_phy_media_type_t;
879
880/* Get the type of medium currently used.  If the board has ports for
881 * modules, a module is present, and we recognise the media type of
882 * the module, then this will be the media type of the module.
883 * Otherwise it will be the media type of the port.
884 */
885extern			void
886efx_phy_media_type_get(
887	__in		efx_nic_t *enp,
888	__out		efx_phy_media_type_t *typep);
889
890extern					efx_rc_t
891efx_phy_module_get_info(
892	__in				efx_nic_t *enp,
893	__in				uint8_t dev_addr,
894	__in				uint8_t offset,
895	__in				uint8_t len,
896	__out_bcount(len)		uint8_t *data);
897
898#if EFSYS_OPT_PHY_STATS
899
900/* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */
901typedef enum efx_phy_stat_e {
902	EFX_PHY_STAT_OUI,
903	EFX_PHY_STAT_PMA_PMD_LINK_UP,
904	EFX_PHY_STAT_PMA_PMD_RX_FAULT,
905	EFX_PHY_STAT_PMA_PMD_TX_FAULT,
906	EFX_PHY_STAT_PMA_PMD_REV_A,
907	EFX_PHY_STAT_PMA_PMD_REV_B,
908	EFX_PHY_STAT_PMA_PMD_REV_C,
909	EFX_PHY_STAT_PMA_PMD_REV_D,
910	EFX_PHY_STAT_PCS_LINK_UP,
911	EFX_PHY_STAT_PCS_RX_FAULT,
912	EFX_PHY_STAT_PCS_TX_FAULT,
913	EFX_PHY_STAT_PCS_BER,
914	EFX_PHY_STAT_PCS_BLOCK_ERRORS,
915	EFX_PHY_STAT_PHY_XS_LINK_UP,
916	EFX_PHY_STAT_PHY_XS_RX_FAULT,
917	EFX_PHY_STAT_PHY_XS_TX_FAULT,
918	EFX_PHY_STAT_PHY_XS_ALIGN,
919	EFX_PHY_STAT_PHY_XS_SYNC_A,
920	EFX_PHY_STAT_PHY_XS_SYNC_B,
921	EFX_PHY_STAT_PHY_XS_SYNC_C,
922	EFX_PHY_STAT_PHY_XS_SYNC_D,
923	EFX_PHY_STAT_AN_LINK_UP,
924	EFX_PHY_STAT_AN_MASTER,
925	EFX_PHY_STAT_AN_LOCAL_RX_OK,
926	EFX_PHY_STAT_AN_REMOTE_RX_OK,
927	EFX_PHY_STAT_CL22EXT_LINK_UP,
928	EFX_PHY_STAT_SNR_A,
929	EFX_PHY_STAT_SNR_B,
930	EFX_PHY_STAT_SNR_C,
931	EFX_PHY_STAT_SNR_D,
932	EFX_PHY_STAT_PMA_PMD_SIGNAL_A,
933	EFX_PHY_STAT_PMA_PMD_SIGNAL_B,
934	EFX_PHY_STAT_PMA_PMD_SIGNAL_C,
935	EFX_PHY_STAT_PMA_PMD_SIGNAL_D,
936	EFX_PHY_STAT_AN_COMPLETE,
937	EFX_PHY_STAT_PMA_PMD_REV_MAJOR,
938	EFX_PHY_STAT_PMA_PMD_REV_MINOR,
939	EFX_PHY_STAT_PMA_PMD_REV_MICRO,
940	EFX_PHY_STAT_PCS_FW_VERSION_0,
941	EFX_PHY_STAT_PCS_FW_VERSION_1,
942	EFX_PHY_STAT_PCS_FW_VERSION_2,
943	EFX_PHY_STAT_PCS_FW_VERSION_3,
944	EFX_PHY_STAT_PCS_FW_BUILD_YY,
945	EFX_PHY_STAT_PCS_FW_BUILD_MM,
946	EFX_PHY_STAT_PCS_FW_BUILD_DD,
947	EFX_PHY_STAT_PCS_OP_MODE,
948	EFX_PHY_NSTATS
949} efx_phy_stat_t;
950
951/* END MKCONFIG GENERATED PhyHeaderStatsBlock */
952
953#if EFSYS_OPT_NAMES
954
955extern					const char *
956efx_phy_stat_name(
957	__in				efx_nic_t *enp,
958	__in				efx_phy_stat_t stat);
959
960#endif	/* EFSYS_OPT_NAMES */
961
962#define	EFX_PHY_STATS_SIZE 0x100
963
964extern	__checkReturn			efx_rc_t
965efx_phy_stats_update(
966	__in				efx_nic_t *enp,
967	__in				efsys_mem_t *esmp,
968	__inout_ecount(EFX_PHY_NSTATS)	uint32_t *stat);
969
970#endif	/* EFSYS_OPT_PHY_STATS */
971
972
973#if EFSYS_OPT_BIST
974
975typedef enum efx_bist_type_e {
976	EFX_BIST_TYPE_UNKNOWN,
977	EFX_BIST_TYPE_PHY_NORMAL,
978	EFX_BIST_TYPE_PHY_CABLE_SHORT,
979	EFX_BIST_TYPE_PHY_CABLE_LONG,
980	EFX_BIST_TYPE_MC_MEM,	/* Test the MC DMEM and IMEM */
981	EFX_BIST_TYPE_SAT_MEM,	/* Test the DMEM and IMEM of satellite cpus*/
982	EFX_BIST_TYPE_REG,	/* Test the register memories */
983	EFX_BIST_TYPE_NTYPES,
984} efx_bist_type_t;
985
986typedef enum efx_bist_result_e {
987	EFX_BIST_RESULT_UNKNOWN,
988	EFX_BIST_RESULT_RUNNING,
989	EFX_BIST_RESULT_PASSED,
990	EFX_BIST_RESULT_FAILED,
991} efx_bist_result_t;
992
993typedef enum efx_phy_cable_status_e {
994	EFX_PHY_CABLE_STATUS_OK,
995	EFX_PHY_CABLE_STATUS_INVALID,
996	EFX_PHY_CABLE_STATUS_OPEN,
997	EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT,
998	EFX_PHY_CABLE_STATUS_INTERPAIRSHORT,
999	EFX_PHY_CABLE_STATUS_BUSY,
1000} efx_phy_cable_status_t;
1001
1002typedef enum efx_bist_value_e {
1003	EFX_BIST_PHY_CABLE_LENGTH_A,
1004	EFX_BIST_PHY_CABLE_LENGTH_B,
1005	EFX_BIST_PHY_CABLE_LENGTH_C,
1006	EFX_BIST_PHY_CABLE_LENGTH_D,
1007	EFX_BIST_PHY_CABLE_STATUS_A,
1008	EFX_BIST_PHY_CABLE_STATUS_B,
1009	EFX_BIST_PHY_CABLE_STATUS_C,
1010	EFX_BIST_PHY_CABLE_STATUS_D,
1011	EFX_BIST_FAULT_CODE,
1012	/* Memory BIST specific values. These match to the MC_CMD_BIST_POLL
1013	 * response. */
1014	EFX_BIST_MEM_TEST,
1015	EFX_BIST_MEM_ADDR,
1016	EFX_BIST_MEM_BUS,
1017	EFX_BIST_MEM_EXPECT,
1018	EFX_BIST_MEM_ACTUAL,
1019	EFX_BIST_MEM_ECC,
1020	EFX_BIST_MEM_ECC_PARITY,
1021	EFX_BIST_MEM_ECC_FATAL,
1022	EFX_BIST_NVALUES,
1023} efx_bist_value_t;
1024
1025extern	__checkReturn		efx_rc_t
1026efx_bist_enable_offline(
1027	__in			efx_nic_t *enp);
1028
1029extern	__checkReturn		efx_rc_t
1030efx_bist_start(
1031	__in			efx_nic_t *enp,
1032	__in			efx_bist_type_t type);
1033
1034extern	__checkReturn		efx_rc_t
1035efx_bist_poll(
1036	__in			efx_nic_t *enp,
1037	__in			efx_bist_type_t type,
1038	__out			efx_bist_result_t *resultp,
1039	__out_opt		uint32_t *value_maskp,
1040	__out_ecount_opt(count)	unsigned long *valuesp,
1041	__in			size_t count);
1042
1043extern				void
1044efx_bist_stop(
1045	__in			efx_nic_t *enp,
1046	__in			efx_bist_type_t type);
1047
1048#endif	/* EFSYS_OPT_BIST */
1049
1050#define	EFX_FEATURE_IPV6		0x00000001
1051#define	EFX_FEATURE_LFSR_HASH_INSERT	0x00000002
1052#define	EFX_FEATURE_LINK_EVENTS		0x00000004
1053#define	EFX_FEATURE_PERIODIC_MAC_STATS	0x00000008
1054#define	EFX_FEATURE_WOL			0x00000010
1055#define	EFX_FEATURE_MCDI		0x00000020
1056#define	EFX_FEATURE_LOOKAHEAD_SPLIT	0x00000040
1057#define	EFX_FEATURE_MAC_HEADER_FILTERS	0x00000080
1058#define	EFX_FEATURE_TURBO		0x00000100
1059#define	EFX_FEATURE_MCDI_DMA		0x00000200
1060#define	EFX_FEATURE_TX_SRC_FILTERS	0x00000400
1061#define	EFX_FEATURE_PIO_BUFFERS		0x00000800
1062#define	EFX_FEATURE_FW_ASSISTED_TSO	0x00001000
1063#define	EFX_FEATURE_FW_ASSISTED_TSO_V2	0x00002000
1064
1065typedef struct efx_nic_cfg_s {
1066	uint32_t		enc_board_type;
1067	uint32_t		enc_phy_type;
1068#if EFSYS_OPT_NAMES
1069	char			enc_phy_name[21];
1070#endif
1071	char			enc_phy_revision[21];
1072	efx_mon_type_t		enc_mon_type;
1073#if EFSYS_OPT_MON_STATS
1074	uint32_t		enc_mon_stat_dma_buf_size;
1075	uint32_t		enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32];
1076#endif
1077	unsigned int		enc_features;
1078	uint8_t			enc_mac_addr[6];
1079	uint8_t			enc_port;	/* PHY port number */
1080	uint32_t		enc_func_flags;
1081	uint32_t		enc_intr_vec_base;
1082	uint32_t		enc_intr_limit;
1083	uint32_t		enc_evq_limit;
1084	uint32_t		enc_txq_limit;
1085	uint32_t		enc_rxq_limit;
1086	uint32_t		enc_buftbl_limit;
1087	uint32_t		enc_piobuf_limit;
1088	uint32_t		enc_piobuf_size;
1089	uint32_t		enc_piobuf_min_alloc_size;
1090	uint32_t		enc_evq_timer_quantum_ns;
1091	uint32_t		enc_evq_timer_max_us;
1092	uint32_t		enc_clk_mult;
1093	uint32_t		enc_rx_prefix_size;
1094	uint32_t		enc_rx_buf_align_start;
1095	uint32_t		enc_rx_buf_align_end;
1096#if EFSYS_OPT_LOOPBACK
1097	efx_qword_t		enc_loopback_types[EFX_LINK_NMODES];
1098#endif	/* EFSYS_OPT_LOOPBACK */
1099#if EFSYS_OPT_PHY_FLAGS
1100	uint32_t		enc_phy_flags_mask;
1101#endif	/* EFSYS_OPT_PHY_FLAGS */
1102#if EFSYS_OPT_PHY_LED_CONTROL
1103	uint32_t		enc_led_mask;
1104#endif	/* EFSYS_OPT_PHY_LED_CONTROL */
1105#if EFSYS_OPT_PHY_STATS
1106	uint64_t		enc_phy_stat_mask;
1107#endif	/* EFSYS_OPT_PHY_STATS */
1108#if EFSYS_OPT_SIENA
1109	uint8_t			enc_mcdi_mdio_channel;
1110#if EFSYS_OPT_PHY_STATS
1111	uint32_t		enc_mcdi_phy_stat_mask;
1112#endif	/* EFSYS_OPT_PHY_STATS */
1113#endif /* EFSYS_OPT_SIENA */
1114#if (EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
1115#if EFSYS_OPT_MON_STATS
1116	uint32_t		*enc_mcdi_sensor_maskp;
1117	uint32_t		enc_mcdi_sensor_mask_size;
1118#endif	/* EFSYS_OPT_MON_STATS */
1119#endif	/* (EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
1120#if EFSYS_OPT_BIST
1121	uint32_t		enc_bist_mask;
1122#endif	/* EFSYS_OPT_BIST */
1123#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
1124	uint32_t		enc_pf;
1125	uint32_t		enc_vf;
1126	uint32_t		enc_privilege_mask;
1127#endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
1128	boolean_t		enc_bug26807_workaround;
1129	boolean_t		enc_bug35388_workaround;
1130	boolean_t		enc_bug41750_workaround;
1131	boolean_t		enc_bug61265_workaround;
1132	boolean_t		enc_rx_batching_enabled;
1133	/* Maximum number of descriptors completed in an rx event. */
1134	uint32_t		enc_rx_batch_max;
1135	/* Number of rx descriptors the hardware requires for a push. */
1136	uint32_t		enc_rx_push_align;
1137	/*
1138	 * Maximum number of bytes into the packet the TCP header can start for
1139	 * the hardware to apply TSO packet edits.
1140	 */
1141	uint32_t		enc_tx_tso_tcp_header_offset_limit;
1142	boolean_t		enc_fw_assisted_tso_enabled;
1143	boolean_t		enc_fw_assisted_tso_v2_enabled;
1144	boolean_t		enc_hw_tx_insert_vlan_enabled;
1145	/* Datapath firmware vadapter/vport/vswitch support */
1146	boolean_t		enc_datapath_cap_evb;
1147	boolean_t		enc_rx_disable_scatter_supported;
1148	boolean_t		enc_allow_set_mac_with_installed_filters;
1149	boolean_t		enc_enhanced_set_mac_supported;
1150	boolean_t		enc_init_evq_v2_supported;
1151	/* External port identifier */
1152	uint8_t			enc_external_port;
1153	uint32_t		enc_mcdi_max_payload_length;
1154	/* VPD may be per-PF or global */
1155	boolean_t		enc_vpd_is_global;
1156	/* Minimum unidirectional bandwidth in Mb/s to max out all ports */
1157	uint32_t		enc_required_pcie_bandwidth_mbps;
1158	uint32_t		enc_max_pcie_link_gen;
1159} efx_nic_cfg_t;
1160
1161#define	EFX_PCI_FUNCTION_IS_PF(_encp)	((_encp)->enc_vf == 0xffff)
1162#define	EFX_PCI_FUNCTION_IS_VF(_encp)	((_encp)->enc_vf != 0xffff)
1163
1164#define	EFX_PCI_FUNCTION(_encp)	\
1165	(EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf)
1166
1167#define	EFX_PCI_VF_PARENT(_encp)	((_encp)->enc_pf)
1168
1169extern			const efx_nic_cfg_t *
1170efx_nic_cfg_get(
1171	__in		efx_nic_t *enp);
1172
1173/* Driver resource limits (minimum required/maximum usable). */
1174typedef struct efx_drv_limits_s {
1175	uint32_t	edl_min_evq_count;
1176	uint32_t	edl_max_evq_count;
1177
1178	uint32_t	edl_min_rxq_count;
1179	uint32_t	edl_max_rxq_count;
1180
1181	uint32_t	edl_min_txq_count;
1182	uint32_t	edl_max_txq_count;
1183
1184	/* PIO blocks (sub-allocated from piobuf) */
1185	uint32_t	edl_min_pio_alloc_size;
1186	uint32_t	edl_max_pio_alloc_count;
1187} efx_drv_limits_t;
1188
1189extern	__checkReturn	efx_rc_t
1190efx_nic_set_drv_limits(
1191	__inout		efx_nic_t *enp,
1192	__in		efx_drv_limits_t *edlp);
1193
1194typedef enum efx_nic_region_e {
1195	EFX_REGION_VI,			/* Memory BAR UC mapping */
1196	EFX_REGION_PIO_WRITE_VI,	/* Memory BAR WC mapping */
1197} efx_nic_region_t;
1198
1199extern	__checkReturn	efx_rc_t
1200efx_nic_get_bar_region(
1201	__in		efx_nic_t *enp,
1202	__in		efx_nic_region_t region,
1203	__out		uint32_t *offsetp,
1204	__out		size_t *sizep);
1205
1206extern	__checkReturn	efx_rc_t
1207efx_nic_get_vi_pool(
1208	__in		efx_nic_t *enp,
1209	__out		uint32_t *evq_countp,
1210	__out		uint32_t *rxq_countp,
1211	__out		uint32_t *txq_countp);
1212
1213
1214#if EFSYS_OPT_VPD
1215
1216typedef enum efx_vpd_tag_e {
1217	EFX_VPD_ID = 0x02,
1218	EFX_VPD_END = 0x0f,
1219	EFX_VPD_RO = 0x10,
1220	EFX_VPD_RW = 0x11,
1221} efx_vpd_tag_t;
1222
1223typedef uint16_t efx_vpd_keyword_t;
1224
1225typedef struct efx_vpd_value_s {
1226	efx_vpd_tag_t		evv_tag;
1227	efx_vpd_keyword_t	evv_keyword;
1228	uint8_t			evv_length;
1229	uint8_t			evv_value[0x100];
1230} efx_vpd_value_t;
1231
1232
1233#define	EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8))
1234
1235extern	__checkReturn		efx_rc_t
1236efx_vpd_init(
1237	__in			efx_nic_t *enp);
1238
1239extern	__checkReturn		efx_rc_t
1240efx_vpd_size(
1241	__in			efx_nic_t *enp,
1242	__out			size_t *sizep);
1243
1244extern	__checkReturn		efx_rc_t
1245efx_vpd_read(
1246	__in			efx_nic_t *enp,
1247	__out_bcount(size)	caddr_t data,
1248	__in			size_t size);
1249
1250extern	__checkReturn		efx_rc_t
1251efx_vpd_verify(
1252	__in			efx_nic_t *enp,
1253	__in_bcount(size)	caddr_t data,
1254	__in			size_t size);
1255
1256extern	__checkReturn		efx_rc_t
1257efx_vpd_reinit(
1258	__in			efx_nic_t *enp,
1259	__in_bcount(size)	caddr_t data,
1260	__in			size_t size);
1261
1262extern	__checkReturn		efx_rc_t
1263efx_vpd_get(
1264	__in			efx_nic_t *enp,
1265	__in_bcount(size)	caddr_t data,
1266	__in			size_t size,
1267	__inout			efx_vpd_value_t *evvp);
1268
1269extern	__checkReturn		efx_rc_t
1270efx_vpd_set(
1271	__in			efx_nic_t *enp,
1272	__inout_bcount(size)	caddr_t data,
1273	__in			size_t size,
1274	__in			efx_vpd_value_t *evvp);
1275
1276extern	__checkReturn		efx_rc_t
1277efx_vpd_next(
1278	__in			efx_nic_t *enp,
1279	__inout_bcount(size)	caddr_t data,
1280	__in			size_t size,
1281	__out			efx_vpd_value_t *evvp,
1282	__inout			unsigned int *contp);
1283
1284extern	__checkReturn		efx_rc_t
1285efx_vpd_write(
1286	__in			efx_nic_t *enp,
1287	__in_bcount(size)	caddr_t data,
1288	__in			size_t size);
1289
1290extern				void
1291efx_vpd_fini(
1292	__in			efx_nic_t *enp);
1293
1294#endif	/* EFSYS_OPT_VPD */
1295
1296/* NVRAM */
1297
1298#if EFSYS_OPT_NVRAM
1299
1300typedef enum efx_nvram_type_e {
1301	EFX_NVRAM_INVALID = 0,
1302	EFX_NVRAM_BOOTROM,
1303	EFX_NVRAM_BOOTROM_CFG,
1304	EFX_NVRAM_MC_FIRMWARE,
1305	EFX_NVRAM_MC_GOLDEN,
1306	EFX_NVRAM_PHY,
1307	EFX_NVRAM_NULLPHY,
1308	EFX_NVRAM_FPGA,
1309	EFX_NVRAM_FCFW,
1310	EFX_NVRAM_CPLD,
1311	EFX_NVRAM_FPGA_BACKUP,
1312	EFX_NVRAM_DYNAMIC_CFG,
1313	EFX_NVRAM_LICENSE,
1314	EFX_NVRAM_NTYPES,
1315} efx_nvram_type_t;
1316
1317extern	__checkReturn		efx_rc_t
1318efx_nvram_init(
1319	__in			efx_nic_t *enp);
1320
1321#if EFSYS_OPT_DIAG
1322
1323extern	__checkReturn		efx_rc_t
1324efx_nvram_test(
1325	__in			efx_nic_t *enp);
1326
1327#endif	/* EFSYS_OPT_DIAG */
1328
1329extern	__checkReturn		efx_rc_t
1330efx_nvram_size(
1331	__in			efx_nic_t *enp,
1332	__in			efx_nvram_type_t type,
1333	__out			size_t *sizep);
1334
1335extern	__checkReturn		efx_rc_t
1336efx_nvram_rw_start(
1337	__in			efx_nic_t *enp,
1338	__in			efx_nvram_type_t type,
1339	__out_opt		size_t *pref_chunkp);
1340
1341extern				void
1342efx_nvram_rw_finish(
1343	__in			efx_nic_t *enp,
1344	__in			efx_nvram_type_t type);
1345
1346extern	__checkReturn		efx_rc_t
1347efx_nvram_get_version(
1348	__in			efx_nic_t *enp,
1349	__in			efx_nvram_type_t type,
1350	__out			uint32_t *subtypep,
1351	__out_ecount(4)		uint16_t version[4]);
1352
1353extern	__checkReturn		efx_rc_t
1354efx_nvram_read_chunk(
1355	__in			efx_nic_t *enp,
1356	__in			efx_nvram_type_t type,
1357	__in			unsigned int offset,
1358	__out_bcount(size)	caddr_t data,
1359	__in			size_t size);
1360
1361extern	__checkReturn		efx_rc_t
1362efx_nvram_set_version(
1363	__in			efx_nic_t *enp,
1364	__in			efx_nvram_type_t type,
1365	__in_ecount(4)		uint16_t version[4]);
1366
1367extern	__checkReturn		efx_rc_t
1368efx_nvram_validate(
1369	__in			efx_nic_t *enp,
1370	__in			efx_nvram_type_t type,
1371	__in_bcount(partn_size)	caddr_t partn_data,
1372	__in			size_t partn_size);
1373
1374extern	 __checkReturn		efx_rc_t
1375efx_nvram_erase(
1376	__in			efx_nic_t *enp,
1377	__in			efx_nvram_type_t type);
1378
1379extern	__checkReturn		efx_rc_t
1380efx_nvram_write_chunk(
1381	__in			efx_nic_t *enp,
1382	__in			efx_nvram_type_t type,
1383	__in			unsigned int offset,
1384	__in_bcount(size)	caddr_t data,
1385	__in			size_t size);
1386
1387extern				void
1388efx_nvram_fini(
1389	__in			efx_nic_t *enp);
1390
1391#endif	/* EFSYS_OPT_NVRAM */
1392
1393#if EFSYS_OPT_BOOTCFG
1394
1395extern				efx_rc_t
1396efx_bootcfg_read(
1397	__in			efx_nic_t *enp,
1398	__out_bcount(size)	caddr_t data,
1399	__in			size_t size);
1400
1401extern				efx_rc_t
1402efx_bootcfg_write(
1403	__in			efx_nic_t *enp,
1404	__in_bcount(size)	caddr_t data,
1405	__in			size_t size);
1406
1407#endif	/* EFSYS_OPT_BOOTCFG */
1408
1409#if EFSYS_OPT_WOL
1410
1411typedef enum efx_wol_type_e {
1412	EFX_WOL_TYPE_INVALID,
1413	EFX_WOL_TYPE_MAGIC,
1414	EFX_WOL_TYPE_BITMAP,
1415	EFX_WOL_TYPE_LINK,
1416	EFX_WOL_NTYPES,
1417} efx_wol_type_t;
1418
1419typedef enum efx_lightsout_offload_type_e {
1420	EFX_LIGHTSOUT_OFFLOAD_TYPE_INVALID,
1421	EFX_LIGHTSOUT_OFFLOAD_TYPE_ARP,
1422	EFX_LIGHTSOUT_OFFLOAD_TYPE_NS,
1423} efx_lightsout_offload_type_t;
1424
1425#define	EFX_WOL_BITMAP_MASK_SIZE    (48)
1426#define	EFX_WOL_BITMAP_VALUE_SIZE   (128)
1427
1428typedef union efx_wol_param_u {
1429	struct {
1430		uint8_t mac_addr[6];
1431	} ewp_magic;
1432	struct {
1433		uint8_t mask[EFX_WOL_BITMAP_MASK_SIZE];   /* 1 bit per byte */
1434		uint8_t value[EFX_WOL_BITMAP_VALUE_SIZE]; /* value to match */
1435		uint8_t value_len;
1436	} ewp_bitmap;
1437} efx_wol_param_t;
1438
1439typedef union efx_lightsout_offload_param_u {
1440	struct {
1441		uint8_t mac_addr[6];
1442		uint32_t ip;
1443	} elop_arp;
1444	struct {
1445		uint8_t mac_addr[6];
1446		uint32_t solicited_node[4];
1447		uint32_t ip[4];
1448	} elop_ns;
1449} efx_lightsout_offload_param_t;
1450
1451extern	__checkReturn	efx_rc_t
1452efx_wol_init(
1453	__in		efx_nic_t *enp);
1454
1455extern	__checkReturn	efx_rc_t
1456efx_wol_filter_clear(
1457	__in		efx_nic_t *enp);
1458
1459extern	__checkReturn	efx_rc_t
1460efx_wol_filter_add(
1461	__in		efx_nic_t *enp,
1462	__in		efx_wol_type_t type,
1463	__in		efx_wol_param_t *paramp,
1464	__out		uint32_t *filter_idp);
1465
1466extern	__checkReturn	efx_rc_t
1467efx_wol_filter_remove(
1468	__in		efx_nic_t *enp,
1469	__in		uint32_t filter_id);
1470
1471extern	__checkReturn	efx_rc_t
1472efx_lightsout_offload_add(
1473	__in		efx_nic_t *enp,
1474	__in		efx_lightsout_offload_type_t type,
1475	__in		efx_lightsout_offload_param_t *paramp,
1476	__out		uint32_t *filter_idp);
1477
1478extern	__checkReturn	efx_rc_t
1479efx_lightsout_offload_remove(
1480	__in		efx_nic_t *enp,
1481	__in		efx_lightsout_offload_type_t type,
1482	__in		uint32_t filter_id);
1483
1484extern			void
1485efx_wol_fini(
1486	__in		efx_nic_t *enp);
1487
1488#endif	/* EFSYS_OPT_WOL */
1489
1490#if EFSYS_OPT_DIAG
1491
1492typedef enum efx_pattern_type_t {
1493	EFX_PATTERN_BYTE_INCREMENT = 0,
1494	EFX_PATTERN_ALL_THE_SAME,
1495	EFX_PATTERN_BIT_ALTERNATE,
1496	EFX_PATTERN_BYTE_ALTERNATE,
1497	EFX_PATTERN_BYTE_CHANGING,
1498	EFX_PATTERN_BIT_SWEEP,
1499	EFX_PATTERN_NTYPES
1500} efx_pattern_type_t;
1501
1502typedef			void
1503(*efx_sram_pattern_fn_t)(
1504	__in		size_t row,
1505	__in		boolean_t negate,
1506	__out		efx_qword_t *eqp);
1507
1508extern	__checkReturn	efx_rc_t
1509efx_sram_test(
1510	__in		efx_nic_t *enp,
1511	__in		efx_pattern_type_t type);
1512
1513#endif	/* EFSYS_OPT_DIAG */
1514
1515extern	__checkReturn	efx_rc_t
1516efx_sram_buf_tbl_set(
1517	__in		efx_nic_t *enp,
1518	__in		uint32_t id,
1519	__in		efsys_mem_t *esmp,
1520	__in		size_t n);
1521
1522extern		void
1523efx_sram_buf_tbl_clear(
1524	__in	efx_nic_t *enp,
1525	__in	uint32_t id,
1526	__in	size_t n);
1527
1528#define	EFX_BUF_TBL_SIZE	0x20000
1529
1530#define	EFX_BUF_SIZE		4096
1531
1532/* EV */
1533
1534typedef struct efx_evq_s	efx_evq_t;
1535
1536#if EFSYS_OPT_QSTATS
1537
1538/* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 6f3843f5fe7cc843 */
1539typedef enum efx_ev_qstat_e {
1540	EV_ALL,
1541	EV_RX,
1542	EV_RX_OK,
1543	EV_RX_FRM_TRUNC,
1544	EV_RX_TOBE_DISC,
1545	EV_RX_PAUSE_FRM_ERR,
1546	EV_RX_BUF_OWNER_ID_ERR,
1547	EV_RX_IPV4_HDR_CHKSUM_ERR,
1548	EV_RX_TCP_UDP_CHKSUM_ERR,
1549	EV_RX_ETH_CRC_ERR,
1550	EV_RX_IP_FRAG_ERR,
1551	EV_RX_MCAST_PKT,
1552	EV_RX_MCAST_HASH_MATCH,
1553	EV_RX_TCP_IPV4,
1554	EV_RX_TCP_IPV6,
1555	EV_RX_UDP_IPV4,
1556	EV_RX_UDP_IPV6,
1557	EV_RX_OTHER_IPV4,
1558	EV_RX_OTHER_IPV6,
1559	EV_RX_NON_IP,
1560	EV_RX_BATCH,
1561	EV_TX,
1562	EV_TX_WQ_FF_FULL,
1563	EV_TX_PKT_ERR,
1564	EV_TX_PKT_TOO_BIG,
1565	EV_TX_UNEXPECTED,
1566	EV_GLOBAL,
1567	EV_GLOBAL_MNT,
1568	EV_DRIVER,
1569	EV_DRIVER_SRM_UPD_DONE,
1570	EV_DRIVER_TX_DESCQ_FLS_DONE,
1571	EV_DRIVER_RX_DESCQ_FLS_DONE,
1572	EV_DRIVER_RX_DESCQ_FLS_FAILED,
1573	EV_DRIVER_RX_DSC_ERROR,
1574	EV_DRIVER_TX_DSC_ERROR,
1575	EV_DRV_GEN,
1576	EV_MCDI_RESPONSE,
1577	EV_NQSTATS
1578} efx_ev_qstat_t;
1579
1580/* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */
1581
1582#endif	/* EFSYS_OPT_QSTATS */
1583
1584extern	__checkReturn	efx_rc_t
1585efx_ev_init(
1586	__in		efx_nic_t *enp);
1587
1588extern		void
1589efx_ev_fini(
1590	__in		efx_nic_t *enp);
1591
1592#define	EFX_EVQ_MAXNEVS		32768
1593#define	EFX_EVQ_MINNEVS		512
1594
1595#define	EFX_EVQ_SIZE(_nevs)	((_nevs) * sizeof (efx_qword_t))
1596#define	EFX_EVQ_NBUFS(_nevs)	(EFX_EVQ_SIZE(_nevs) / EFX_BUF_SIZE)
1597
1598extern	__checkReturn	efx_rc_t
1599efx_ev_qcreate(
1600	__in		efx_nic_t *enp,
1601	__in		unsigned int index,
1602	__in		efsys_mem_t *esmp,
1603	__in		size_t n,
1604	__in		uint32_t id,
1605	__in		uint32_t us,
1606	__deref_out	efx_evq_t **eepp);
1607
1608extern		void
1609efx_ev_qpost(
1610	__in		efx_evq_t *eep,
1611	__in		uint16_t data);
1612
1613typedef __checkReturn	boolean_t
1614(*efx_initialized_ev_t)(
1615	__in_opt	void *arg);
1616
1617#define	EFX_PKT_UNICAST		0x0004
1618#define	EFX_PKT_START		0x0008
1619
1620#define	EFX_PKT_VLAN_TAGGED	0x0010
1621#define	EFX_CKSUM_TCPUDP	0x0020
1622#define	EFX_CKSUM_IPV4		0x0040
1623#define	EFX_PKT_CONT		0x0080
1624
1625#define	EFX_CHECK_VLAN		0x0100
1626#define	EFX_PKT_TCP		0x0200
1627#define	EFX_PKT_UDP		0x0400
1628#define	EFX_PKT_IPV4		0x0800
1629
1630#define	EFX_PKT_IPV6		0x1000
1631#define	EFX_PKT_PREFIX_LEN	0x2000
1632#define	EFX_ADDR_MISMATCH	0x4000
1633#define	EFX_DISCARD		0x8000
1634
1635#define	EFX_EV_RX_NLABELS	32
1636#define	EFX_EV_TX_NLABELS	32
1637
1638typedef	__checkReturn	boolean_t
1639(*efx_rx_ev_t)(
1640	__in_opt	void *arg,
1641	__in		uint32_t label,
1642	__in		uint32_t id,
1643	__in		uint32_t size,
1644	__in		uint16_t flags);
1645
1646typedef	__checkReturn	boolean_t
1647(*efx_tx_ev_t)(
1648	__in_opt	void *arg,
1649	__in		uint32_t label,
1650	__in		uint32_t id);
1651
1652#define	EFX_EXCEPTION_RX_RECOVERY	0x00000001
1653#define	EFX_EXCEPTION_RX_DSC_ERROR	0x00000002
1654#define	EFX_EXCEPTION_TX_DSC_ERROR	0x00000003
1655#define	EFX_EXCEPTION_UNKNOWN_SENSOREVT	0x00000004
1656#define	EFX_EXCEPTION_FWALERT_SRAM	0x00000005
1657#define	EFX_EXCEPTION_UNKNOWN_FWALERT	0x00000006
1658#define	EFX_EXCEPTION_RX_ERROR		0x00000007
1659#define	EFX_EXCEPTION_TX_ERROR		0x00000008
1660#define	EFX_EXCEPTION_EV_ERROR		0x00000009
1661
1662typedef	__checkReturn	boolean_t
1663(*efx_exception_ev_t)(
1664	__in_opt	void *arg,
1665	__in		uint32_t label,
1666	__in		uint32_t data);
1667
1668typedef	__checkReturn	boolean_t
1669(*efx_rxq_flush_done_ev_t)(
1670	__in_opt	void *arg,
1671	__in		uint32_t rxq_index);
1672
1673typedef	__checkReturn	boolean_t
1674(*efx_rxq_flush_failed_ev_t)(
1675	__in_opt	void *arg,
1676	__in		uint32_t rxq_index);
1677
1678typedef	__checkReturn	boolean_t
1679(*efx_txq_flush_done_ev_t)(
1680	__in_opt	void *arg,
1681	__in		uint32_t txq_index);
1682
1683typedef	__checkReturn	boolean_t
1684(*efx_software_ev_t)(
1685	__in_opt	void *arg,
1686	__in		uint16_t magic);
1687
1688typedef	__checkReturn	boolean_t
1689(*efx_sram_ev_t)(
1690	__in_opt	void *arg,
1691	__in		uint32_t code);
1692
1693#define	EFX_SRAM_CLEAR		0
1694#define	EFX_SRAM_UPDATE		1
1695#define	EFX_SRAM_ILLEGAL_CLEAR	2
1696
1697typedef	__checkReturn	boolean_t
1698(*efx_wake_up_ev_t)(
1699	__in_opt	void *arg,
1700	__in		uint32_t label);
1701
1702typedef	__checkReturn	boolean_t
1703(*efx_timer_ev_t)(
1704	__in_opt	void *arg,
1705	__in		uint32_t label);
1706
1707typedef __checkReturn	boolean_t
1708(*efx_link_change_ev_t)(
1709	__in_opt	void *arg,
1710	__in		efx_link_mode_t	link_mode);
1711
1712#if EFSYS_OPT_MON_STATS
1713
1714typedef __checkReturn	boolean_t
1715(*efx_monitor_ev_t)(
1716	__in_opt	void *arg,
1717	__in		efx_mon_stat_t id,
1718	__in		efx_mon_stat_value_t value);
1719
1720#endif	/* EFSYS_OPT_MON_STATS */
1721
1722#if EFSYS_OPT_MAC_STATS
1723
1724typedef __checkReturn	boolean_t
1725(*efx_mac_stats_ev_t)(
1726	__in_opt	void *arg,
1727	__in		uint32_t generation
1728	);
1729
1730#endif	/* EFSYS_OPT_MAC_STATS */
1731
1732typedef struct efx_ev_callbacks_s {
1733	efx_initialized_ev_t		eec_initialized;
1734	efx_rx_ev_t			eec_rx;
1735	efx_tx_ev_t			eec_tx;
1736	efx_exception_ev_t		eec_exception;
1737	efx_rxq_flush_done_ev_t		eec_rxq_flush_done;
1738	efx_rxq_flush_failed_ev_t	eec_rxq_flush_failed;
1739	efx_txq_flush_done_ev_t		eec_txq_flush_done;
1740	efx_software_ev_t		eec_software;
1741	efx_sram_ev_t			eec_sram;
1742	efx_wake_up_ev_t		eec_wake_up;
1743	efx_timer_ev_t			eec_timer;
1744	efx_link_change_ev_t		eec_link_change;
1745#if EFSYS_OPT_MON_STATS
1746	efx_monitor_ev_t		eec_monitor;
1747#endif	/* EFSYS_OPT_MON_STATS */
1748#if EFSYS_OPT_MAC_STATS
1749	efx_mac_stats_ev_t		eec_mac_stats;
1750#endif	/* EFSYS_OPT_MAC_STATS */
1751} efx_ev_callbacks_t;
1752
1753extern	__checkReturn	boolean_t
1754efx_ev_qpending(
1755	__in		efx_evq_t *eep,
1756	__in		unsigned int count);
1757
1758#if EFSYS_OPT_EV_PREFETCH
1759
1760extern			void
1761efx_ev_qprefetch(
1762	__in		efx_evq_t *eep,
1763	__in		unsigned int count);
1764
1765#endif	/* EFSYS_OPT_EV_PREFETCH */
1766
1767extern			void
1768efx_ev_qpoll(
1769	__in		efx_evq_t *eep,
1770	__inout		unsigned int *countp,
1771	__in		const efx_ev_callbacks_t *eecp,
1772	__in_opt	void *arg);
1773
1774extern	__checkReturn	efx_rc_t
1775efx_ev_usecs_to_ticks(
1776	__in		efx_nic_t *enp,
1777	__in		unsigned int usecs,
1778	__out		unsigned int *ticksp);
1779
1780extern	__checkReturn	efx_rc_t
1781efx_ev_qmoderate(
1782	__in		efx_evq_t *eep,
1783	__in		unsigned int us);
1784
1785extern	__checkReturn	efx_rc_t
1786efx_ev_qprime(
1787	__in		efx_evq_t *eep,
1788	__in		unsigned int count);
1789
1790#if EFSYS_OPT_QSTATS
1791
1792#if EFSYS_OPT_NAMES
1793
1794extern		const char *
1795efx_ev_qstat_name(
1796	__in	efx_nic_t *enp,
1797	__in	unsigned int id);
1798
1799#endif	/* EFSYS_OPT_NAMES */
1800
1801extern					void
1802efx_ev_qstats_update(
1803	__in				efx_evq_t *eep,
1804	__inout_ecount(EV_NQSTATS)	efsys_stat_t *stat);
1805
1806#endif	/* EFSYS_OPT_QSTATS */
1807
1808extern		void
1809efx_ev_qdestroy(
1810	__in	efx_evq_t *eep);
1811
1812/* RX */
1813
1814extern	__checkReturn	efx_rc_t
1815efx_rx_init(
1816	__inout		efx_nic_t *enp);
1817
1818extern		void
1819efx_rx_fini(
1820	__in		efx_nic_t *enp);
1821
1822#if EFSYS_OPT_RX_SCATTER
1823	__checkReturn	efx_rc_t
1824efx_rx_scatter_enable(
1825	__in		efx_nic_t *enp,
1826	__in		unsigned int buf_size);
1827#endif	/* EFSYS_OPT_RX_SCATTER */
1828
1829#if EFSYS_OPT_RX_SCALE
1830
1831typedef enum efx_rx_hash_alg_e {
1832	EFX_RX_HASHALG_LFSR = 0,
1833	EFX_RX_HASHALG_TOEPLITZ
1834} efx_rx_hash_alg_t;
1835
1836typedef enum efx_rx_hash_type_e {
1837	EFX_RX_HASH_IPV4 = 0,
1838	EFX_RX_HASH_TCPIPV4,
1839	EFX_RX_HASH_IPV6,
1840	EFX_RX_HASH_TCPIPV6,
1841} efx_rx_hash_type_t;
1842
1843typedef enum efx_rx_hash_support_e {
1844	EFX_RX_HASH_UNAVAILABLE = 0,	/* Hardware hash not inserted */
1845	EFX_RX_HASH_AVAILABLE		/* Insert hash with/without RSS */
1846} efx_rx_hash_support_t;
1847
1848#define	EFX_RSS_TBL_SIZE	128	/* Rows in RX indirection table */
1849#define	EFX_MAXRSS		64	/* RX indirection entry range */
1850#define	EFX_MAXRSS_LEGACY	16	/* See bug16611 and bug17213 */
1851
1852typedef enum efx_rx_scale_support_e {
1853	EFX_RX_SCALE_UNAVAILABLE = 0,	/* Not supported */
1854	EFX_RX_SCALE_EXCLUSIVE,		/* Writable key/indirection table */
1855	EFX_RX_SCALE_SHARED		/* Read-only key/indirection table */
1856} efx_rx_scale_support_t;
1857
1858extern	__checkReturn	efx_rc_t
1859efx_rx_hash_support_get(
1860	__in		efx_nic_t *enp,
1861	__out		efx_rx_hash_support_t *supportp);
1862
1863
1864extern	__checkReturn	efx_rc_t
1865efx_rx_scale_support_get(
1866	__in		efx_nic_t *enp,
1867	__out		efx_rx_scale_support_t *supportp);
1868
1869extern	__checkReturn	efx_rc_t
1870efx_rx_scale_mode_set(
1871	__in	efx_nic_t *enp,
1872	__in	efx_rx_hash_alg_t alg,
1873	__in	efx_rx_hash_type_t type,
1874	__in	boolean_t insert);
1875
1876extern	__checkReturn	efx_rc_t
1877efx_rx_scale_tbl_set(
1878	__in		efx_nic_t *enp,
1879	__in_ecount(n)	unsigned int *table,
1880	__in		size_t n);
1881
1882extern	__checkReturn	efx_rc_t
1883efx_rx_scale_key_set(
1884	__in		efx_nic_t *enp,
1885	__in_ecount(n)	uint8_t *key,
1886	__in		size_t n);
1887
1888extern	__checkReturn	uint32_t
1889efx_psuedo_hdr_hash_get(
1890	__in		efx_nic_t *enp,
1891	__in		efx_rx_hash_alg_t func,
1892	__in		uint8_t *buffer);
1893
1894#endif	/* EFSYS_OPT_RX_SCALE */
1895
1896extern	__checkReturn	efx_rc_t
1897efx_psuedo_hdr_pkt_length_get(
1898	__in		efx_nic_t *enp,
1899	__in		uint8_t *buffer,
1900	__out		uint16_t *pkt_lengthp);
1901
1902#define	EFX_RXQ_MAXNDESCS		4096
1903#define	EFX_RXQ_MINNDESCS		512
1904
1905#define	EFX_RXQ_SIZE(_ndescs)		((_ndescs) * sizeof (efx_qword_t))
1906#define	EFX_RXQ_NBUFS(_ndescs)		(EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
1907#define	EFX_RXQ_LIMIT(_ndescs)		((_ndescs) - 16)
1908#define	EFX_RXQ_DC_NDESCS(_dcsize)	(8 << _dcsize)
1909
1910typedef enum efx_rxq_type_e {
1911	EFX_RXQ_TYPE_DEFAULT,
1912	EFX_RXQ_TYPE_SCATTER,
1913	EFX_RXQ_NTYPES
1914} efx_rxq_type_t;
1915
1916extern	__checkReturn	efx_rc_t
1917efx_rx_qcreate(
1918	__in		efx_nic_t *enp,
1919	__in		unsigned int index,
1920	__in		unsigned int label,
1921	__in		efx_rxq_type_t type,
1922	__in		efsys_mem_t *esmp,
1923	__in		size_t n,
1924	__in		uint32_t id,
1925	__in		efx_evq_t *eep,
1926	__deref_out	efx_rxq_t **erpp);
1927
1928typedef struct efx_buffer_s {
1929	efsys_dma_addr_t	eb_addr;
1930	size_t			eb_size;
1931	boolean_t		eb_eop;
1932} efx_buffer_t;
1933
1934typedef struct efx_desc_s {
1935	efx_qword_t ed_eq;
1936} efx_desc_t;
1937
1938extern			void
1939efx_rx_qpost(
1940	__in		efx_rxq_t *erp,
1941	__in_ecount(n)	efsys_dma_addr_t *addrp,
1942	__in		size_t size,
1943	__in		unsigned int n,
1944	__in		unsigned int completed,
1945	__in		unsigned int added);
1946
1947extern		void
1948efx_rx_qpush(
1949	__in	efx_rxq_t *erp,
1950	__in	unsigned int added,
1951	__inout	unsigned int *pushedp);
1952
1953extern	__checkReturn	efx_rc_t
1954efx_rx_qflush(
1955	__in	efx_rxq_t *erp);
1956
1957extern		void
1958efx_rx_qenable(
1959	__in	efx_rxq_t *erp);
1960
1961extern		void
1962efx_rx_qdestroy(
1963	__in	efx_rxq_t *erp);
1964
1965/* TX */
1966
1967typedef struct efx_txq_s	efx_txq_t;
1968
1969#if EFSYS_OPT_QSTATS
1970
1971/* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */
1972typedef enum efx_tx_qstat_e {
1973	TX_POST,
1974	TX_POST_PIO,
1975	TX_NQSTATS
1976} efx_tx_qstat_t;
1977
1978/* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */
1979
1980#endif	/* EFSYS_OPT_QSTATS */
1981
1982extern	__checkReturn	efx_rc_t
1983efx_tx_init(
1984	__in		efx_nic_t *enp);
1985
1986extern		void
1987efx_tx_fini(
1988	__in	efx_nic_t *enp);
1989
1990#define	EFX_BUG35388_WORKAROUND(_encp)					\
1991	(((_encp) == NULL) ? 1 : ((_encp)->enc_bug35388_workaround != 0))
1992
1993#define	EFX_TXQ_MAXNDESCS(_encp)					\
1994	((EFX_BUG35388_WORKAROUND(_encp)) ? 2048 : 4096)
1995
1996#define	EFX_TXQ_MINNDESCS		512
1997
1998#define	EFX_TXQ_SIZE(_ndescs)		((_ndescs) * sizeof (efx_qword_t))
1999#define	EFX_TXQ_NBUFS(_ndescs)		(EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
2000#define	EFX_TXQ_LIMIT(_ndescs)		((_ndescs) - 16)
2001#define	EFX_TXQ_DC_NDESCS(_dcsize)	(8 << _dcsize)
2002
2003#define	EFX_TXQ_MAX_BUFS 8 /* Maximum independent of EFX_BUG35388_WORKAROUND. */
2004
2005#define	EFX_TXQ_CKSUM_IPV4	0x0001
2006#define	EFX_TXQ_CKSUM_TCPUDP	0x0002
2007#define	EFX_TXQ_FATSOV2		0x0004
2008
2009extern	__checkReturn	efx_rc_t
2010efx_tx_qcreate(
2011	__in		efx_nic_t *enp,
2012	__in		unsigned int index,
2013	__in		unsigned int label,
2014	__in		efsys_mem_t *esmp,
2015	__in		size_t n,
2016	__in		uint32_t id,
2017	__in		uint16_t flags,
2018	__in		efx_evq_t *eep,
2019	__deref_out	efx_txq_t **etpp,
2020	__out		unsigned int *addedp);
2021
2022extern	__checkReturn	efx_rc_t
2023efx_tx_qpost(
2024	__in		efx_txq_t *etp,
2025	__in_ecount(n)	efx_buffer_t *eb,
2026	__in		unsigned int n,
2027	__in		unsigned int completed,
2028	__inout		unsigned int *addedp);
2029
2030extern	__checkReturn	efx_rc_t
2031efx_tx_qpace(
2032	__in		efx_txq_t *etp,
2033	__in		unsigned int ns);
2034
2035extern			void
2036efx_tx_qpush(
2037	__in		efx_txq_t *etp,
2038	__in		unsigned int added,
2039	__in		unsigned int pushed);
2040
2041extern	__checkReturn	efx_rc_t
2042efx_tx_qflush(
2043	__in		efx_txq_t *etp);
2044
2045extern			void
2046efx_tx_qenable(
2047	__in		efx_txq_t *etp);
2048
2049extern	__checkReturn	efx_rc_t
2050efx_tx_qpio_enable(
2051	__in		efx_txq_t *etp);
2052
2053extern			void
2054efx_tx_qpio_disable(
2055	__in		efx_txq_t *etp);
2056
2057extern	__checkReturn	efx_rc_t
2058efx_tx_qpio_write(
2059	__in			efx_txq_t *etp,
2060	__in_ecount(buf_length)	uint8_t *buffer,
2061	__in			size_t buf_length,
2062	__in			size_t pio_buf_offset);
2063
2064extern	__checkReturn	efx_rc_t
2065efx_tx_qpio_post(
2066	__in			efx_txq_t *etp,
2067	__in			size_t pkt_length,
2068	__in			unsigned int completed,
2069	__inout			unsigned int *addedp);
2070
2071extern	__checkReturn	efx_rc_t
2072efx_tx_qdesc_post(
2073	__in		efx_txq_t *etp,
2074	__in_ecount(n)	efx_desc_t *ed,
2075	__in		unsigned int n,
2076	__in		unsigned int completed,
2077	__inout		unsigned int *addedp);
2078
2079extern	void
2080efx_tx_qdesc_dma_create(
2081	__in	efx_txq_t *etp,
2082	__in	efsys_dma_addr_t addr,
2083	__in	size_t size,
2084	__in	boolean_t eop,
2085	__out	efx_desc_t *edp);
2086
2087extern	void
2088efx_tx_qdesc_tso_create(
2089	__in	efx_txq_t *etp,
2090	__in	uint16_t ipv4_id,
2091	__in	uint32_t tcp_seq,
2092	__in	uint8_t  tcp_flags,
2093	__out	efx_desc_t *edp);
2094
2095/* Number of FATSOv2 option descriptors */
2096#define	EFX_TX_FATSOV2_OPT_NDESCS		2
2097
2098/* Maximum number of DMA segments per TSO packet (not superframe) */
2099#define	EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX	24
2100
2101extern	void
2102efx_tx_qdesc_tso2_create(
2103	__in			efx_txq_t *etp,
2104	__in			uint16_t ipv4_id,
2105	__in			uint32_t tcp_seq,
2106	__in			uint16_t tcp_mss,
2107	__out_ecount(count)	efx_desc_t *edp,
2108	__in			int count);
2109
2110extern	void
2111efx_tx_qdesc_vlantci_create(
2112	__in	efx_txq_t *etp,
2113	__in	uint16_t tci,
2114	__out	efx_desc_t *edp);
2115
2116#if EFSYS_OPT_QSTATS
2117
2118#if EFSYS_OPT_NAMES
2119
2120extern		const char *
2121efx_tx_qstat_name(
2122	__in	efx_nic_t *etp,
2123	__in	unsigned int id);
2124
2125#endif	/* EFSYS_OPT_NAMES */
2126
2127extern					void
2128efx_tx_qstats_update(
2129	__in				efx_txq_t *etp,
2130	__inout_ecount(TX_NQSTATS)	efsys_stat_t *stat);
2131
2132#endif	/* EFSYS_OPT_QSTATS */
2133
2134extern		void
2135efx_tx_qdestroy(
2136	__in	efx_txq_t *etp);
2137
2138
2139/* FILTER */
2140
2141#if EFSYS_OPT_FILTER
2142
2143#define	EFX_ETHER_TYPE_IPV4 0x0800
2144#define	EFX_ETHER_TYPE_IPV6 0x86DD
2145
2146#define	EFX_IPPROTO_TCP 6
2147#define	EFX_IPPROTO_UDP 17
2148
2149typedef enum efx_filter_flag_e {
2150	EFX_FILTER_FLAG_RX_RSS = 0x01,		/* use RSS to spread across
2151						 * multiple queues */
2152	EFX_FILTER_FLAG_RX_SCATTER = 0x02,	/* enable RX scatter */
2153	EFX_FILTER_FLAG_RX_OVER_AUTO = 0x04,	/* Override an automatic filter
2154						 * (priority EFX_FILTER_PRI_AUTO).
2155						 * May only be set by the filter
2156						 * implementation for each type.
2157						 * A removal request will
2158						 * restore the automatic filter
2159						 * in its place. */
2160	EFX_FILTER_FLAG_RX = 0x08,		/* Filter is for RX */
2161	EFX_FILTER_FLAG_TX = 0x10,		/* Filter is for TX */
2162} efx_filter_flag_t;
2163
2164typedef enum efx_filter_match_flags_e {
2165	EFX_FILTER_MATCH_REM_HOST = 0x0001,	/* Match by remote IP host
2166						 * address */
2167	EFX_FILTER_MATCH_LOC_HOST = 0x0002,	/* Match by local IP host
2168						 * address */
2169	EFX_FILTER_MATCH_REM_MAC = 0x0004,	/* Match by remote MAC address */
2170	EFX_FILTER_MATCH_REM_PORT = 0x0008,	/* Match by remote TCP/UDP port */
2171	EFX_FILTER_MATCH_LOC_MAC = 0x0010,	/* Match by remote TCP/UDP port */
2172	EFX_FILTER_MATCH_LOC_PORT = 0x0020,	/* Match by local TCP/UDP port */
2173	EFX_FILTER_MATCH_ETHER_TYPE = 0x0040,	/* Match by Ether-type */
2174	EFX_FILTER_MATCH_INNER_VID = 0x0080,	/* Match by inner VLAN ID */
2175	EFX_FILTER_MATCH_OUTER_VID = 0x0100,	/* Match by outer VLAN ID */
2176	EFX_FILTER_MATCH_IP_PROTO = 0x0200,	/* Match by IP transport
2177						 * protocol */
2178	EFX_FILTER_MATCH_LOC_MAC_IG = 0x0400,	/* Match by local MAC address
2179						 * I/G bit. Used for RX default
2180						 * unicast and multicast/
2181						 * broadcast filters. */
2182} efx_filter_match_flags_t;
2183
2184typedef enum efx_filter_priority_s {
2185	EFX_FILTER_PRI_HINT = 0,	/* Performance hint */
2186	EFX_FILTER_PRI_AUTO,		/* Automatic filter based on device
2187					 * address list or hardware
2188					 * requirements. This may only be used
2189					 * by the filter implementation for
2190					 * each NIC type. */
2191	EFX_FILTER_PRI_MANUAL,		/* Manually configured filter */
2192	EFX_FILTER_PRI_REQUIRED,	/* Required for correct behaviour of the
2193					 * client (e.g. SR-IOV, HyperV VMQ etc.)
2194					 */
2195} efx_filter_priority_t;
2196
2197/*
2198 * FIXME: All these fields are assumed to be in little-endian byte order.
2199 * It may be better for some to be big-endian. See bug42804.
2200 */
2201
2202typedef struct efx_filter_spec_s {
2203	uint32_t	efs_match_flags:12;
2204	uint32_t	efs_priority:2;
2205	uint32_t	efs_flags:6;
2206	uint32_t	efs_dmaq_id:12;
2207	uint32_t	efs_rss_context;
2208	uint16_t	efs_outer_vid;
2209	uint16_t	efs_inner_vid;
2210	uint8_t		efs_loc_mac[EFX_MAC_ADDR_LEN];
2211	uint8_t		efs_rem_mac[EFX_MAC_ADDR_LEN];
2212	uint16_t	efs_ether_type;
2213	uint8_t		efs_ip_proto;
2214	uint16_t	efs_loc_port;
2215	uint16_t	efs_rem_port;
2216	efx_oword_t	efs_rem_host;
2217	efx_oword_t	efs_loc_host;
2218} efx_filter_spec_t;
2219
2220
2221/* Default values for use in filter specifications */
2222#define	EFX_FILTER_SPEC_RSS_CONTEXT_DEFAULT	0xffffffff
2223#define	EFX_FILTER_SPEC_RX_DMAQ_ID_DROP		0xfff
2224#define	EFX_FILTER_SPEC_VID_UNSPEC		0xffff
2225
2226extern	__checkReturn	efx_rc_t
2227efx_filter_init(
2228	__in		efx_nic_t *enp);
2229
2230extern			void
2231efx_filter_fini(
2232	__in		efx_nic_t *enp);
2233
2234extern	__checkReturn	efx_rc_t
2235efx_filter_insert(
2236	__in		efx_nic_t *enp,
2237	__inout		efx_filter_spec_t *spec);
2238
2239extern	__checkReturn	efx_rc_t
2240efx_filter_remove(
2241	__in		efx_nic_t *enp,
2242	__inout		efx_filter_spec_t *spec);
2243
2244extern	__checkReturn	efx_rc_t
2245efx_filter_restore(
2246	__in		efx_nic_t *enp);
2247
2248extern	__checkReturn	efx_rc_t
2249efx_filter_supported_filters(
2250	__in		efx_nic_t *enp,
2251	__out		uint32_t *list,
2252	__out		size_t *length);
2253
2254extern			void
2255efx_filter_spec_init_rx(
2256	__out		efx_filter_spec_t *spec,
2257	__in		efx_filter_priority_t priority,
2258	__in		efx_filter_flag_t flags,
2259	__in		efx_rxq_t *erp);
2260
2261extern			void
2262efx_filter_spec_init_tx(
2263	__out		efx_filter_spec_t *spec,
2264	__in		efx_txq_t *etp);
2265
2266extern	__checkReturn	efx_rc_t
2267efx_filter_spec_set_ipv4_local(
2268	__inout		efx_filter_spec_t *spec,
2269	__in		uint8_t proto,
2270	__in		uint32_t host,
2271	__in		uint16_t port);
2272
2273extern	__checkReturn	efx_rc_t
2274efx_filter_spec_set_ipv4_full(
2275	__inout		efx_filter_spec_t *spec,
2276	__in		uint8_t proto,
2277	__in		uint32_t lhost,
2278	__in		uint16_t lport,
2279	__in		uint32_t rhost,
2280	__in		uint16_t rport);
2281
2282extern	__checkReturn	efx_rc_t
2283efx_filter_spec_set_eth_local(
2284	__inout		efx_filter_spec_t *spec,
2285	__in		uint16_t vid,
2286	__in		const uint8_t *addr);
2287
2288extern	__checkReturn	efx_rc_t
2289efx_filter_spec_set_uc_def(
2290	__inout		efx_filter_spec_t *spec);
2291
2292extern	__checkReturn	efx_rc_t
2293efx_filter_spec_set_mc_def(
2294	__inout		efx_filter_spec_t *spec);
2295
2296#endif	/* EFSYS_OPT_FILTER */
2297
2298/* HASH */
2299
2300extern	__checkReturn		uint32_t
2301efx_hash_dwords(
2302	__in_ecount(count)	uint32_t const *input,
2303	__in			size_t count,
2304	__in			uint32_t init);
2305
2306extern	__checkReturn		uint32_t
2307efx_hash_bytes(
2308	__in_ecount(length)	uint8_t const *input,
2309	__in			size_t length,
2310	__in			uint32_t init);
2311
2312#if EFSYS_OPT_LICENSING
2313
2314/* LICENSING */
2315
2316typedef struct efx_key_stats_s {
2317	uint32_t	eks_valid;
2318	uint32_t	eks_invalid;
2319	uint32_t	eks_blacklisted;
2320	uint32_t	eks_unverifiable;
2321	uint32_t	eks_wrong_node;
2322	uint32_t	eks_licensed_apps_lo;
2323	uint32_t	eks_licensed_apps_hi;
2324	uint32_t	eks_licensed_features_lo;
2325	uint32_t	eks_licensed_features_hi;
2326} efx_key_stats_t;
2327
2328extern	__checkReturn		efx_rc_t
2329efx_lic_init(
2330	__in			efx_nic_t *enp);
2331
2332extern				void
2333efx_lic_fini(
2334	__in			efx_nic_t *enp);
2335
2336extern	__checkReturn	boolean_t
2337efx_lic_check_support(
2338	__in			efx_nic_t *enp);
2339
2340extern	__checkReturn	efx_rc_t
2341efx_lic_update_licenses(
2342	__in		efx_nic_t *enp);
2343
2344extern	__checkReturn	efx_rc_t
2345efx_lic_get_key_stats(
2346	__in		efx_nic_t *enp,
2347	__out		efx_key_stats_t *ksp);
2348
2349extern	__checkReturn	efx_rc_t
2350efx_lic_app_state(
2351	__in		efx_nic_t *enp,
2352	__in		uint64_t app_id,
2353	__out		boolean_t *licensedp);
2354
2355extern	__checkReturn	efx_rc_t
2356efx_lic_get_id(
2357	__in		efx_nic_t *enp,
2358	__in		size_t buffer_size,
2359	__out		uint32_t *typep,
2360	__out		size_t *lengthp,
2361	__out_opt	uint8_t *bufferp);
2362
2363
2364extern	__checkReturn		efx_rc_t
2365efx_lic_find_start(
2366	__in			efx_nic_t *enp,
2367	__in_bcount(buffer_size)
2368				caddr_t bufferp,
2369	__in			size_t buffer_size,
2370	__out			uint32_t *startp
2371	);
2372
2373extern	__checkReturn		efx_rc_t
2374efx_lic_find_end(
2375	__in			efx_nic_t *enp,
2376	__in_bcount(buffer_size)
2377				caddr_t bufferp,
2378	__in			size_t buffer_size,
2379	__in			uint32_t offset,
2380	__out			uint32_t *endp
2381	);
2382
2383extern	__checkReturn	__success(return != B_FALSE)	boolean_t
2384efx_lic_find_key(
2385	__in			efx_nic_t *enp,
2386	__in_bcount(buffer_size)
2387				caddr_t bufferp,
2388	__in			size_t buffer_size,
2389	__in			uint32_t offset,
2390	__out			uint32_t *startp,
2391	__out			uint32_t *lengthp
2392	);
2393
2394extern	__checkReturn	__success(return != B_FALSE)	boolean_t
2395efx_lic_validate_key(
2396	__in			efx_nic_t *enp,
2397	__in_bcount(length)	caddr_t keyp,
2398	__in			uint32_t length
2399	);
2400
2401extern	__checkReturn		efx_rc_t
2402efx_lic_read_key(
2403	__in			efx_nic_t *enp,
2404	__in_bcount(buffer_size)
2405				caddr_t bufferp,
2406	__in			size_t buffer_size,
2407	__in			uint32_t offset,
2408	__in			uint32_t length,
2409	__out_bcount_part(key_max_size, *lengthp)
2410				caddr_t keyp,
2411	__in			size_t key_max_size,
2412	__out			uint32_t *lengthp
2413	);
2414
2415extern	__checkReturn		efx_rc_t
2416efx_lic_write_key(
2417	__in			efx_nic_t *enp,
2418	__in_bcount(buffer_size)
2419				caddr_t bufferp,
2420	__in			size_t buffer_size,
2421	__in			uint32_t offset,
2422	__in_bcount(length)	caddr_t keyp,
2423	__in			uint32_t length,
2424	__out			uint32_t *lengthp
2425	);
2426
2427	__checkReturn		efx_rc_t
2428efx_lic_delete_key(
2429	__in			efx_nic_t *enp,
2430	__in_bcount(buffer_size)
2431				caddr_t bufferp,
2432	__in			size_t buffer_size,
2433	__in			uint32_t offset,
2434	__in			uint32_t length,
2435	__in			uint32_t end,
2436	__out			uint32_t *deltap
2437	);
2438
2439extern	__checkReturn		efx_rc_t
2440efx_lic_create_partition(
2441	__in			efx_nic_t *enp,
2442	__in_bcount(buffer_size)
2443				caddr_t bufferp,
2444	__in			size_t buffer_size
2445	);
2446
2447extern	__checkReturn		efx_rc_t
2448efx_lic_finish_partition(
2449	__in			efx_nic_t *enp,
2450	__in_bcount(buffer_size)
2451				caddr_t bufferp,
2452	__in			size_t buffer_size
2453	);
2454
2455#endif	/* EFSYS_OPT_LICENSING */
2456
2457
2458
2459#ifdef	__cplusplus
2460}
2461#endif
2462
2463#endif	/* _SYS_EFX_H */
2464