ef10_impl.h revision 311486
1/*- 2 * Copyright (c) 2015-2016 Solarflare Communications Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * The views and conclusions contained in the software and documentation are 27 * those of the authors and should not be interpreted as representing official 28 * policies, either expressed or implied, of the FreeBSD Project. 29 * 30 * $FreeBSD: stable/11/sys/dev/sfxge/common/ef10_impl.h 311486 2017-01-06 07:19:03Z arybchik $ 31 */ 32 33#ifndef _SYS_EF10_IMPL_H 34#define _SYS_EF10_IMPL_H 35 36#ifdef __cplusplus 37extern "C" { 38#endif 39 40#if (EFSYS_OPT_HUNTINGTON && EFSYS_OPT_MEDFORD) 41#define EF10_MAX_PIOBUF_NBUFS MAX(HUNT_PIOBUF_NBUFS, MEDFORD_PIOBUF_NBUFS) 42#elif EFSYS_OPT_HUNTINGTON 43#define EF10_MAX_PIOBUF_NBUFS HUNT_PIOBUF_NBUFS 44#elif EFSYS_OPT_MEDFORD 45#define EF10_MAX_PIOBUF_NBUFS MEDFORD_PIOBUF_NBUFS 46#endif 47 48/* 49 * FIXME: This is just a power of 2 which fits in an MCDI v1 message, and could 50 * possibly be increased, or the write size reported by newer firmware used 51 * instead. 52 */ 53#define EF10_NVRAM_CHUNK 0x80 54 55/* Alignment requirement for value written to RX WPTR: 56 * the WPTR must be aligned to an 8 descriptor boundary 57 */ 58#define EF10_RX_WPTR_ALIGN 8 59 60/* 61 * Max byte offset into the packet the TCP header must start for the hardware 62 * to be able to parse the packet correctly. 63 */ 64#define EF10_TCP_HEADER_OFFSET_LIMIT 208 65 66/* Invalid RSS context handle */ 67#define EF10_RSS_CONTEXT_INVALID (0xffffffff) 68 69 70/* EV */ 71 72 __checkReturn efx_rc_t 73ef10_ev_init( 74 __in efx_nic_t *enp); 75 76 void 77ef10_ev_fini( 78 __in efx_nic_t *enp); 79 80 __checkReturn efx_rc_t 81ef10_ev_qcreate( 82 __in efx_nic_t *enp, 83 __in unsigned int index, 84 __in efsys_mem_t *esmp, 85 __in size_t n, 86 __in uint32_t id, 87 __in uint32_t us, 88 __in uint32_t flags, 89 __in efx_evq_t *eep); 90 91 void 92ef10_ev_qdestroy( 93 __in efx_evq_t *eep); 94 95 __checkReturn efx_rc_t 96ef10_ev_qprime( 97 __in efx_evq_t *eep, 98 __in unsigned int count); 99 100 void 101ef10_ev_qpost( 102 __in efx_evq_t *eep, 103 __in uint16_t data); 104 105 __checkReturn efx_rc_t 106ef10_ev_qmoderate( 107 __in efx_evq_t *eep, 108 __in unsigned int us); 109 110#if EFSYS_OPT_QSTATS 111 void 112ef10_ev_qstats_update( 113 __in efx_evq_t *eep, 114 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat); 115#endif /* EFSYS_OPT_QSTATS */ 116 117 void 118ef10_ev_rxlabel_init( 119 __in efx_evq_t *eep, 120 __in efx_rxq_t *erp, 121 __in unsigned int label); 122 123 void 124ef10_ev_rxlabel_fini( 125 __in efx_evq_t *eep, 126 __in unsigned int label); 127 128/* INTR */ 129 130 __checkReturn efx_rc_t 131ef10_intr_init( 132 __in efx_nic_t *enp, 133 __in efx_intr_type_t type, 134 __in efsys_mem_t *esmp); 135 136 void 137ef10_intr_enable( 138 __in efx_nic_t *enp); 139 140 void 141ef10_intr_disable( 142 __in efx_nic_t *enp); 143 144 void 145ef10_intr_disable_unlocked( 146 __in efx_nic_t *enp); 147 148 __checkReturn efx_rc_t 149ef10_intr_trigger( 150 __in efx_nic_t *enp, 151 __in unsigned int level); 152 153 void 154ef10_intr_status_line( 155 __in efx_nic_t *enp, 156 __out boolean_t *fatalp, 157 __out uint32_t *qmaskp); 158 159 void 160ef10_intr_status_message( 161 __in efx_nic_t *enp, 162 __in unsigned int message, 163 __out boolean_t *fatalp); 164 165 void 166ef10_intr_fatal( 167 __in efx_nic_t *enp); 168 void 169ef10_intr_fini( 170 __in efx_nic_t *enp); 171 172/* NIC */ 173 174extern __checkReturn efx_rc_t 175ef10_nic_probe( 176 __in efx_nic_t *enp); 177 178extern __checkReturn efx_rc_t 179ef10_nic_set_drv_limits( 180 __inout efx_nic_t *enp, 181 __in efx_drv_limits_t *edlp); 182 183extern __checkReturn efx_rc_t 184ef10_nic_get_vi_pool( 185 __in efx_nic_t *enp, 186 __out uint32_t *vi_countp); 187 188extern __checkReturn efx_rc_t 189ef10_nic_get_bar_region( 190 __in efx_nic_t *enp, 191 __in efx_nic_region_t region, 192 __out uint32_t *offsetp, 193 __out size_t *sizep); 194 195extern __checkReturn efx_rc_t 196ef10_nic_reset( 197 __in efx_nic_t *enp); 198 199extern __checkReturn efx_rc_t 200ef10_nic_init( 201 __in efx_nic_t *enp); 202 203#if EFSYS_OPT_DIAG 204 205extern __checkReturn efx_rc_t 206ef10_nic_register_test( 207 __in efx_nic_t *enp); 208 209#endif /* EFSYS_OPT_DIAG */ 210 211extern void 212ef10_nic_fini( 213 __in efx_nic_t *enp); 214 215extern void 216ef10_nic_unprobe( 217 __in efx_nic_t *enp); 218 219 220/* MAC */ 221 222extern __checkReturn efx_rc_t 223ef10_mac_poll( 224 __in efx_nic_t *enp, 225 __out efx_link_mode_t *link_modep); 226 227extern __checkReturn efx_rc_t 228ef10_mac_up( 229 __in efx_nic_t *enp, 230 __out boolean_t *mac_upp); 231 232extern __checkReturn efx_rc_t 233ef10_mac_addr_set( 234 __in efx_nic_t *enp); 235 236extern __checkReturn efx_rc_t 237ef10_mac_pdu_set( 238 __in efx_nic_t *enp); 239 240extern __checkReturn efx_rc_t 241ef10_mac_pdu_get( 242 __in efx_nic_t *enp, 243 __out size_t *pdu); 244 245extern __checkReturn efx_rc_t 246ef10_mac_reconfigure( 247 __in efx_nic_t *enp); 248 249extern __checkReturn efx_rc_t 250ef10_mac_multicast_list_set( 251 __in efx_nic_t *enp); 252 253extern __checkReturn efx_rc_t 254ef10_mac_filter_default_rxq_set( 255 __in efx_nic_t *enp, 256 __in efx_rxq_t *erp, 257 __in boolean_t using_rss); 258 259extern void 260ef10_mac_filter_default_rxq_clear( 261 __in efx_nic_t *enp); 262 263#if EFSYS_OPT_LOOPBACK 264 265extern __checkReturn efx_rc_t 266ef10_mac_loopback_set( 267 __in efx_nic_t *enp, 268 __in efx_link_mode_t link_mode, 269 __in efx_loopback_type_t loopback_type); 270 271#endif /* EFSYS_OPT_LOOPBACK */ 272 273#if EFSYS_OPT_MAC_STATS 274 275extern __checkReturn efx_rc_t 276ef10_mac_stats_get_mask( 277 __in efx_nic_t *enp, 278 __inout_bcount(mask_size) uint32_t *maskp, 279 __in size_t mask_size); 280 281extern __checkReturn efx_rc_t 282ef10_mac_stats_update( 283 __in efx_nic_t *enp, 284 __in efsys_mem_t *esmp, 285 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat, 286 __inout_opt uint32_t *generationp); 287 288#endif /* EFSYS_OPT_MAC_STATS */ 289 290 291/* MCDI */ 292 293#if EFSYS_OPT_MCDI 294 295extern __checkReturn efx_rc_t 296ef10_mcdi_init( 297 __in efx_nic_t *enp, 298 __in const efx_mcdi_transport_t *mtp); 299 300extern void 301ef10_mcdi_fini( 302 __in efx_nic_t *enp); 303 304extern void 305ef10_mcdi_send_request( 306 __in efx_nic_t *enp, 307 __in_bcount(hdr_len) void *hdrp, 308 __in size_t hdr_len, 309 __in_bcount(sdu_len) void *sdup, 310 __in size_t sdu_len); 311 312extern __checkReturn boolean_t 313ef10_mcdi_poll_response( 314 __in efx_nic_t *enp); 315 316extern void 317ef10_mcdi_read_response( 318 __in efx_nic_t *enp, 319 __out_bcount(length) void *bufferp, 320 __in size_t offset, 321 __in size_t length); 322 323extern efx_rc_t 324ef10_mcdi_poll_reboot( 325 __in efx_nic_t *enp); 326 327extern __checkReturn efx_rc_t 328ef10_mcdi_feature_supported( 329 __in efx_nic_t *enp, 330 __in efx_mcdi_feature_id_t id, 331 __out boolean_t *supportedp); 332 333extern void 334ef10_mcdi_get_timeout( 335 __in efx_nic_t *enp, 336 __in efx_mcdi_req_t *emrp, 337 __out uint32_t *timeoutp); 338 339#endif /* EFSYS_OPT_MCDI */ 340 341/* NVRAM */ 342 343#if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD 344 345extern __checkReturn efx_rc_t 346ef10_nvram_buf_read_tlv( 347 __in efx_nic_t *enp, 348 __in_bcount(max_seg_size) caddr_t seg_data, 349 __in size_t max_seg_size, 350 __in uint32_t tag, 351 __deref_out_bcount_opt(*sizep) caddr_t *datap, 352 __out size_t *sizep); 353 354extern __checkReturn efx_rc_t 355ef10_nvram_buf_write_tlv( 356 __inout_bcount(partn_size) caddr_t partn_data, 357 __in size_t partn_size, 358 __in uint32_t tag, 359 __in_bcount(tag_size) caddr_t tag_data, 360 __in size_t tag_size, 361 __out size_t *total_lengthp); 362 363extern __checkReturn efx_rc_t 364ef10_nvram_partn_read_tlv( 365 __in efx_nic_t *enp, 366 __in uint32_t partn, 367 __in uint32_t tag, 368 __deref_out_bcount_opt(*sizep) caddr_t *datap, 369 __out size_t *sizep); 370 371extern __checkReturn efx_rc_t 372ef10_nvram_partn_write_tlv( 373 __in efx_nic_t *enp, 374 __in uint32_t partn, 375 __in uint32_t tag, 376 __in_bcount(size) caddr_t data, 377 __in size_t size); 378 379extern __checkReturn efx_rc_t 380ef10_nvram_partn_write_segment_tlv( 381 __in efx_nic_t *enp, 382 __in uint32_t partn, 383 __in uint32_t tag, 384 __in_bcount(size) caddr_t data, 385 __in size_t size, 386 __in boolean_t all_segments); 387 388extern __checkReturn efx_rc_t 389ef10_nvram_partn_lock( 390 __in efx_nic_t *enp, 391 __in uint32_t partn); 392 393extern __checkReturn efx_rc_t 394ef10_nvram_partn_unlock( 395 __in efx_nic_t *enp, 396 __in uint32_t partn); 397 398#endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */ 399 400#if EFSYS_OPT_NVRAM 401 402#if EFSYS_OPT_DIAG 403 404extern __checkReturn efx_rc_t 405ef10_nvram_test( 406 __in efx_nic_t *enp); 407 408#endif /* EFSYS_OPT_DIAG */ 409 410extern __checkReturn efx_rc_t 411ef10_nvram_type_to_partn( 412 __in efx_nic_t *enp, 413 __in efx_nvram_type_t type, 414 __out uint32_t *partnp); 415 416extern __checkReturn efx_rc_t 417ef10_nvram_partn_size( 418 __in efx_nic_t *enp, 419 __in uint32_t partn, 420 __out size_t *sizep); 421 422extern __checkReturn efx_rc_t 423ef10_nvram_partn_rw_start( 424 __in efx_nic_t *enp, 425 __in uint32_t partn, 426 __out size_t *chunk_sizep); 427 428extern __checkReturn efx_rc_t 429ef10_nvram_partn_read_mode( 430 __in efx_nic_t *enp, 431 __in uint32_t partn, 432 __in unsigned int offset, 433 __out_bcount(size) caddr_t data, 434 __in size_t size, 435 __in uint32_t mode); 436 437extern __checkReturn efx_rc_t 438ef10_nvram_partn_read( 439 __in efx_nic_t *enp, 440 __in uint32_t partn, 441 __in unsigned int offset, 442 __out_bcount(size) caddr_t data, 443 __in size_t size); 444 445extern __checkReturn efx_rc_t 446ef10_nvram_partn_erase( 447 __in efx_nic_t *enp, 448 __in uint32_t partn, 449 __in unsigned int offset, 450 __in size_t size); 451 452extern __checkReturn efx_rc_t 453ef10_nvram_partn_write( 454 __in efx_nic_t *enp, 455 __in uint32_t partn, 456 __in unsigned int offset, 457 __out_bcount(size) caddr_t data, 458 __in size_t size); 459 460extern __checkReturn efx_rc_t 461ef10_nvram_partn_rw_finish( 462 __in efx_nic_t *enp, 463 __in uint32_t partn); 464 465extern __checkReturn efx_rc_t 466ef10_nvram_partn_get_version( 467 __in efx_nic_t *enp, 468 __in uint32_t partn, 469 __out uint32_t *subtypep, 470 __out_ecount(4) uint16_t version[4]); 471 472extern __checkReturn efx_rc_t 473ef10_nvram_partn_set_version( 474 __in efx_nic_t *enp, 475 __in uint32_t partn, 476 __in_ecount(4) uint16_t version[4]); 477 478extern __checkReturn efx_rc_t 479ef10_nvram_buffer_validate( 480 __in efx_nic_t *enp, 481 __in uint32_t partn, 482 __in_bcount(buffer_size) 483 caddr_t bufferp, 484 __in size_t buffer_size); 485 486extern __checkReturn efx_rc_t 487ef10_nvram_buffer_create( 488 __in efx_nic_t *enp, 489 __in uint16_t partn_type, 490 __in_bcount(buffer_size) 491 caddr_t bufferp, 492 __in size_t buffer_size); 493 494extern __checkReturn efx_rc_t 495ef10_nvram_buffer_find_item_start( 496 __in_bcount(buffer_size) 497 caddr_t bufferp, 498 __in size_t buffer_size, 499 __out uint32_t *startp 500 ); 501 502extern __checkReturn efx_rc_t 503ef10_nvram_buffer_find_end( 504 __in_bcount(buffer_size) 505 caddr_t bufferp, 506 __in size_t buffer_size, 507 __in uint32_t offset, 508 __out uint32_t *endp 509 ); 510 511extern __checkReturn __success(return != B_FALSE) boolean_t 512ef10_nvram_buffer_find_item( 513 __in_bcount(buffer_size) 514 caddr_t bufferp, 515 __in size_t buffer_size, 516 __in uint32_t offset, 517 __out uint32_t *startp, 518 __out uint32_t *lengthp 519 ); 520 521extern __checkReturn efx_rc_t 522ef10_nvram_buffer_get_item( 523 __in_bcount(buffer_size) 524 caddr_t bufferp, 525 __in size_t buffer_size, 526 __in uint32_t offset, 527 __in uint32_t length, 528 __out_bcount_part(item_max_size, *lengthp) 529 caddr_t itemp, 530 __in size_t item_max_size, 531 __out uint32_t *lengthp 532 ); 533 534extern __checkReturn efx_rc_t 535ef10_nvram_buffer_insert_item( 536 __in_bcount(buffer_size) 537 caddr_t bufferp, 538 __in size_t buffer_size, 539 __in uint32_t offset, 540 __in_bcount(length) caddr_t keyp, 541 __in uint32_t length, 542 __out uint32_t *lengthp 543 ); 544 545extern __checkReturn efx_rc_t 546ef10_nvram_buffer_delete_item( 547 __in_bcount(buffer_size) 548 caddr_t bufferp, 549 __in size_t buffer_size, 550 __in uint32_t offset, 551 __in uint32_t length, 552 __in uint32_t end 553 ); 554 555extern __checkReturn efx_rc_t 556ef10_nvram_buffer_finish( 557 __in_bcount(buffer_size) 558 caddr_t bufferp, 559 __in size_t buffer_size 560 ); 561 562#endif /* EFSYS_OPT_NVRAM */ 563 564 565/* PHY */ 566 567typedef struct ef10_link_state_s { 568 uint32_t els_adv_cap_mask; 569 uint32_t els_lp_cap_mask; 570 unsigned int els_fcntl; 571 efx_link_mode_t els_link_mode; 572#if EFSYS_OPT_LOOPBACK 573 efx_loopback_type_t els_loopback; 574#endif 575 boolean_t els_mac_up; 576} ef10_link_state_t; 577 578extern void 579ef10_phy_link_ev( 580 __in efx_nic_t *enp, 581 __in efx_qword_t *eqp, 582 __out efx_link_mode_t *link_modep); 583 584extern __checkReturn efx_rc_t 585ef10_phy_get_link( 586 __in efx_nic_t *enp, 587 __out ef10_link_state_t *elsp); 588 589extern __checkReturn efx_rc_t 590ef10_phy_power( 591 __in efx_nic_t *enp, 592 __in boolean_t on); 593 594extern __checkReturn efx_rc_t 595ef10_phy_reconfigure( 596 __in efx_nic_t *enp); 597 598extern __checkReturn efx_rc_t 599ef10_phy_verify( 600 __in efx_nic_t *enp); 601 602extern __checkReturn efx_rc_t 603ef10_phy_oui_get( 604 __in efx_nic_t *enp, 605 __out uint32_t *ouip); 606 607#if EFSYS_OPT_PHY_STATS 608 609extern __checkReturn efx_rc_t 610ef10_phy_stats_update( 611 __in efx_nic_t *enp, 612 __in efsys_mem_t *esmp, 613 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat); 614 615#endif /* EFSYS_OPT_PHY_STATS */ 616 617#if EFSYS_OPT_BIST 618 619extern __checkReturn efx_rc_t 620ef10_bist_enable_offline( 621 __in efx_nic_t *enp); 622 623extern __checkReturn efx_rc_t 624ef10_bist_start( 625 __in efx_nic_t *enp, 626 __in efx_bist_type_t type); 627 628extern __checkReturn efx_rc_t 629ef10_bist_poll( 630 __in efx_nic_t *enp, 631 __in efx_bist_type_t type, 632 __out efx_bist_result_t *resultp, 633 __out_opt __drv_when(count > 0, __notnull) 634 uint32_t *value_maskp, 635 __out_ecount_opt(count) __drv_when(count > 0, __notnull) 636 unsigned long *valuesp, 637 __in size_t count); 638 639extern void 640ef10_bist_stop( 641 __in efx_nic_t *enp, 642 __in efx_bist_type_t type); 643 644#endif /* EFSYS_OPT_BIST */ 645 646/* TX */ 647 648extern __checkReturn efx_rc_t 649ef10_tx_init( 650 __in efx_nic_t *enp); 651 652extern void 653ef10_tx_fini( 654 __in efx_nic_t *enp); 655 656extern __checkReturn efx_rc_t 657ef10_tx_qcreate( 658 __in efx_nic_t *enp, 659 __in unsigned int index, 660 __in unsigned int label, 661 __in efsys_mem_t *esmp, 662 __in size_t n, 663 __in uint32_t id, 664 __in uint16_t flags, 665 __in efx_evq_t *eep, 666 __in efx_txq_t *etp, 667 __out unsigned int *addedp); 668 669extern void 670ef10_tx_qdestroy( 671 __in efx_txq_t *etp); 672 673extern __checkReturn efx_rc_t 674ef10_tx_qpost( 675 __in efx_txq_t *etp, 676 __in_ecount(n) efx_buffer_t *eb, 677 __in unsigned int n, 678 __in unsigned int completed, 679 __inout unsigned int *addedp); 680 681extern void 682ef10_tx_qpush( 683 __in efx_txq_t *etp, 684 __in unsigned int added, 685 __in unsigned int pushed); 686 687extern __checkReturn efx_rc_t 688ef10_tx_qpace( 689 __in efx_txq_t *etp, 690 __in unsigned int ns); 691 692extern __checkReturn efx_rc_t 693ef10_tx_qflush( 694 __in efx_txq_t *etp); 695 696extern void 697ef10_tx_qenable( 698 __in efx_txq_t *etp); 699 700extern __checkReturn efx_rc_t 701ef10_tx_qpio_enable( 702 __in efx_txq_t *etp); 703 704extern void 705ef10_tx_qpio_disable( 706 __in efx_txq_t *etp); 707 708extern __checkReturn efx_rc_t 709ef10_tx_qpio_write( 710 __in efx_txq_t *etp, 711 __in_ecount(buf_length) uint8_t *buffer, 712 __in size_t buf_length, 713 __in size_t pio_buf_offset); 714 715extern __checkReturn efx_rc_t 716ef10_tx_qpio_post( 717 __in efx_txq_t *etp, 718 __in size_t pkt_length, 719 __in unsigned int completed, 720 __inout unsigned int *addedp); 721 722extern __checkReturn efx_rc_t 723ef10_tx_qdesc_post( 724 __in efx_txq_t *etp, 725 __in_ecount(n) efx_desc_t *ed, 726 __in unsigned int n, 727 __in unsigned int completed, 728 __inout unsigned int *addedp); 729 730extern void 731ef10_tx_qdesc_dma_create( 732 __in efx_txq_t *etp, 733 __in efsys_dma_addr_t addr, 734 __in size_t size, 735 __in boolean_t eop, 736 __out efx_desc_t *edp); 737 738extern void 739ef10_tx_qdesc_tso_create( 740 __in efx_txq_t *etp, 741 __in uint16_t ipv4_id, 742 __in uint32_t tcp_seq, 743 __in uint8_t tcp_flags, 744 __out efx_desc_t *edp); 745 746extern void 747ef10_tx_qdesc_tso2_create( 748 __in efx_txq_t *etp, 749 __in uint16_t ipv4_id, 750 __in uint32_t tcp_seq, 751 __in uint16_t tcp_mss, 752 __out_ecount(count) efx_desc_t *edp, 753 __in int count); 754 755extern void 756ef10_tx_qdesc_vlantci_create( 757 __in efx_txq_t *etp, 758 __in uint16_t vlan_tci, 759 __out efx_desc_t *edp); 760 761 762#if EFSYS_OPT_QSTATS 763 764extern void 765ef10_tx_qstats_update( 766 __in efx_txq_t *etp, 767 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat); 768 769#endif /* EFSYS_OPT_QSTATS */ 770 771typedef uint32_t efx_piobuf_handle_t; 772 773#define EFX_PIOBUF_HANDLE_INVALID ((efx_piobuf_handle_t) -1) 774 775extern __checkReturn efx_rc_t 776ef10_nic_pio_alloc( 777 __inout efx_nic_t *enp, 778 __out uint32_t *bufnump, 779 __out efx_piobuf_handle_t *handlep, 780 __out uint32_t *blknump, 781 __out uint32_t *offsetp, 782 __out size_t *sizep); 783 784extern __checkReturn efx_rc_t 785ef10_nic_pio_free( 786 __inout efx_nic_t *enp, 787 __in uint32_t bufnum, 788 __in uint32_t blknum); 789 790extern __checkReturn efx_rc_t 791ef10_nic_pio_link( 792 __inout efx_nic_t *enp, 793 __in uint32_t vi_index, 794 __in efx_piobuf_handle_t handle); 795 796extern __checkReturn efx_rc_t 797ef10_nic_pio_unlink( 798 __inout efx_nic_t *enp, 799 __in uint32_t vi_index); 800 801 802/* VPD */ 803 804#if EFSYS_OPT_VPD 805 806extern __checkReturn efx_rc_t 807ef10_vpd_init( 808 __in efx_nic_t *enp); 809 810extern __checkReturn efx_rc_t 811ef10_vpd_size( 812 __in efx_nic_t *enp, 813 __out size_t *sizep); 814 815extern __checkReturn efx_rc_t 816ef10_vpd_read( 817 __in efx_nic_t *enp, 818 __out_bcount(size) caddr_t data, 819 __in size_t size); 820 821extern __checkReturn efx_rc_t 822ef10_vpd_verify( 823 __in efx_nic_t *enp, 824 __in_bcount(size) caddr_t data, 825 __in size_t size); 826 827extern __checkReturn efx_rc_t 828ef10_vpd_reinit( 829 __in efx_nic_t *enp, 830 __in_bcount(size) caddr_t data, 831 __in size_t size); 832 833extern __checkReturn efx_rc_t 834ef10_vpd_get( 835 __in efx_nic_t *enp, 836 __in_bcount(size) caddr_t data, 837 __in size_t size, 838 __inout efx_vpd_value_t *evvp); 839 840extern __checkReturn efx_rc_t 841ef10_vpd_set( 842 __in efx_nic_t *enp, 843 __in_bcount(size) caddr_t data, 844 __in size_t size, 845 __in efx_vpd_value_t *evvp); 846 847extern __checkReturn efx_rc_t 848ef10_vpd_next( 849 __in efx_nic_t *enp, 850 __in_bcount(size) caddr_t data, 851 __in size_t size, 852 __out efx_vpd_value_t *evvp, 853 __inout unsigned int *contp); 854 855extern __checkReturn efx_rc_t 856ef10_vpd_write( 857 __in efx_nic_t *enp, 858 __in_bcount(size) caddr_t data, 859 __in size_t size); 860 861extern void 862ef10_vpd_fini( 863 __in efx_nic_t *enp); 864 865#endif /* EFSYS_OPT_VPD */ 866 867 868/* RX */ 869 870extern __checkReturn efx_rc_t 871ef10_rx_init( 872 __in efx_nic_t *enp); 873 874#if EFSYS_OPT_RX_SCATTER 875extern __checkReturn efx_rc_t 876ef10_rx_scatter_enable( 877 __in efx_nic_t *enp, 878 __in unsigned int buf_size); 879#endif /* EFSYS_OPT_RX_SCATTER */ 880 881 882#if EFSYS_OPT_RX_SCALE 883 884extern __checkReturn efx_rc_t 885ef10_rx_scale_mode_set( 886 __in efx_nic_t *enp, 887 __in efx_rx_hash_alg_t alg, 888 __in efx_rx_hash_type_t type, 889 __in boolean_t insert); 890 891extern __checkReturn efx_rc_t 892ef10_rx_scale_key_set( 893 __in efx_nic_t *enp, 894 __in_ecount(n) uint8_t *key, 895 __in size_t n); 896 897extern __checkReturn efx_rc_t 898ef10_rx_scale_tbl_set( 899 __in efx_nic_t *enp, 900 __in_ecount(n) unsigned int *table, 901 __in size_t n); 902 903extern __checkReturn uint32_t 904ef10_rx_prefix_hash( 905 __in efx_nic_t *enp, 906 __in efx_rx_hash_alg_t func, 907 __in uint8_t *buffer); 908 909#endif /* EFSYS_OPT_RX_SCALE */ 910 911extern __checkReturn efx_rc_t 912ef10_rx_prefix_pktlen( 913 __in efx_nic_t *enp, 914 __in uint8_t *buffer, 915 __out uint16_t *lengthp); 916 917extern void 918ef10_rx_qpost( 919 __in efx_rxq_t *erp, 920 __in_ecount(n) efsys_dma_addr_t *addrp, 921 __in size_t size, 922 __in unsigned int n, 923 __in unsigned int completed, 924 __in unsigned int added); 925 926extern void 927ef10_rx_qpush( 928 __in efx_rxq_t *erp, 929 __in unsigned int added, 930 __inout unsigned int *pushedp); 931 932extern __checkReturn efx_rc_t 933ef10_rx_qflush( 934 __in efx_rxq_t *erp); 935 936extern void 937ef10_rx_qenable( 938 __in efx_rxq_t *erp); 939 940extern __checkReturn efx_rc_t 941ef10_rx_qcreate( 942 __in efx_nic_t *enp, 943 __in unsigned int index, 944 __in unsigned int label, 945 __in efx_rxq_type_t type, 946 __in efsys_mem_t *esmp, 947 __in size_t n, 948 __in uint32_t id, 949 __in efx_evq_t *eep, 950 __in efx_rxq_t *erp); 951 952extern void 953ef10_rx_qdestroy( 954 __in efx_rxq_t *erp); 955 956extern void 957ef10_rx_fini( 958 __in efx_nic_t *enp); 959 960#if EFSYS_OPT_FILTER 961 962typedef struct ef10_filter_handle_s { 963 uint32_t efh_lo; 964 uint32_t efh_hi; 965} ef10_filter_handle_t; 966 967typedef struct ef10_filter_entry_s { 968 uintptr_t efe_spec; /* pointer to filter spec plus busy bit */ 969 ef10_filter_handle_t efe_handle; 970} ef10_filter_entry_t; 971 972/* 973 * BUSY flag indicates that an update is in progress. 974 * AUTO_OLD flag is used to mark and sweep MAC packet filters. 975 */ 976#define EFX_EF10_FILTER_FLAG_BUSY 1U 977#define EFX_EF10_FILTER_FLAG_AUTO_OLD 2U 978#define EFX_EF10_FILTER_FLAGS 3U 979 980/* 981 * Size of the hash table used by the driver. Doesn't need to be the 982 * same size as the hardware's table. 983 */ 984#define EFX_EF10_FILTER_TBL_ROWS 8192 985 986/* Only need to allow for one directed and one unknown unicast filter */ 987#define EFX_EF10_FILTER_UNICAST_FILTERS_MAX 2 988 989/* Allow for the broadcast address to be added to the multicast list */ 990#define EFX_EF10_FILTER_MULTICAST_FILTERS_MAX (EFX_MAC_MULTICAST_LIST_MAX + 1) 991 992typedef struct ef10_filter_table_s { 993 ef10_filter_entry_t eft_entry[EFX_EF10_FILTER_TBL_ROWS]; 994 efx_rxq_t *eft_default_rxq; 995 boolean_t eft_using_rss; 996 uint32_t eft_unicst_filter_indexes[ 997 EFX_EF10_FILTER_UNICAST_FILTERS_MAX]; 998 uint32_t eft_unicst_filter_count; 999 uint32_t eft_mulcst_filter_indexes[ 1000 EFX_EF10_FILTER_MULTICAST_FILTERS_MAX]; 1001 uint32_t eft_mulcst_filter_count; 1002 boolean_t eft_using_all_mulcst; 1003} ef10_filter_table_t; 1004 1005 __checkReturn efx_rc_t 1006ef10_filter_init( 1007 __in efx_nic_t *enp); 1008 1009 void 1010ef10_filter_fini( 1011 __in efx_nic_t *enp); 1012 1013 __checkReturn efx_rc_t 1014ef10_filter_restore( 1015 __in efx_nic_t *enp); 1016 1017 __checkReturn efx_rc_t 1018ef10_filter_add( 1019 __in efx_nic_t *enp, 1020 __inout efx_filter_spec_t *spec, 1021 __in boolean_t may_replace); 1022 1023 __checkReturn efx_rc_t 1024ef10_filter_delete( 1025 __in efx_nic_t *enp, 1026 __inout efx_filter_spec_t *spec); 1027 1028extern __checkReturn efx_rc_t 1029ef10_filter_supported_filters( 1030 __in efx_nic_t *enp, 1031 __out_ecount(buffer_length) uint32_t *buffer, 1032 __in size_t buffer_length, 1033 __out size_t *list_lengthp); 1034 1035extern __checkReturn efx_rc_t 1036ef10_filter_reconfigure( 1037 __in efx_nic_t *enp, 1038 __in_ecount(6) uint8_t const *mac_addr, 1039 __in boolean_t all_unicst, 1040 __in boolean_t mulcst, 1041 __in boolean_t all_mulcst, 1042 __in boolean_t brdcst, 1043 __in_ecount(6*count) uint8_t const *addrs, 1044 __in uint32_t count); 1045 1046extern void 1047ef10_filter_get_default_rxq( 1048 __in efx_nic_t *enp, 1049 __out efx_rxq_t **erpp, 1050 __out boolean_t *using_rss); 1051 1052extern void 1053ef10_filter_default_rxq_set( 1054 __in efx_nic_t *enp, 1055 __in efx_rxq_t *erp, 1056 __in boolean_t using_rss); 1057 1058extern void 1059ef10_filter_default_rxq_clear( 1060 __in efx_nic_t *enp); 1061 1062 1063#endif /* EFSYS_OPT_FILTER */ 1064 1065extern __checkReturn efx_rc_t 1066efx_mcdi_get_function_info( 1067 __in efx_nic_t *enp, 1068 __out uint32_t *pfp, 1069 __out_opt uint32_t *vfp); 1070 1071extern __checkReturn efx_rc_t 1072efx_mcdi_privilege_mask( 1073 __in efx_nic_t *enp, 1074 __in uint32_t pf, 1075 __in uint32_t vf, 1076 __out uint32_t *maskp); 1077 1078extern __checkReturn efx_rc_t 1079efx_mcdi_get_port_assignment( 1080 __in efx_nic_t *enp, 1081 __out uint32_t *portp); 1082 1083extern __checkReturn efx_rc_t 1084efx_mcdi_get_port_modes( 1085 __in efx_nic_t *enp, 1086 __out uint32_t *modesp, 1087 __out_opt uint32_t *current_modep); 1088 1089extern __checkReturn efx_rc_t 1090ef10_nic_get_port_mode_bandwidth( 1091 __in uint32_t port_mode, 1092 __out uint32_t *bandwidth_mbpsp); 1093 1094extern __checkReturn efx_rc_t 1095efx_mcdi_get_mac_address_pf( 1096 __in efx_nic_t *enp, 1097 __out_ecount_opt(6) uint8_t mac_addrp[6]); 1098 1099extern __checkReturn efx_rc_t 1100efx_mcdi_get_mac_address_vf( 1101 __in efx_nic_t *enp, 1102 __out_ecount_opt(6) uint8_t mac_addrp[6]); 1103 1104extern __checkReturn efx_rc_t 1105efx_mcdi_get_clock( 1106 __in efx_nic_t *enp, 1107 __out uint32_t *sys_freqp, 1108 __out uint32_t *dpcpu_freqp); 1109 1110 1111extern __checkReturn efx_rc_t 1112efx_mcdi_get_vector_cfg( 1113 __in efx_nic_t *enp, 1114 __out_opt uint32_t *vec_basep, 1115 __out_opt uint32_t *pf_nvecp, 1116 __out_opt uint32_t *vf_nvecp); 1117 1118extern __checkReturn efx_rc_t 1119ef10_get_datapath_caps( 1120 __in efx_nic_t *enp); 1121 1122extern __checkReturn efx_rc_t 1123ef10_get_privilege_mask( 1124 __in efx_nic_t *enp, 1125 __out uint32_t *maskp); 1126 1127extern __checkReturn efx_rc_t 1128ef10_external_port_mapping( 1129 __in efx_nic_t *enp, 1130 __in uint32_t port, 1131 __out uint8_t *external_portp); 1132 1133 1134#ifdef __cplusplus 1135} 1136#endif 1137 1138#endif /* _SYS_EF10_IMPL_H */ 1139