1/*-
2 * Copyright (c) 2015-2016 Solarflare Communications Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,
9 *    this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 *    this list of conditions and the following disclaimer in the documentation
12 *    and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
29 *
30 * $FreeBSD: stable/11/sys/dev/sfxge/common/ef10_impl.h 342441 2018-12-25 07:21:35Z arybchik $
31 */
32
33#ifndef	_SYS_EF10_IMPL_H
34#define	_SYS_EF10_IMPL_H
35
36#ifdef	__cplusplus
37extern "C" {
38#endif
39
40#if (EFSYS_OPT_HUNTINGTON && EFSYS_OPT_MEDFORD)
41#define	EF10_MAX_PIOBUF_NBUFS	MAX(HUNT_PIOBUF_NBUFS, MEDFORD_PIOBUF_NBUFS)
42#elif EFSYS_OPT_HUNTINGTON
43#define	EF10_MAX_PIOBUF_NBUFS	HUNT_PIOBUF_NBUFS
44#elif EFSYS_OPT_MEDFORD
45#define	EF10_MAX_PIOBUF_NBUFS	MEDFORD_PIOBUF_NBUFS
46#endif
47
48/*
49 * FIXME: This is just a power of 2 which fits in an MCDI v1 message, and could
50 * possibly be increased, or the write size reported by newer firmware used
51 * instead.
52 */
53#define	EF10_NVRAM_CHUNK 0x80
54
55/* Alignment requirement for value written to RX WPTR:
56 *  the WPTR must be aligned to an 8 descriptor boundary
57 */
58#define	EF10_RX_WPTR_ALIGN 8
59
60/*
61 * Max byte offset into the packet the TCP header must start for the hardware
62 * to be able to parse the packet correctly.
63 */
64#define	EF10_TCP_HEADER_OFFSET_LIMIT	208
65
66/* Invalid RSS context handle */
67#define	EF10_RSS_CONTEXT_INVALID	(0xffffffff)
68
69
70/* EV */
71
72	__checkReturn	efx_rc_t
73ef10_ev_init(
74	__in		efx_nic_t *enp);
75
76			void
77ef10_ev_fini(
78	__in		efx_nic_t *enp);
79
80	__checkReturn	efx_rc_t
81ef10_ev_qcreate(
82	__in		efx_nic_t *enp,
83	__in		unsigned int index,
84	__in		efsys_mem_t *esmp,
85	__in		size_t n,
86	__in		uint32_t id,
87	__in		uint32_t us,
88	__in		uint32_t flags,
89	__in		efx_evq_t *eep);
90
91			void
92ef10_ev_qdestroy(
93	__in		efx_evq_t *eep);
94
95	__checkReturn	efx_rc_t
96ef10_ev_qprime(
97	__in		efx_evq_t *eep,
98	__in		unsigned int count);
99
100			void
101ef10_ev_qpost(
102	__in	efx_evq_t *eep,
103	__in	uint16_t data);
104
105	__checkReturn	efx_rc_t
106ef10_ev_qmoderate(
107	__in		efx_evq_t *eep,
108	__in		unsigned int us);
109
110#if EFSYS_OPT_QSTATS
111			void
112ef10_ev_qstats_update(
113	__in				efx_evq_t *eep,
114	__inout_ecount(EV_NQSTATS)	efsys_stat_t *stat);
115#endif /* EFSYS_OPT_QSTATS */
116
117		void
118ef10_ev_rxlabel_init(
119	__in		efx_evq_t *eep,
120	__in		efx_rxq_t *erp,
121	__in		unsigned int label);
122
123		void
124ef10_ev_rxlabel_fini(
125	__in		efx_evq_t *eep,
126	__in		unsigned int label);
127
128/* INTR */
129
130	__checkReturn	efx_rc_t
131ef10_intr_init(
132	__in		efx_nic_t *enp,
133	__in		efx_intr_type_t type,
134	__in		efsys_mem_t *esmp);
135
136			void
137ef10_intr_enable(
138	__in		efx_nic_t *enp);
139
140			void
141ef10_intr_disable(
142	__in		efx_nic_t *enp);
143
144			void
145ef10_intr_disable_unlocked(
146	__in		efx_nic_t *enp);
147
148	__checkReturn	efx_rc_t
149ef10_intr_trigger(
150	__in		efx_nic_t *enp,
151	__in		unsigned int level);
152
153			void
154ef10_intr_status_line(
155	__in		efx_nic_t *enp,
156	__out		boolean_t *fatalp,
157	__out		uint32_t *qmaskp);
158
159			void
160ef10_intr_status_message(
161	__in		efx_nic_t *enp,
162	__in		unsigned int message,
163	__out		boolean_t *fatalp);
164
165			void
166ef10_intr_fatal(
167	__in		efx_nic_t *enp);
168			void
169ef10_intr_fini(
170	__in		efx_nic_t *enp);
171
172/* NIC */
173
174extern	__checkReturn	efx_rc_t
175ef10_nic_probe(
176	__in		efx_nic_t *enp);
177
178extern	__checkReturn	efx_rc_t
179ef10_nic_set_drv_limits(
180	__inout		efx_nic_t *enp,
181	__in		efx_drv_limits_t *edlp);
182
183extern	__checkReturn	efx_rc_t
184ef10_nic_get_vi_pool(
185	__in		efx_nic_t *enp,
186	__out		uint32_t *vi_countp);
187
188extern	__checkReturn	efx_rc_t
189ef10_nic_get_bar_region(
190	__in		efx_nic_t *enp,
191	__in		efx_nic_region_t region,
192	__out		uint32_t *offsetp,
193	__out		size_t *sizep);
194
195extern	__checkReturn	efx_rc_t
196ef10_nic_reset(
197	__in		efx_nic_t *enp);
198
199extern	__checkReturn	efx_rc_t
200ef10_nic_init(
201	__in		efx_nic_t *enp);
202
203#if EFSYS_OPT_DIAG
204
205extern	__checkReturn	efx_rc_t
206ef10_nic_register_test(
207	__in		efx_nic_t *enp);
208
209#endif	/* EFSYS_OPT_DIAG */
210
211extern			void
212ef10_nic_fini(
213	__in		efx_nic_t *enp);
214
215extern			void
216ef10_nic_unprobe(
217	__in		efx_nic_t *enp);
218
219
220/* MAC */
221
222extern	__checkReturn	efx_rc_t
223ef10_mac_poll(
224	__in		efx_nic_t *enp,
225	__out		efx_link_mode_t *link_modep);
226
227extern	__checkReturn	efx_rc_t
228ef10_mac_up(
229	__in		efx_nic_t *enp,
230	__out		boolean_t *mac_upp);
231
232extern	__checkReturn	efx_rc_t
233ef10_mac_addr_set(
234	__in	efx_nic_t *enp);
235
236extern	__checkReturn	efx_rc_t
237ef10_mac_pdu_set(
238	__in	efx_nic_t *enp);
239
240extern	__checkReturn	efx_rc_t
241ef10_mac_pdu_get(
242	__in	efx_nic_t *enp,
243	__out	size_t *pdu);
244
245extern	__checkReturn	efx_rc_t
246ef10_mac_reconfigure(
247	__in	efx_nic_t *enp);
248
249extern	__checkReturn	efx_rc_t
250ef10_mac_multicast_list_set(
251	__in				efx_nic_t *enp);
252
253extern	__checkReturn	efx_rc_t
254ef10_mac_filter_default_rxq_set(
255	__in		efx_nic_t *enp,
256	__in		efx_rxq_t *erp,
257	__in		boolean_t using_rss);
258
259extern			void
260ef10_mac_filter_default_rxq_clear(
261	__in		efx_nic_t *enp);
262
263#if EFSYS_OPT_LOOPBACK
264
265extern	__checkReturn	efx_rc_t
266ef10_mac_loopback_set(
267	__in		efx_nic_t *enp,
268	__in		efx_link_mode_t link_mode,
269	__in		efx_loopback_type_t loopback_type);
270
271#endif	/* EFSYS_OPT_LOOPBACK */
272
273#if EFSYS_OPT_MAC_STATS
274
275extern	__checkReturn			efx_rc_t
276ef10_mac_stats_get_mask(
277	__in				efx_nic_t *enp,
278	__inout_bcount(mask_size)	uint32_t *maskp,
279	__in				size_t mask_size);
280
281extern	__checkReturn			efx_rc_t
282ef10_mac_stats_update(
283	__in				efx_nic_t *enp,
284	__in				efsys_mem_t *esmp,
285	__inout_ecount(EFX_MAC_NSTATS)	efsys_stat_t *stat,
286	__inout_opt			uint32_t *generationp);
287
288#endif	/* EFSYS_OPT_MAC_STATS */
289
290
291/* MCDI */
292
293#if EFSYS_OPT_MCDI
294
295extern	__checkReturn	efx_rc_t
296ef10_mcdi_init(
297	__in		efx_nic_t *enp,
298	__in		const efx_mcdi_transport_t *mtp);
299
300extern			void
301ef10_mcdi_fini(
302	__in		efx_nic_t *enp);
303
304extern			void
305ef10_mcdi_send_request(
306	__in			efx_nic_t *enp,
307	__in_bcount(hdr_len)	void *hdrp,
308	__in			size_t hdr_len,
309	__in_bcount(sdu_len)	void *sdup,
310	__in			size_t sdu_len);
311
312extern	__checkReturn	boolean_t
313ef10_mcdi_poll_response(
314	__in		efx_nic_t *enp);
315
316extern			void
317ef10_mcdi_read_response(
318	__in			efx_nic_t *enp,
319	__out_bcount(length)	void *bufferp,
320	__in			size_t offset,
321	__in			size_t length);
322
323extern			efx_rc_t
324ef10_mcdi_poll_reboot(
325	__in		efx_nic_t *enp);
326
327extern	__checkReturn	efx_rc_t
328ef10_mcdi_feature_supported(
329	__in		efx_nic_t *enp,
330	__in		efx_mcdi_feature_id_t id,
331	__out		boolean_t *supportedp);
332
333extern			void
334ef10_mcdi_get_timeout(
335	__in		efx_nic_t *enp,
336	__in		efx_mcdi_req_t *emrp,
337	__out		uint32_t *timeoutp);
338
339#endif /* EFSYS_OPT_MCDI */
340
341/* NVRAM */
342
343#if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
344
345extern	__checkReturn		efx_rc_t
346ef10_nvram_buf_read_tlv(
347	__in				efx_nic_t *enp,
348	__in_bcount(max_seg_size)	caddr_t seg_data,
349	__in				size_t max_seg_size,
350	__in				uint32_t tag,
351	__deref_out_bcount_opt(*sizep)	caddr_t *datap,
352	__out				size_t *sizep);
353
354extern	__checkReturn		efx_rc_t
355ef10_nvram_buf_write_tlv(
356	__inout_bcount(partn_size)	caddr_t partn_data,
357	__in				size_t partn_size,
358	__in				uint32_t tag,
359	__in_bcount(tag_size)		caddr_t tag_data,
360	__in				size_t tag_size,
361	__out				size_t *total_lengthp);
362
363extern	__checkReturn		efx_rc_t
364ef10_nvram_partn_read_tlv(
365	__in				efx_nic_t *enp,
366	__in				uint32_t partn,
367	__in				uint32_t tag,
368	__deref_out_bcount_opt(*sizep)	caddr_t *datap,
369	__out				size_t *sizep);
370
371extern	__checkReturn		efx_rc_t
372ef10_nvram_partn_write_tlv(
373	__in			efx_nic_t *enp,
374	__in			uint32_t partn,
375	__in			uint32_t tag,
376	__in_bcount(size)	caddr_t data,
377	__in			size_t size);
378
379extern	__checkReturn		efx_rc_t
380ef10_nvram_partn_write_segment_tlv(
381	__in			efx_nic_t *enp,
382	__in			uint32_t partn,
383	__in			uint32_t tag,
384	__in_bcount(size)	caddr_t data,
385	__in			size_t size,
386	__in			boolean_t all_segments);
387
388extern	__checkReturn		efx_rc_t
389ef10_nvram_partn_lock(
390	__in			efx_nic_t *enp,
391	__in			uint32_t partn);
392
393extern	__checkReturn		efx_rc_t
394ef10_nvram_partn_unlock(
395	__in			efx_nic_t *enp,
396	__in			uint32_t partn,
397	__out_opt		uint32_t *resultp);
398
399#endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
400
401#if EFSYS_OPT_NVRAM
402
403#if EFSYS_OPT_DIAG
404
405extern	__checkReturn		efx_rc_t
406ef10_nvram_test(
407	__in			efx_nic_t *enp);
408
409#endif	/* EFSYS_OPT_DIAG */
410
411extern	__checkReturn		efx_rc_t
412ef10_nvram_type_to_partn(
413	__in			efx_nic_t *enp,
414	__in			efx_nvram_type_t type,
415	__out			uint32_t *partnp);
416
417extern	__checkReturn		efx_rc_t
418ef10_nvram_partn_size(
419	__in			efx_nic_t *enp,
420	__in			uint32_t partn,
421	__out			size_t *sizep);
422
423extern	__checkReturn		efx_rc_t
424ef10_nvram_partn_rw_start(
425	__in			efx_nic_t *enp,
426	__in			uint32_t partn,
427	__out			size_t *chunk_sizep);
428
429extern	__checkReturn		efx_rc_t
430ef10_nvram_partn_read_mode(
431	__in			efx_nic_t *enp,
432	__in			uint32_t partn,
433	__in			unsigned int offset,
434	__out_bcount(size)	caddr_t data,
435	__in			size_t size,
436	__in			uint32_t mode);
437
438extern	__checkReturn		efx_rc_t
439ef10_nvram_partn_read(
440	__in			efx_nic_t *enp,
441	__in			uint32_t partn,
442	__in			unsigned int offset,
443	__in_bcount(size)	caddr_t data,
444	__in			size_t size);
445
446extern	__checkReturn		efx_rc_t
447ef10_nvram_partn_erase(
448	__in			efx_nic_t *enp,
449	__in			uint32_t partn,
450	__in			unsigned int offset,
451	__in			size_t size);
452
453extern	__checkReturn		efx_rc_t
454ef10_nvram_partn_write(
455	__in			efx_nic_t *enp,
456	__in			uint32_t partn,
457	__in			unsigned int offset,
458	__out_bcount(size)	caddr_t data,
459	__in			size_t size);
460
461extern	__checkReturn		efx_rc_t
462ef10_nvram_partn_rw_finish(
463	__in			efx_nic_t *enp,
464	__in			uint32_t partn);
465
466extern	__checkReturn		efx_rc_t
467ef10_nvram_partn_get_version(
468	__in			efx_nic_t *enp,
469	__in			uint32_t partn,
470	__out			uint32_t *subtypep,
471	__out_ecount(4)		uint16_t version[4]);
472
473extern	__checkReturn		efx_rc_t
474ef10_nvram_partn_set_version(
475	__in			efx_nic_t *enp,
476	__in			uint32_t partn,
477	__in_ecount(4)		uint16_t version[4]);
478
479extern	__checkReturn		efx_rc_t
480ef10_nvram_buffer_validate(
481	__in			efx_nic_t *enp,
482	__in			uint32_t partn,
483	__in_bcount(buffer_size)
484				caddr_t bufferp,
485	__in			size_t buffer_size);
486
487extern	__checkReturn		efx_rc_t
488ef10_nvram_buffer_create(
489	__in			efx_nic_t *enp,
490	__in			uint16_t partn_type,
491	__in_bcount(buffer_size)
492				caddr_t bufferp,
493	__in			size_t buffer_size);
494
495extern	__checkReturn		efx_rc_t
496ef10_nvram_buffer_find_item_start(
497	__in_bcount(buffer_size)
498				caddr_t bufferp,
499	__in			size_t buffer_size,
500	__out			uint32_t *startp
501	);
502
503extern	__checkReturn		efx_rc_t
504ef10_nvram_buffer_find_end(
505	__in_bcount(buffer_size)
506				caddr_t bufferp,
507	__in			size_t buffer_size,
508	__in			uint32_t offset,
509	__out			uint32_t *endp
510	);
511
512extern	__checkReturn	__success(return != B_FALSE)	boolean_t
513ef10_nvram_buffer_find_item(
514	__in_bcount(buffer_size)
515				caddr_t bufferp,
516	__in			size_t buffer_size,
517	__in			uint32_t offset,
518	__out			uint32_t *startp,
519	__out			uint32_t *lengthp
520	);
521
522extern	__checkReturn		efx_rc_t
523ef10_nvram_buffer_get_item(
524	__in_bcount(buffer_size)
525				caddr_t bufferp,
526	__in			size_t buffer_size,
527	__in			uint32_t offset,
528	__in			uint32_t length,
529	__out_bcount_part(item_max_size, *lengthp)
530				caddr_t itemp,
531	__in			size_t item_max_size,
532	__out			uint32_t *lengthp
533	);
534
535extern	__checkReturn		efx_rc_t
536ef10_nvram_buffer_insert_item(
537	__in_bcount(buffer_size)
538				caddr_t bufferp,
539	__in			size_t buffer_size,
540	__in			uint32_t offset,
541	__in_bcount(length)	caddr_t keyp,
542	__in			uint32_t length,
543	__out			uint32_t *lengthp
544	);
545
546extern	__checkReturn		efx_rc_t
547ef10_nvram_buffer_delete_item(
548	__in_bcount(buffer_size)
549				caddr_t bufferp,
550	__in			size_t buffer_size,
551	__in			uint32_t offset,
552	__in			uint32_t length,
553	__in			uint32_t end
554	);
555
556extern	__checkReturn		efx_rc_t
557ef10_nvram_buffer_finish(
558	__in_bcount(buffer_size)
559				caddr_t bufferp,
560	__in			size_t buffer_size
561	);
562
563#endif	/* EFSYS_OPT_NVRAM */
564
565
566/* PHY */
567
568typedef struct ef10_link_state_s {
569	uint32_t		els_adv_cap_mask;
570	uint32_t		els_lp_cap_mask;
571	unsigned int		els_fcntl;
572	efx_link_mode_t		els_link_mode;
573#if EFSYS_OPT_LOOPBACK
574	efx_loopback_type_t	els_loopback;
575#endif
576	boolean_t		els_mac_up;
577} ef10_link_state_t;
578
579extern			void
580ef10_phy_link_ev(
581	__in		efx_nic_t *enp,
582	__in		efx_qword_t *eqp,
583	__out		efx_link_mode_t *link_modep);
584
585extern	__checkReturn	efx_rc_t
586ef10_phy_get_link(
587	__in		efx_nic_t *enp,
588	__out		ef10_link_state_t *elsp);
589
590extern	__checkReturn	efx_rc_t
591ef10_phy_power(
592	__in		efx_nic_t *enp,
593	__in		boolean_t on);
594
595extern	__checkReturn	efx_rc_t
596ef10_phy_reconfigure(
597	__in		efx_nic_t *enp);
598
599extern	__checkReturn	efx_rc_t
600ef10_phy_verify(
601	__in		efx_nic_t *enp);
602
603extern	__checkReturn	efx_rc_t
604ef10_phy_oui_get(
605	__in		efx_nic_t *enp,
606	__out		uint32_t *ouip);
607
608#if EFSYS_OPT_PHY_STATS
609
610extern	__checkReturn			efx_rc_t
611ef10_phy_stats_update(
612	__in				efx_nic_t *enp,
613	__in				efsys_mem_t *esmp,
614	__inout_ecount(EFX_PHY_NSTATS)	uint32_t *stat);
615
616#endif	/* EFSYS_OPT_PHY_STATS */
617
618#if EFSYS_OPT_BIST
619
620extern	__checkReturn		efx_rc_t
621ef10_bist_enable_offline(
622	__in			efx_nic_t *enp);
623
624extern	__checkReturn		efx_rc_t
625ef10_bist_start(
626	__in			efx_nic_t *enp,
627	__in			efx_bist_type_t type);
628
629extern	__checkReturn		efx_rc_t
630ef10_bist_poll(
631	__in			efx_nic_t *enp,
632	__in			efx_bist_type_t type,
633	__out			efx_bist_result_t *resultp,
634	__out_opt __drv_when(count > 0, __notnull)
635	uint32_t	*value_maskp,
636	__out_ecount_opt(count)	__drv_when(count > 0, __notnull)
637	unsigned long	*valuesp,
638	__in			size_t count);
639
640extern				void
641ef10_bist_stop(
642	__in			efx_nic_t *enp,
643	__in			efx_bist_type_t type);
644
645#endif	/* EFSYS_OPT_BIST */
646
647/* TX */
648
649extern	__checkReturn	efx_rc_t
650ef10_tx_init(
651	__in		efx_nic_t *enp);
652
653extern			void
654ef10_tx_fini(
655	__in		efx_nic_t *enp);
656
657extern	__checkReturn	efx_rc_t
658ef10_tx_qcreate(
659	__in		efx_nic_t *enp,
660	__in		unsigned int index,
661	__in		unsigned int label,
662	__in		efsys_mem_t *esmp,
663	__in		size_t n,
664	__in		uint32_t id,
665	__in		uint16_t flags,
666	__in		efx_evq_t *eep,
667	__in		efx_txq_t *etp,
668	__out		unsigned int *addedp);
669
670extern		void
671ef10_tx_qdestroy(
672	__in		efx_txq_t *etp);
673
674extern	__checkReturn	efx_rc_t
675ef10_tx_qpost(
676	__in		efx_txq_t *etp,
677	__in_ecount(n)	efx_buffer_t *eb,
678	__in		unsigned int n,
679	__in		unsigned int completed,
680	__inout		unsigned int *addedp);
681
682extern			void
683ef10_tx_qpush(
684	__in		efx_txq_t *etp,
685	__in		unsigned int added,
686	__in		unsigned int pushed);
687
688extern	__checkReturn	efx_rc_t
689ef10_tx_qpace(
690	__in		efx_txq_t *etp,
691	__in		unsigned int ns);
692
693extern	__checkReturn	efx_rc_t
694ef10_tx_qflush(
695	__in		efx_txq_t *etp);
696
697extern			void
698ef10_tx_qenable(
699	__in		efx_txq_t *etp);
700
701extern	__checkReturn	efx_rc_t
702ef10_tx_qpio_enable(
703	__in		efx_txq_t *etp);
704
705extern			void
706ef10_tx_qpio_disable(
707	__in		efx_txq_t *etp);
708
709extern	__checkReturn	efx_rc_t
710ef10_tx_qpio_write(
711	__in			efx_txq_t *etp,
712	__in_ecount(buf_length)	uint8_t *buffer,
713	__in			size_t buf_length,
714	__in			size_t pio_buf_offset);
715
716extern	__checkReturn	efx_rc_t
717ef10_tx_qpio_post(
718	__in			efx_txq_t *etp,
719	__in			size_t pkt_length,
720	__in			unsigned int completed,
721	__inout			unsigned int *addedp);
722
723extern	__checkReturn	efx_rc_t
724ef10_tx_qdesc_post(
725	__in		efx_txq_t *etp,
726	__in_ecount(n)	efx_desc_t *ed,
727	__in		unsigned int n,
728	__in		unsigned int completed,
729	__inout		unsigned int *addedp);
730
731extern	void
732ef10_tx_qdesc_dma_create(
733	__in	efx_txq_t *etp,
734	__in	efsys_dma_addr_t addr,
735	__in	size_t size,
736	__in	boolean_t eop,
737	__out	efx_desc_t *edp);
738
739extern	void
740ef10_tx_qdesc_tso_create(
741	__in	efx_txq_t *etp,
742	__in	uint16_t ipv4_id,
743	__in	uint32_t tcp_seq,
744	__in	uint8_t	 tcp_flags,
745	__out	efx_desc_t *edp);
746
747extern	void
748ef10_tx_qdesc_tso2_create(
749	__in			efx_txq_t *etp,
750	__in			uint16_t ipv4_id,
751	__in			uint32_t tcp_seq,
752	__in			uint16_t tcp_mss,
753	__out_ecount(count)	efx_desc_t *edp,
754	__in			int count);
755
756extern	void
757ef10_tx_qdesc_vlantci_create(
758	__in	efx_txq_t *etp,
759	__in	uint16_t vlan_tci,
760	__out	efx_desc_t *edp);
761
762extern	void
763ef10_tx_qdesc_checksum_create(
764	__in	efx_txq_t *etp,
765	__in	uint16_t flags,
766	__out	efx_desc_t *edp);
767
768#if EFSYS_OPT_QSTATS
769
770extern			void
771ef10_tx_qstats_update(
772	__in				efx_txq_t *etp,
773	__inout_ecount(TX_NQSTATS)	efsys_stat_t *stat);
774
775#endif /* EFSYS_OPT_QSTATS */
776
777typedef uint32_t	efx_piobuf_handle_t;
778
779#define	EFX_PIOBUF_HANDLE_INVALID	((efx_piobuf_handle_t) -1)
780
781extern	__checkReturn	efx_rc_t
782ef10_nic_pio_alloc(
783	__inout		efx_nic_t *enp,
784	__out		uint32_t *bufnump,
785	__out		efx_piobuf_handle_t *handlep,
786	__out		uint32_t *blknump,
787	__out		uint32_t *offsetp,
788	__out		size_t *sizep);
789
790extern	__checkReturn	efx_rc_t
791ef10_nic_pio_free(
792	__inout		efx_nic_t *enp,
793	__in		uint32_t bufnum,
794	__in		uint32_t blknum);
795
796extern	__checkReturn	efx_rc_t
797ef10_nic_pio_link(
798	__inout		efx_nic_t *enp,
799	__in		uint32_t vi_index,
800	__in		efx_piobuf_handle_t handle);
801
802extern	__checkReturn	efx_rc_t
803ef10_nic_pio_unlink(
804	__inout		efx_nic_t *enp,
805	__in		uint32_t vi_index);
806
807
808/* VPD */
809
810#if EFSYS_OPT_VPD
811
812extern	__checkReturn		efx_rc_t
813ef10_vpd_init(
814	__in			efx_nic_t *enp);
815
816extern	__checkReturn		efx_rc_t
817ef10_vpd_size(
818	__in			efx_nic_t *enp,
819	__out			size_t *sizep);
820
821extern	__checkReturn		efx_rc_t
822ef10_vpd_read(
823	__in			efx_nic_t *enp,
824	__out_bcount(size)	caddr_t data,
825	__in			size_t size);
826
827extern	__checkReturn		efx_rc_t
828ef10_vpd_verify(
829	__in			efx_nic_t *enp,
830	__in_bcount(size)	caddr_t data,
831	__in			size_t size);
832
833extern	__checkReturn		efx_rc_t
834ef10_vpd_reinit(
835	__in			efx_nic_t *enp,
836	__in_bcount(size)	caddr_t data,
837	__in			size_t size);
838
839extern	__checkReturn		efx_rc_t
840ef10_vpd_get(
841	__in			efx_nic_t *enp,
842	__in_bcount(size)	caddr_t data,
843	__in			size_t size,
844	__inout			efx_vpd_value_t *evvp);
845
846extern	__checkReturn		efx_rc_t
847ef10_vpd_set(
848	__in			efx_nic_t *enp,
849	__in_bcount(size)	caddr_t data,
850	__in			size_t size,
851	__in			efx_vpd_value_t *evvp);
852
853extern	__checkReturn		efx_rc_t
854ef10_vpd_next(
855	__in			efx_nic_t *enp,
856	__in_bcount(size)	caddr_t data,
857	__in			size_t size,
858	__out			efx_vpd_value_t *evvp,
859	__inout			unsigned int *contp);
860
861extern __checkReturn		efx_rc_t
862ef10_vpd_write(
863	__in			efx_nic_t *enp,
864	__in_bcount(size)	caddr_t data,
865	__in			size_t size);
866
867extern				void
868ef10_vpd_fini(
869	__in			efx_nic_t *enp);
870
871#endif	/* EFSYS_OPT_VPD */
872
873
874/* RX */
875
876extern	__checkReturn	efx_rc_t
877ef10_rx_init(
878	__in		efx_nic_t *enp);
879
880#if EFSYS_OPT_RX_SCATTER
881extern	__checkReturn	efx_rc_t
882ef10_rx_scatter_enable(
883	__in		efx_nic_t *enp,
884	__in		unsigned int buf_size);
885#endif	/* EFSYS_OPT_RX_SCATTER */
886
887
888#if EFSYS_OPT_RX_SCALE
889
890extern	__checkReturn	efx_rc_t
891ef10_rx_scale_mode_set(
892	__in		efx_nic_t *enp,
893	__in		efx_rx_hash_alg_t alg,
894	__in		efx_rx_hash_type_t type,
895	__in		boolean_t insert);
896
897extern	__checkReturn	efx_rc_t
898ef10_rx_scale_key_set(
899	__in		efx_nic_t *enp,
900	__in_ecount(n)	uint8_t *key,
901	__in		size_t n);
902
903extern	__checkReturn	efx_rc_t
904ef10_rx_scale_tbl_set(
905	__in		efx_nic_t *enp,
906	__in_ecount(n)	unsigned int *table,
907	__in		size_t n);
908
909extern	__checkReturn	uint32_t
910ef10_rx_prefix_hash(
911	__in		efx_nic_t *enp,
912	__in		efx_rx_hash_alg_t func,
913	__in		uint8_t *buffer);
914
915#endif /* EFSYS_OPT_RX_SCALE */
916
917extern	__checkReturn	efx_rc_t
918ef10_rx_prefix_pktlen(
919	__in		efx_nic_t *enp,
920	__in		uint8_t *buffer,
921	__out		uint16_t *lengthp);
922
923extern			void
924ef10_rx_qpost(
925	__in		efx_rxq_t *erp,
926	__in_ecount(n)	efsys_dma_addr_t *addrp,
927	__in		size_t size,
928	__in		unsigned int n,
929	__in		unsigned int completed,
930	__in		unsigned int added);
931
932extern			void
933ef10_rx_qpush(
934	__in		efx_rxq_t *erp,
935	__in		unsigned int added,
936	__inout		unsigned int *pushedp);
937
938extern	__checkReturn	efx_rc_t
939ef10_rx_qflush(
940	__in		efx_rxq_t *erp);
941
942extern		void
943ef10_rx_qenable(
944	__in		efx_rxq_t *erp);
945
946extern	__checkReturn	efx_rc_t
947ef10_rx_qcreate(
948	__in		efx_nic_t *enp,
949	__in		unsigned int index,
950	__in		unsigned int label,
951	__in		efx_rxq_type_t type,
952	__in		efsys_mem_t *esmp,
953	__in		size_t n,
954	__in		uint32_t id,
955	__in		efx_evq_t *eep,
956	__in		efx_rxq_t *erp);
957
958extern			void
959ef10_rx_qdestroy(
960	__in		efx_rxq_t *erp);
961
962extern			void
963ef10_rx_fini(
964	__in		efx_nic_t *enp);
965
966#if EFSYS_OPT_FILTER
967
968typedef struct ef10_filter_handle_s {
969	uint32_t	efh_lo;
970	uint32_t	efh_hi;
971} ef10_filter_handle_t;
972
973typedef struct ef10_filter_entry_s {
974	uintptr_t efe_spec; /* pointer to filter spec plus busy bit */
975	ef10_filter_handle_t efe_handle;
976} ef10_filter_entry_t;
977
978/*
979 * BUSY flag indicates that an update is in progress.
980 * AUTO_OLD flag is used to mark and sweep MAC packet filters.
981 */
982#define	EFX_EF10_FILTER_FLAG_BUSY	1U
983#define	EFX_EF10_FILTER_FLAG_AUTO_OLD	2U
984#define	EFX_EF10_FILTER_FLAGS		3U
985
986/*
987 * Size of the hash table used by the driver. Doesn't need to be the
988 * same size as the hardware's table.
989 */
990#define	EFX_EF10_FILTER_TBL_ROWS 8192
991
992/* Only need to allow for one directed and one unknown unicast filter */
993#define	EFX_EF10_FILTER_UNICAST_FILTERS_MAX	2
994
995/* Allow for the broadcast address to be added to the multicast list */
996#define	EFX_EF10_FILTER_MULTICAST_FILTERS_MAX	(EFX_MAC_MULTICAST_LIST_MAX + 1)
997
998/*
999 * For encapsulated packets, there is one filter each for each combination of
1000 * IPv4 or IPv6 outer frame, VXLAN, GENEVE or NVGRE packet type, and unicast or
1001 * multicast inner frames.
1002 */
1003#define EFX_EF10_FILTER_ENCAP_FILTERS_MAX	12
1004
1005typedef struct ef10_filter_table_s {
1006	ef10_filter_entry_t	eft_entry[EFX_EF10_FILTER_TBL_ROWS];
1007	efx_rxq_t		*eft_default_rxq;
1008	boolean_t		eft_using_rss;
1009	uint32_t		eft_unicst_filter_indexes[
1010	    EFX_EF10_FILTER_UNICAST_FILTERS_MAX];
1011	uint32_t		eft_unicst_filter_count;
1012	uint32_t		eft_mulcst_filter_indexes[
1013	    EFX_EF10_FILTER_MULTICAST_FILTERS_MAX];
1014	uint32_t		eft_mulcst_filter_count;
1015	boolean_t		eft_using_all_mulcst;
1016	uint32_t		eft_encap_filter_indexes[
1017	    EFX_EF10_FILTER_ENCAP_FILTERS_MAX];
1018	uint32_t		eft_encap_filter_count;
1019} ef10_filter_table_t;
1020
1021	__checkReturn	efx_rc_t
1022ef10_filter_init(
1023	__in		efx_nic_t *enp);
1024
1025			void
1026ef10_filter_fini(
1027	__in		efx_nic_t *enp);
1028
1029	__checkReturn	efx_rc_t
1030ef10_filter_restore(
1031	__in		efx_nic_t *enp);
1032
1033	__checkReturn	efx_rc_t
1034ef10_filter_add(
1035	__in		efx_nic_t *enp,
1036	__inout		efx_filter_spec_t *spec,
1037	__in		boolean_t may_replace);
1038
1039	__checkReturn	efx_rc_t
1040ef10_filter_delete(
1041	__in		efx_nic_t *enp,
1042	__inout		efx_filter_spec_t *spec);
1043
1044extern	__checkReturn	efx_rc_t
1045ef10_filter_supported_filters(
1046	__in				efx_nic_t *enp,
1047	__out_ecount(buffer_length)	uint32_t *buffer,
1048	__in				size_t buffer_length,
1049	__out				size_t *list_lengthp);
1050
1051extern	__checkReturn	efx_rc_t
1052ef10_filter_reconfigure(
1053	__in				efx_nic_t *enp,
1054	__in_ecount(6)			uint8_t const *mac_addr,
1055	__in				boolean_t all_unicst,
1056	__in				boolean_t mulcst,
1057	__in				boolean_t all_mulcst,
1058	__in				boolean_t brdcst,
1059	__in_ecount(6*count)		uint8_t const *addrs,
1060	__in				uint32_t count);
1061
1062extern		void
1063ef10_filter_get_default_rxq(
1064	__in		efx_nic_t *enp,
1065	__out		efx_rxq_t **erpp,
1066	__out		boolean_t *using_rss);
1067
1068extern		void
1069ef10_filter_default_rxq_set(
1070	__in		efx_nic_t *enp,
1071	__in		efx_rxq_t *erp,
1072	__in		boolean_t using_rss);
1073
1074extern		void
1075ef10_filter_default_rxq_clear(
1076	__in		efx_nic_t *enp);
1077
1078
1079#endif /* EFSYS_OPT_FILTER */
1080
1081extern	__checkReturn			efx_rc_t
1082efx_mcdi_get_function_info(
1083	__in				efx_nic_t *enp,
1084	__out				uint32_t *pfp,
1085	__out_opt			uint32_t *vfp);
1086
1087extern	__checkReturn		efx_rc_t
1088efx_mcdi_privilege_mask(
1089	__in			efx_nic_t *enp,
1090	__in			uint32_t pf,
1091	__in			uint32_t vf,
1092	__out			uint32_t *maskp);
1093
1094extern	__checkReturn	efx_rc_t
1095efx_mcdi_get_port_assignment(
1096	__in		efx_nic_t *enp,
1097	__out		uint32_t *portp);
1098
1099extern	__checkReturn	efx_rc_t
1100efx_mcdi_get_port_modes(
1101	__in		efx_nic_t *enp,
1102	__out		uint32_t *modesp,
1103	__out_opt	uint32_t *current_modep);
1104
1105extern	__checkReturn	efx_rc_t
1106ef10_nic_get_port_mode_bandwidth(
1107	__in		uint32_t port_mode,
1108	__out		uint32_t *bandwidth_mbpsp);
1109
1110extern	__checkReturn	efx_rc_t
1111efx_mcdi_get_mac_address_pf(
1112	__in			efx_nic_t *enp,
1113	__out_ecount_opt(6)	uint8_t mac_addrp[6]);
1114
1115extern	__checkReturn	efx_rc_t
1116efx_mcdi_get_mac_address_vf(
1117	__in			efx_nic_t *enp,
1118	__out_ecount_opt(6)	uint8_t mac_addrp[6]);
1119
1120extern	__checkReturn	efx_rc_t
1121efx_mcdi_get_clock(
1122	__in		efx_nic_t *enp,
1123	__out		uint32_t *sys_freqp,
1124	__out		uint32_t *dpcpu_freqp);
1125
1126
1127extern	__checkReturn	efx_rc_t
1128efx_mcdi_get_vector_cfg(
1129	__in		efx_nic_t *enp,
1130	__out_opt	uint32_t *vec_basep,
1131	__out_opt	uint32_t *pf_nvecp,
1132	__out_opt	uint32_t *vf_nvecp);
1133
1134extern	__checkReturn	efx_rc_t
1135ef10_get_datapath_caps(
1136	__in		efx_nic_t *enp);
1137
1138extern	__checkReturn		efx_rc_t
1139ef10_get_privilege_mask(
1140	__in			efx_nic_t *enp,
1141	__out			uint32_t *maskp);
1142
1143extern	__checkReturn	efx_rc_t
1144ef10_external_port_mapping(
1145	__in		efx_nic_t *enp,
1146	__in		uint32_t port,
1147	__out		uint8_t *external_portp);
1148
1149
1150#ifdef	__cplusplus
1151}
1152#endif
1153
1154#endif	/* _SYS_EF10_IMPL_H */
1155