ef10_impl.h revision 310944
1/*- 2 * Copyright (c) 2015-2016 Solarflare Communications Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * The views and conclusions contained in the software and documentation are 27 * those of the authors and should not be interpreted as representing official 28 * policies, either expressed or implied, of the FreeBSD Project. 29 * 30 * $FreeBSD: stable/11/sys/dev/sfxge/common/ef10_impl.h 310944 2016-12-31 11:26:29Z arybchik $ 31 */ 32 33#ifndef _SYS_EF10_IMPL_H 34#define _SYS_EF10_IMPL_H 35 36#ifdef __cplusplus 37extern "C" { 38#endif 39 40#if (EFSYS_OPT_HUNTINGTON && EFSYS_OPT_MEDFORD) 41#define EF10_MAX_PIOBUF_NBUFS MAX(HUNT_PIOBUF_NBUFS, MEDFORD_PIOBUF_NBUFS) 42#elif EFSYS_OPT_HUNTINGTON 43#define EF10_MAX_PIOBUF_NBUFS HUNT_PIOBUF_NBUFS 44#elif EFSYS_OPT_MEDFORD 45#define EF10_MAX_PIOBUF_NBUFS MEDFORD_PIOBUF_NBUFS 46#endif 47 48/* 49 * FIXME: This is just a power of 2 which fits in an MCDI v1 message, and could 50 * possibly be increased, or the write size reported by newer firmware used 51 * instead. 52 */ 53#define EF10_NVRAM_CHUNK 0x80 54 55/* Alignment requirement for value written to RX WPTR: 56 * the WPTR must be aligned to an 8 descriptor boundary 57 */ 58#define EF10_RX_WPTR_ALIGN 8 59 60/* 61 * Max byte offset into the packet the TCP header must start for the hardware 62 * to be able to parse the packet correctly. 63 */ 64#define EF10_TCP_HEADER_OFFSET_LIMIT 208 65 66/* Invalid RSS context handle */ 67#define EF10_RSS_CONTEXT_INVALID (0xffffffff) 68 69 70/* EV */ 71 72 __checkReturn efx_rc_t 73ef10_ev_init( 74 __in efx_nic_t *enp); 75 76 void 77ef10_ev_fini( 78 __in efx_nic_t *enp); 79 80 __checkReturn efx_rc_t 81ef10_ev_qcreate( 82 __in efx_nic_t *enp, 83 __in unsigned int index, 84 __in efsys_mem_t *esmp, 85 __in size_t n, 86 __in uint32_t id, 87 __in uint32_t us, 88 __in uint32_t flags, 89 __in efx_evq_t *eep); 90 91 void 92ef10_ev_qdestroy( 93 __in efx_evq_t *eep); 94 95 __checkReturn efx_rc_t 96ef10_ev_qprime( 97 __in efx_evq_t *eep, 98 __in unsigned int count); 99 100 void 101ef10_ev_qpost( 102 __in efx_evq_t *eep, 103 __in uint16_t data); 104 105 __checkReturn efx_rc_t 106ef10_ev_qmoderate( 107 __in efx_evq_t *eep, 108 __in unsigned int us); 109 110#if EFSYS_OPT_QSTATS 111 void 112ef10_ev_qstats_update( 113 __in efx_evq_t *eep, 114 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat); 115#endif /* EFSYS_OPT_QSTATS */ 116 117 void 118ef10_ev_rxlabel_init( 119 __in efx_evq_t *eep, 120 __in efx_rxq_t *erp, 121 __in unsigned int label); 122 123 void 124ef10_ev_rxlabel_fini( 125 __in efx_evq_t *eep, 126 __in unsigned int label); 127 128/* INTR */ 129 130 __checkReturn efx_rc_t 131ef10_intr_init( 132 __in efx_nic_t *enp, 133 __in efx_intr_type_t type, 134 __in efsys_mem_t *esmp); 135 136 void 137ef10_intr_enable( 138 __in efx_nic_t *enp); 139 140 void 141ef10_intr_disable( 142 __in efx_nic_t *enp); 143 144 void 145ef10_intr_disable_unlocked( 146 __in efx_nic_t *enp); 147 148 __checkReturn efx_rc_t 149ef10_intr_trigger( 150 __in efx_nic_t *enp, 151 __in unsigned int level); 152 153 void 154ef10_intr_status_line( 155 __in efx_nic_t *enp, 156 __out boolean_t *fatalp, 157 __out uint32_t *qmaskp); 158 159 void 160ef10_intr_status_message( 161 __in efx_nic_t *enp, 162 __in unsigned int message, 163 __out boolean_t *fatalp); 164 165 void 166ef10_intr_fatal( 167 __in efx_nic_t *enp); 168 void 169ef10_intr_fini( 170 __in efx_nic_t *enp); 171 172/* NIC */ 173 174extern __checkReturn efx_rc_t 175ef10_nic_probe( 176 __in efx_nic_t *enp); 177 178extern __checkReturn efx_rc_t 179ef10_nic_set_drv_limits( 180 __inout efx_nic_t *enp, 181 __in efx_drv_limits_t *edlp); 182 183extern __checkReturn efx_rc_t 184ef10_nic_get_vi_pool( 185 __in efx_nic_t *enp, 186 __out uint32_t *vi_countp); 187 188extern __checkReturn efx_rc_t 189ef10_nic_get_bar_region( 190 __in efx_nic_t *enp, 191 __in efx_nic_region_t region, 192 __out uint32_t *offsetp, 193 __out size_t *sizep); 194 195extern __checkReturn efx_rc_t 196ef10_nic_reset( 197 __in efx_nic_t *enp); 198 199extern __checkReturn efx_rc_t 200ef10_nic_init( 201 __in efx_nic_t *enp); 202 203#if EFSYS_OPT_DIAG 204 205extern __checkReturn efx_rc_t 206ef10_nic_register_test( 207 __in efx_nic_t *enp); 208 209#endif /* EFSYS_OPT_DIAG */ 210 211extern void 212ef10_nic_fini( 213 __in efx_nic_t *enp); 214 215extern void 216ef10_nic_unprobe( 217 __in efx_nic_t *enp); 218 219 220/* MAC */ 221 222extern __checkReturn efx_rc_t 223ef10_mac_poll( 224 __in efx_nic_t *enp, 225 __out efx_link_mode_t *link_modep); 226 227extern __checkReturn efx_rc_t 228ef10_mac_up( 229 __in efx_nic_t *enp, 230 __out boolean_t *mac_upp); 231 232extern __checkReturn efx_rc_t 233ef10_mac_addr_set( 234 __in efx_nic_t *enp); 235 236extern __checkReturn efx_rc_t 237ef10_mac_pdu_set( 238 __in efx_nic_t *enp); 239 240extern __checkReturn efx_rc_t 241ef10_mac_pdu_get( 242 __in efx_nic_t *enp, 243 __out size_t *pdu); 244 245extern __checkReturn efx_rc_t 246ef10_mac_reconfigure( 247 __in efx_nic_t *enp); 248 249extern __checkReturn efx_rc_t 250ef10_mac_multicast_list_set( 251 __in efx_nic_t *enp); 252 253extern __checkReturn efx_rc_t 254ef10_mac_filter_default_rxq_set( 255 __in efx_nic_t *enp, 256 __in efx_rxq_t *erp, 257 __in boolean_t using_rss); 258 259extern void 260ef10_mac_filter_default_rxq_clear( 261 __in efx_nic_t *enp); 262 263#if EFSYS_OPT_LOOPBACK 264 265extern __checkReturn efx_rc_t 266ef10_mac_loopback_set( 267 __in efx_nic_t *enp, 268 __in efx_link_mode_t link_mode, 269 __in efx_loopback_type_t loopback_type); 270 271#endif /* EFSYS_OPT_LOOPBACK */ 272 273#if EFSYS_OPT_MAC_STATS 274 275extern __checkReturn efx_rc_t 276ef10_mac_stats_update( 277 __in efx_nic_t *enp, 278 __in efsys_mem_t *esmp, 279 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat, 280 __inout_opt uint32_t *generationp); 281 282#endif /* EFSYS_OPT_MAC_STATS */ 283 284 285/* MCDI */ 286 287#if EFSYS_OPT_MCDI 288 289extern __checkReturn efx_rc_t 290ef10_mcdi_init( 291 __in efx_nic_t *enp, 292 __in const efx_mcdi_transport_t *mtp); 293 294extern void 295ef10_mcdi_fini( 296 __in efx_nic_t *enp); 297 298extern void 299ef10_mcdi_send_request( 300 __in efx_nic_t *enp, 301 __in_bcount(hdr_len) void *hdrp, 302 __in size_t hdr_len, 303 __in_bcount(sdu_len) void *sdup, 304 __in size_t sdu_len); 305 306extern __checkReturn boolean_t 307ef10_mcdi_poll_response( 308 __in efx_nic_t *enp); 309 310extern void 311ef10_mcdi_read_response( 312 __in efx_nic_t *enp, 313 __out_bcount(length) void *bufferp, 314 __in size_t offset, 315 __in size_t length); 316 317extern efx_rc_t 318ef10_mcdi_poll_reboot( 319 __in efx_nic_t *enp); 320 321extern __checkReturn efx_rc_t 322ef10_mcdi_feature_supported( 323 __in efx_nic_t *enp, 324 __in efx_mcdi_feature_id_t id, 325 __out boolean_t *supportedp); 326 327#endif /* EFSYS_OPT_MCDI */ 328 329/* NVRAM */ 330 331#if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD 332 333extern __checkReturn efx_rc_t 334ef10_nvram_buf_read_tlv( 335 __in efx_nic_t *enp, 336 __in_bcount(max_seg_size) caddr_t seg_data, 337 __in size_t max_seg_size, 338 __in uint32_t tag, 339 __deref_out_bcount_opt(*sizep) caddr_t *datap, 340 __out size_t *sizep); 341 342extern __checkReturn efx_rc_t 343ef10_nvram_buf_write_tlv( 344 __inout_bcount(partn_size) caddr_t partn_data, 345 __in size_t partn_size, 346 __in uint32_t tag, 347 __in_bcount(tag_size) caddr_t tag_data, 348 __in size_t tag_size, 349 __out size_t *total_lengthp); 350 351extern __checkReturn efx_rc_t 352ef10_nvram_partn_read_tlv( 353 __in efx_nic_t *enp, 354 __in uint32_t partn, 355 __in uint32_t tag, 356 __deref_out_bcount_opt(*sizep) caddr_t *datap, 357 __out size_t *sizep); 358 359extern __checkReturn efx_rc_t 360ef10_nvram_partn_write_tlv( 361 __in efx_nic_t *enp, 362 __in uint32_t partn, 363 __in uint32_t tag, 364 __in_bcount(size) caddr_t data, 365 __in size_t size); 366 367extern __checkReturn efx_rc_t 368ef10_nvram_partn_write_segment_tlv( 369 __in efx_nic_t *enp, 370 __in uint32_t partn, 371 __in uint32_t tag, 372 __in_bcount(size) caddr_t data, 373 __in size_t size, 374 __in boolean_t all_segments); 375 376extern __checkReturn efx_rc_t 377ef10_nvram_partn_lock( 378 __in efx_nic_t *enp, 379 __in uint32_t partn); 380 381extern void 382ef10_nvram_partn_unlock( 383 __in efx_nic_t *enp, 384 __in uint32_t partn); 385 386#endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */ 387 388#if EFSYS_OPT_NVRAM 389 390#if EFSYS_OPT_DIAG 391 392extern __checkReturn efx_rc_t 393ef10_nvram_test( 394 __in efx_nic_t *enp); 395 396#endif /* EFSYS_OPT_DIAG */ 397 398extern __checkReturn efx_rc_t 399ef10_nvram_type_to_partn( 400 __in efx_nic_t *enp, 401 __in efx_nvram_type_t type, 402 __out uint32_t *partnp); 403 404extern __checkReturn efx_rc_t 405ef10_nvram_partn_size( 406 __in efx_nic_t *enp, 407 __in uint32_t partn, 408 __out size_t *sizep); 409 410extern __checkReturn efx_rc_t 411ef10_nvram_partn_rw_start( 412 __in efx_nic_t *enp, 413 __in uint32_t partn, 414 __out size_t *chunk_sizep); 415 416extern __checkReturn efx_rc_t 417ef10_nvram_partn_read_mode( 418 __in efx_nic_t *enp, 419 __in uint32_t partn, 420 __in unsigned int offset, 421 __out_bcount(size) caddr_t data, 422 __in size_t size, 423 __in uint32_t mode); 424 425extern __checkReturn efx_rc_t 426ef10_nvram_partn_read( 427 __in efx_nic_t *enp, 428 __in uint32_t partn, 429 __in unsigned int offset, 430 __out_bcount(size) caddr_t data, 431 __in size_t size); 432 433extern __checkReturn efx_rc_t 434ef10_nvram_partn_erase( 435 __in efx_nic_t *enp, 436 __in uint32_t partn, 437 __in unsigned int offset, 438 __in size_t size); 439 440extern __checkReturn efx_rc_t 441ef10_nvram_partn_write( 442 __in efx_nic_t *enp, 443 __in uint32_t partn, 444 __in unsigned int offset, 445 __out_bcount(size) caddr_t data, 446 __in size_t size); 447 448extern void 449ef10_nvram_partn_rw_finish( 450 __in efx_nic_t *enp, 451 __in uint32_t partn); 452 453extern __checkReturn efx_rc_t 454ef10_nvram_partn_get_version( 455 __in efx_nic_t *enp, 456 __in uint32_t partn, 457 __out uint32_t *subtypep, 458 __out_ecount(4) uint16_t version[4]); 459 460extern __checkReturn efx_rc_t 461ef10_nvram_partn_set_version( 462 __in efx_nic_t *enp, 463 __in uint32_t partn, 464 __in_ecount(4) uint16_t version[4]); 465 466extern __checkReturn efx_rc_t 467ef10_nvram_buffer_validate( 468 __in efx_nic_t *enp, 469 __in uint32_t partn, 470 __in_bcount(buffer_size) 471 caddr_t bufferp, 472 __in size_t buffer_size); 473 474extern __checkReturn efx_rc_t 475ef10_nvram_buffer_create( 476 __in efx_nic_t *enp, 477 __in uint16_t partn_type, 478 __in_bcount(buffer_size) 479 caddr_t bufferp, 480 __in size_t buffer_size); 481 482extern __checkReturn efx_rc_t 483ef10_nvram_buffer_find_item_start( 484 __in_bcount(buffer_size) 485 caddr_t bufferp, 486 __in size_t buffer_size, 487 __out uint32_t *startp 488 ); 489 490extern __checkReturn efx_rc_t 491ef10_nvram_buffer_find_end( 492 __in_bcount(buffer_size) 493 caddr_t bufferp, 494 __in size_t buffer_size, 495 __in uint32_t offset, 496 __out uint32_t *endp 497 ); 498 499extern __checkReturn __success(return != B_FALSE) boolean_t 500ef10_nvram_buffer_find_item( 501 __in_bcount(buffer_size) 502 caddr_t bufferp, 503 __in size_t buffer_size, 504 __in uint32_t offset, 505 __out uint32_t *startp, 506 __out uint32_t *lengthp 507 ); 508 509extern __checkReturn efx_rc_t 510ef10_nvram_buffer_get_item( 511 __in_bcount(buffer_size) 512 caddr_t bufferp, 513 __in size_t buffer_size, 514 __in uint32_t offset, 515 __in uint32_t length, 516 __out_bcount_part(item_max_size, *lengthp) 517 caddr_t itemp, 518 __in size_t item_max_size, 519 __out uint32_t *lengthp 520 ); 521 522extern __checkReturn efx_rc_t 523ef10_nvram_buffer_insert_item( 524 __in_bcount(buffer_size) 525 caddr_t bufferp, 526 __in size_t buffer_size, 527 __in uint32_t offset, 528 __in_bcount(length) caddr_t keyp, 529 __in uint32_t length, 530 __out uint32_t *lengthp 531 ); 532 533extern __checkReturn efx_rc_t 534ef10_nvram_buffer_delete_item( 535 __in_bcount(buffer_size) 536 caddr_t bufferp, 537 __in size_t buffer_size, 538 __in uint32_t offset, 539 __in uint32_t length, 540 __in uint32_t end 541 ); 542 543extern __checkReturn efx_rc_t 544ef10_nvram_buffer_finish( 545 __in_bcount(buffer_size) 546 caddr_t bufferp, 547 __in size_t buffer_size 548 ); 549 550#endif /* EFSYS_OPT_NVRAM */ 551 552 553/* PHY */ 554 555typedef struct ef10_link_state_s { 556 uint32_t els_adv_cap_mask; 557 uint32_t els_lp_cap_mask; 558 unsigned int els_fcntl; 559 efx_link_mode_t els_link_mode; 560#if EFSYS_OPT_LOOPBACK 561 efx_loopback_type_t els_loopback; 562#endif 563 boolean_t els_mac_up; 564} ef10_link_state_t; 565 566extern void 567ef10_phy_link_ev( 568 __in efx_nic_t *enp, 569 __in efx_qword_t *eqp, 570 __out efx_link_mode_t *link_modep); 571 572extern __checkReturn efx_rc_t 573ef10_phy_get_link( 574 __in efx_nic_t *enp, 575 __out ef10_link_state_t *elsp); 576 577extern __checkReturn efx_rc_t 578ef10_phy_power( 579 __in efx_nic_t *enp, 580 __in boolean_t on); 581 582extern __checkReturn efx_rc_t 583ef10_phy_reconfigure( 584 __in efx_nic_t *enp); 585 586extern __checkReturn efx_rc_t 587ef10_phy_verify( 588 __in efx_nic_t *enp); 589 590extern __checkReturn efx_rc_t 591ef10_phy_oui_get( 592 __in efx_nic_t *enp, 593 __out uint32_t *ouip); 594 595#if EFSYS_OPT_PHY_STATS 596 597extern __checkReturn efx_rc_t 598ef10_phy_stats_update( 599 __in efx_nic_t *enp, 600 __in efsys_mem_t *esmp, 601 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat); 602 603#endif /* EFSYS_OPT_PHY_STATS */ 604 605#if EFSYS_OPT_BIST 606 607extern __checkReturn efx_rc_t 608ef10_bist_enable_offline( 609 __in efx_nic_t *enp); 610 611extern __checkReturn efx_rc_t 612ef10_bist_start( 613 __in efx_nic_t *enp, 614 __in efx_bist_type_t type); 615 616extern __checkReturn efx_rc_t 617ef10_bist_poll( 618 __in efx_nic_t *enp, 619 __in efx_bist_type_t type, 620 __out efx_bist_result_t *resultp, 621 __out_opt __drv_when(count > 0, __notnull) 622 uint32_t *value_maskp, 623 __out_ecount_opt(count) __drv_when(count > 0, __notnull) 624 unsigned long *valuesp, 625 __in size_t count); 626 627extern void 628ef10_bist_stop( 629 __in efx_nic_t *enp, 630 __in efx_bist_type_t type); 631 632#endif /* EFSYS_OPT_BIST */ 633 634/* TX */ 635 636extern __checkReturn efx_rc_t 637ef10_tx_init( 638 __in efx_nic_t *enp); 639 640extern void 641ef10_tx_fini( 642 __in efx_nic_t *enp); 643 644extern __checkReturn efx_rc_t 645ef10_tx_qcreate( 646 __in efx_nic_t *enp, 647 __in unsigned int index, 648 __in unsigned int label, 649 __in efsys_mem_t *esmp, 650 __in size_t n, 651 __in uint32_t id, 652 __in uint16_t flags, 653 __in efx_evq_t *eep, 654 __in efx_txq_t *etp, 655 __out unsigned int *addedp); 656 657extern void 658ef10_tx_qdestroy( 659 __in efx_txq_t *etp); 660 661extern __checkReturn efx_rc_t 662ef10_tx_qpost( 663 __in efx_txq_t *etp, 664 __in_ecount(n) efx_buffer_t *eb, 665 __in unsigned int n, 666 __in unsigned int completed, 667 __inout unsigned int *addedp); 668 669extern void 670ef10_tx_qpush( 671 __in efx_txq_t *etp, 672 __in unsigned int added, 673 __in unsigned int pushed); 674 675extern __checkReturn efx_rc_t 676ef10_tx_qpace( 677 __in efx_txq_t *etp, 678 __in unsigned int ns); 679 680extern __checkReturn efx_rc_t 681ef10_tx_qflush( 682 __in efx_txq_t *etp); 683 684extern void 685ef10_tx_qenable( 686 __in efx_txq_t *etp); 687 688extern __checkReturn efx_rc_t 689ef10_tx_qpio_enable( 690 __in efx_txq_t *etp); 691 692extern void 693ef10_tx_qpio_disable( 694 __in efx_txq_t *etp); 695 696extern __checkReturn efx_rc_t 697ef10_tx_qpio_write( 698 __in efx_txq_t *etp, 699 __in_ecount(buf_length) uint8_t *buffer, 700 __in size_t buf_length, 701 __in size_t pio_buf_offset); 702 703extern __checkReturn efx_rc_t 704ef10_tx_qpio_post( 705 __in efx_txq_t *etp, 706 __in size_t pkt_length, 707 __in unsigned int completed, 708 __inout unsigned int *addedp); 709 710extern __checkReturn efx_rc_t 711ef10_tx_qdesc_post( 712 __in efx_txq_t *etp, 713 __in_ecount(n) efx_desc_t *ed, 714 __in unsigned int n, 715 __in unsigned int completed, 716 __inout unsigned int *addedp); 717 718extern void 719ef10_tx_qdesc_dma_create( 720 __in efx_txq_t *etp, 721 __in efsys_dma_addr_t addr, 722 __in size_t size, 723 __in boolean_t eop, 724 __out efx_desc_t *edp); 725 726extern void 727ef10_tx_qdesc_tso_create( 728 __in efx_txq_t *etp, 729 __in uint16_t ipv4_id, 730 __in uint32_t tcp_seq, 731 __in uint8_t tcp_flags, 732 __out efx_desc_t *edp); 733 734extern void 735ef10_tx_qdesc_tso2_create( 736 __in efx_txq_t *etp, 737 __in uint16_t ipv4_id, 738 __in uint32_t tcp_seq, 739 __in uint16_t tcp_mss, 740 __out_ecount(count) efx_desc_t *edp, 741 __in int count); 742 743extern void 744ef10_tx_qdesc_vlantci_create( 745 __in efx_txq_t *etp, 746 __in uint16_t vlan_tci, 747 __out efx_desc_t *edp); 748 749 750#if EFSYS_OPT_QSTATS 751 752extern void 753ef10_tx_qstats_update( 754 __in efx_txq_t *etp, 755 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat); 756 757#endif /* EFSYS_OPT_QSTATS */ 758 759typedef uint32_t efx_piobuf_handle_t; 760 761#define EFX_PIOBUF_HANDLE_INVALID ((efx_piobuf_handle_t) -1) 762 763extern __checkReturn efx_rc_t 764ef10_nic_pio_alloc( 765 __inout efx_nic_t *enp, 766 __out uint32_t *bufnump, 767 __out efx_piobuf_handle_t *handlep, 768 __out uint32_t *blknump, 769 __out uint32_t *offsetp, 770 __out size_t *sizep); 771 772extern __checkReturn efx_rc_t 773ef10_nic_pio_free( 774 __inout efx_nic_t *enp, 775 __in uint32_t bufnum, 776 __in uint32_t blknum); 777 778extern __checkReturn efx_rc_t 779ef10_nic_pio_link( 780 __inout efx_nic_t *enp, 781 __in uint32_t vi_index, 782 __in efx_piobuf_handle_t handle); 783 784extern __checkReturn efx_rc_t 785ef10_nic_pio_unlink( 786 __inout efx_nic_t *enp, 787 __in uint32_t vi_index); 788 789 790/* VPD */ 791 792#if EFSYS_OPT_VPD 793 794extern __checkReturn efx_rc_t 795ef10_vpd_init( 796 __in efx_nic_t *enp); 797 798extern __checkReturn efx_rc_t 799ef10_vpd_size( 800 __in efx_nic_t *enp, 801 __out size_t *sizep); 802 803extern __checkReturn efx_rc_t 804ef10_vpd_read( 805 __in efx_nic_t *enp, 806 __out_bcount(size) caddr_t data, 807 __in size_t size); 808 809extern __checkReturn efx_rc_t 810ef10_vpd_verify( 811 __in efx_nic_t *enp, 812 __in_bcount(size) caddr_t data, 813 __in size_t size); 814 815extern __checkReturn efx_rc_t 816ef10_vpd_reinit( 817 __in efx_nic_t *enp, 818 __in_bcount(size) caddr_t data, 819 __in size_t size); 820 821extern __checkReturn efx_rc_t 822ef10_vpd_get( 823 __in efx_nic_t *enp, 824 __in_bcount(size) caddr_t data, 825 __in size_t size, 826 __inout efx_vpd_value_t *evvp); 827 828extern __checkReturn efx_rc_t 829ef10_vpd_set( 830 __in efx_nic_t *enp, 831 __in_bcount(size) caddr_t data, 832 __in size_t size, 833 __in efx_vpd_value_t *evvp); 834 835extern __checkReturn efx_rc_t 836ef10_vpd_next( 837 __in efx_nic_t *enp, 838 __in_bcount(size) caddr_t data, 839 __in size_t size, 840 __out efx_vpd_value_t *evvp, 841 __inout unsigned int *contp); 842 843extern __checkReturn efx_rc_t 844ef10_vpd_write( 845 __in efx_nic_t *enp, 846 __in_bcount(size) caddr_t data, 847 __in size_t size); 848 849extern void 850ef10_vpd_fini( 851 __in efx_nic_t *enp); 852 853#endif /* EFSYS_OPT_VPD */ 854 855 856/* RX */ 857 858extern __checkReturn efx_rc_t 859ef10_rx_init( 860 __in efx_nic_t *enp); 861 862#if EFSYS_OPT_RX_SCATTER 863extern __checkReturn efx_rc_t 864ef10_rx_scatter_enable( 865 __in efx_nic_t *enp, 866 __in unsigned int buf_size); 867#endif /* EFSYS_OPT_RX_SCATTER */ 868 869 870#if EFSYS_OPT_RX_SCALE 871 872extern __checkReturn efx_rc_t 873ef10_rx_scale_mode_set( 874 __in efx_nic_t *enp, 875 __in efx_rx_hash_alg_t alg, 876 __in efx_rx_hash_type_t type, 877 __in boolean_t insert); 878 879extern __checkReturn efx_rc_t 880ef10_rx_scale_key_set( 881 __in efx_nic_t *enp, 882 __in_ecount(n) uint8_t *key, 883 __in size_t n); 884 885extern __checkReturn efx_rc_t 886ef10_rx_scale_tbl_set( 887 __in efx_nic_t *enp, 888 __in_ecount(n) unsigned int *table, 889 __in size_t n); 890 891extern __checkReturn uint32_t 892ef10_rx_prefix_hash( 893 __in efx_nic_t *enp, 894 __in efx_rx_hash_alg_t func, 895 __in uint8_t *buffer); 896 897#endif /* EFSYS_OPT_RX_SCALE */ 898 899extern __checkReturn efx_rc_t 900ef10_rx_prefix_pktlen( 901 __in efx_nic_t *enp, 902 __in uint8_t *buffer, 903 __out uint16_t *lengthp); 904 905extern void 906ef10_rx_qpost( 907 __in efx_rxq_t *erp, 908 __in_ecount(n) efsys_dma_addr_t *addrp, 909 __in size_t size, 910 __in unsigned int n, 911 __in unsigned int completed, 912 __in unsigned int added); 913 914extern void 915ef10_rx_qpush( 916 __in efx_rxq_t *erp, 917 __in unsigned int added, 918 __inout unsigned int *pushedp); 919 920extern __checkReturn efx_rc_t 921ef10_rx_qflush( 922 __in efx_rxq_t *erp); 923 924extern void 925ef10_rx_qenable( 926 __in efx_rxq_t *erp); 927 928extern __checkReturn efx_rc_t 929ef10_rx_qcreate( 930 __in efx_nic_t *enp, 931 __in unsigned int index, 932 __in unsigned int label, 933 __in efx_rxq_type_t type, 934 __in efsys_mem_t *esmp, 935 __in size_t n, 936 __in uint32_t id, 937 __in efx_evq_t *eep, 938 __in efx_rxq_t *erp); 939 940extern void 941ef10_rx_qdestroy( 942 __in efx_rxq_t *erp); 943 944extern void 945ef10_rx_fini( 946 __in efx_nic_t *enp); 947 948#if EFSYS_OPT_FILTER 949 950typedef struct ef10_filter_handle_s { 951 uint32_t efh_lo; 952 uint32_t efh_hi; 953} ef10_filter_handle_t; 954 955typedef struct ef10_filter_entry_s { 956 uintptr_t efe_spec; /* pointer to filter spec plus busy bit */ 957 ef10_filter_handle_t efe_handle; 958} ef10_filter_entry_t; 959 960/* 961 * BUSY flag indicates that an update is in progress. 962 * AUTO_OLD flag is used to mark and sweep MAC packet filters. 963 */ 964#define EFX_EF10_FILTER_FLAG_BUSY 1U 965#define EFX_EF10_FILTER_FLAG_AUTO_OLD 2U 966#define EFX_EF10_FILTER_FLAGS 3U 967 968/* 969 * Size of the hash table used by the driver. Doesn't need to be the 970 * same size as the hardware's table. 971 */ 972#define EFX_EF10_FILTER_TBL_ROWS 8192 973 974/* Only need to allow for one directed and one unknown unicast filter */ 975#define EFX_EF10_FILTER_UNICAST_FILTERS_MAX 2 976 977/* Allow for the broadcast address to be added to the multicast list */ 978#define EFX_EF10_FILTER_MULTICAST_FILTERS_MAX (EFX_MAC_MULTICAST_LIST_MAX + 1) 979 980typedef struct ef10_filter_table_s { 981 ef10_filter_entry_t eft_entry[EFX_EF10_FILTER_TBL_ROWS]; 982 efx_rxq_t *eft_default_rxq; 983 boolean_t eft_using_rss; 984 uint32_t eft_unicst_filter_indexes[ 985 EFX_EF10_FILTER_UNICAST_FILTERS_MAX]; 986 uint32_t eft_unicst_filter_count; 987 uint32_t eft_mulcst_filter_indexes[ 988 EFX_EF10_FILTER_MULTICAST_FILTERS_MAX]; 989 uint32_t eft_mulcst_filter_count; 990 boolean_t eft_using_all_mulcst; 991} ef10_filter_table_t; 992 993 __checkReturn efx_rc_t 994ef10_filter_init( 995 __in efx_nic_t *enp); 996 997 void 998ef10_filter_fini( 999 __in efx_nic_t *enp); 1000 1001 __checkReturn efx_rc_t 1002ef10_filter_restore( 1003 __in efx_nic_t *enp); 1004 1005 __checkReturn efx_rc_t 1006ef10_filter_add( 1007 __in efx_nic_t *enp, 1008 __inout efx_filter_spec_t *spec, 1009 __in boolean_t may_replace); 1010 1011 __checkReturn efx_rc_t 1012ef10_filter_delete( 1013 __in efx_nic_t *enp, 1014 __inout efx_filter_spec_t *spec); 1015 1016extern __checkReturn efx_rc_t 1017ef10_filter_supported_filters( 1018 __in efx_nic_t *enp, 1019 __out uint32_t *list, 1020 __out size_t *length); 1021 1022extern __checkReturn efx_rc_t 1023ef10_filter_reconfigure( 1024 __in efx_nic_t *enp, 1025 __in_ecount(6) uint8_t const *mac_addr, 1026 __in boolean_t all_unicst, 1027 __in boolean_t mulcst, 1028 __in boolean_t all_mulcst, 1029 __in boolean_t brdcst, 1030 __in_ecount(6*count) uint8_t const *addrs, 1031 __in uint32_t count); 1032 1033extern void 1034ef10_filter_get_default_rxq( 1035 __in efx_nic_t *enp, 1036 __out efx_rxq_t **erpp, 1037 __out boolean_t *using_rss); 1038 1039extern void 1040ef10_filter_default_rxq_set( 1041 __in efx_nic_t *enp, 1042 __in efx_rxq_t *erp, 1043 __in boolean_t using_rss); 1044 1045extern void 1046ef10_filter_default_rxq_clear( 1047 __in efx_nic_t *enp); 1048 1049 1050#endif /* EFSYS_OPT_FILTER */ 1051 1052extern __checkReturn efx_rc_t 1053efx_mcdi_get_function_info( 1054 __in efx_nic_t *enp, 1055 __out uint32_t *pfp, 1056 __out_opt uint32_t *vfp); 1057 1058extern __checkReturn efx_rc_t 1059efx_mcdi_privilege_mask( 1060 __in efx_nic_t *enp, 1061 __in uint32_t pf, 1062 __in uint32_t vf, 1063 __out uint32_t *maskp); 1064 1065extern __checkReturn efx_rc_t 1066efx_mcdi_get_port_assignment( 1067 __in efx_nic_t *enp, 1068 __out uint32_t *portp); 1069 1070extern __checkReturn efx_rc_t 1071efx_mcdi_get_port_modes( 1072 __in efx_nic_t *enp, 1073 __out uint32_t *modesp, 1074 __out_opt uint32_t *current_modep); 1075 1076extern __checkReturn efx_rc_t 1077ef10_nic_get_port_mode_bandwidth( 1078 __in uint32_t port_mode, 1079 __out uint32_t *bandwidth_mbpsp); 1080 1081extern __checkReturn efx_rc_t 1082efx_mcdi_get_mac_address_pf( 1083 __in efx_nic_t *enp, 1084 __out_ecount_opt(6) uint8_t mac_addrp[6]); 1085 1086extern __checkReturn efx_rc_t 1087efx_mcdi_get_mac_address_vf( 1088 __in efx_nic_t *enp, 1089 __out_ecount_opt(6) uint8_t mac_addrp[6]); 1090 1091extern __checkReturn efx_rc_t 1092efx_mcdi_get_clock( 1093 __in efx_nic_t *enp, 1094 __out uint32_t *sys_freqp, 1095 __out uint32_t *dpcpu_freqp); 1096 1097 1098extern __checkReturn efx_rc_t 1099efx_mcdi_get_vector_cfg( 1100 __in efx_nic_t *enp, 1101 __out_opt uint32_t *vec_basep, 1102 __out_opt uint32_t *pf_nvecp, 1103 __out_opt uint32_t *vf_nvecp); 1104 1105extern __checkReturn efx_rc_t 1106ef10_get_datapath_caps( 1107 __in efx_nic_t *enp); 1108 1109extern __checkReturn efx_rc_t 1110ef10_get_privilege_mask( 1111 __in efx_nic_t *enp, 1112 __out uint32_t *maskp); 1113 1114extern __checkReturn efx_rc_t 1115ef10_external_port_mapping( 1116 __in efx_nic_t *enp, 1117 __in uint32_t port, 1118 __out uint8_t *external_portp); 1119 1120 1121#ifdef __cplusplus 1122} 1123#endif 1124 1125#endif /* _SYS_EF10_IMPL_H */ 1126