ef10_impl.h revision 300607
1/*- 2 * Copyright (c) 2015-2016 Solarflare Communications Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * The views and conclusions contained in the software and documentation are 27 * those of the authors and should not be interpreted as representing official 28 * policies, either expressed or implied, of the FreeBSD Project. 29 * 30 * $FreeBSD: head/sys/dev/sfxge/common/ef10_impl.h 300607 2016-05-24 12:16:57Z arybchik $ 31 */ 32 33#ifndef _SYS_EF10_IMPL_H 34#define _SYS_EF10_IMPL_H 35 36#ifdef __cplusplus 37extern "C" { 38#endif 39 40#if (EFSYS_OPT_HUNTINGTON && EFSYS_OPT_MEDFORD) 41#define EF10_MAX_PIOBUF_NBUFS MAX(HUNT_PIOBUF_NBUFS, MEDFORD_PIOBUF_NBUFS) 42#elif EFSYS_OPT_HUNTINGTON 43#define EF10_MAX_PIOBUF_NBUFS HUNT_PIOBUF_NBUFS 44#elif EFSYS_OPT_MEDFORD 45#define EF10_MAX_PIOBUF_NBUFS MEDFORD_PIOBUF_NBUFS 46#endif 47 48/* 49 * FIXME: This is just a power of 2 which fits in an MCDI v1 message, and could 50 * possibly be increased, or the write size reported by newer firmware used 51 * instead. 52 */ 53#define EF10_NVRAM_CHUNK 0x80 54 55/* Alignment requirement for value written to RX WPTR: 56 * the WPTR must be aligned to an 8 descriptor boundary 57 */ 58#define EF10_RX_WPTR_ALIGN 8 59 60/* 61 * Max byte offset into the packet the TCP header must start for the hardware 62 * to be able to parse the packet correctly. 63 */ 64#define EF10_TCP_HEADER_OFFSET_LIMIT 208 65 66/* Invalid RSS context handle */ 67#define EF10_RSS_CONTEXT_INVALID (0xffffffff) 68 69 70/* EV */ 71 72 __checkReturn efx_rc_t 73ef10_ev_init( 74 __in efx_nic_t *enp); 75 76 void 77ef10_ev_fini( 78 __in efx_nic_t *enp); 79 80 __checkReturn efx_rc_t 81ef10_ev_qcreate( 82 __in efx_nic_t *enp, 83 __in unsigned int index, 84 __in efsys_mem_t *esmp, 85 __in size_t n, 86 __in uint32_t id, 87 __in efx_evq_t *eep); 88 89 void 90ef10_ev_qdestroy( 91 __in efx_evq_t *eep); 92 93 __checkReturn efx_rc_t 94ef10_ev_qprime( 95 __in efx_evq_t *eep, 96 __in unsigned int count); 97 98 void 99ef10_ev_qpost( 100 __in efx_evq_t *eep, 101 __in uint16_t data); 102 103 __checkReturn efx_rc_t 104ef10_ev_qmoderate( 105 __in efx_evq_t *eep, 106 __in unsigned int us); 107 108#if EFSYS_OPT_QSTATS 109 void 110ef10_ev_qstats_update( 111 __in efx_evq_t *eep, 112 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat); 113#endif /* EFSYS_OPT_QSTATS */ 114 115 void 116ef10_ev_rxlabel_init( 117 __in efx_evq_t *eep, 118 __in efx_rxq_t *erp, 119 __in unsigned int label); 120 121 void 122ef10_ev_rxlabel_fini( 123 __in efx_evq_t *eep, 124 __in unsigned int label); 125 126/* INTR */ 127 128 __checkReturn efx_rc_t 129ef10_intr_init( 130 __in efx_nic_t *enp, 131 __in efx_intr_type_t type, 132 __in efsys_mem_t *esmp); 133 134 void 135ef10_intr_enable( 136 __in efx_nic_t *enp); 137 138 void 139ef10_intr_disable( 140 __in efx_nic_t *enp); 141 142 void 143ef10_intr_disable_unlocked( 144 __in efx_nic_t *enp); 145 146 __checkReturn efx_rc_t 147ef10_intr_trigger( 148 __in efx_nic_t *enp, 149 __in unsigned int level); 150 151 void 152ef10_intr_status_line( 153 __in efx_nic_t *enp, 154 __out boolean_t *fatalp, 155 __out uint32_t *qmaskp); 156 157 void 158ef10_intr_status_message( 159 __in efx_nic_t *enp, 160 __in unsigned int message, 161 __out boolean_t *fatalp); 162 163 void 164ef10_intr_fatal( 165 __in efx_nic_t *enp); 166 void 167ef10_intr_fini( 168 __in efx_nic_t *enp); 169 170/* NIC */ 171 172extern __checkReturn efx_rc_t 173ef10_nic_probe( 174 __in efx_nic_t *enp); 175 176extern __checkReturn efx_rc_t 177ef10_nic_set_drv_limits( 178 __inout efx_nic_t *enp, 179 __in efx_drv_limits_t *edlp); 180 181extern __checkReturn efx_rc_t 182ef10_nic_get_vi_pool( 183 __in efx_nic_t *enp, 184 __out uint32_t *vi_countp); 185 186extern __checkReturn efx_rc_t 187ef10_nic_get_bar_region( 188 __in efx_nic_t *enp, 189 __in efx_nic_region_t region, 190 __out uint32_t *offsetp, 191 __out size_t *sizep); 192 193extern __checkReturn efx_rc_t 194ef10_nic_reset( 195 __in efx_nic_t *enp); 196 197extern __checkReturn efx_rc_t 198ef10_nic_init( 199 __in efx_nic_t *enp); 200 201#if EFSYS_OPT_DIAG 202 203extern __checkReturn efx_rc_t 204ef10_nic_register_test( 205 __in efx_nic_t *enp); 206 207#endif /* EFSYS_OPT_DIAG */ 208 209extern void 210ef10_nic_fini( 211 __in efx_nic_t *enp); 212 213extern void 214ef10_nic_unprobe( 215 __in efx_nic_t *enp); 216 217 218/* MAC */ 219 220extern __checkReturn efx_rc_t 221ef10_mac_poll( 222 __in efx_nic_t *enp, 223 __out efx_link_mode_t *link_modep); 224 225extern __checkReturn efx_rc_t 226ef10_mac_up( 227 __in efx_nic_t *enp, 228 __out boolean_t *mac_upp); 229 230extern __checkReturn efx_rc_t 231ef10_mac_addr_set( 232 __in efx_nic_t *enp); 233 234extern __checkReturn efx_rc_t 235ef10_mac_pdu_set( 236 __in efx_nic_t *enp); 237 238extern __checkReturn efx_rc_t 239ef10_mac_pdu_get( 240 __in efx_nic_t *enp, 241 __out size_t *pdu); 242 243extern __checkReturn efx_rc_t 244ef10_mac_reconfigure( 245 __in efx_nic_t *enp); 246 247extern __checkReturn efx_rc_t 248ef10_mac_multicast_list_set( 249 __in efx_nic_t *enp); 250 251extern __checkReturn efx_rc_t 252ef10_mac_filter_default_rxq_set( 253 __in efx_nic_t *enp, 254 __in efx_rxq_t *erp, 255 __in boolean_t using_rss); 256 257extern void 258ef10_mac_filter_default_rxq_clear( 259 __in efx_nic_t *enp); 260 261#if EFSYS_OPT_LOOPBACK 262 263extern __checkReturn efx_rc_t 264ef10_mac_loopback_set( 265 __in efx_nic_t *enp, 266 __in efx_link_mode_t link_mode, 267 __in efx_loopback_type_t loopback_type); 268 269#endif /* EFSYS_OPT_LOOPBACK */ 270 271#if EFSYS_OPT_MAC_STATS 272 273extern __checkReturn efx_rc_t 274ef10_mac_stats_update( 275 __in efx_nic_t *enp, 276 __in efsys_mem_t *esmp, 277 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat, 278 __inout_opt uint32_t *generationp); 279 280#endif /* EFSYS_OPT_MAC_STATS */ 281 282 283/* MCDI */ 284 285#if EFSYS_OPT_MCDI 286 287extern __checkReturn efx_rc_t 288ef10_mcdi_init( 289 __in efx_nic_t *enp, 290 __in const efx_mcdi_transport_t *mtp); 291 292extern void 293ef10_mcdi_fini( 294 __in efx_nic_t *enp); 295 296extern void 297ef10_mcdi_send_request( 298 __in efx_nic_t *enp, 299 __in void *hdrp, 300 __in size_t hdr_len, 301 __in void *sdup, 302 __in size_t sdu_len); 303 304extern __checkReturn boolean_t 305ef10_mcdi_poll_response( 306 __in efx_nic_t *enp); 307 308extern void 309ef10_mcdi_read_response( 310 __in efx_nic_t *enp, 311 __out_bcount(length) void *bufferp, 312 __in size_t offset, 313 __in size_t length); 314 315extern efx_rc_t 316ef10_mcdi_poll_reboot( 317 __in efx_nic_t *enp); 318 319extern __checkReturn efx_rc_t 320ef10_mcdi_feature_supported( 321 __in efx_nic_t *enp, 322 __in efx_mcdi_feature_id_t id, 323 __out boolean_t *supportedp); 324 325#endif /* EFSYS_OPT_MCDI */ 326 327/* NVRAM */ 328 329#if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD 330 331extern __checkReturn efx_rc_t 332ef10_nvram_buf_read_tlv( 333 __in efx_nic_t *enp, 334 __in_bcount(max_seg_size) caddr_t seg_data, 335 __in size_t max_seg_size, 336 __in uint32_t tag, 337 __deref_out_bcount_opt(*sizep) caddr_t *datap, 338 __out size_t *sizep); 339 340extern __checkReturn efx_rc_t 341ef10_nvram_buf_write_tlv( 342 __inout_bcount(partn_size) caddr_t partn_data, 343 __in size_t partn_size, 344 __in uint32_t tag, 345 __in_bcount(tag_size) caddr_t tag_data, 346 __in size_t tag_size, 347 __out size_t *total_lengthp); 348 349extern __checkReturn efx_rc_t 350ef10_nvram_partn_read_tlv( 351 __in efx_nic_t *enp, 352 __in uint32_t partn, 353 __in uint32_t tag, 354 __deref_out_bcount_opt(*sizep) caddr_t *datap, 355 __out size_t *sizep); 356 357extern __checkReturn efx_rc_t 358ef10_nvram_partn_write_tlv( 359 __in efx_nic_t *enp, 360 __in uint32_t partn, 361 __in uint32_t tag, 362 __in_bcount(size) caddr_t data, 363 __in size_t size); 364 365extern __checkReturn efx_rc_t 366ef10_nvram_partn_write_segment_tlv( 367 __in efx_nic_t *enp, 368 __in uint32_t partn, 369 __in uint32_t tag, 370 __in_bcount(size) caddr_t data, 371 __in size_t size, 372 __in boolean_t all_segments); 373 374extern __checkReturn efx_rc_t 375ef10_nvram_partn_lock( 376 __in efx_nic_t *enp, 377 __in uint32_t partn); 378 379extern void 380ef10_nvram_partn_unlock( 381 __in efx_nic_t *enp, 382 __in uint32_t partn); 383 384#endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */ 385 386#if EFSYS_OPT_NVRAM 387 388#if EFSYS_OPT_DIAG 389 390extern __checkReturn efx_rc_t 391ef10_nvram_test( 392 __in efx_nic_t *enp); 393 394#endif /* EFSYS_OPT_DIAG */ 395 396extern __checkReturn efx_rc_t 397ef10_nvram_type_to_partn( 398 __in efx_nic_t *enp, 399 __in efx_nvram_type_t type, 400 __out uint32_t *partnp); 401 402extern __checkReturn efx_rc_t 403ef10_nvram_partn_size( 404 __in efx_nic_t *enp, 405 __in uint32_t partn, 406 __out size_t *sizep); 407 408extern __checkReturn efx_rc_t 409ef10_nvram_partn_rw_start( 410 __in efx_nic_t *enp, 411 __in uint32_t partn, 412 __out size_t *chunk_sizep); 413 414extern __checkReturn efx_rc_t 415ef10_nvram_partn_read_mode( 416 __in efx_nic_t *enp, 417 __in uint32_t partn, 418 __in unsigned int offset, 419 __out_bcount(size) caddr_t data, 420 __in size_t size, 421 __in uint32_t mode); 422 423extern __checkReturn efx_rc_t 424ef10_nvram_partn_read( 425 __in efx_nic_t *enp, 426 __in uint32_t partn, 427 __in unsigned int offset, 428 __out_bcount(size) caddr_t data, 429 __in size_t size); 430 431extern __checkReturn efx_rc_t 432ef10_nvram_partn_erase( 433 __in efx_nic_t *enp, 434 __in uint32_t partn, 435 __in unsigned int offset, 436 __in size_t size); 437 438extern __checkReturn efx_rc_t 439ef10_nvram_partn_write( 440 __in efx_nic_t *enp, 441 __in uint32_t partn, 442 __in unsigned int offset, 443 __out_bcount(size) caddr_t data, 444 __in size_t size); 445 446extern void 447ef10_nvram_partn_rw_finish( 448 __in efx_nic_t *enp, 449 __in uint32_t partn); 450 451extern __checkReturn efx_rc_t 452ef10_nvram_partn_get_version( 453 __in efx_nic_t *enp, 454 __in uint32_t partn, 455 __out uint32_t *subtypep, 456 __out_ecount(4) uint16_t version[4]); 457 458extern __checkReturn efx_rc_t 459ef10_nvram_partn_set_version( 460 __in efx_nic_t *enp, 461 __in uint32_t partn, 462 __in_ecount(4) uint16_t version[4]); 463 464extern __checkReturn efx_rc_t 465ef10_nvram_buffer_validate( 466 __in efx_nic_t *enp, 467 __in uint32_t partn, 468 __in_bcount(buffer_size) 469 caddr_t bufferp, 470 __in size_t buffer_size); 471 472extern __checkReturn efx_rc_t 473ef10_nvram_buffer_create( 474 __in efx_nic_t *enp, 475 __in uint16_t partn_type, 476 __in_bcount(buffer_size) 477 caddr_t bufferp, 478 __in size_t buffer_size); 479 480extern __checkReturn efx_rc_t 481ef10_nvram_buffer_find_item_start( 482 __in_bcount(buffer_size) 483 caddr_t bufferp, 484 __in size_t buffer_size, 485 __out uint32_t *startp 486 ); 487 488extern __checkReturn efx_rc_t 489ef10_nvram_buffer_find_end( 490 __in_bcount(buffer_size) 491 caddr_t bufferp, 492 __in size_t buffer_size, 493 __in uint32_t offset, 494 __out uint32_t *endp 495 ); 496 497extern __checkReturn __success(return != B_FALSE) boolean_t 498ef10_nvram_buffer_find_item( 499 __in_bcount(buffer_size) 500 caddr_t bufferp, 501 __in size_t buffer_size, 502 __in uint32_t offset, 503 __out uint32_t *startp, 504 __out uint32_t *lengthp 505 ); 506 507extern __checkReturn efx_rc_t 508ef10_nvram_buffer_get_item( 509 __in_bcount(buffer_size) 510 caddr_t bufferp, 511 __in size_t buffer_size, 512 __in uint32_t offset, 513 __in uint32_t length, 514 __out_bcount_part(item_max_size, *lengthp) 515 caddr_t itemp, 516 __in size_t item_max_size, 517 __out uint32_t *lengthp 518 ); 519 520extern __checkReturn efx_rc_t 521ef10_nvram_buffer_insert_item( 522 __in_bcount(buffer_size) 523 caddr_t bufferp, 524 __in size_t buffer_size, 525 __in uint32_t offset, 526 __in_bcount(length) caddr_t keyp, 527 __in uint32_t length, 528 __out uint32_t *lengthp 529 ); 530 531extern __checkReturn efx_rc_t 532ef10_nvram_buffer_delete_item( 533 __in_bcount(buffer_size) 534 caddr_t bufferp, 535 __in size_t buffer_size, 536 __in uint32_t offset, 537 __in uint32_t length, 538 __in uint32_t end 539 ); 540 541extern __checkReturn efx_rc_t 542ef10_nvram_buffer_finish( 543 __in_bcount(buffer_size) 544 caddr_t bufferp, 545 __in size_t buffer_size 546 ); 547 548#endif /* EFSYS_OPT_NVRAM */ 549 550 551/* PHY */ 552 553typedef struct ef10_link_state_s { 554 uint32_t els_adv_cap_mask; 555 uint32_t els_lp_cap_mask; 556 unsigned int els_fcntl; 557 efx_link_mode_t els_link_mode; 558#if EFSYS_OPT_LOOPBACK 559 efx_loopback_type_t els_loopback; 560#endif 561 boolean_t els_mac_up; 562} ef10_link_state_t; 563 564extern void 565ef10_phy_link_ev( 566 __in efx_nic_t *enp, 567 __in efx_qword_t *eqp, 568 __out efx_link_mode_t *link_modep); 569 570extern __checkReturn efx_rc_t 571ef10_phy_get_link( 572 __in efx_nic_t *enp, 573 __out ef10_link_state_t *elsp); 574 575extern __checkReturn efx_rc_t 576ef10_phy_power( 577 __in efx_nic_t *enp, 578 __in boolean_t on); 579 580extern __checkReturn efx_rc_t 581ef10_phy_reconfigure( 582 __in efx_nic_t *enp); 583 584extern __checkReturn efx_rc_t 585ef10_phy_verify( 586 __in efx_nic_t *enp); 587 588extern __checkReturn efx_rc_t 589ef10_phy_oui_get( 590 __in efx_nic_t *enp, 591 __out uint32_t *ouip); 592 593#if EFSYS_OPT_PHY_STATS 594 595extern __checkReturn efx_rc_t 596ef10_phy_stats_update( 597 __in efx_nic_t *enp, 598 __in efsys_mem_t *esmp, 599 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat); 600 601#endif /* EFSYS_OPT_PHY_STATS */ 602 603 604/* TX */ 605 606extern __checkReturn efx_rc_t 607ef10_tx_init( 608 __in efx_nic_t *enp); 609 610extern void 611ef10_tx_fini( 612 __in efx_nic_t *enp); 613 614extern __checkReturn efx_rc_t 615ef10_tx_qcreate( 616 __in efx_nic_t *enp, 617 __in unsigned int index, 618 __in unsigned int label, 619 __in efsys_mem_t *esmp, 620 __in size_t n, 621 __in uint32_t id, 622 __in uint16_t flags, 623 __in efx_evq_t *eep, 624 __in efx_txq_t *etp, 625 __out unsigned int *addedp); 626 627extern void 628ef10_tx_qdestroy( 629 __in efx_txq_t *etp); 630 631extern __checkReturn efx_rc_t 632ef10_tx_qpost( 633 __in efx_txq_t *etp, 634 __in_ecount(n) efx_buffer_t *eb, 635 __in unsigned int n, 636 __in unsigned int completed, 637 __inout unsigned int *addedp); 638 639extern void 640ef10_tx_qpush( 641 __in efx_txq_t *etp, 642 __in unsigned int added, 643 __in unsigned int pushed); 644 645extern __checkReturn efx_rc_t 646ef10_tx_qpace( 647 __in efx_txq_t *etp, 648 __in unsigned int ns); 649 650extern __checkReturn efx_rc_t 651ef10_tx_qflush( 652 __in efx_txq_t *etp); 653 654extern void 655ef10_tx_qenable( 656 __in efx_txq_t *etp); 657 658extern __checkReturn efx_rc_t 659ef10_tx_qpio_enable( 660 __in efx_txq_t *etp); 661 662extern void 663ef10_tx_qpio_disable( 664 __in efx_txq_t *etp); 665 666extern __checkReturn efx_rc_t 667ef10_tx_qpio_write( 668 __in efx_txq_t *etp, 669 __in_ecount(buf_length) uint8_t *buffer, 670 __in size_t buf_length, 671 __in size_t pio_buf_offset); 672 673extern __checkReturn efx_rc_t 674ef10_tx_qpio_post( 675 __in efx_txq_t *etp, 676 __in size_t pkt_length, 677 __in unsigned int completed, 678 __inout unsigned int *addedp); 679 680extern __checkReturn efx_rc_t 681ef10_tx_qdesc_post( 682 __in efx_txq_t *etp, 683 __in_ecount(n) efx_desc_t *ed, 684 __in unsigned int n, 685 __in unsigned int completed, 686 __inout unsigned int *addedp); 687 688extern void 689ef10_tx_qdesc_dma_create( 690 __in efx_txq_t *etp, 691 __in efsys_dma_addr_t addr, 692 __in size_t size, 693 __in boolean_t eop, 694 __out efx_desc_t *edp); 695 696extern void 697ef10_tx_qdesc_tso_create( 698 __in efx_txq_t *etp, 699 __in uint16_t ipv4_id, 700 __in uint32_t tcp_seq, 701 __in uint8_t tcp_flags, 702 __out efx_desc_t *edp); 703 704extern void 705ef10_tx_qdesc_tso2_create( 706 __in efx_txq_t *etp, 707 __in uint16_t ipv4_id, 708 __in uint32_t tcp_seq, 709 __in uint16_t tcp_mss, 710 __out_ecount(count) efx_desc_t *edp, 711 __in int count); 712 713extern void 714ef10_tx_qdesc_vlantci_create( 715 __in efx_txq_t *etp, 716 __in uint16_t vlan_tci, 717 __out efx_desc_t *edp); 718 719 720#if EFSYS_OPT_QSTATS 721 722extern void 723ef10_tx_qstats_update( 724 __in efx_txq_t *etp, 725 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat); 726 727#endif /* EFSYS_OPT_QSTATS */ 728 729typedef uint32_t efx_piobuf_handle_t; 730 731#define EFX_PIOBUF_HANDLE_INVALID ((efx_piobuf_handle_t) -1) 732 733extern __checkReturn efx_rc_t 734ef10_nic_pio_alloc( 735 __inout efx_nic_t *enp, 736 __out uint32_t *bufnump, 737 __out efx_piobuf_handle_t *handlep, 738 __out uint32_t *blknump, 739 __out uint32_t *offsetp, 740 __out size_t *sizep); 741 742extern __checkReturn efx_rc_t 743ef10_nic_pio_free( 744 __inout efx_nic_t *enp, 745 __in uint32_t bufnum, 746 __in uint32_t blknum); 747 748extern __checkReturn efx_rc_t 749ef10_nic_pio_link( 750 __inout efx_nic_t *enp, 751 __in uint32_t vi_index, 752 __in efx_piobuf_handle_t handle); 753 754extern __checkReturn efx_rc_t 755ef10_nic_pio_unlink( 756 __inout efx_nic_t *enp, 757 __in uint32_t vi_index); 758 759 760/* VPD */ 761 762#if EFSYS_OPT_VPD 763 764extern __checkReturn efx_rc_t 765ef10_vpd_init( 766 __in efx_nic_t *enp); 767 768extern __checkReturn efx_rc_t 769ef10_vpd_size( 770 __in efx_nic_t *enp, 771 __out size_t *sizep); 772 773extern __checkReturn efx_rc_t 774ef10_vpd_read( 775 __in efx_nic_t *enp, 776 __out_bcount(size) caddr_t data, 777 __in size_t size); 778 779extern __checkReturn efx_rc_t 780ef10_vpd_verify( 781 __in efx_nic_t *enp, 782 __in_bcount(size) caddr_t data, 783 __in size_t size); 784 785extern __checkReturn efx_rc_t 786ef10_vpd_reinit( 787 __in efx_nic_t *enp, 788 __in_bcount(size) caddr_t data, 789 __in size_t size); 790 791extern __checkReturn efx_rc_t 792ef10_vpd_get( 793 __in efx_nic_t *enp, 794 __in_bcount(size) caddr_t data, 795 __in size_t size, 796 __inout efx_vpd_value_t *evvp); 797 798extern __checkReturn efx_rc_t 799ef10_vpd_set( 800 __in efx_nic_t *enp, 801 __in_bcount(size) caddr_t data, 802 __in size_t size, 803 __in efx_vpd_value_t *evvp); 804 805extern __checkReturn efx_rc_t 806ef10_vpd_next( 807 __in efx_nic_t *enp, 808 __in_bcount(size) caddr_t data, 809 __in size_t size, 810 __out efx_vpd_value_t *evvp, 811 __inout unsigned int *contp); 812 813extern __checkReturn efx_rc_t 814ef10_vpd_write( 815 __in efx_nic_t *enp, 816 __in_bcount(size) caddr_t data, 817 __in size_t size); 818 819extern void 820ef10_vpd_fini( 821 __in efx_nic_t *enp); 822 823#endif /* EFSYS_OPT_VPD */ 824 825 826/* RX */ 827 828extern __checkReturn efx_rc_t 829ef10_rx_init( 830 __in efx_nic_t *enp); 831 832#if EFSYS_OPT_RX_SCATTER 833extern __checkReturn efx_rc_t 834ef10_rx_scatter_enable( 835 __in efx_nic_t *enp, 836 __in unsigned int buf_size); 837#endif /* EFSYS_OPT_RX_SCATTER */ 838 839 840#if EFSYS_OPT_RX_SCALE 841 842extern __checkReturn efx_rc_t 843ef10_rx_scale_mode_set( 844 __in efx_nic_t *enp, 845 __in efx_rx_hash_alg_t alg, 846 __in efx_rx_hash_type_t type, 847 __in boolean_t insert); 848 849extern __checkReturn efx_rc_t 850ef10_rx_scale_key_set( 851 __in efx_nic_t *enp, 852 __in_ecount(n) uint8_t *key, 853 __in size_t n); 854 855extern __checkReturn efx_rc_t 856ef10_rx_scale_tbl_set( 857 __in efx_nic_t *enp, 858 __in_ecount(n) unsigned int *table, 859 __in size_t n); 860 861extern __checkReturn uint32_t 862ef10_rx_prefix_hash( 863 __in efx_nic_t *enp, 864 __in efx_rx_hash_alg_t func, 865 __in uint8_t *buffer); 866 867#endif /* EFSYS_OPT_RX_SCALE */ 868 869extern __checkReturn efx_rc_t 870ef10_rx_prefix_pktlen( 871 __in efx_nic_t *enp, 872 __in uint8_t *buffer, 873 __out uint16_t *lengthp); 874 875extern void 876ef10_rx_qpost( 877 __in efx_rxq_t *erp, 878 __in_ecount(n) efsys_dma_addr_t *addrp, 879 __in size_t size, 880 __in unsigned int n, 881 __in unsigned int completed, 882 __in unsigned int added); 883 884extern void 885ef10_rx_qpush( 886 __in efx_rxq_t *erp, 887 __in unsigned int added, 888 __inout unsigned int *pushedp); 889 890extern __checkReturn efx_rc_t 891ef10_rx_qflush( 892 __in efx_rxq_t *erp); 893 894extern void 895ef10_rx_qenable( 896 __in efx_rxq_t *erp); 897 898extern __checkReturn efx_rc_t 899ef10_rx_qcreate( 900 __in efx_nic_t *enp, 901 __in unsigned int index, 902 __in unsigned int label, 903 __in efx_rxq_type_t type, 904 __in efsys_mem_t *esmp, 905 __in size_t n, 906 __in uint32_t id, 907 __in efx_evq_t *eep, 908 __in efx_rxq_t *erp); 909 910extern void 911ef10_rx_qdestroy( 912 __in efx_rxq_t *erp); 913 914extern void 915ef10_rx_fini( 916 __in efx_nic_t *enp); 917 918#if EFSYS_OPT_FILTER 919 920typedef struct ef10_filter_handle_s { 921 uint32_t efh_lo; 922 uint32_t efh_hi; 923} ef10_filter_handle_t; 924 925typedef struct ef10_filter_entry_s { 926 uintptr_t efe_spec; /* pointer to filter spec plus busy bit */ 927 ef10_filter_handle_t efe_handle; 928} ef10_filter_entry_t; 929 930/* 931 * BUSY flag indicates that an update is in progress. 932 * AUTO_OLD flag is used to mark and sweep MAC packet filters. 933 */ 934#define EFX_EF10_FILTER_FLAG_BUSY 1U 935#define EFX_EF10_FILTER_FLAG_AUTO_OLD 2U 936#define EFX_EF10_FILTER_FLAGS 3U 937 938/* 939 * Size of the hash table used by the driver. Doesn't need to be the 940 * same size as the hardware's table. 941 */ 942#define EFX_EF10_FILTER_TBL_ROWS 8192 943 944/* Only need to allow for one directed and one unknown unicast filter */ 945#define EFX_EF10_FILTER_UNICAST_FILTERS_MAX 2 946 947/* Allow for the broadcast address to be added to the multicast list */ 948#define EFX_EF10_FILTER_MULTICAST_FILTERS_MAX (EFX_MAC_MULTICAST_LIST_MAX + 1) 949 950typedef struct ef10_filter_table_s { 951 ef10_filter_entry_t eft_entry[EFX_EF10_FILTER_TBL_ROWS]; 952 efx_rxq_t * eft_default_rxq; 953 boolean_t eft_using_rss; 954 uint32_t eft_unicst_filter_indexes[ 955 EFX_EF10_FILTER_UNICAST_FILTERS_MAX]; 956 boolean_t eft_unicst_filter_count; 957 uint32_t eft_mulcst_filter_indexes[ 958 EFX_EF10_FILTER_MULTICAST_FILTERS_MAX]; 959 uint32_t eft_mulcst_filter_count; 960 boolean_t eft_using_all_mulcst; 961} ef10_filter_table_t; 962 963 __checkReturn efx_rc_t 964ef10_filter_init( 965 __in efx_nic_t *enp); 966 967 void 968ef10_filter_fini( 969 __in efx_nic_t *enp); 970 971 __checkReturn efx_rc_t 972ef10_filter_restore( 973 __in efx_nic_t *enp); 974 975 __checkReturn efx_rc_t 976ef10_filter_add( 977 __in efx_nic_t *enp, 978 __inout efx_filter_spec_t *spec, 979 __in boolean_t may_replace); 980 981 __checkReturn efx_rc_t 982ef10_filter_delete( 983 __in efx_nic_t *enp, 984 __inout efx_filter_spec_t *spec); 985 986extern __checkReturn efx_rc_t 987ef10_filter_supported_filters( 988 __in efx_nic_t *enp, 989 __out uint32_t *list, 990 __out size_t *length); 991 992extern __checkReturn efx_rc_t 993ef10_filter_reconfigure( 994 __in efx_nic_t *enp, 995 __in_ecount(6) uint8_t const *mac_addr, 996 __in boolean_t all_unicst, 997 __in boolean_t mulcst, 998 __in boolean_t all_mulcst, 999 __in boolean_t brdcst, 1000 __in_ecount(6*count) uint8_t const *addrs, 1001 __in uint32_t count); 1002 1003extern void 1004ef10_filter_get_default_rxq( 1005 __in efx_nic_t *enp, 1006 __out efx_rxq_t **erpp, 1007 __out boolean_t *using_rss); 1008 1009extern void 1010ef10_filter_default_rxq_set( 1011 __in efx_nic_t *enp, 1012 __in efx_rxq_t *erp, 1013 __in boolean_t using_rss); 1014 1015extern void 1016ef10_filter_default_rxq_clear( 1017 __in efx_nic_t *enp); 1018 1019 1020#endif /* EFSYS_OPT_FILTER */ 1021 1022extern __checkReturn efx_rc_t 1023efx_mcdi_get_function_info( 1024 __in efx_nic_t *enp, 1025 __out uint32_t *pfp, 1026 __out_opt uint32_t *vfp); 1027 1028extern __checkReturn efx_rc_t 1029efx_mcdi_privilege_mask( 1030 __in efx_nic_t *enp, 1031 __in uint32_t pf, 1032 __in uint32_t vf, 1033 __out uint32_t *maskp); 1034 1035extern __checkReturn efx_rc_t 1036efx_mcdi_get_port_assignment( 1037 __in efx_nic_t *enp, 1038 __out uint32_t *portp); 1039 1040extern __checkReturn efx_rc_t 1041efx_mcdi_get_port_modes( 1042 __in efx_nic_t *enp, 1043 __out uint32_t *modesp, 1044 __out_opt uint32_t *current_modep); 1045 1046extern __checkReturn efx_rc_t 1047ef10_nic_get_port_mode_bandwidth( 1048 __in uint32_t port_mode, 1049 __out uint32_t *bandwidth_mbpsp); 1050 1051extern __checkReturn efx_rc_t 1052efx_mcdi_get_mac_address_pf( 1053 __in efx_nic_t *enp, 1054 __out_ecount_opt(6) uint8_t mac_addrp[6]); 1055 1056extern __checkReturn efx_rc_t 1057efx_mcdi_get_mac_address_vf( 1058 __in efx_nic_t *enp, 1059 __out_ecount_opt(6) uint8_t mac_addrp[6]); 1060 1061extern __checkReturn efx_rc_t 1062efx_mcdi_get_clock( 1063 __in efx_nic_t *enp, 1064 __out uint32_t *sys_freqp, 1065 __out uint32_t *dpcpu_freqp); 1066 1067 1068extern __checkReturn efx_rc_t 1069efx_mcdi_get_vector_cfg( 1070 __in efx_nic_t *enp, 1071 __out_opt uint32_t *vec_basep, 1072 __out_opt uint32_t *pf_nvecp, 1073 __out_opt uint32_t *vf_nvecp); 1074 1075extern __checkReturn efx_rc_t 1076ef10_get_datapath_caps( 1077 __in efx_nic_t *enp); 1078 1079extern __checkReturn efx_rc_t 1080ef10_get_privilege_mask( 1081 __in efx_nic_t *enp, 1082 __out uint32_t *maskp); 1083 1084extern __checkReturn efx_rc_t 1085ef10_external_port_mapping( 1086 __in efx_nic_t *enp, 1087 __in uint32_t port, 1088 __out uint8_t *external_portp); 1089 1090 1091#ifdef __cplusplus 1092} 1093#endif 1094 1095#endif /* _SYS_EF10_IMPL_H */ 1096