ef10_impl.h revision 299720 
1/*-
2 * Copyright (c) 2015 Solarflare Communications Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,
9 *    this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 *    this list of conditions and the following disclaimer in the documentation
12 *    and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
29 *
30 * $FreeBSD: head/sys/dev/sfxge/common/ef10_impl.h 299720 2016-05-14 06:02:00Z arybchik $
31 */
32
33#ifndef	_SYS_EF10_IMPL_H
34#define	_SYS_EF10_IMPL_H
35
36#ifdef	__cplusplus
37extern "C" {
38#endif
39
40#if (EFSYS_OPT_HUNTINGTON && EFSYS_OPT_MEDFORD)
41#define	EF10_MAX_PIOBUF_NBUFS	MAX(HUNT_PIOBUF_NBUFS, MEDFORD_PIOBUF_NBUFS)
42#elif EFSYS_OPT_HUNTINGTON
43#define	EF10_MAX_PIOBUF_NBUFS	HUNT_PIOBUF_NBUFS
44#elif EFSYS_OPT_MEDFORD
45#define	EF10_MAX_PIOBUF_NBUFS	MEDFORD_PIOBUF_NBUFS
46#endif
47
48/*
49 * FIXME: This is just a power of 2 which fits in an MCDI v1 message, and could
50 * possibly be increased, or the write size reported by newer firmware used
51 * instead.
52 */
53#define	EF10_NVRAM_CHUNK 0x80
54
55/* Alignment requirement for value written to RX WPTR:
56 *  the WPTR must be aligned to an 8 descriptor boundary
57 */
58#define	EF10_RX_WPTR_ALIGN 8
59
60/*
61 * Max byte offset into the packet the TCP header must start for the hardware
62 * to be able to parse the packet correctly.
63 */
64#define	EF10_TCP_HEADER_OFFSET_LIMIT	208
65
66/* Invalid RSS context handle */
67#define	EF10_RSS_CONTEXT_INVALID	(0xffffffff)
68
69
70/* EV */
71
72	__checkReturn	efx_rc_t
73ef10_ev_init(
74	__in		efx_nic_t *enp);
75
76			void
77ef10_ev_fini(
78	__in		efx_nic_t *enp);
79
80	__checkReturn	efx_rc_t
81ef10_ev_qcreate(
82	__in		efx_nic_t *enp,
83	__in		unsigned int index,
84	__in		efsys_mem_t *esmp,
85	__in		size_t n,
86	__in		uint32_t id,
87	__in		efx_evq_t *eep);
88
89			void
90ef10_ev_qdestroy(
91	__in		efx_evq_t *eep);
92
93	__checkReturn	efx_rc_t
94ef10_ev_qprime(
95	__in		efx_evq_t *eep,
96	__in		unsigned int count);
97
98			void
99ef10_ev_qpost(
100	__in	efx_evq_t *eep,
101	__in	uint16_t data);
102
103	__checkReturn	efx_rc_t
104ef10_ev_qmoderate(
105	__in		efx_evq_t *eep,
106	__in		unsigned int us);
107
108#if EFSYS_OPT_QSTATS
109			void
110ef10_ev_qstats_update(
111	__in				efx_evq_t *eep,
112	__inout_ecount(EV_NQSTATS)	efsys_stat_t *stat);
113#endif /* EFSYS_OPT_QSTATS */
114
115		void
116ef10_ev_rxlabel_init(
117	__in		efx_evq_t *eep,
118	__in		efx_rxq_t *erp,
119	__in		unsigned int label);
120
121		void
122ef10_ev_rxlabel_fini(
123	__in		efx_evq_t *eep,
124	__in		unsigned int label);
125
126/* INTR */
127
128	__checkReturn	efx_rc_t
129ef10_intr_init(
130	__in		efx_nic_t *enp,
131	__in		efx_intr_type_t type,
132	__in		efsys_mem_t *esmp);
133
134			void
135ef10_intr_enable(
136	__in		efx_nic_t *enp);
137
138			void
139ef10_intr_disable(
140	__in		efx_nic_t *enp);
141
142			void
143ef10_intr_disable_unlocked(
144	__in		efx_nic_t *enp);
145
146	__checkReturn	efx_rc_t
147ef10_intr_trigger(
148	__in		efx_nic_t *enp,
149	__in		unsigned int level);
150
151			void
152ef10_intr_status_line(
153	__in		efx_nic_t *enp,
154	__out		boolean_t *fatalp,
155	__out		uint32_t *qmaskp);
156
157			void
158ef10_intr_status_message(
159	__in		efx_nic_t *enp,
160	__in		unsigned int message,
161	__out		boolean_t *fatalp);
162
163			void
164ef10_intr_fatal(
165	__in		efx_nic_t *enp);
166			void
167ef10_intr_fini(
168	__in		efx_nic_t *enp);
169
170/* NIC */
171
172extern	__checkReturn	efx_rc_t
173ef10_nic_probe(
174	__in		efx_nic_t *enp);
175
176extern	__checkReturn	efx_rc_t
177ef10_nic_set_drv_limits(
178	__inout		efx_nic_t *enp,
179	__in		efx_drv_limits_t *edlp);
180
181extern	__checkReturn	efx_rc_t
182ef10_nic_get_vi_pool(
183	__in		efx_nic_t *enp,
184	__out		uint32_t *vi_countp);
185
186extern	__checkReturn	efx_rc_t
187ef10_nic_get_bar_region(
188	__in		efx_nic_t *enp,
189	__in		efx_nic_region_t region,
190	__out		uint32_t *offsetp,
191	__out		size_t *sizep);
192
193extern	__checkReturn	efx_rc_t
194ef10_nic_reset(
195	__in		efx_nic_t *enp);
196
197extern	__checkReturn	efx_rc_t
198ef10_nic_init(
199	__in		efx_nic_t *enp);
200
201#if EFSYS_OPT_DIAG
202
203extern	__checkReturn	efx_rc_t
204ef10_nic_register_test(
205	__in		efx_nic_t *enp);
206
207#endif	/* EFSYS_OPT_DIAG */
208
209extern			void
210ef10_nic_fini(
211	__in		efx_nic_t *enp);
212
213extern			void
214ef10_nic_unprobe(
215	__in		efx_nic_t *enp);
216
217
218/* MAC */
219
220extern	__checkReturn	efx_rc_t
221ef10_mac_poll(
222	__in		efx_nic_t *enp,
223	__out		efx_link_mode_t *link_modep);
224
225extern	__checkReturn	efx_rc_t
226ef10_mac_up(
227	__in		efx_nic_t *enp,
228	__out		boolean_t *mac_upp);
229
230extern	__checkReturn	efx_rc_t
231ef10_mac_addr_set(
232	__in	efx_nic_t *enp);
233
234extern	__checkReturn	efx_rc_t
235ef10_mac_pdu_set(
236	__in	efx_nic_t *enp);
237
238extern	__checkReturn	efx_rc_t
239ef10_mac_reconfigure(
240	__in	efx_nic_t *enp);
241
242extern	__checkReturn	efx_rc_t
243ef10_mac_multicast_list_set(
244	__in				efx_nic_t *enp);
245
246extern	__checkReturn	efx_rc_t
247ef10_mac_filter_default_rxq_set(
248	__in		efx_nic_t *enp,
249	__in		efx_rxq_t *erp,
250	__in		boolean_t using_rss);
251
252extern			void
253ef10_mac_filter_default_rxq_clear(
254	__in		efx_nic_t *enp);
255
256#if EFSYS_OPT_LOOPBACK
257
258extern	__checkReturn	efx_rc_t
259ef10_mac_loopback_set(
260	__in		efx_nic_t *enp,
261	__in		efx_link_mode_t link_mode,
262	__in		efx_loopback_type_t loopback_type);
263
264#endif	/* EFSYS_OPT_LOOPBACK */
265
266#if EFSYS_OPT_MAC_STATS
267
268extern	__checkReturn			efx_rc_t
269ef10_mac_stats_update(
270	__in				efx_nic_t *enp,
271	__in				efsys_mem_t *esmp,
272	__inout_ecount(EFX_MAC_NSTATS)	efsys_stat_t *stat,
273	__inout_opt			uint32_t *generationp);
274
275#endif	/* EFSYS_OPT_MAC_STATS */
276
277
278/* MCDI */
279
280#if EFSYS_OPT_MCDI
281
282extern	__checkReturn	efx_rc_t
283ef10_mcdi_init(
284	__in		efx_nic_t *enp,
285	__in		const efx_mcdi_transport_t *mtp);
286
287extern			void
288ef10_mcdi_fini(
289	__in		efx_nic_t *enp);
290
291extern			void
292ef10_mcdi_send_request(
293	__in		efx_nic_t *enp,
294	__in		void *hdrp,
295	__in		size_t hdr_len,
296	__in		void *sdup,
297	__in		size_t sdu_len);
298
299extern	__checkReturn	boolean_t
300ef10_mcdi_poll_response(
301	__in		efx_nic_t *enp);
302
303extern			void
304ef10_mcdi_read_response(
305	__in			efx_nic_t *enp,
306	__out_bcount(length)	void *bufferp,
307	__in			size_t offset,
308	__in			size_t length);
309
310extern			efx_rc_t
311ef10_mcdi_poll_reboot(
312	__in		efx_nic_t *enp);
313
314extern	__checkReturn	efx_rc_t
315ef10_mcdi_feature_supported(
316	__in		efx_nic_t *enp,
317	__in		efx_mcdi_feature_id_t id,
318	__out		boolean_t *supportedp);
319
320#endif /* EFSYS_OPT_MCDI */
321
322/* NVRAM */
323
324#if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
325
326extern	__checkReturn		efx_rc_t
327ef10_nvram_buf_read_tlv(
328	__in				efx_nic_t *enp,
329	__in_bcount(max_seg_size)	caddr_t seg_data,
330	__in				size_t max_seg_size,
331	__in				uint32_t tag,
332	__deref_out_bcount_opt(*sizep)	caddr_t *datap,
333	__out				size_t *sizep);
334
335extern	__checkReturn		efx_rc_t
336ef10_nvram_buf_write_tlv(
337	__inout_bcount(partn_size)	caddr_t partn_data,
338	__in				size_t partn_size,
339	__in				uint32_t tag,
340	__in_bcount(tag_size)		caddr_t tag_data,
341	__in				size_t tag_size,
342	__out				size_t *total_lengthp);
343
344extern	__checkReturn		efx_rc_t
345ef10_nvram_partn_read_tlv(
346	__in				efx_nic_t *enp,
347	__in				uint32_t partn,
348	__in				uint32_t tag,
349	__deref_out_bcount_opt(*sizep)	caddr_t *datap,
350	__out				size_t *sizep);
351
352extern	__checkReturn		efx_rc_t
353ef10_nvram_partn_write_tlv(
354	__in			efx_nic_t *enp,
355	__in			uint32_t partn,
356	__in			uint32_t tag,
357	__in_bcount(size)	caddr_t data,
358	__in			size_t size);
359
360extern	__checkReturn		efx_rc_t
361ef10_nvram_partn_write_segment_tlv(
362	__in			efx_nic_t *enp,
363	__in			uint32_t partn,
364	__in			uint32_t tag,
365	__in_bcount(size)	caddr_t data,
366	__in			size_t size,
367	__in			boolean_t all_segments);
368
369extern	__checkReturn		efx_rc_t
370ef10_nvram_partn_lock(
371	__in			efx_nic_t *enp,
372	__in			uint32_t partn);
373
374extern				void
375ef10_nvram_partn_unlock(
376	__in			efx_nic_t *enp,
377	__in			uint32_t partn);
378
379#endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
380
381#if EFSYS_OPT_NVRAM
382
383#if EFSYS_OPT_DIAG
384
385extern	__checkReturn		efx_rc_t
386ef10_nvram_test(
387	__in			efx_nic_t *enp);
388
389#endif	/* EFSYS_OPT_DIAG */
390
391extern	__checkReturn		efx_rc_t
392ef10_nvram_type_to_partn(
393	__in			efx_nic_t *enp,
394	__in			efx_nvram_type_t type,
395	__out			uint32_t *partnp);
396
397extern	__checkReturn		efx_rc_t
398ef10_nvram_partn_size(
399	__in			efx_nic_t *enp,
400	__in			uint32_t partn,
401	__out			size_t *sizep);
402
403extern	__checkReturn		efx_rc_t
404ef10_nvram_partn_rw_start(
405	__in			efx_nic_t *enp,
406	__in			uint32_t partn,
407	__out			size_t *chunk_sizep);
408
409extern	__checkReturn		efx_rc_t
410ef10_nvram_partn_read_mode(
411	__in			efx_nic_t *enp,
412	__in			uint32_t partn,
413	__in			unsigned int offset,
414	__out_bcount(size)	caddr_t data,
415	__in			size_t size,
416	__in			uint32_t mode);
417
418extern	__checkReturn		efx_rc_t
419ef10_nvram_partn_read(
420	__in			efx_nic_t *enp,
421	__in			uint32_t partn,
422	__in			unsigned int offset,
423	__out_bcount(size)	caddr_t data,
424	__in			size_t size);
425
426extern	__checkReturn		efx_rc_t
427ef10_nvram_partn_erase(
428	__in			efx_nic_t *enp,
429	__in			uint32_t partn,
430	__in			unsigned int offset,
431	__in			size_t size);
432
433extern	__checkReturn		efx_rc_t
434ef10_nvram_partn_write(
435	__in			efx_nic_t *enp,
436	__in			uint32_t partn,
437	__in			unsigned int offset,
438	__out_bcount(size)	caddr_t data,
439	__in			size_t size);
440
441extern				void
442ef10_nvram_partn_rw_finish(
443	__in			efx_nic_t *enp,
444	__in			uint32_t partn);
445
446extern	__checkReturn		efx_rc_t
447ef10_nvram_partn_get_version(
448	__in			efx_nic_t *enp,
449	__in			uint32_t partn,
450	__out			uint32_t *subtypep,
451	__out_ecount(4)		uint16_t version[4]);
452
453extern	__checkReturn		efx_rc_t
454ef10_nvram_partn_set_version(
455	__in			efx_nic_t *enp,
456	__in			uint32_t partn,
457	__in_ecount(4)		uint16_t version[4]);
458
459extern	__checkReturn		efx_rc_t
460ef10_nvram_buffer_validate(
461	__in			efx_nic_t *enp,
462	__in			uint32_t partn,
463	__in_bcount(buffer_size)
464				caddr_t bufferp,
465	__in			size_t buffer_size);
466
467extern	__checkReturn		efx_rc_t
468ef10_nvram_buffer_create(
469	__in			efx_nic_t *enp,
470	__in			uint16_t partn_type,
471	__in_bcount(buffer_size)
472				caddr_t bufferp,
473	__in			size_t buffer_size);
474
475extern	__checkReturn		efx_rc_t
476ef10_nvram_buffer_find_item_start(
477	__in_bcount(buffer_size)
478				caddr_t bufferp,
479	__in			size_t buffer_size,
480	__out			uint32_t *startp
481	);
482
483extern	__checkReturn		efx_rc_t
484ef10_nvram_buffer_find_end(
485	__in_bcount(buffer_size)
486				caddr_t bufferp,
487	__in			size_t buffer_size,
488	__in			uint32_t offset,
489	__out			uint32_t *endp
490	);
491
492extern	__checkReturn	__success(return != B_FALSE)	boolean_t
493ef10_nvram_buffer_find_item(
494	__in_bcount(buffer_size)
495				caddr_t bufferp,
496	__in			size_t buffer_size,
497	__in			uint32_t offset,
498	__out			uint32_t *startp,
499	__out			uint32_t *lengthp
500	);
501
502extern	__checkReturn		efx_rc_t
503ef10_nvram_buffer_get_item(
504	__in_bcount(buffer_size)
505				caddr_t bufferp,
506	__in			size_t buffer_size,
507	__in			uint32_t offset,
508	__in			uint32_t length,
509	__out_bcount_part(item_max_size, *lengthp)
510				caddr_t itemp,
511	__in			size_t item_max_size,
512	__out			uint32_t *lengthp
513	);
514
515extern	__checkReturn		efx_rc_t
516ef10_nvram_buffer_insert_item(
517	__in_bcount(buffer_size)
518				caddr_t bufferp,
519	__in			size_t buffer_size,
520	__in			uint32_t offset,
521	__in_bcount(length)	caddr_t keyp,
522	__in			uint32_t length,
523	__out			uint32_t *lengthp
524	);
525
526extern	__checkReturn		efx_rc_t
527ef10_nvram_buffer_delete_item(
528	__in_bcount(buffer_size)
529				caddr_t bufferp,
530	__in			size_t buffer_size,
531	__in			uint32_t offset,
532	__in			uint32_t length,
533	__in			uint32_t end
534	);
535
536extern	__checkReturn		efx_rc_t
537ef10_nvram_buffer_finish(
538	__in_bcount(buffer_size)
539				caddr_t bufferp,
540	__in			size_t buffer_size
541	);
542
543#endif	/* EFSYS_OPT_NVRAM */
544
545
546/* PHY */
547
548typedef struct ef10_link_state_s {
549	uint32_t		els_adv_cap_mask;
550	uint32_t		els_lp_cap_mask;
551	unsigned int		els_fcntl;
552	efx_link_mode_t		els_link_mode;
553#if EFSYS_OPT_LOOPBACK
554	efx_loopback_type_t	els_loopback;
555#endif
556	boolean_t		els_mac_up;
557} ef10_link_state_t;
558
559extern			void
560ef10_phy_link_ev(
561	__in		efx_nic_t *enp,
562	__in		efx_qword_t *eqp,
563	__out		efx_link_mode_t *link_modep);
564
565extern	__checkReturn	efx_rc_t
566ef10_phy_get_link(
567	__in		efx_nic_t *enp,
568	__out		ef10_link_state_t *elsp);
569
570extern	__checkReturn	efx_rc_t
571ef10_phy_power(
572	__in		efx_nic_t *enp,
573	__in		boolean_t on);
574
575extern	__checkReturn	efx_rc_t
576ef10_phy_reconfigure(
577	__in		efx_nic_t *enp);
578
579extern	__checkReturn	efx_rc_t
580ef10_phy_verify(
581	__in		efx_nic_t *enp);
582
583extern	__checkReturn	efx_rc_t
584ef10_phy_oui_get(
585	__in		efx_nic_t *enp,
586	__out		uint32_t *ouip);
587
588#if EFSYS_OPT_PHY_STATS
589
590extern	__checkReturn			efx_rc_t
591ef10_phy_stats_update(
592	__in				efx_nic_t *enp,
593	__in				efsys_mem_t *esmp,
594	__inout_ecount(EFX_PHY_NSTATS)	uint32_t *stat);
595
596#endif	/* EFSYS_OPT_PHY_STATS */
597
598#if EFSYS_OPT_PHY_PROPS
599
600#if EFSYS_OPT_NAMES
601
602extern		const char *
603ef10_phy_prop_name(
604	__in	efx_nic_t *enp,
605	__in	unsigned int id);
606
607#endif	/* EFSYS_OPT_NAMES */
608
609extern	__checkReturn	efx_rc_t
610ef10_phy_prop_get(
611	__in		efx_nic_t *enp,
612	__in		unsigned int id,
613	__in		uint32_t flags,
614	__out		uint32_t *valp);
615
616extern	__checkReturn	efx_rc_t
617ef10_phy_prop_set(
618	__in		efx_nic_t *enp,
619	__in		unsigned int id,
620	__in		uint32_t val);
621
622#endif	/* EFSYS_OPT_PHY_PROPS */
623
624
625/* TX */
626
627extern	__checkReturn	efx_rc_t
628ef10_tx_init(
629	__in		efx_nic_t *enp);
630
631extern			void
632ef10_tx_fini(
633	__in		efx_nic_t *enp);
634
635extern	__checkReturn	efx_rc_t
636ef10_tx_qcreate(
637	__in		efx_nic_t *enp,
638	__in		unsigned int index,
639	__in		unsigned int label,
640	__in		efsys_mem_t *esmp,
641	__in		size_t n,
642	__in		uint32_t id,
643	__in		uint16_t flags,
644	__in		efx_evq_t *eep,
645	__in		efx_txq_t *etp,
646	__out		unsigned int *addedp);
647
648extern		void
649ef10_tx_qdestroy(
650	__in		efx_txq_t *etp);
651
652extern	__checkReturn	efx_rc_t
653ef10_tx_qpost(
654	__in		efx_txq_t *etp,
655	__in_ecount(n)	efx_buffer_t *eb,
656	__in		unsigned int n,
657	__in		unsigned int completed,
658	__inout		unsigned int *addedp);
659
660extern			void
661ef10_tx_qpush(
662	__in		efx_txq_t *etp,
663	__in		unsigned int added,
664	__in		unsigned int pushed);
665
666extern	__checkReturn	efx_rc_t
667ef10_tx_qpace(
668	__in		efx_txq_t *etp,
669	__in		unsigned int ns);
670
671extern	__checkReturn	efx_rc_t
672ef10_tx_qflush(
673	__in		efx_txq_t *etp);
674
675extern			void
676ef10_tx_qenable(
677	__in		efx_txq_t *etp);
678
679extern	__checkReturn	efx_rc_t
680ef10_tx_qpio_enable(
681	__in		efx_txq_t *etp);
682
683extern			void
684ef10_tx_qpio_disable(
685	__in		efx_txq_t *etp);
686
687extern	__checkReturn	efx_rc_t
688ef10_tx_qpio_write(
689	__in			efx_txq_t *etp,
690	__in_ecount(buf_length)	uint8_t *buffer,
691	__in			size_t buf_length,
692	__in			size_t pio_buf_offset);
693
694extern	__checkReturn	efx_rc_t
695ef10_tx_qpio_post(
696	__in			efx_txq_t *etp,
697	__in			size_t pkt_length,
698	__in			unsigned int completed,
699	__inout			unsigned int *addedp);
700
701extern	__checkReturn	efx_rc_t
702ef10_tx_qdesc_post(
703	__in		efx_txq_t *etp,
704	__in_ecount(n)	efx_desc_t *ed,
705	__in		unsigned int n,
706	__in		unsigned int completed,
707	__inout		unsigned int *addedp);
708
709extern	void
710ef10_tx_qdesc_dma_create(
711	__in	efx_txq_t *etp,
712	__in	efsys_dma_addr_t addr,
713	__in	size_t size,
714	__in	boolean_t eop,
715	__out	efx_desc_t *edp);
716
717extern	void
718ef10_tx_qdesc_tso_create(
719	__in	efx_txq_t *etp,
720	__in	uint16_t ipv4_id,
721	__in	uint32_t tcp_seq,
722	__in	uint8_t	 tcp_flags,
723	__out	efx_desc_t *edp);
724
725extern	void
726ef10_tx_qdesc_tso2_create(
727	__in			efx_txq_t *etp,
728	__in			uint16_t ipv4_id,
729	__in			uint32_t tcp_seq,
730	__in			uint16_t tcp_mss,
731	__out_ecount(count)	efx_desc_t *edp,
732	__in			int count);
733
734extern	void
735ef10_tx_qdesc_vlantci_create(
736	__in	efx_txq_t *etp,
737	__in	uint16_t vlan_tci,
738	__out	efx_desc_t *edp);
739
740
741#if EFSYS_OPT_QSTATS
742
743extern			void
744ef10_tx_qstats_update(
745	__in				efx_txq_t *etp,
746	__inout_ecount(TX_NQSTATS)	efsys_stat_t *stat);
747
748#endif /* EFSYS_OPT_QSTATS */
749
750typedef uint32_t	efx_piobuf_handle_t;
751
752#define	EFX_PIOBUF_HANDLE_INVALID	((efx_piobuf_handle_t) -1)
753
754extern	__checkReturn	efx_rc_t
755ef10_nic_pio_alloc(
756	__inout		efx_nic_t *enp,
757	__out		uint32_t *bufnump,
758	__out		efx_piobuf_handle_t *handlep,
759	__out		uint32_t *blknump,
760	__out		uint32_t *offsetp,
761	__out		size_t *sizep);
762
763extern	__checkReturn	efx_rc_t
764ef10_nic_pio_free(
765	__inout		efx_nic_t *enp,
766	__in		uint32_t bufnum,
767	__in		uint32_t blknum);
768
769extern	__checkReturn	efx_rc_t
770ef10_nic_pio_link(
771	__inout		efx_nic_t *enp,
772	__in		uint32_t vi_index,
773	__in		efx_piobuf_handle_t handle);
774
775extern	__checkReturn	efx_rc_t
776ef10_nic_pio_unlink(
777	__inout		efx_nic_t *enp,
778	__in		uint32_t vi_index);
779
780
781/* VPD */
782
783#if EFSYS_OPT_VPD
784
785extern	__checkReturn		efx_rc_t
786ef10_vpd_init(
787	__in			efx_nic_t *enp);
788
789extern	__checkReturn		efx_rc_t
790ef10_vpd_size(
791	__in			efx_nic_t *enp,
792	__out			size_t *sizep);
793
794extern	__checkReturn		efx_rc_t
795ef10_vpd_read(
796	__in			efx_nic_t *enp,
797	__out_bcount(size)	caddr_t data,
798	__in			size_t size);
799
800extern	__checkReturn		efx_rc_t
801ef10_vpd_verify(
802	__in			efx_nic_t *enp,
803	__in_bcount(size)	caddr_t data,
804	__in			size_t size);
805
806extern	__checkReturn		efx_rc_t
807ef10_vpd_reinit(
808	__in			efx_nic_t *enp,
809	__in_bcount(size)	caddr_t data,
810	__in			size_t size);
811
812extern	__checkReturn		efx_rc_t
813ef10_vpd_get(
814	__in			efx_nic_t *enp,
815	__in_bcount(size)	caddr_t data,
816	__in			size_t size,
817	__inout			efx_vpd_value_t *evvp);
818
819extern	__checkReturn		efx_rc_t
820ef10_vpd_set(
821	__in			efx_nic_t *enp,
822	__in_bcount(size)	caddr_t data,
823	__in			size_t size,
824	__in			efx_vpd_value_t *evvp);
825
826extern	__checkReturn		efx_rc_t
827ef10_vpd_next(
828	__in			efx_nic_t *enp,
829	__in_bcount(size)	caddr_t data,
830	__in			size_t size,
831	__out			efx_vpd_value_t *evvp,
832	__inout			unsigned int *contp);
833
834extern __checkReturn		efx_rc_t
835ef10_vpd_write(
836	__in			efx_nic_t *enp,
837	__in_bcount(size)	caddr_t data,
838	__in			size_t size);
839
840extern				void
841ef10_vpd_fini(
842	__in			efx_nic_t *enp);
843
844#endif	/* EFSYS_OPT_VPD */
845
846
847/* RX */
848
849extern	__checkReturn	efx_rc_t
850ef10_rx_init(
851	__in		efx_nic_t *enp);
852
853#if EFSYS_OPT_RX_SCATTER
854extern	__checkReturn	efx_rc_t
855ef10_rx_scatter_enable(
856	__in		efx_nic_t *enp,
857	__in		unsigned int buf_size);
858#endif	/* EFSYS_OPT_RX_SCATTER */
859
860
861#if EFSYS_OPT_RX_SCALE
862
863extern	__checkReturn	efx_rc_t
864ef10_rx_scale_mode_set(
865	__in		efx_nic_t *enp,
866	__in		efx_rx_hash_alg_t alg,
867	__in		efx_rx_hash_type_t type,
868	__in		boolean_t insert);
869
870extern	__checkReturn	efx_rc_t
871ef10_rx_scale_key_set(
872	__in		efx_nic_t *enp,
873	__in_ecount(n)	uint8_t *key,
874	__in		size_t n);
875
876extern	__checkReturn	efx_rc_t
877ef10_rx_scale_tbl_set(
878	__in		efx_nic_t *enp,
879	__in_ecount(n)	unsigned int *table,
880	__in		size_t n);
881
882extern	__checkReturn	uint32_t
883ef10_rx_prefix_hash(
884	__in		efx_nic_t *enp,
885	__in		efx_rx_hash_alg_t func,
886	__in		uint8_t *buffer);
887
888#endif /* EFSYS_OPT_RX_SCALE */
889
890extern	__checkReturn	efx_rc_t
891ef10_rx_prefix_pktlen(
892	__in		efx_nic_t *enp,
893	__in		uint8_t *buffer,
894	__out		uint16_t *lengthp);
895
896extern			void
897ef10_rx_qpost(
898	__in		efx_rxq_t *erp,
899	__in_ecount(n)	efsys_dma_addr_t *addrp,
900	__in		size_t size,
901	__in		unsigned int n,
902	__in		unsigned int completed,
903	__in		unsigned int added);
904
905extern			void
906ef10_rx_qpush(
907	__in		efx_rxq_t *erp,
908	__in		unsigned int added,
909	__inout		unsigned int *pushedp);
910
911extern	__checkReturn	efx_rc_t
912ef10_rx_qflush(
913	__in		efx_rxq_t *erp);
914
915extern		void
916ef10_rx_qenable(
917	__in		efx_rxq_t *erp);
918
919extern	__checkReturn	efx_rc_t
920ef10_rx_qcreate(
921	__in		efx_nic_t *enp,
922	__in		unsigned int index,
923	__in		unsigned int label,
924	__in		efx_rxq_type_t type,
925	__in		efsys_mem_t *esmp,
926	__in		size_t n,
927	__in		uint32_t id,
928	__in		efx_evq_t *eep,
929	__in		efx_rxq_t *erp);
930
931extern			void
932ef10_rx_qdestroy(
933	__in		efx_rxq_t *erp);
934
935extern			void
936ef10_rx_fini(
937	__in		efx_nic_t *enp);
938
939#if EFSYS_OPT_FILTER
940
941typedef struct ef10_filter_handle_s {
942	uint32_t	efh_lo;
943	uint32_t	efh_hi;
944} ef10_filter_handle_t;
945
946typedef struct ef10_filter_entry_s {
947	uintptr_t efe_spec; /* pointer to filter spec plus busy bit */
948	ef10_filter_handle_t efe_handle;
949} ef10_filter_entry_t;
950
951/*
952 * BUSY flag indicates that an update is in progress.
953 * AUTO_OLD flag is used to mark and sweep MAC packet filters.
954 */
955#define	EFX_EF10_FILTER_FLAG_BUSY	1U
956#define	EFX_EF10_FILTER_FLAG_AUTO_OLD	2U
957#define	EFX_EF10_FILTER_FLAGS		3U
958
959/*
960 * Size of the hash table used by the driver. Doesn't need to be the
961 * same size as the hardware's table.
962 */
963#define	EFX_EF10_FILTER_TBL_ROWS 8192
964
965/* Only need to allow for one directed and one unknown unicast filter */
966#define	EFX_EF10_FILTER_UNICAST_FILTERS_MAX	2
967
968/* Allow for the broadcast address to be added to the multicast list */
969#define	EFX_EF10_FILTER_MULTICAST_FILTERS_MAX	(EFX_MAC_MULTICAST_LIST_MAX + 1)
970
971typedef struct ef10_filter_table_s {
972	ef10_filter_entry_t	eft_entry[EFX_EF10_FILTER_TBL_ROWS];
973	efx_rxq_t *		eft_default_rxq;
974	boolean_t		eft_using_rss;
975	uint32_t		eft_unicst_filter_indexes[
976	    EFX_EF10_FILTER_UNICAST_FILTERS_MAX];
977	boolean_t		eft_unicst_filter_count;
978	uint32_t		eft_mulcst_filter_indexes[
979	    EFX_EF10_FILTER_MULTICAST_FILTERS_MAX];
980	uint32_t		eft_mulcst_filter_count;
981	boolean_t		eft_using_all_mulcst;
982} ef10_filter_table_t;
983
984	__checkReturn	efx_rc_t
985ef10_filter_init(
986	__in		efx_nic_t *enp);
987
988			void
989ef10_filter_fini(
990	__in		efx_nic_t *enp);
991
992	__checkReturn	efx_rc_t
993ef10_filter_restore(
994	__in		efx_nic_t *enp);
995
996	__checkReturn	efx_rc_t
997ef10_filter_add(
998	__in		efx_nic_t *enp,
999	__inout		efx_filter_spec_t *spec,
1000	__in		boolean_t may_replace);
1001
1002	__checkReturn	efx_rc_t
1003ef10_filter_delete(
1004	__in		efx_nic_t *enp,
1005	__inout		efx_filter_spec_t *spec);
1006
1007extern	__checkReturn	efx_rc_t
1008ef10_filter_supported_filters(
1009	__in		efx_nic_t *enp,
1010	__out		uint32_t *list,
1011	__out		size_t *length);
1012
1013extern	__checkReturn	efx_rc_t
1014ef10_filter_reconfigure(
1015	__in				efx_nic_t *enp,
1016	__in_ecount(6)			uint8_t const *mac_addr,
1017	__in				boolean_t all_unicst,
1018	__in				boolean_t mulcst,
1019	__in				boolean_t all_mulcst,
1020	__in				boolean_t brdcst,
1021	__in_ecount(6*count)		uint8_t const *addrs,
1022	__in				uint32_t count);
1023
1024extern		void
1025ef10_filter_get_default_rxq(
1026	__in		efx_nic_t *enp,
1027	__out		efx_rxq_t **erpp,
1028	__out		boolean_t *using_rss);
1029
1030extern		void
1031ef10_filter_default_rxq_set(
1032	__in		efx_nic_t *enp,
1033	__in		efx_rxq_t *erp,
1034	__in		boolean_t using_rss);
1035
1036extern		void
1037ef10_filter_default_rxq_clear(
1038	__in		efx_nic_t *enp);
1039
1040
1041#endif /* EFSYS_OPT_FILTER */
1042
1043extern	__checkReturn			efx_rc_t
1044efx_mcdi_get_function_info(
1045	__in				efx_nic_t *enp,
1046	__out				uint32_t *pfp,
1047	__out_opt			uint32_t *vfp);
1048
1049extern	__checkReturn		efx_rc_t
1050efx_mcdi_privilege_mask(
1051	__in			efx_nic_t *enp,
1052	__in			uint32_t pf,
1053	__in			uint32_t vf,
1054	__out			uint32_t *maskp);
1055
1056extern	__checkReturn	efx_rc_t
1057efx_mcdi_get_port_assignment(
1058	__in		efx_nic_t *enp,
1059	__out		uint32_t *portp);
1060
1061extern	__checkReturn	efx_rc_t
1062efx_mcdi_get_port_modes(
1063	__in		efx_nic_t *enp,
1064	__out		uint32_t *modesp);
1065
1066extern	__checkReturn	efx_rc_t
1067efx_mcdi_get_mac_address_pf(
1068	__in			efx_nic_t *enp,
1069	__out_ecount_opt(6)	uint8_t mac_addrp[6]);
1070
1071extern	__checkReturn	efx_rc_t
1072efx_mcdi_get_mac_address_vf(
1073	__in			efx_nic_t *enp,
1074	__out_ecount_opt(6)	uint8_t mac_addrp[6]);
1075
1076extern	__checkReturn	efx_rc_t
1077efx_mcdi_get_clock(
1078	__in		efx_nic_t *enp,
1079	__out		uint32_t *sys_freqp);
1080
1081extern	__checkReturn	efx_rc_t
1082efx_mcdi_get_vector_cfg(
1083	__in		efx_nic_t *enp,
1084	__out_opt	uint32_t *vec_basep,
1085	__out_opt	uint32_t *pf_nvecp,
1086	__out_opt	uint32_t *vf_nvecp);
1087
1088extern	__checkReturn	efx_rc_t
1089ef10_get_datapath_caps(
1090	__in		efx_nic_t *enp);
1091
1092extern	__checkReturn		efx_rc_t
1093ef10_get_privilege_mask(
1094	__in			efx_nic_t *enp,
1095	__out			uint32_t *maskp);
1096
1097extern	__checkReturn	efx_rc_t
1098ef10_external_port_mapping(
1099	__in		efx_nic_t *enp,
1100	__in		uint32_t port,
1101	__out		uint8_t *external_portp);
1102
1103
1104#ifdef	__cplusplus
1105}
1106#endif
1107
1108#endif	/* _SYS_EF10_IMPL_H */
1109