ef10_impl.h revision 310939
1252265Sjimharris/*- 2252265Sjimharris * Copyright (c) 2015-2016 Solarflare Communications Inc. 3252265Sjimharris * All rights reserved. 4252265Sjimharris * 5252265Sjimharris * Redistribution and use in source and binary forms, with or without 6252265Sjimharris * modification, are permitted provided that the following conditions are met: 7252265Sjimharris * 8252265Sjimharris * 1. Redistributions of source code must retain the above copyright notice, 9252265Sjimharris * this list of conditions and the following disclaimer. 10252265Sjimharris * 2. Redistributions in binary form must reproduce the above copyright notice, 11252265Sjimharris * this list of conditions and the following disclaimer in the documentation 12252265Sjimharris * and/or other materials provided with the distribution. 13252265Sjimharris * 14252265Sjimharris * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 15252265Sjimharris * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 16252265Sjimharris * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 17252265Sjimharris * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 18252265Sjimharris * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 19252265Sjimharris * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 20252265Sjimharris * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 21252265Sjimharris * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 22252265Sjimharris * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 23252265Sjimharris * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 24252265Sjimharris * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25252265Sjimharris * 26252265Sjimharris * The views and conclusions contained in the software and documentation are 27252265Sjimharris * those of the authors and should not be interpreted as representing official 28252265Sjimharris * policies, either expressed or implied, of the FreeBSD Project. 29252265Sjimharris * 30252265Sjimharris * $FreeBSD: stable/11/sys/dev/sfxge/common/ef10_impl.h 310939 2016-12-31 11:21:49Z arybchik $ 31252265Sjimharris */ 32252265Sjimharris 33252265Sjimharris#ifndef _SYS_EF10_IMPL_H 34252265Sjimharris#define _SYS_EF10_IMPL_H 35252265Sjimharris 36252265Sjimharris#ifdef __cplusplus 37252265Sjimharrisextern "C" { 38252265Sjimharris#endif 39252265Sjimharris 40252265Sjimharris#if (EFSYS_OPT_HUNTINGTON && EFSYS_OPT_MEDFORD) 41252265Sjimharris#define EF10_MAX_PIOBUF_NBUFS MAX(HUNT_PIOBUF_NBUFS, MEDFORD_PIOBUF_NBUFS) 42252265Sjimharris#elif EFSYS_OPT_HUNTINGTON 43252265Sjimharris#define EF10_MAX_PIOBUF_NBUFS HUNT_PIOBUF_NBUFS 44252265Sjimharris#elif EFSYS_OPT_MEDFORD 45252265Sjimharris#define EF10_MAX_PIOBUF_NBUFS MEDFORD_PIOBUF_NBUFS 46252265Sjimharris#endif 47252265Sjimharris 48252265Sjimharris/* 49252265Sjimharris * FIXME: This is just a power of 2 which fits in an MCDI v1 message, and could 50252265Sjimharris * possibly be increased, or the write size reported by newer firmware used 51252265Sjimharris * instead. 52252265Sjimharris */ 53252265Sjimharris#define EF10_NVRAM_CHUNK 0x80 54252658Sjimharris 55252659Sjimharris/* Alignment requirement for value written to RX WPTR: 56252660Sjimharris * the WPTR must be aligned to an 8 descriptor boundary 57252265Sjimharris */ 58252265Sjimharris#define EF10_RX_WPTR_ALIGN 8 59252265Sjimharris 60/* 61 * Max byte offset into the packet the TCP header must start for the hardware 62 * to be able to parse the packet correctly. 63 */ 64#define EF10_TCP_HEADER_OFFSET_LIMIT 208 65 66/* Invalid RSS context handle */ 67#define EF10_RSS_CONTEXT_INVALID (0xffffffff) 68 69 70/* EV */ 71 72 __checkReturn efx_rc_t 73ef10_ev_init( 74 __in efx_nic_t *enp); 75 76 void 77ef10_ev_fini( 78 __in efx_nic_t *enp); 79 80 __checkReturn efx_rc_t 81ef10_ev_qcreate( 82 __in efx_nic_t *enp, 83 __in unsigned int index, 84 __in efsys_mem_t *esmp, 85 __in size_t n, 86 __in uint32_t id, 87 __in uint32_t us, 88 __in uint32_t flags, 89 __in efx_evq_t *eep); 90 91 void 92ef10_ev_qdestroy( 93 __in efx_evq_t *eep); 94 95 __checkReturn efx_rc_t 96ef10_ev_qprime( 97 __in efx_evq_t *eep, 98 __in unsigned int count); 99 100 void 101ef10_ev_qpost( 102 __in efx_evq_t *eep, 103 __in uint16_t data); 104 105 __checkReturn efx_rc_t 106ef10_ev_qmoderate( 107 __in efx_evq_t *eep, 108 __in unsigned int us); 109 110#if EFSYS_OPT_QSTATS 111 void 112ef10_ev_qstats_update( 113 __in efx_evq_t *eep, 114 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat); 115#endif /* EFSYS_OPT_QSTATS */ 116 117 void 118ef10_ev_rxlabel_init( 119 __in efx_evq_t *eep, 120 __in efx_rxq_t *erp, 121 __in unsigned int label); 122 123 void 124ef10_ev_rxlabel_fini( 125 __in efx_evq_t *eep, 126 __in unsigned int label); 127 128/* INTR */ 129 130 __checkReturn efx_rc_t 131ef10_intr_init( 132 __in efx_nic_t *enp, 133 __in efx_intr_type_t type, 134 __in efsys_mem_t *esmp); 135 136 void 137ef10_intr_enable( 138 __in efx_nic_t *enp); 139 140 void 141ef10_intr_disable( 142 __in efx_nic_t *enp); 143 144 void 145ef10_intr_disable_unlocked( 146 __in efx_nic_t *enp); 147 148 __checkReturn efx_rc_t 149ef10_intr_trigger( 150 __in efx_nic_t *enp, 151 __in unsigned int level); 152 153 void 154ef10_intr_status_line( 155 __in efx_nic_t *enp, 156 __out boolean_t *fatalp, 157 __out uint32_t *qmaskp); 158 159 void 160ef10_intr_status_message( 161 __in efx_nic_t *enp, 162 __in unsigned int message, 163 __out boolean_t *fatalp); 164 165 void 166ef10_intr_fatal( 167 __in efx_nic_t *enp); 168 void 169ef10_intr_fini( 170 __in efx_nic_t *enp); 171 172/* NIC */ 173 174extern __checkReturn efx_rc_t 175ef10_nic_probe( 176 __in efx_nic_t *enp); 177 178extern __checkReturn efx_rc_t 179ef10_nic_set_drv_limits( 180 __inout efx_nic_t *enp, 181 __in efx_drv_limits_t *edlp); 182 183extern __checkReturn efx_rc_t 184ef10_nic_get_vi_pool( 185 __in efx_nic_t *enp, 186 __out uint32_t *vi_countp); 187 188extern __checkReturn efx_rc_t 189ef10_nic_get_bar_region( 190 __in efx_nic_t *enp, 191 __in efx_nic_region_t region, 192 __out uint32_t *offsetp, 193 __out size_t *sizep); 194 195extern __checkReturn efx_rc_t 196ef10_nic_reset( 197 __in efx_nic_t *enp); 198 199extern __checkReturn efx_rc_t 200ef10_nic_init( 201 __in efx_nic_t *enp); 202 203#if EFSYS_OPT_DIAG 204 205extern __checkReturn efx_rc_t 206ef10_nic_register_test( 207 __in efx_nic_t *enp); 208 209#endif /* EFSYS_OPT_DIAG */ 210 211extern void 212ef10_nic_fini( 213 __in efx_nic_t *enp); 214 215extern void 216ef10_nic_unprobe( 217 __in efx_nic_t *enp); 218 219 220/* MAC */ 221 222extern __checkReturn efx_rc_t 223ef10_mac_poll( 224 __in efx_nic_t *enp, 225 __out efx_link_mode_t *link_modep); 226 227extern __checkReturn efx_rc_t 228ef10_mac_up( 229 __in efx_nic_t *enp, 230 __out boolean_t *mac_upp); 231 232extern __checkReturn efx_rc_t 233ef10_mac_addr_set( 234 __in efx_nic_t *enp); 235 236extern __checkReturn efx_rc_t 237ef10_mac_pdu_set( 238 __in efx_nic_t *enp); 239 240extern __checkReturn efx_rc_t 241ef10_mac_pdu_get( 242 __in efx_nic_t *enp, 243 __out size_t *pdu); 244 245extern __checkReturn efx_rc_t 246ef10_mac_reconfigure( 247 __in efx_nic_t *enp); 248 249extern __checkReturn efx_rc_t 250ef10_mac_multicast_list_set( 251 __in efx_nic_t *enp); 252 253extern __checkReturn efx_rc_t 254ef10_mac_filter_default_rxq_set( 255 __in efx_nic_t *enp, 256 __in efx_rxq_t *erp, 257 __in boolean_t using_rss); 258 259extern void 260ef10_mac_filter_default_rxq_clear( 261 __in efx_nic_t *enp); 262 263#if EFSYS_OPT_LOOPBACK 264 265extern __checkReturn efx_rc_t 266ef10_mac_loopback_set( 267 __in efx_nic_t *enp, 268 __in efx_link_mode_t link_mode, 269 __in efx_loopback_type_t loopback_type); 270 271#endif /* EFSYS_OPT_LOOPBACK */ 272 273#if EFSYS_OPT_MAC_STATS 274 275extern __checkReturn efx_rc_t 276ef10_mac_stats_update( 277 __in efx_nic_t *enp, 278 __in efsys_mem_t *esmp, 279 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat, 280 __inout_opt uint32_t *generationp); 281 282#endif /* EFSYS_OPT_MAC_STATS */ 283 284 285/* MCDI */ 286 287#if EFSYS_OPT_MCDI 288 289extern __checkReturn efx_rc_t 290ef10_mcdi_init( 291 __in efx_nic_t *enp, 292 __in const efx_mcdi_transport_t *mtp); 293 294extern void 295ef10_mcdi_fini( 296 __in efx_nic_t *enp); 297 298extern void 299ef10_mcdi_send_request( 300 __in efx_nic_t *enp, 301 __in_bcount(hdr_len) void *hdrp, 302 __in size_t hdr_len, 303 __in_bcount(sdu_len) void *sdup, 304 __in size_t sdu_len); 305 306extern __checkReturn boolean_t 307ef10_mcdi_poll_response( 308 __in efx_nic_t *enp); 309 310extern void 311ef10_mcdi_read_response( 312 __in efx_nic_t *enp, 313 __out_bcount(length) void *bufferp, 314 __in size_t offset, 315 __in size_t length); 316 317extern efx_rc_t 318ef10_mcdi_poll_reboot( 319 __in efx_nic_t *enp); 320 321extern __checkReturn efx_rc_t 322ef10_mcdi_feature_supported( 323 __in efx_nic_t *enp, 324 __in efx_mcdi_feature_id_t id, 325 __out boolean_t *supportedp); 326 327#endif /* EFSYS_OPT_MCDI */ 328 329/* NVRAM */ 330 331#if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD 332 333extern __checkReturn efx_rc_t 334ef10_nvram_buf_read_tlv( 335 __in efx_nic_t *enp, 336 __in_bcount(max_seg_size) caddr_t seg_data, 337 __in size_t max_seg_size, 338 __in uint32_t tag, 339 __deref_out_bcount_opt(*sizep) caddr_t *datap, 340 __out size_t *sizep); 341 342extern __checkReturn efx_rc_t 343ef10_nvram_buf_write_tlv( 344 __inout_bcount(partn_size) caddr_t partn_data, 345 __in size_t partn_size, 346 __in uint32_t tag, 347 __in_bcount(tag_size) caddr_t tag_data, 348 __in size_t tag_size, 349 __out size_t *total_lengthp); 350 351extern __checkReturn efx_rc_t 352ef10_nvram_partn_read_tlv( 353 __in efx_nic_t *enp, 354 __in uint32_t partn, 355 __in uint32_t tag, 356 __deref_out_bcount_opt(*sizep) caddr_t *datap, 357 __out size_t *sizep); 358 359extern __checkReturn efx_rc_t 360ef10_nvram_partn_write_tlv( 361 __in efx_nic_t *enp, 362 __in uint32_t partn, 363 __in uint32_t tag, 364 __in_bcount(size) caddr_t data, 365 __in size_t size); 366 367extern __checkReturn efx_rc_t 368ef10_nvram_partn_write_segment_tlv( 369 __in efx_nic_t *enp, 370 __in uint32_t partn, 371 __in uint32_t tag, 372 __in_bcount(size) caddr_t data, 373 __in size_t size, 374 __in boolean_t all_segments); 375 376extern __checkReturn efx_rc_t 377ef10_nvram_partn_lock( 378 __in efx_nic_t *enp, 379 __in uint32_t partn); 380 381extern void 382ef10_nvram_partn_unlock( 383 __in efx_nic_t *enp, 384 __in uint32_t partn); 385 386#endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */ 387 388#if EFSYS_OPT_NVRAM 389 390#if EFSYS_OPT_DIAG 391 392extern __checkReturn efx_rc_t 393ef10_nvram_test( 394 __in efx_nic_t *enp); 395 396#endif /* EFSYS_OPT_DIAG */ 397 398extern __checkReturn efx_rc_t 399ef10_nvram_type_to_partn( 400 __in efx_nic_t *enp, 401 __in efx_nvram_type_t type, 402 __out uint32_t *partnp); 403 404extern __checkReturn efx_rc_t 405ef10_nvram_partn_size( 406 __in efx_nic_t *enp, 407 __in uint32_t partn, 408 __out size_t *sizep); 409 410extern __checkReturn efx_rc_t 411ef10_nvram_partn_rw_start( 412 __in efx_nic_t *enp, 413 __in uint32_t partn, 414 __out size_t *chunk_sizep); 415 416extern __checkReturn efx_rc_t 417ef10_nvram_partn_read_mode( 418 __in efx_nic_t *enp, 419 __in uint32_t partn, 420 __in unsigned int offset, 421 __out_bcount(size) caddr_t data, 422 __in size_t size, 423 __in uint32_t mode); 424 425extern __checkReturn efx_rc_t 426ef10_nvram_partn_read( 427 __in efx_nic_t *enp, 428 __in uint32_t partn, 429 __in unsigned int offset, 430 __out_bcount(size) caddr_t data, 431 __in size_t size); 432 433extern __checkReturn efx_rc_t 434ef10_nvram_partn_erase( 435 __in efx_nic_t *enp, 436 __in uint32_t partn, 437 __in unsigned int offset, 438 __in size_t size); 439 440extern __checkReturn efx_rc_t 441ef10_nvram_partn_write( 442 __in efx_nic_t *enp, 443 __in uint32_t partn, 444 __in unsigned int offset, 445 __out_bcount(size) caddr_t data, 446 __in size_t size); 447 448extern void 449ef10_nvram_partn_rw_finish( 450 __in efx_nic_t *enp, 451 __in uint32_t partn); 452 453extern __checkReturn efx_rc_t 454ef10_nvram_partn_get_version( 455 __in efx_nic_t *enp, 456 __in uint32_t partn, 457 __out uint32_t *subtypep, 458 __out_ecount(4) uint16_t version[4]); 459 460extern __checkReturn efx_rc_t 461ef10_nvram_partn_set_version( 462 __in efx_nic_t *enp, 463 __in uint32_t partn, 464 __in_ecount(4) uint16_t version[4]); 465 466extern __checkReturn efx_rc_t 467ef10_nvram_buffer_validate( 468 __in efx_nic_t *enp, 469 __in uint32_t partn, 470 __in_bcount(buffer_size) 471 caddr_t bufferp, 472 __in size_t buffer_size); 473 474extern __checkReturn efx_rc_t 475ef10_nvram_buffer_create( 476 __in efx_nic_t *enp, 477 __in uint16_t partn_type, 478 __in_bcount(buffer_size) 479 caddr_t bufferp, 480 __in size_t buffer_size); 481 482extern __checkReturn efx_rc_t 483ef10_nvram_buffer_find_item_start( 484 __in_bcount(buffer_size) 485 caddr_t bufferp, 486 __in size_t buffer_size, 487 __out uint32_t *startp 488 ); 489 490extern __checkReturn efx_rc_t 491ef10_nvram_buffer_find_end( 492 __in_bcount(buffer_size) 493 caddr_t bufferp, 494 __in size_t buffer_size, 495 __in uint32_t offset, 496 __out uint32_t *endp 497 ); 498 499extern __checkReturn __success(return != B_FALSE) boolean_t 500ef10_nvram_buffer_find_item( 501 __in_bcount(buffer_size) 502 caddr_t bufferp, 503 __in size_t buffer_size, 504 __in uint32_t offset, 505 __out uint32_t *startp, 506 __out uint32_t *lengthp 507 ); 508 509extern __checkReturn efx_rc_t 510ef10_nvram_buffer_get_item( 511 __in_bcount(buffer_size) 512 caddr_t bufferp, 513 __in size_t buffer_size, 514 __in uint32_t offset, 515 __in uint32_t length, 516 __out_bcount_part(item_max_size, *lengthp) 517 caddr_t itemp, 518 __in size_t item_max_size, 519 __out uint32_t *lengthp 520 ); 521 522extern __checkReturn efx_rc_t 523ef10_nvram_buffer_insert_item( 524 __in_bcount(buffer_size) 525 caddr_t bufferp, 526 __in size_t buffer_size, 527 __in uint32_t offset, 528 __in_bcount(length) caddr_t keyp, 529 __in uint32_t length, 530 __out uint32_t *lengthp 531 ); 532 533extern __checkReturn efx_rc_t 534ef10_nvram_buffer_delete_item( 535 __in_bcount(buffer_size) 536 caddr_t bufferp, 537 __in size_t buffer_size, 538 __in uint32_t offset, 539 __in uint32_t length, 540 __in uint32_t end 541 ); 542 543extern __checkReturn efx_rc_t 544ef10_nvram_buffer_finish( 545 __in_bcount(buffer_size) 546 caddr_t bufferp, 547 __in size_t buffer_size 548 ); 549 550#endif /* EFSYS_OPT_NVRAM */ 551 552 553/* PHY */ 554 555typedef struct ef10_link_state_s { 556 uint32_t els_adv_cap_mask; 557 uint32_t els_lp_cap_mask; 558 unsigned int els_fcntl; 559 efx_link_mode_t els_link_mode; 560#if EFSYS_OPT_LOOPBACK 561 efx_loopback_type_t els_loopback; 562#endif 563 boolean_t els_mac_up; 564} ef10_link_state_t; 565 566extern void 567ef10_phy_link_ev( 568 __in efx_nic_t *enp, 569 __in efx_qword_t *eqp, 570 __out efx_link_mode_t *link_modep); 571 572extern __checkReturn efx_rc_t 573ef10_phy_get_link( 574 __in efx_nic_t *enp, 575 __out ef10_link_state_t *elsp); 576 577extern __checkReturn efx_rc_t 578ef10_phy_power( 579 __in efx_nic_t *enp, 580 __in boolean_t on); 581 582extern __checkReturn efx_rc_t 583ef10_phy_reconfigure( 584 __in efx_nic_t *enp); 585 586extern __checkReturn efx_rc_t 587ef10_phy_verify( 588 __in efx_nic_t *enp); 589 590extern __checkReturn efx_rc_t 591ef10_phy_oui_get( 592 __in efx_nic_t *enp, 593 __out uint32_t *ouip); 594 595#if EFSYS_OPT_PHY_STATS 596 597extern __checkReturn efx_rc_t 598ef10_phy_stats_update( 599 __in efx_nic_t *enp, 600 __in efsys_mem_t *esmp, 601 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat); 602 603#endif /* EFSYS_OPT_PHY_STATS */ 604 605 606/* TX */ 607 608extern __checkReturn efx_rc_t 609ef10_tx_init( 610 __in efx_nic_t *enp); 611 612extern void 613ef10_tx_fini( 614 __in efx_nic_t *enp); 615 616extern __checkReturn efx_rc_t 617ef10_tx_qcreate( 618 __in efx_nic_t *enp, 619 __in unsigned int index, 620 __in unsigned int label, 621 __in efsys_mem_t *esmp, 622 __in size_t n, 623 __in uint32_t id, 624 __in uint16_t flags, 625 __in efx_evq_t *eep, 626 __in efx_txq_t *etp, 627 __out unsigned int *addedp); 628 629extern void 630ef10_tx_qdestroy( 631 __in efx_txq_t *etp); 632 633extern __checkReturn efx_rc_t 634ef10_tx_qpost( 635 __in efx_txq_t *etp, 636 __in_ecount(n) efx_buffer_t *eb, 637 __in unsigned int n, 638 __in unsigned int completed, 639 __inout unsigned int *addedp); 640 641extern void 642ef10_tx_qpush( 643 __in efx_txq_t *etp, 644 __in unsigned int added, 645 __in unsigned int pushed); 646 647extern __checkReturn efx_rc_t 648ef10_tx_qpace( 649 __in efx_txq_t *etp, 650 __in unsigned int ns); 651 652extern __checkReturn efx_rc_t 653ef10_tx_qflush( 654 __in efx_txq_t *etp); 655 656extern void 657ef10_tx_qenable( 658 __in efx_txq_t *etp); 659 660extern __checkReturn efx_rc_t 661ef10_tx_qpio_enable( 662 __in efx_txq_t *etp); 663 664extern void 665ef10_tx_qpio_disable( 666 __in efx_txq_t *etp); 667 668extern __checkReturn efx_rc_t 669ef10_tx_qpio_write( 670 __in efx_txq_t *etp, 671 __in_ecount(buf_length) uint8_t *buffer, 672 __in size_t buf_length, 673 __in size_t pio_buf_offset); 674 675extern __checkReturn efx_rc_t 676ef10_tx_qpio_post( 677 __in efx_txq_t *etp, 678 __in size_t pkt_length, 679 __in unsigned int completed, 680 __inout unsigned int *addedp); 681 682extern __checkReturn efx_rc_t 683ef10_tx_qdesc_post( 684 __in efx_txq_t *etp, 685 __in_ecount(n) efx_desc_t *ed, 686 __in unsigned int n, 687 __in unsigned int completed, 688 __inout unsigned int *addedp); 689 690extern void 691ef10_tx_qdesc_dma_create( 692 __in efx_txq_t *etp, 693 __in efsys_dma_addr_t addr, 694 __in size_t size, 695 __in boolean_t eop, 696 __out efx_desc_t *edp); 697 698extern void 699ef10_tx_qdesc_tso_create( 700 __in efx_txq_t *etp, 701 __in uint16_t ipv4_id, 702 __in uint32_t tcp_seq, 703 __in uint8_t tcp_flags, 704 __out efx_desc_t *edp); 705 706extern void 707ef10_tx_qdesc_tso2_create( 708 __in efx_txq_t *etp, 709 __in uint16_t ipv4_id, 710 __in uint32_t tcp_seq, 711 __in uint16_t tcp_mss, 712 __out_ecount(count) efx_desc_t *edp, 713 __in int count); 714 715extern void 716ef10_tx_qdesc_vlantci_create( 717 __in efx_txq_t *etp, 718 __in uint16_t vlan_tci, 719 __out efx_desc_t *edp); 720 721 722#if EFSYS_OPT_QSTATS 723 724extern void 725ef10_tx_qstats_update( 726 __in efx_txq_t *etp, 727 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat); 728 729#endif /* EFSYS_OPT_QSTATS */ 730 731typedef uint32_t efx_piobuf_handle_t; 732 733#define EFX_PIOBUF_HANDLE_INVALID ((efx_piobuf_handle_t) -1) 734 735extern __checkReturn efx_rc_t 736ef10_nic_pio_alloc( 737 __inout efx_nic_t *enp, 738 __out uint32_t *bufnump, 739 __out efx_piobuf_handle_t *handlep, 740 __out uint32_t *blknump, 741 __out uint32_t *offsetp, 742 __out size_t *sizep); 743 744extern __checkReturn efx_rc_t 745ef10_nic_pio_free( 746 __inout efx_nic_t *enp, 747 __in uint32_t bufnum, 748 __in uint32_t blknum); 749 750extern __checkReturn efx_rc_t 751ef10_nic_pio_link( 752 __inout efx_nic_t *enp, 753 __in uint32_t vi_index, 754 __in efx_piobuf_handle_t handle); 755 756extern __checkReturn efx_rc_t 757ef10_nic_pio_unlink( 758 __inout efx_nic_t *enp, 759 __in uint32_t vi_index); 760 761 762/* VPD */ 763 764#if EFSYS_OPT_VPD 765 766extern __checkReturn efx_rc_t 767ef10_vpd_init( 768 __in efx_nic_t *enp); 769 770extern __checkReturn efx_rc_t 771ef10_vpd_size( 772 __in efx_nic_t *enp, 773 __out size_t *sizep); 774 775extern __checkReturn efx_rc_t 776ef10_vpd_read( 777 __in efx_nic_t *enp, 778 __out_bcount(size) caddr_t data, 779 __in size_t size); 780 781extern __checkReturn efx_rc_t 782ef10_vpd_verify( 783 __in efx_nic_t *enp, 784 __in_bcount(size) caddr_t data, 785 __in size_t size); 786 787extern __checkReturn efx_rc_t 788ef10_vpd_reinit( 789 __in efx_nic_t *enp, 790 __in_bcount(size) caddr_t data, 791 __in size_t size); 792 793extern __checkReturn efx_rc_t 794ef10_vpd_get( 795 __in efx_nic_t *enp, 796 __in_bcount(size) caddr_t data, 797 __in size_t size, 798 __inout efx_vpd_value_t *evvp); 799 800extern __checkReturn efx_rc_t 801ef10_vpd_set( 802 __in efx_nic_t *enp, 803 __in_bcount(size) caddr_t data, 804 __in size_t size, 805 __in efx_vpd_value_t *evvp); 806 807extern __checkReturn efx_rc_t 808ef10_vpd_next( 809 __in efx_nic_t *enp, 810 __in_bcount(size) caddr_t data, 811 __in size_t size, 812 __out efx_vpd_value_t *evvp, 813 __inout unsigned int *contp); 814 815extern __checkReturn efx_rc_t 816ef10_vpd_write( 817 __in efx_nic_t *enp, 818 __in_bcount(size) caddr_t data, 819 __in size_t size); 820 821extern void 822ef10_vpd_fini( 823 __in efx_nic_t *enp); 824 825#endif /* EFSYS_OPT_VPD */ 826 827 828/* RX */ 829 830extern __checkReturn efx_rc_t 831ef10_rx_init( 832 __in efx_nic_t *enp); 833 834#if EFSYS_OPT_RX_SCATTER 835extern __checkReturn efx_rc_t 836ef10_rx_scatter_enable( 837 __in efx_nic_t *enp, 838 __in unsigned int buf_size); 839#endif /* EFSYS_OPT_RX_SCATTER */ 840 841 842#if EFSYS_OPT_RX_SCALE 843 844extern __checkReturn efx_rc_t 845ef10_rx_scale_mode_set( 846 __in efx_nic_t *enp, 847 __in efx_rx_hash_alg_t alg, 848 __in efx_rx_hash_type_t type, 849 __in boolean_t insert); 850 851extern __checkReturn efx_rc_t 852ef10_rx_scale_key_set( 853 __in efx_nic_t *enp, 854 __in_ecount(n) uint8_t *key, 855 __in size_t n); 856 857extern __checkReturn efx_rc_t 858ef10_rx_scale_tbl_set( 859 __in efx_nic_t *enp, 860 __in_ecount(n) unsigned int *table, 861 __in size_t n); 862 863extern __checkReturn uint32_t 864ef10_rx_prefix_hash( 865 __in efx_nic_t *enp, 866 __in efx_rx_hash_alg_t func, 867 __in uint8_t *buffer); 868 869#endif /* EFSYS_OPT_RX_SCALE */ 870 871extern __checkReturn efx_rc_t 872ef10_rx_prefix_pktlen( 873 __in efx_nic_t *enp, 874 __in uint8_t *buffer, 875 __out uint16_t *lengthp); 876 877extern void 878ef10_rx_qpost( 879 __in efx_rxq_t *erp, 880 __in_ecount(n) efsys_dma_addr_t *addrp, 881 __in size_t size, 882 __in unsigned int n, 883 __in unsigned int completed, 884 __in unsigned int added); 885 886extern void 887ef10_rx_qpush( 888 __in efx_rxq_t *erp, 889 __in unsigned int added, 890 __inout unsigned int *pushedp); 891 892extern __checkReturn efx_rc_t 893ef10_rx_qflush( 894 __in efx_rxq_t *erp); 895 896extern void 897ef10_rx_qenable( 898 __in efx_rxq_t *erp); 899 900extern __checkReturn efx_rc_t 901ef10_rx_qcreate( 902 __in efx_nic_t *enp, 903 __in unsigned int index, 904 __in unsigned int label, 905 __in efx_rxq_type_t type, 906 __in efsys_mem_t *esmp, 907 __in size_t n, 908 __in uint32_t id, 909 __in efx_evq_t *eep, 910 __in efx_rxq_t *erp); 911 912extern void 913ef10_rx_qdestroy( 914 __in efx_rxq_t *erp); 915 916extern void 917ef10_rx_fini( 918 __in efx_nic_t *enp); 919 920#if EFSYS_OPT_FILTER 921 922typedef struct ef10_filter_handle_s { 923 uint32_t efh_lo; 924 uint32_t efh_hi; 925} ef10_filter_handle_t; 926 927typedef struct ef10_filter_entry_s { 928 uintptr_t efe_spec; /* pointer to filter spec plus busy bit */ 929 ef10_filter_handle_t efe_handle; 930} ef10_filter_entry_t; 931 932/* 933 * BUSY flag indicates that an update is in progress. 934 * AUTO_OLD flag is used to mark and sweep MAC packet filters. 935 */ 936#define EFX_EF10_FILTER_FLAG_BUSY 1U 937#define EFX_EF10_FILTER_FLAG_AUTO_OLD 2U 938#define EFX_EF10_FILTER_FLAGS 3U 939 940/* 941 * Size of the hash table used by the driver. Doesn't need to be the 942 * same size as the hardware's table. 943 */ 944#define EFX_EF10_FILTER_TBL_ROWS 8192 945 946/* Only need to allow for one directed and one unknown unicast filter */ 947#define EFX_EF10_FILTER_UNICAST_FILTERS_MAX 2 948 949/* Allow for the broadcast address to be added to the multicast list */ 950#define EFX_EF10_FILTER_MULTICAST_FILTERS_MAX (EFX_MAC_MULTICAST_LIST_MAX + 1) 951 952typedef struct ef10_filter_table_s { 953 ef10_filter_entry_t eft_entry[EFX_EF10_FILTER_TBL_ROWS]; 954 efx_rxq_t *eft_default_rxq; 955 boolean_t eft_using_rss; 956 uint32_t eft_unicst_filter_indexes[ 957 EFX_EF10_FILTER_UNICAST_FILTERS_MAX]; 958 uint32_t eft_unicst_filter_count; 959 uint32_t eft_mulcst_filter_indexes[ 960 EFX_EF10_FILTER_MULTICAST_FILTERS_MAX]; 961 uint32_t eft_mulcst_filter_count; 962 boolean_t eft_using_all_mulcst; 963} ef10_filter_table_t; 964 965 __checkReturn efx_rc_t 966ef10_filter_init( 967 __in efx_nic_t *enp); 968 969 void 970ef10_filter_fini( 971 __in efx_nic_t *enp); 972 973 __checkReturn efx_rc_t 974ef10_filter_restore( 975 __in efx_nic_t *enp); 976 977 __checkReturn efx_rc_t 978ef10_filter_add( 979 __in efx_nic_t *enp, 980 __inout efx_filter_spec_t *spec, 981 __in boolean_t may_replace); 982 983 __checkReturn efx_rc_t 984ef10_filter_delete( 985 __in efx_nic_t *enp, 986 __inout efx_filter_spec_t *spec); 987 988extern __checkReturn efx_rc_t 989ef10_filter_supported_filters( 990 __in efx_nic_t *enp, 991 __out uint32_t *list, 992 __out size_t *length); 993 994extern __checkReturn efx_rc_t 995ef10_filter_reconfigure( 996 __in efx_nic_t *enp, 997 __in_ecount(6) uint8_t const *mac_addr, 998 __in boolean_t all_unicst, 999 __in boolean_t mulcst, 1000 __in boolean_t all_mulcst, 1001 __in boolean_t brdcst, 1002 __in_ecount(6*count) uint8_t const *addrs, 1003 __in uint32_t count); 1004 1005extern void 1006ef10_filter_get_default_rxq( 1007 __in efx_nic_t *enp, 1008 __out efx_rxq_t **erpp, 1009 __out boolean_t *using_rss); 1010 1011extern void 1012ef10_filter_default_rxq_set( 1013 __in efx_nic_t *enp, 1014 __in efx_rxq_t *erp, 1015 __in boolean_t using_rss); 1016 1017extern void 1018ef10_filter_default_rxq_clear( 1019 __in efx_nic_t *enp); 1020 1021 1022#endif /* EFSYS_OPT_FILTER */ 1023 1024extern __checkReturn efx_rc_t 1025efx_mcdi_get_function_info( 1026 __in efx_nic_t *enp, 1027 __out uint32_t *pfp, 1028 __out_opt uint32_t *vfp); 1029 1030extern __checkReturn efx_rc_t 1031efx_mcdi_privilege_mask( 1032 __in efx_nic_t *enp, 1033 __in uint32_t pf, 1034 __in uint32_t vf, 1035 __out uint32_t *maskp); 1036 1037extern __checkReturn efx_rc_t 1038efx_mcdi_get_port_assignment( 1039 __in efx_nic_t *enp, 1040 __out uint32_t *portp); 1041 1042extern __checkReturn efx_rc_t 1043efx_mcdi_get_port_modes( 1044 __in efx_nic_t *enp, 1045 __out uint32_t *modesp, 1046 __out_opt uint32_t *current_modep); 1047 1048extern __checkReturn efx_rc_t 1049ef10_nic_get_port_mode_bandwidth( 1050 __in uint32_t port_mode, 1051 __out uint32_t *bandwidth_mbpsp); 1052 1053extern __checkReturn efx_rc_t 1054efx_mcdi_get_mac_address_pf( 1055 __in efx_nic_t *enp, 1056 __out_ecount_opt(6) uint8_t mac_addrp[6]); 1057 1058extern __checkReturn efx_rc_t 1059efx_mcdi_get_mac_address_vf( 1060 __in efx_nic_t *enp, 1061 __out_ecount_opt(6) uint8_t mac_addrp[6]); 1062 1063extern __checkReturn efx_rc_t 1064efx_mcdi_get_clock( 1065 __in efx_nic_t *enp, 1066 __out uint32_t *sys_freqp, 1067 __out uint32_t *dpcpu_freqp); 1068 1069 1070extern __checkReturn efx_rc_t 1071efx_mcdi_get_vector_cfg( 1072 __in efx_nic_t *enp, 1073 __out_opt uint32_t *vec_basep, 1074 __out_opt uint32_t *pf_nvecp, 1075 __out_opt uint32_t *vf_nvecp); 1076 1077extern __checkReturn efx_rc_t 1078ef10_get_datapath_caps( 1079 __in efx_nic_t *enp); 1080 1081extern __checkReturn efx_rc_t 1082ef10_get_privilege_mask( 1083 __in efx_nic_t *enp, 1084 __out uint32_t *maskp); 1085 1086extern __checkReturn efx_rc_t 1087ef10_external_port_mapping( 1088 __in efx_nic_t *enp, 1089 __in uint32_t port, 1090 __out uint8_t *external_portp); 1091 1092 1093#ifdef __cplusplus 1094} 1095#endif 1096 1097#endif /* _SYS_EF10_IMPL_H */ 1098