if_sf.c revision 93818
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/dev/sf/if_sf.c 93818 2002-04-04 21:03:38Z jhb $ 33 */ 34 35/* 36 * Adaptec AIC-6915 "Starfire" PCI fast ethernet driver for FreeBSD. 37 * Programming manual is available from: 38 * ftp.adaptec.com:/pub/BBS/userguides/aic6915_pg.pdf. 39 * 40 * Written by Bill Paul <wpaul@ctr.columbia.edu> 41 * Department of Electical Engineering 42 * Columbia University, New York City 43 */ 44 45/* 46 * The Adaptec AIC-6915 "Starfire" is a 64-bit 10/100 PCI ethernet 47 * controller designed with flexibility and reducing CPU load in mind. 48 * The Starfire offers high and low priority buffer queues, a 49 * producer/consumer index mechanism and several different buffer 50 * queue and completion queue descriptor types. Any one of a number 51 * of different driver designs can be used, depending on system and 52 * OS requirements. This driver makes use of type0 transmit frame 53 * descriptors (since BSD fragments packets across an mbuf chain) 54 * and two RX buffer queues prioritized on size (one queue for small 55 * frames that will fit into a single mbuf, another with full size 56 * mbuf clusters for everything else). The producer/consumer indexes 57 * and completion queues are also used. 58 * 59 * One downside to the Starfire has to do with alignment: buffer 60 * queues must be aligned on 256-byte boundaries, and receive buffers 61 * must be aligned on longword boundaries. The receive buffer alignment 62 * causes problems on the Alpha platform, where the packet payload 63 * should be longword aligned. There is no simple way around this. 64 * 65 * For receive filtering, the Starfire offers 16 perfect filter slots 66 * and a 512-bit hash table. 67 * 68 * The Starfire has no internal transceiver, relying instead on an 69 * external MII-based transceiver. Accessing registers on external 70 * PHYs is done through a special register map rather than with the 71 * usual bitbang MDIO method. 72 * 73 * Acesssing the registers on the Starfire is a little tricky. The 74 * Starfire has a 512K internal register space. When programmed for 75 * PCI memory mapped mode, the entire register space can be accessed 76 * directly. However in I/O space mode, only 256 bytes are directly 77 * mapped into PCI I/O space. The other registers can be accessed 78 * indirectly using the SF_INDIRECTIO_ADDR and SF_INDIRECTIO_DATA 79 * registers inside the 256-byte I/O window. 80 */ 81 82#include <sys/param.h> 83#include <sys/systm.h> 84#include <sys/sockio.h> 85#include <sys/mbuf.h> 86#include <sys/malloc.h> 87#include <sys/kernel.h> 88#include <sys/socket.h> 89 90#include <net/if.h> 91#include <net/if_arp.h> 92#include <net/ethernet.h> 93#include <net/if_dl.h> 94#include <net/if_media.h> 95 96#include <net/bpf.h> 97 98#include <vm/vm.h> /* for vtophys */ 99#include <vm/pmap.h> /* for vtophys */ 100#include <machine/bus_pio.h> 101#include <machine/bus_memio.h> 102#include <machine/bus.h> 103#include <machine/resource.h> 104#include <sys/bus.h> 105#include <sys/rman.h> 106 107#include <dev/mii/mii.h> 108#include <dev/mii/miivar.h> 109 110/* "controller miibus0" required. See GENERIC if you get errors here. */ 111#include "miibus_if.h" 112 113#include <pci/pcireg.h> 114#include <pci/pcivar.h> 115 116#define SF_USEIOSPACE 117 118#include <pci/if_sfreg.h> 119 120MODULE_DEPEND(sf, miibus, 1, 1, 1); 121 122#ifndef lint 123static const char rcsid[] = 124 "$FreeBSD: head/sys/dev/sf/if_sf.c 93818 2002-04-04 21:03:38Z jhb $"; 125#endif 126 127static struct sf_type sf_devs[] = { 128 { AD_VENDORID, AD_DEVICEID_STARFIRE, 129 "Adaptec AIC-6915 10/100BaseTX" }, 130 { 0, 0, NULL } 131}; 132 133static int sf_probe (device_t); 134static int sf_attach (device_t); 135static int sf_detach (device_t); 136static void sf_intr (void *); 137static void sf_stats_update (void *); 138static void sf_rxeof (struct sf_softc *); 139static void sf_txeof (struct sf_softc *); 140static int sf_encap (struct sf_softc *, 141 struct sf_tx_bufdesc_type0 *, 142 struct mbuf *); 143static void sf_start (struct ifnet *); 144static int sf_ioctl (struct ifnet *, u_long, caddr_t); 145static void sf_init (void *); 146static void sf_stop (struct sf_softc *); 147static void sf_watchdog (struct ifnet *); 148static void sf_shutdown (device_t); 149static int sf_ifmedia_upd (struct ifnet *); 150static void sf_ifmedia_sts (struct ifnet *, struct ifmediareq *); 151static void sf_reset (struct sf_softc *); 152static int sf_init_rx_ring (struct sf_softc *); 153static void sf_init_tx_ring (struct sf_softc *); 154static int sf_newbuf (struct sf_softc *, 155 struct sf_rx_bufdesc_type0 *, 156 struct mbuf *); 157static void sf_setmulti (struct sf_softc *); 158static int sf_setperf (struct sf_softc *, int, caddr_t); 159static int sf_sethash (struct sf_softc *, caddr_t, int); 160#ifdef notdef 161static int sf_setvlan (struct sf_softc *, int, u_int32_t); 162#endif 163 164static u_int8_t sf_read_eeprom (struct sf_softc *, int); 165static u_int32_t sf_calchash (caddr_t); 166 167static int sf_miibus_readreg (device_t, int, int); 168static int sf_miibus_writereg (device_t, int, int, int); 169static void sf_miibus_statchg (device_t); 170 171static u_int32_t csr_read_4 (struct sf_softc *, int); 172static void csr_write_4 (struct sf_softc *, int, u_int32_t); 173static void sf_txthresh_adjust (struct sf_softc *); 174 175#ifdef SF_USEIOSPACE 176#define SF_RES SYS_RES_IOPORT 177#define SF_RID SF_PCI_LOIO 178#else 179#define SF_RES SYS_RES_MEMORY 180#define SF_RID SF_PCI_LOMEM 181#endif 182 183static device_method_t sf_methods[] = { 184 /* Device interface */ 185 DEVMETHOD(device_probe, sf_probe), 186 DEVMETHOD(device_attach, sf_attach), 187 DEVMETHOD(device_detach, sf_detach), 188 DEVMETHOD(device_shutdown, sf_shutdown), 189 190 /* bus interface */ 191 DEVMETHOD(bus_print_child, bus_generic_print_child), 192 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 193 194 /* MII interface */ 195 DEVMETHOD(miibus_readreg, sf_miibus_readreg), 196 DEVMETHOD(miibus_writereg, sf_miibus_writereg), 197 DEVMETHOD(miibus_statchg, sf_miibus_statchg), 198 199 { 0, 0 } 200}; 201 202static driver_t sf_driver = { 203 "sf", 204 sf_methods, 205 sizeof(struct sf_softc), 206}; 207 208static devclass_t sf_devclass; 209 210DRIVER_MODULE(if_sf, pci, sf_driver, sf_devclass, 0, 0); 211DRIVER_MODULE(miibus, sf, miibus_driver, miibus_devclass, 0, 0); 212 213#define SF_SETBIT(sc, reg, x) \ 214 csr_write_4(sc, reg, csr_read_4(sc, reg) | x) 215 216#define SF_CLRBIT(sc, reg, x) \ 217 csr_write_4(sc, reg, csr_read_4(sc, reg) & ~x) 218 219static u_int32_t csr_read_4(sc, reg) 220 struct sf_softc *sc; 221 int reg; 222{ 223 u_int32_t val; 224 225#ifdef SF_USEIOSPACE 226 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); 227 val = CSR_READ_4(sc, SF_INDIRECTIO_DATA); 228#else 229 val = CSR_READ_4(sc, (reg + SF_RMAP_INTREG_BASE)); 230#endif 231 232 return(val); 233} 234 235static u_int8_t sf_read_eeprom(sc, reg) 236 struct sf_softc *sc; 237 int reg; 238{ 239 u_int8_t val; 240 241 val = (csr_read_4(sc, SF_EEADDR_BASE + 242 (reg & 0xFFFFFFFC)) >> (8 * (reg & 3))) & 0xFF; 243 244 return(val); 245} 246 247static void csr_write_4(sc, reg, val) 248 struct sf_softc *sc; 249 int reg; 250 u_int32_t val; 251{ 252#ifdef SF_USEIOSPACE 253 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); 254 CSR_WRITE_4(sc, SF_INDIRECTIO_DATA, val); 255#else 256 CSR_WRITE_4(sc, (reg + SF_RMAP_INTREG_BASE), val); 257#endif 258 return; 259} 260 261static u_int32_t sf_calchash(addr) 262 caddr_t addr; 263{ 264 u_int32_t crc, carry; 265 int i, j; 266 u_int8_t c; 267 268 /* Compute CRC for the address value. */ 269 crc = 0xFFFFFFFF; /* initial value */ 270 271 for (i = 0; i < 6; i++) { 272 c = *(addr + i); 273 for (j = 0; j < 8; j++) { 274 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 275 crc <<= 1; 276 c >>= 1; 277 if (carry) 278 crc = (crc ^ 0x04c11db6) | carry; 279 } 280 } 281 282 /* return the filter bit position */ 283 return(crc >> 23 & 0x1FF); 284} 285 286/* 287 * Copy the address 'mac' into the perfect RX filter entry at 288 * offset 'idx.' The perfect filter only has 16 entries so do 289 * some sanity tests. 290 */ 291static int sf_setperf(sc, idx, mac) 292 struct sf_softc *sc; 293 int idx; 294 caddr_t mac; 295{ 296 u_int16_t *p; 297 298 if (idx < 0 || idx > SF_RXFILT_PERFECT_CNT) 299 return(EINVAL); 300 301 if (mac == NULL) 302 return(EINVAL); 303 304 p = (u_int16_t *)mac; 305 306 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 307 (idx * SF_RXFILT_PERFECT_SKIP), htons(p[2])); 308 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 309 (idx * SF_RXFILT_PERFECT_SKIP) + 4, htons(p[1])); 310 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 311 (idx * SF_RXFILT_PERFECT_SKIP) + 8, htons(p[0])); 312 313 return(0); 314} 315 316/* 317 * Set the bit in the 512-bit hash table that corresponds to the 318 * specified mac address 'mac.' If 'prio' is nonzero, update the 319 * priority hash table instead of the filter hash table. 320 */ 321static int sf_sethash(sc, mac, prio) 322 struct sf_softc *sc; 323 caddr_t mac; 324 int prio; 325{ 326 u_int32_t h = 0; 327 328 if (mac == NULL) 329 return(EINVAL); 330 331 h = sf_calchash(mac); 332 333 if (prio) { 334 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_PRIOOFF + 335 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); 336 } else { 337 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_ADDROFF + 338 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); 339 } 340 341 return(0); 342} 343 344#ifdef notdef 345/* 346 * Set a VLAN tag in the receive filter. 347 */ 348static int sf_setvlan(sc, idx, vlan) 349 struct sf_softc *sc; 350 int idx; 351 u_int32_t vlan; 352{ 353 if (idx < 0 || idx >> SF_RXFILT_HASH_CNT) 354 return(EINVAL); 355 356 csr_write_4(sc, SF_RXFILT_HASH_BASE + 357 (idx * SF_RXFILT_HASH_SKIP) + SF_RXFILT_HASH_VLANOFF, vlan); 358 359 return(0); 360} 361#endif 362 363static int sf_miibus_readreg(dev, phy, reg) 364 device_t dev; 365 int phy, reg; 366{ 367 struct sf_softc *sc; 368 int i; 369 u_int32_t val = 0; 370 371 sc = device_get_softc(dev); 372 373 for (i = 0; i < SF_TIMEOUT; i++) { 374 val = csr_read_4(sc, SF_PHY_REG(phy, reg)); 375 if (val & SF_MII_DATAVALID) 376 break; 377 } 378 379 if (i == SF_TIMEOUT) 380 return(0); 381 382 if ((val & 0x0000FFFF) == 0xFFFF) 383 return(0); 384 385 return(val & 0x0000FFFF); 386} 387 388static int sf_miibus_writereg(dev, phy, reg, val) 389 device_t dev; 390 int phy, reg, val; 391{ 392 struct sf_softc *sc; 393 int i; 394 int busy; 395 396 sc = device_get_softc(dev); 397 398 csr_write_4(sc, SF_PHY_REG(phy, reg), val); 399 400 for (i = 0; i < SF_TIMEOUT; i++) { 401 busy = csr_read_4(sc, SF_PHY_REG(phy, reg)); 402 if (!(busy & SF_MII_BUSY)) 403 break; 404 } 405 406 return(0); 407} 408 409static void sf_miibus_statchg(dev) 410 device_t dev; 411{ 412 struct sf_softc *sc; 413 struct mii_data *mii; 414 415 sc = device_get_softc(dev); 416 mii = device_get_softc(sc->sf_miibus); 417 418 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 419 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 420 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_FDX); 421 } else { 422 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 423 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_HDX); 424 } 425 426 return; 427} 428 429static void sf_setmulti(sc) 430 struct sf_softc *sc; 431{ 432 struct ifnet *ifp; 433 int i; 434 struct ifmultiaddr *ifma; 435 u_int8_t dummy[] = { 0, 0, 0, 0, 0, 0 }; 436 437 ifp = &sc->arpcom.ac_if; 438 439 /* First zot all the existing filters. */ 440 for (i = 1; i < SF_RXFILT_PERFECT_CNT; i++) 441 sf_setperf(sc, i, (char *)&dummy); 442 for (i = SF_RXFILT_HASH_BASE; 443 i < (SF_RXFILT_HASH_MAX + 1); i += 4) 444 csr_write_4(sc, i, 0); 445 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI); 446 447 /* Now program new ones. */ 448 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 449 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI); 450 } else { 451 i = 1; 452 TAILQ_FOREACH_REVERSE(ifma, &ifp->if_multiaddrs, ifmultihead, ifma_link) { 453 if (ifma->ifma_addr->sa_family != AF_LINK) 454 continue; 455 /* 456 * Program the first 15 multicast groups 457 * into the perfect filter. For all others, 458 * use the hash table. 459 */ 460 if (i < SF_RXFILT_PERFECT_CNT) { 461 sf_setperf(sc, i, 462 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 463 i++; 464 continue; 465 } 466 467 sf_sethash(sc, 468 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 0); 469 } 470 } 471 472 return; 473} 474 475/* 476 * Set media options. 477 */ 478static int sf_ifmedia_upd(ifp) 479 struct ifnet *ifp; 480{ 481 struct sf_softc *sc; 482 struct mii_data *mii; 483 484 sc = ifp->if_softc; 485 mii = device_get_softc(sc->sf_miibus); 486 sc->sf_link = 0; 487 if (mii->mii_instance) { 488 struct mii_softc *miisc; 489 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 490 mii_phy_reset(miisc); 491 } 492 mii_mediachg(mii); 493 494 return(0); 495} 496 497/* 498 * Report current media status. 499 */ 500static void sf_ifmedia_sts(ifp, ifmr) 501 struct ifnet *ifp; 502 struct ifmediareq *ifmr; 503{ 504 struct sf_softc *sc; 505 struct mii_data *mii; 506 507 sc = ifp->if_softc; 508 mii = device_get_softc(sc->sf_miibus); 509 510 mii_pollstat(mii); 511 ifmr->ifm_active = mii->mii_media_active; 512 ifmr->ifm_status = mii->mii_media_status; 513 514 return; 515} 516 517static int sf_ioctl(ifp, command, data) 518 struct ifnet *ifp; 519 u_long command; 520 caddr_t data; 521{ 522 struct sf_softc *sc = ifp->if_softc; 523 struct ifreq *ifr = (struct ifreq *) data; 524 struct mii_data *mii; 525 int error = 0; 526 527 SF_LOCK(sc); 528 529 switch(command) { 530 case SIOCSIFADDR: 531 case SIOCGIFADDR: 532 case SIOCSIFMTU: 533 error = ether_ioctl(ifp, command, data); 534 break; 535 case SIOCSIFFLAGS: 536 if (ifp->if_flags & IFF_UP) { 537 if (ifp->if_flags & IFF_RUNNING && 538 ifp->if_flags & IFF_PROMISC && 539 !(sc->sf_if_flags & IFF_PROMISC)) { 540 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 541 } else if (ifp->if_flags & IFF_RUNNING && 542 !(ifp->if_flags & IFF_PROMISC) && 543 sc->sf_if_flags & IFF_PROMISC) { 544 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 545 } else if (!(ifp->if_flags & IFF_RUNNING)) 546 sf_init(sc); 547 } else { 548 if (ifp->if_flags & IFF_RUNNING) 549 sf_stop(sc); 550 } 551 sc->sf_if_flags = ifp->if_flags; 552 error = 0; 553 break; 554 case SIOCADDMULTI: 555 case SIOCDELMULTI: 556 sf_setmulti(sc); 557 error = 0; 558 break; 559 case SIOCGIFMEDIA: 560 case SIOCSIFMEDIA: 561 mii = device_get_softc(sc->sf_miibus); 562 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 563 break; 564 default: 565 error = EINVAL; 566 break; 567 } 568 569 SF_UNLOCK(sc); 570 571 return(error); 572} 573 574static void sf_reset(sc) 575 struct sf_softc *sc; 576{ 577 register int i; 578 579 csr_write_4(sc, SF_GEN_ETH_CTL, 0); 580 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 581 DELAY(1000); 582 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 583 584 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_RESET); 585 586 for (i = 0; i < SF_TIMEOUT; i++) { 587 DELAY(10); 588 if (!(csr_read_4(sc, SF_PCI_DEVCFG) & SF_PCIDEVCFG_RESET)) 589 break; 590 } 591 592 if (i == SF_TIMEOUT) 593 printf("sf%d: reset never completed!\n", sc->sf_unit); 594 595 /* Wait a little while for the chip to get its brains in order. */ 596 DELAY(1000); 597 return; 598} 599 600/* 601 * Probe for an Adaptec AIC-6915 chip. Check the PCI vendor and device 602 * IDs against our list and return a device name if we find a match. 603 * We also check the subsystem ID so that we can identify exactly which 604 * NIC has been found, if possible. 605 */ 606static int sf_probe(dev) 607 device_t dev; 608{ 609 struct sf_type *t; 610 611 t = sf_devs; 612 613 while(t->sf_name != NULL) { 614 if ((pci_get_vendor(dev) == t->sf_vid) && 615 (pci_get_device(dev) == t->sf_did)) { 616 switch((pci_read_config(dev, 617 SF_PCI_SUBVEN_ID, 4) >> 16) & 0xFFFF) { 618 case AD_SUBSYSID_62011_REV0: 619 case AD_SUBSYSID_62011_REV1: 620 device_set_desc(dev, 621 "Adaptec ANA-62011 10/100BaseTX"); 622 return(0); 623 break; 624 case AD_SUBSYSID_62022: 625 device_set_desc(dev, 626 "Adaptec ANA-62022 10/100BaseTX"); 627 return(0); 628 break; 629 case AD_SUBSYSID_62044_REV0: 630 case AD_SUBSYSID_62044_REV1: 631 device_set_desc(dev, 632 "Adaptec ANA-62044 10/100BaseTX"); 633 return(0); 634 break; 635 case AD_SUBSYSID_62020: 636 device_set_desc(dev, 637 "Adaptec ANA-62020 10/100BaseFX"); 638 return(0); 639 break; 640 case AD_SUBSYSID_69011: 641 device_set_desc(dev, 642 "Adaptec ANA-69011 10/100BaseTX"); 643 return(0); 644 break; 645 default: 646 device_set_desc(dev, t->sf_name); 647 return(0); 648 break; 649 } 650 } 651 t++; 652 } 653 654 return(ENXIO); 655} 656 657/* 658 * Attach the interface. Allocate softc structures, do ifmedia 659 * setup and ethernet/BPF attach. 660 */ 661static int sf_attach(dev) 662 device_t dev; 663{ 664 int i; 665 u_int32_t command; 666 struct sf_softc *sc; 667 struct ifnet *ifp; 668 int unit, rid, error = 0; 669 670 sc = device_get_softc(dev); 671 unit = device_get_unit(dev); 672 bzero(sc, sizeof(struct sf_softc)); 673 674 mtx_init(&sc->sf_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 675 MTX_DEF | MTX_RECURSE); 676 SF_LOCK(sc); 677 /* 678 * Handle power management nonsense. 679 */ 680 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 681 u_int32_t iobase, membase, irq; 682 683 /* Save important PCI config data. */ 684 iobase = pci_read_config(dev, SF_PCI_LOIO, 4); 685 membase = pci_read_config(dev, SF_PCI_LOMEM, 4); 686 irq = pci_read_config(dev, SF_PCI_INTLINE, 4); 687 688 /* Reset the power state. */ 689 printf("sf%d: chip is in D%d power mode " 690 "-- setting to D0\n", unit, 691 pci_get_powerstate(dev)); 692 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 693 694 /* Restore PCI config data. */ 695 pci_write_config(dev, SF_PCI_LOIO, iobase, 4); 696 pci_write_config(dev, SF_PCI_LOMEM, membase, 4); 697 pci_write_config(dev, SF_PCI_INTLINE, irq, 4); 698 } 699 700 /* 701 * Map control/status registers. 702 */ 703 pci_enable_busmaster(dev); 704 pci_enable_io(dev, SYS_RES_IOPORT); 705 pci_enable_io(dev, SYS_RES_MEMORY); 706 command = pci_read_config(dev, PCIR_COMMAND, 4); 707 708#ifdef SF_USEIOSPACE 709 if (!(command & PCIM_CMD_PORTEN)) { 710 printf("sf%d: failed to enable I/O ports!\n", unit); 711 error = ENXIO; 712 goto fail; 713 } 714#else 715 if (!(command & PCIM_CMD_MEMEN)) { 716 printf("sf%d: failed to enable memory mapping!\n", unit); 717 error = ENXIO; 718 goto fail; 719 } 720#endif 721 722 rid = SF_RID; 723 sc->sf_res = bus_alloc_resource(dev, SF_RES, &rid, 724 0, ~0, 1, RF_ACTIVE); 725 726 if (sc->sf_res == NULL) { 727 printf ("sf%d: couldn't map ports\n", unit); 728 error = ENXIO; 729 goto fail; 730 } 731 732 sc->sf_btag = rman_get_bustag(sc->sf_res); 733 sc->sf_bhandle = rman_get_bushandle(sc->sf_res); 734 735 /* Allocate interrupt */ 736 rid = 0; 737 sc->sf_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 738 RF_SHAREABLE | RF_ACTIVE); 739 740 if (sc->sf_irq == NULL) { 741 printf("sf%d: couldn't map interrupt\n", unit); 742 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 743 error = ENXIO; 744 goto fail; 745 } 746 747 error = bus_setup_intr(dev, sc->sf_irq, INTR_TYPE_NET, 748 sf_intr, sc, &sc->sf_intrhand); 749 750 if (error) { 751 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_res); 752 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 753 printf("sf%d: couldn't set up irq\n", unit); 754 goto fail; 755 } 756 757 callout_handle_init(&sc->sf_stat_ch); 758 /* Reset the adapter. */ 759 sf_reset(sc); 760 761 /* 762 * Get station address from the EEPROM. 763 */ 764 for (i = 0; i < ETHER_ADDR_LEN; i++) 765 sc->arpcom.ac_enaddr[i] = 766 sf_read_eeprom(sc, SF_EE_NODEADDR + ETHER_ADDR_LEN - i); 767 768 /* 769 * An Adaptec chip was detected. Inform the world. 770 */ 771 printf("sf%d: Ethernet address: %6D\n", unit, 772 sc->arpcom.ac_enaddr, ":"); 773 774 sc->sf_unit = unit; 775 776 /* Allocate the descriptor queues. */ 777 sc->sf_ldata = contigmalloc(sizeof(struct sf_list_data), M_DEVBUF, 778 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 779 780 if (sc->sf_ldata == NULL) { 781 printf("sf%d: no memory for list buffers!\n", unit); 782 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand); 783 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq); 784 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 785 error = ENXIO; 786 goto fail; 787 } 788 789 bzero(sc->sf_ldata, sizeof(struct sf_list_data)); 790 791 /* Do MII setup. */ 792 if (mii_phy_probe(dev, &sc->sf_miibus, 793 sf_ifmedia_upd, sf_ifmedia_sts)) { 794 printf("sf%d: MII without any phy!\n", sc->sf_unit); 795 contigfree(sc->sf_ldata,sizeof(struct sf_list_data),M_DEVBUF); 796 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand); 797 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq); 798 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 799 error = ENXIO; 800 goto fail; 801 } 802 803 ifp = &sc->arpcom.ac_if; 804 ifp->if_softc = sc; 805 ifp->if_unit = unit; 806 ifp->if_name = "sf"; 807 ifp->if_mtu = ETHERMTU; 808 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 809 ifp->if_ioctl = sf_ioctl; 810 ifp->if_output = ether_output; 811 ifp->if_start = sf_start; 812 ifp->if_watchdog = sf_watchdog; 813 ifp->if_init = sf_init; 814 ifp->if_baudrate = 10000000; 815 ifp->if_snd.ifq_maxlen = SF_TX_DLIST_CNT - 1; 816 817 /* 818 * Call MI attach routine. 819 */ 820 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 821 SF_UNLOCK(sc); 822 return(0); 823 824fail: 825 SF_UNLOCK(sc); 826 mtx_destroy(&sc->sf_mtx); 827 return(error); 828} 829 830static int sf_detach(dev) 831 device_t dev; 832{ 833 struct sf_softc *sc; 834 struct ifnet *ifp; 835 836 sc = device_get_softc(dev); 837 SF_LOCK(sc); 838 ifp = &sc->arpcom.ac_if; 839 840 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 841 sf_stop(sc); 842 843 bus_generic_detach(dev); 844 device_delete_child(dev, sc->sf_miibus); 845 846 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand); 847 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq); 848 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 849 850 contigfree(sc->sf_ldata, sizeof(struct sf_list_data), M_DEVBUF); 851 852 SF_UNLOCK(sc); 853 mtx_destroy(&sc->sf_mtx); 854 855 return(0); 856} 857 858static int sf_init_rx_ring(sc) 859 struct sf_softc *sc; 860{ 861 struct sf_list_data *ld; 862 int i; 863 864 ld = sc->sf_ldata; 865 866 bzero((char *)ld->sf_rx_dlist_big, 867 sizeof(struct sf_rx_bufdesc_type0) * SF_RX_DLIST_CNT); 868 bzero((char *)ld->sf_rx_clist, 869 sizeof(struct sf_rx_cmpdesc_type3) * SF_RX_CLIST_CNT); 870 871 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 872 if (sf_newbuf(sc, &ld->sf_rx_dlist_big[i], NULL) == ENOBUFS) 873 return(ENOBUFS); 874 } 875 876 return(0); 877} 878 879static void sf_init_tx_ring(sc) 880 struct sf_softc *sc; 881{ 882 struct sf_list_data *ld; 883 int i; 884 885 ld = sc->sf_ldata; 886 887 bzero((char *)ld->sf_tx_dlist, 888 sizeof(struct sf_tx_bufdesc_type0) * SF_TX_DLIST_CNT); 889 bzero((char *)ld->sf_tx_clist, 890 sizeof(struct sf_tx_cmpdesc_type0) * SF_TX_CLIST_CNT); 891 892 for (i = 0; i < SF_TX_DLIST_CNT; i++) 893 ld->sf_tx_dlist[i].sf_id = SF_TX_BUFDESC_ID; 894 for (i = 0; i < SF_TX_CLIST_CNT; i++) 895 ld->sf_tx_clist[i].sf_type = SF_TXCMPTYPE_TX; 896 897 ld->sf_tx_dlist[SF_TX_DLIST_CNT - 1].sf_end = 1; 898 sc->sf_tx_cnt = 0; 899 900 return; 901} 902 903static int sf_newbuf(sc, c, m) 904 struct sf_softc *sc; 905 struct sf_rx_bufdesc_type0 *c; 906 struct mbuf *m; 907{ 908 struct mbuf *m_new = NULL; 909 910 if (m == NULL) { 911 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 912 if (m_new == NULL) 913 return(ENOBUFS); 914 915 MCLGET(m_new, M_DONTWAIT); 916 if (!(m_new->m_flags & M_EXT)) { 917 m_freem(m_new); 918 return(ENOBUFS); 919 } 920 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 921 } else { 922 m_new = m; 923 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 924 m_new->m_data = m_new->m_ext.ext_buf; 925 } 926 927 m_adj(m_new, sizeof(u_int64_t)); 928 929 c->sf_mbuf = m_new; 930 c->sf_addrlo = SF_RX_HOSTADDR(vtophys(mtod(m_new, caddr_t))); 931 c->sf_valid = 1; 932 933 return(0); 934} 935 936/* 937 * The starfire is programmed to use 'normal' mode for packet reception, 938 * which means we use the consumer/producer model for both the buffer 939 * descriptor queue and the completion descriptor queue. The only problem 940 * with this is that it involves a lot of register accesses: we have to 941 * read the RX completion consumer and producer indexes and the RX buffer 942 * producer index, plus the RX completion consumer and RX buffer producer 943 * indexes have to be updated. It would have been easier if Adaptec had 944 * put each index in a separate register, especially given that the damn 945 * NIC has a 512K register space. 946 * 947 * In spite of all the lovely features that Adaptec crammed into the 6915, 948 * it is marred by one truly stupid design flaw, which is that receive 949 * buffer addresses must be aligned on a longword boundary. This forces 950 * the packet payload to be unaligned, which is suboptimal on the x86 and 951 * completely unuseable on the Alpha. Our only recourse is to copy received 952 * packets into properly aligned buffers before handing them off. 953 */ 954 955static void sf_rxeof(sc) 956 struct sf_softc *sc; 957{ 958 struct ether_header *eh; 959 struct mbuf *m; 960 struct ifnet *ifp; 961 struct sf_rx_bufdesc_type0 *desc; 962 struct sf_rx_cmpdesc_type3 *cur_rx; 963 u_int32_t rxcons, rxprod; 964 int cmpprodidx, cmpconsidx, bufprodidx; 965 966 ifp = &sc->arpcom.ac_if; 967 968 rxcons = csr_read_4(sc, SF_CQ_CONSIDX); 969 rxprod = csr_read_4(sc, SF_RXDQ_PTR_Q1); 970 cmpprodidx = SF_IDX_LO(csr_read_4(sc, SF_CQ_PRODIDX)); 971 cmpconsidx = SF_IDX_LO(rxcons); 972 bufprodidx = SF_IDX_LO(rxprod); 973 974 while (cmpconsidx != cmpprodidx) { 975 struct mbuf *m0; 976 977 cur_rx = &sc->sf_ldata->sf_rx_clist[cmpconsidx]; 978 desc = &sc->sf_ldata->sf_rx_dlist_big[cur_rx->sf_endidx]; 979 m = desc->sf_mbuf; 980 SF_INC(cmpconsidx, SF_RX_CLIST_CNT); 981 SF_INC(bufprodidx, SF_RX_DLIST_CNT); 982 983 if (!(cur_rx->sf_status1 & SF_RXSTAT1_OK)) { 984 ifp->if_ierrors++; 985 sf_newbuf(sc, desc, m); 986 continue; 987 } 988 989 m0 = m_devget(mtod(m, char *), cur_rx->sf_len, ETHER_ALIGN, 990 ifp, NULL); 991 sf_newbuf(sc, desc, m); 992 if (m0 == NULL) { 993 ifp->if_ierrors++; 994 continue; 995 } 996 m = m0; 997 998 eh = mtod(m, struct ether_header *); 999 ifp->if_ipackets++; 1000 1001 /* Remove header from mbuf and pass it on. */ 1002 m_adj(m, sizeof(struct ether_header)); 1003 ether_input(ifp, eh, m); 1004 } 1005 1006 csr_write_4(sc, SF_CQ_CONSIDX, 1007 (rxcons & ~SF_CQ_CONSIDX_RXQ1) | cmpconsidx); 1008 csr_write_4(sc, SF_RXDQ_PTR_Q1, 1009 (rxprod & ~SF_RXDQ_PRODIDX) | bufprodidx); 1010 1011 return; 1012} 1013 1014/* 1015 * Read the transmit status from the completion queue and release 1016 * mbufs. Note that the buffer descriptor index in the completion 1017 * descriptor is an offset from the start of the transmit buffer 1018 * descriptor list in bytes. This is important because the manual 1019 * gives the impression that it should match the producer/consumer 1020 * index, which is the offset in 8 byte blocks. 1021 */ 1022static void sf_txeof(sc) 1023 struct sf_softc *sc; 1024{ 1025 int txcons, cmpprodidx, cmpconsidx; 1026 struct sf_tx_cmpdesc_type1 *cur_cmp; 1027 struct sf_tx_bufdesc_type0 *cur_tx; 1028 struct ifnet *ifp; 1029 1030 ifp = &sc->arpcom.ac_if; 1031 1032 txcons = csr_read_4(sc, SF_CQ_CONSIDX); 1033 cmpprodidx = SF_IDX_HI(csr_read_4(sc, SF_CQ_PRODIDX)); 1034 cmpconsidx = SF_IDX_HI(txcons); 1035 1036 while (cmpconsidx != cmpprodidx) { 1037 cur_cmp = &sc->sf_ldata->sf_tx_clist[cmpconsidx]; 1038 cur_tx = &sc->sf_ldata->sf_tx_dlist[cur_cmp->sf_index >> 7]; 1039 1040 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_OK) 1041 ifp->if_opackets++; 1042 else { 1043 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_UNDERRUN) 1044 sf_txthresh_adjust(sc); 1045 ifp->if_oerrors++; 1046 } 1047 1048 sc->sf_tx_cnt--; 1049 if (cur_tx->sf_mbuf != NULL) { 1050 m_freem(cur_tx->sf_mbuf); 1051 cur_tx->sf_mbuf = NULL; 1052 } else 1053 break; 1054 SF_INC(cmpconsidx, SF_TX_CLIST_CNT); 1055 } 1056 1057 ifp->if_timer = 0; 1058 ifp->if_flags &= ~IFF_OACTIVE; 1059 1060 csr_write_4(sc, SF_CQ_CONSIDX, 1061 (txcons & ~SF_CQ_CONSIDX_TXQ) | 1062 ((cmpconsidx << 16) & 0xFFFF0000)); 1063 1064 return; 1065} 1066 1067static void sf_txthresh_adjust(sc) 1068 struct sf_softc *sc; 1069{ 1070 u_int32_t txfctl; 1071 u_int8_t txthresh; 1072 1073 txfctl = csr_read_4(sc, SF_TX_FRAMCTL); 1074 txthresh = txfctl & SF_TXFRMCTL_TXTHRESH; 1075 if (txthresh < 0xFF) { 1076 txthresh++; 1077 txfctl &= ~SF_TXFRMCTL_TXTHRESH; 1078 txfctl |= txthresh; 1079#ifdef DIAGNOSTIC 1080 printf("sf%d: tx underrun, increasing " 1081 "tx threshold to %d bytes\n", 1082 sc->sf_unit, txthresh * 4); 1083#endif 1084 csr_write_4(sc, SF_TX_FRAMCTL, txfctl); 1085 } 1086 1087 return; 1088} 1089 1090static void sf_intr(arg) 1091 void *arg; 1092{ 1093 struct sf_softc *sc; 1094 struct ifnet *ifp; 1095 u_int32_t status; 1096 1097 sc = arg; 1098 SF_LOCK(sc); 1099 1100 ifp = &sc->arpcom.ac_if; 1101 1102 if (!(csr_read_4(sc, SF_ISR_SHADOW) & SF_ISR_PCIINT_ASSERTED)) { 1103 SF_UNLOCK(sc); 1104 return; 1105 } 1106 1107 /* Disable interrupts. */ 1108 csr_write_4(sc, SF_IMR, 0x00000000); 1109 1110 for (;;) { 1111 status = csr_read_4(sc, SF_ISR); 1112 if (status) 1113 csr_write_4(sc, SF_ISR, status); 1114 1115 if (!(status & SF_INTRS)) 1116 break; 1117 1118 if (status & SF_ISR_RXDQ1_DMADONE) 1119 sf_rxeof(sc); 1120 1121 if (status & SF_ISR_TX_TXDONE || 1122 status & SF_ISR_TX_DMADONE || 1123 status & SF_ISR_TX_QUEUEDONE) 1124 sf_txeof(sc); 1125 1126 if (status & SF_ISR_TX_LOFIFO) 1127 sf_txthresh_adjust(sc); 1128 1129 if (status & SF_ISR_ABNORMALINTR) { 1130 if (status & SF_ISR_STATSOFLOW) { 1131 untimeout(sf_stats_update, sc, 1132 sc->sf_stat_ch); 1133 sf_stats_update(sc); 1134 } else 1135 sf_init(sc); 1136 } 1137 } 1138 1139 /* Re-enable interrupts. */ 1140 csr_write_4(sc, SF_IMR, SF_INTRS); 1141 1142 if (ifp->if_snd.ifq_head != NULL) 1143 sf_start(ifp); 1144 1145 SF_UNLOCK(sc); 1146 return; 1147} 1148 1149static void sf_init(xsc) 1150 void *xsc; 1151{ 1152 struct sf_softc *sc; 1153 struct ifnet *ifp; 1154 struct mii_data *mii; 1155 int i; 1156 1157 sc = xsc; 1158 SF_LOCK(sc); 1159 ifp = &sc->arpcom.ac_if; 1160 mii = device_get_softc(sc->sf_miibus); 1161 1162 sf_stop(sc); 1163 sf_reset(sc); 1164 1165 /* Init all the receive filter registers */ 1166 for (i = SF_RXFILT_PERFECT_BASE; 1167 i < (SF_RXFILT_HASH_MAX + 1); i += 4) 1168 csr_write_4(sc, i, 0); 1169 1170 /* Empty stats counter registers. */ 1171 for (i = 0; i < sizeof(struct sf_stats)/sizeof(u_int32_t); i++) 1172 csr_write_4(sc, SF_STATS_BASE + 1173 (i + sizeof(u_int32_t)), 0); 1174 1175 /* Init our MAC address */ 1176 csr_write_4(sc, SF_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1177 csr_write_4(sc, SF_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1178 sf_setperf(sc, 0, (caddr_t)&sc->arpcom.ac_enaddr); 1179 1180 if (sf_init_rx_ring(sc) == ENOBUFS) { 1181 printf("sf%d: initialization failed: no " 1182 "memory for rx buffers\n", sc->sf_unit); 1183 SF_UNLOCK(sc); 1184 return; 1185 } 1186 1187 sf_init_tx_ring(sc); 1188 1189 csr_write_4(sc, SF_RXFILT, SF_PERFMODE_NORMAL|SF_HASHMODE_WITHVLAN); 1190 1191 /* If we want promiscuous mode, set the allframes bit. */ 1192 if (ifp->if_flags & IFF_PROMISC) { 1193 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 1194 } else { 1195 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 1196 } 1197 1198 if (ifp->if_flags & IFF_BROADCAST) { 1199 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_BROAD); 1200 } else { 1201 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_BROAD); 1202 } 1203 1204 /* 1205 * Load the multicast filter. 1206 */ 1207 sf_setmulti(sc); 1208 1209 /* Init the completion queue indexes */ 1210 csr_write_4(sc, SF_CQ_CONSIDX, 0); 1211 csr_write_4(sc, SF_CQ_PRODIDX, 0); 1212 1213 /* Init the RX completion queue */ 1214 csr_write_4(sc, SF_RXCQ_CTL_1, 1215 vtophys(sc->sf_ldata->sf_rx_clist) & SF_RXCQ_ADDR); 1216 SF_SETBIT(sc, SF_RXCQ_CTL_1, SF_RXCQTYPE_3); 1217 1218 /* Init RX DMA control. */ 1219 SF_SETBIT(sc, SF_RXDMA_CTL, SF_RXDMA_REPORTBADPKTS); 1220 1221 /* Init the RX buffer descriptor queue. */ 1222 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 1223 vtophys(sc->sf_ldata->sf_rx_dlist_big)); 1224 csr_write_4(sc, SF_RXDQ_CTL_1, (MCLBYTES << 16) | SF_DESCSPACE_16BYTES); 1225 csr_write_4(sc, SF_RXDQ_PTR_Q1, SF_RX_DLIST_CNT - 1); 1226 1227 /* Init the TX completion queue */ 1228 csr_write_4(sc, SF_TXCQ_CTL, 1229 vtophys(sc->sf_ldata->sf_tx_clist) & SF_RXCQ_ADDR); 1230 1231 /* Init the TX buffer descriptor queue. */ 1232 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 1233 vtophys(sc->sf_ldata->sf_tx_dlist)); 1234 SF_SETBIT(sc, SF_TX_FRAMCTL, SF_TXFRMCTL_CPLAFTERTX); 1235 csr_write_4(sc, SF_TXDQ_CTL, 1236 SF_TXBUFDESC_TYPE0|SF_TXMINSPACE_128BYTES|SF_TXSKIPLEN_8BYTES); 1237 SF_SETBIT(sc, SF_TXDQ_CTL, SF_TXDQCTL_NODMACMP); 1238 1239 /* Enable autopadding of short TX frames. */ 1240 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_AUTOPAD); 1241 1242 /* Enable interrupts. */ 1243 csr_write_4(sc, SF_IMR, SF_INTRS); 1244 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_INTR_ENB); 1245 1246 /* Enable the RX and TX engines. */ 1247 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_RX_ENB|SF_ETHCTL_RXDMA_ENB); 1248 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_TX_ENB|SF_ETHCTL_TXDMA_ENB); 1249 1250 /*mii_mediachg(mii);*/ 1251 sf_ifmedia_upd(ifp); 1252 1253 ifp->if_flags |= IFF_RUNNING; 1254 ifp->if_flags &= ~IFF_OACTIVE; 1255 1256 sc->sf_stat_ch = timeout(sf_stats_update, sc, hz); 1257 1258 SF_UNLOCK(sc); 1259 1260 return; 1261} 1262 1263static int sf_encap(sc, c, m_head) 1264 struct sf_softc *sc; 1265 struct sf_tx_bufdesc_type0 *c; 1266 struct mbuf *m_head; 1267{ 1268 int frag = 0; 1269 struct sf_frag *f = NULL; 1270 struct mbuf *m; 1271 1272 m = m_head; 1273 1274 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1275 if (m->m_len != 0) { 1276 if (frag == SF_MAXFRAGS) 1277 break; 1278 f = &c->sf_frags[frag]; 1279 if (frag == 0) 1280 f->sf_pktlen = m_head->m_pkthdr.len; 1281 f->sf_fraglen = m->m_len; 1282 f->sf_addr = vtophys(mtod(m, vm_offset_t)); 1283 frag++; 1284 } 1285 } 1286 1287 if (m != NULL) { 1288 struct mbuf *m_new = NULL; 1289 1290 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1291 if (m_new == NULL) { 1292 printf("sf%d: no memory for tx list", sc->sf_unit); 1293 return(1); 1294 } 1295 1296 if (m_head->m_pkthdr.len > MHLEN) { 1297 MCLGET(m_new, M_DONTWAIT); 1298 if (!(m_new->m_flags & M_EXT)) { 1299 m_freem(m_new); 1300 printf("sf%d: no memory for tx list", 1301 sc->sf_unit); 1302 return(1); 1303 } 1304 } 1305 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1306 mtod(m_new, caddr_t)); 1307 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1308 m_freem(m_head); 1309 m_head = m_new; 1310 f = &c->sf_frags[0]; 1311 f->sf_fraglen = f->sf_pktlen = m_head->m_pkthdr.len; 1312 f->sf_addr = vtophys(mtod(m_head, caddr_t)); 1313 frag = 1; 1314 } 1315 1316 c->sf_mbuf = m_head; 1317 c->sf_id = SF_TX_BUFDESC_ID; 1318 c->sf_fragcnt = frag; 1319 c->sf_intr = 1; 1320 c->sf_caltcp = 0; 1321 c->sf_crcen = 1; 1322 1323 return(0); 1324} 1325 1326static void sf_start(ifp) 1327 struct ifnet *ifp; 1328{ 1329 struct sf_softc *sc; 1330 struct sf_tx_bufdesc_type0 *cur_tx = NULL; 1331 struct mbuf *m_head = NULL; 1332 int i, txprod; 1333 1334 sc = ifp->if_softc; 1335 SF_LOCK(sc); 1336 1337 if (!sc->sf_link && ifp->if_snd.ifq_len < 10) { 1338 SF_UNLOCK(sc); 1339 return; 1340 } 1341 1342 if (ifp->if_flags & IFF_OACTIVE) { 1343 SF_UNLOCK(sc); 1344 return; 1345 } 1346 1347 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX); 1348 i = SF_IDX_HI(txprod) >> 4; 1349 1350 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) { 1351 printf("sf%d: TX ring full, resetting\n", sc->sf_unit); 1352 sf_init(sc); 1353 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX); 1354 i = SF_IDX_HI(txprod) >> 4; 1355 } 1356 1357 while(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf == NULL) { 1358 if (sc->sf_tx_cnt >= (SF_TX_DLIST_CNT - 5)) { 1359 ifp->if_flags |= IFF_OACTIVE; 1360 cur_tx = NULL; 1361 break; 1362 } 1363 IF_DEQUEUE(&ifp->if_snd, m_head); 1364 if (m_head == NULL) 1365 break; 1366 1367 cur_tx = &sc->sf_ldata->sf_tx_dlist[i]; 1368 if (sf_encap(sc, cur_tx, m_head)) { 1369 IF_PREPEND(&ifp->if_snd, m_head); 1370 ifp->if_flags |= IFF_OACTIVE; 1371 cur_tx = NULL; 1372 break; 1373 } 1374 1375 /* 1376 * If there's a BPF listener, bounce a copy of this frame 1377 * to him. 1378 */ 1379 if (ifp->if_bpf) 1380 bpf_mtap(ifp, m_head); 1381 1382 SF_INC(i, SF_TX_DLIST_CNT); 1383 sc->sf_tx_cnt++; 1384 /* 1385 * Don't get the TX DMA queue get too full. 1386 */ 1387 if (sc->sf_tx_cnt > 64) 1388 break; 1389 } 1390 1391 if (cur_tx == NULL) { 1392 SF_UNLOCK(sc); 1393 return; 1394 } 1395 1396 /* Transmit */ 1397 csr_write_4(sc, SF_TXDQ_PRODIDX, 1398 (txprod & ~SF_TXDQ_PRODIDX_HIPRIO) | 1399 ((i << 20) & 0xFFFF0000)); 1400 1401 ifp->if_timer = 5; 1402 1403 SF_UNLOCK(sc); 1404 1405 return; 1406} 1407 1408static void sf_stop(sc) 1409 struct sf_softc *sc; 1410{ 1411 int i; 1412 struct ifnet *ifp; 1413 1414 SF_LOCK(sc); 1415 1416 ifp = &sc->arpcom.ac_if; 1417 1418 untimeout(sf_stats_update, sc, sc->sf_stat_ch); 1419 1420 csr_write_4(sc, SF_GEN_ETH_CTL, 0); 1421 csr_write_4(sc, SF_CQ_CONSIDX, 0); 1422 csr_write_4(sc, SF_CQ_PRODIDX, 0); 1423 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 0); 1424 csr_write_4(sc, SF_RXDQ_CTL_1, 0); 1425 csr_write_4(sc, SF_RXDQ_PTR_Q1, 0); 1426 csr_write_4(sc, SF_TXCQ_CTL, 0); 1427 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 0); 1428 csr_write_4(sc, SF_TXDQ_CTL, 0); 1429 sf_reset(sc); 1430 1431 sc->sf_link = 0; 1432 1433 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 1434 if (sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf != NULL) { 1435 m_freem(sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf); 1436 sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf = NULL; 1437 } 1438 } 1439 1440 for (i = 0; i < SF_TX_DLIST_CNT; i++) { 1441 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) { 1442 m_freem(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf); 1443 sc->sf_ldata->sf_tx_dlist[i].sf_mbuf = NULL; 1444 } 1445 } 1446 1447 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 1448 SF_UNLOCK(sc); 1449 1450 return; 1451} 1452 1453/* 1454 * Note: it is important that this function not be interrupted. We 1455 * use a two-stage register access scheme: if we are interrupted in 1456 * between setting the indirect address register and reading from the 1457 * indirect data register, the contents of the address register could 1458 * be changed out from under us. 1459 */ 1460static void sf_stats_update(xsc) 1461 void *xsc; 1462{ 1463 struct sf_softc *sc; 1464 struct ifnet *ifp; 1465 struct mii_data *mii; 1466 struct sf_stats stats; 1467 u_int32_t *ptr; 1468 int i; 1469 1470 sc = xsc; 1471 SF_LOCK(sc); 1472 ifp = &sc->arpcom.ac_if; 1473 mii = device_get_softc(sc->sf_miibus); 1474 1475 ptr = (u_int32_t *)&stats; 1476 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++) 1477 ptr[i] = csr_read_4(sc, SF_STATS_BASE + 1478 (i + sizeof(u_int32_t))); 1479 1480 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++) 1481 csr_write_4(sc, SF_STATS_BASE + 1482 (i + sizeof(u_int32_t)), 0); 1483 1484 ifp->if_collisions += stats.sf_tx_single_colls + 1485 stats.sf_tx_multi_colls + stats.sf_tx_excess_colls; 1486 1487 mii_tick(mii); 1488 1489 if (!sc->sf_link && mii->mii_media_status & IFM_ACTIVE && 1490 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1491 sc->sf_link++; 1492 if (ifp->if_snd.ifq_head != NULL) 1493 sf_start(ifp); 1494 } 1495 1496 sc->sf_stat_ch = timeout(sf_stats_update, sc, hz); 1497 1498 SF_UNLOCK(sc); 1499 1500 return; 1501} 1502 1503static void sf_watchdog(ifp) 1504 struct ifnet *ifp; 1505{ 1506 struct sf_softc *sc; 1507 1508 sc = ifp->if_softc; 1509 1510 SF_LOCK(sc); 1511 1512 ifp->if_oerrors++; 1513 printf("sf%d: watchdog timeout\n", sc->sf_unit); 1514 1515 sf_stop(sc); 1516 sf_reset(sc); 1517 sf_init(sc); 1518 1519 if (ifp->if_snd.ifq_head != NULL) 1520 sf_start(ifp); 1521 1522 SF_UNLOCK(sc); 1523 1524 return; 1525} 1526 1527static void sf_shutdown(dev) 1528 device_t dev; 1529{ 1530 struct sf_softc *sc; 1531 1532 sc = device_get_softc(dev); 1533 1534 sf_stop(sc); 1535 1536 return; 1537} 1538