1/*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: stable/11/sys/dev/sf/if_sf.c 347962 2019-05-18 20:43:13Z brooks $"); 35 36/* 37 * Adaptec AIC-6915 "Starfire" PCI fast ethernet driver for FreeBSD. 38 * Programming manual is available from: 39 * http://download.adaptec.com/pdfs/user_guides/aic6915_pg.pdf. 40 * 41 * Written by Bill Paul <wpaul@ctr.columbia.edu> 42 * Department of Electical Engineering 43 * Columbia University, New York City 44 */ 45/* 46 * The Adaptec AIC-6915 "Starfire" is a 64-bit 10/100 PCI ethernet 47 * controller designed with flexibility and reducing CPU load in mind. 48 * The Starfire offers high and low priority buffer queues, a 49 * producer/consumer index mechanism and several different buffer 50 * queue and completion queue descriptor types. Any one of a number 51 * of different driver designs can be used, depending on system and 52 * OS requirements. This driver makes use of type2 transmit frame 53 * descriptors to take full advantage of fragmented packets buffers 54 * and two RX buffer queues prioritized on size (one queue for small 55 * frames that will fit into a single mbuf, another with full size 56 * mbuf clusters for everything else). The producer/consumer indexes 57 * and completion queues are also used. 58 * 59 * One downside to the Starfire has to do with alignment: buffer 60 * queues must be aligned on 256-byte boundaries, and receive buffers 61 * must be aligned on longword boundaries. The receive buffer alignment 62 * causes problems on the strict alignment architecture, where the 63 * packet payload should be longword aligned. There is no simple way 64 * around this. 65 * 66 * For receive filtering, the Starfire offers 16 perfect filter slots 67 * and a 512-bit hash table. 68 * 69 * The Starfire has no internal transceiver, relying instead on an 70 * external MII-based transceiver. Accessing registers on external 71 * PHYs is done through a special register map rather than with the 72 * usual bitbang MDIO method. 73 * 74 * Acesssing the registers on the Starfire is a little tricky. The 75 * Starfire has a 512K internal register space. When programmed for 76 * PCI memory mapped mode, the entire register space can be accessed 77 * directly. However in I/O space mode, only 256 bytes are directly 78 * mapped into PCI I/O space. The other registers can be accessed 79 * indirectly using the SF_INDIRECTIO_ADDR and SF_INDIRECTIO_DATA 80 * registers inside the 256-byte I/O window. 81 */ 82 83#ifdef HAVE_KERNEL_OPTION_HEADERS 84#include "opt_device_polling.h" 85#endif 86 87#include <sys/param.h> 88#include <sys/systm.h> 89#include <sys/bus.h> 90#include <sys/endian.h> 91#include <sys/kernel.h> 92#include <sys/malloc.h> 93#include <sys/mbuf.h> 94#include <sys/rman.h> 95#include <sys/module.h> 96#include <sys/socket.h> 97#include <sys/sockio.h> 98#include <sys/sysctl.h> 99 100#include <net/bpf.h> 101#include <net/if.h> 102#include <net/if_var.h> 103#include <net/if_arp.h> 104#include <net/ethernet.h> 105#include <net/if_dl.h> 106#include <net/if_media.h> 107#include <net/if_types.h> 108#include <net/if_vlan_var.h> 109 110#include <dev/mii/mii.h> 111#include <dev/mii/miivar.h> 112 113#include <dev/pci/pcireg.h> 114#include <dev/pci/pcivar.h> 115 116#include <machine/bus.h> 117 118#include <dev/sf/if_sfreg.h> 119#include <dev/sf/starfire_rx.h> 120#include <dev/sf/starfire_tx.h> 121 122/* "device miibus" required. See GENERIC if you get errors here. */ 123#include "miibus_if.h" 124 125MODULE_DEPEND(sf, pci, 1, 1, 1); 126MODULE_DEPEND(sf, ether, 1, 1, 1); 127MODULE_DEPEND(sf, miibus, 1, 1, 1); 128 129#undef SF_GFP_DEBUG 130#define SF_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 131/* Define this to activate partial TCP/UDP checksum offload. */ 132#undef SF_PARTIAL_CSUM_SUPPORT 133 134static struct sf_type sf_devs[] = { 135 { AD_VENDORID, AD_DEVICEID_STARFIRE, "Adaptec AIC-6915 10/100BaseTX", 136 AD_SUBSYSID_62011_REV0, "Adaptec ANA-62011 (rev 0) 10/100BaseTX" }, 137 { AD_VENDORID, AD_DEVICEID_STARFIRE, "Adaptec AIC-6915 10/100BaseTX", 138 AD_SUBSYSID_62011_REV1, "Adaptec ANA-62011 (rev 1) 10/100BaseTX" }, 139 { AD_VENDORID, AD_DEVICEID_STARFIRE, "Adaptec AIC-6915 10/100BaseTX", 140 AD_SUBSYSID_62022, "Adaptec ANA-62022 10/100BaseTX" }, 141 { AD_VENDORID, AD_DEVICEID_STARFIRE, "Adaptec AIC-6915 10/100BaseTX", 142 AD_SUBSYSID_62044_REV0, "Adaptec ANA-62044 (rev 0) 10/100BaseTX" }, 143 { AD_VENDORID, AD_DEVICEID_STARFIRE, "Adaptec AIC-6915 10/100BaseTX", 144 AD_SUBSYSID_62044_REV1, "Adaptec ANA-62044 (rev 1) 10/100BaseTX" }, 145 { AD_VENDORID, AD_DEVICEID_STARFIRE, "Adaptec AIC-6915 10/100BaseTX", 146 AD_SUBSYSID_62020, "Adaptec ANA-62020 10/100BaseFX" }, 147 { AD_VENDORID, AD_DEVICEID_STARFIRE, "Adaptec AIC-6915 10/100BaseTX", 148 AD_SUBSYSID_69011, "Adaptec ANA-69011 10/100BaseTX" }, 149}; 150 151static int sf_probe(device_t); 152static int sf_attach(device_t); 153static int sf_detach(device_t); 154static int sf_shutdown(device_t); 155static int sf_suspend(device_t); 156static int sf_resume(device_t); 157static void sf_intr(void *); 158static void sf_tick(void *); 159static void sf_stats_update(struct sf_softc *); 160#ifndef __NO_STRICT_ALIGNMENT 161static __inline void sf_fixup_rx(struct mbuf *); 162#endif 163static int sf_rxeof(struct sf_softc *); 164static void sf_txeof(struct sf_softc *); 165static int sf_encap(struct sf_softc *, struct mbuf **); 166static void sf_start(struct ifnet *); 167static void sf_start_locked(struct ifnet *); 168static int sf_ioctl(struct ifnet *, u_long, caddr_t); 169static void sf_download_fw(struct sf_softc *); 170static void sf_init(void *); 171static void sf_init_locked(struct sf_softc *); 172static void sf_stop(struct sf_softc *); 173static void sf_watchdog(struct sf_softc *); 174static int sf_ifmedia_upd(struct ifnet *); 175static int sf_ifmedia_upd_locked(struct ifnet *); 176static void sf_ifmedia_sts(struct ifnet *, struct ifmediareq *); 177static void sf_reset(struct sf_softc *); 178static int sf_dma_alloc(struct sf_softc *); 179static void sf_dma_free(struct sf_softc *); 180static int sf_init_rx_ring(struct sf_softc *); 181static void sf_init_tx_ring(struct sf_softc *); 182static int sf_newbuf(struct sf_softc *, int); 183static void sf_rxfilter(struct sf_softc *); 184static int sf_setperf(struct sf_softc *, int, uint8_t *); 185static int sf_sethash(struct sf_softc *, caddr_t, int); 186#ifdef notdef 187static int sf_setvlan(struct sf_softc *, int, uint32_t); 188#endif 189 190static uint8_t sf_read_eeprom(struct sf_softc *, int); 191 192static int sf_miibus_readreg(device_t, int, int); 193static int sf_miibus_writereg(device_t, int, int, int); 194static void sf_miibus_statchg(device_t); 195#ifdef DEVICE_POLLING 196static int sf_poll(struct ifnet *ifp, enum poll_cmd cmd, int count); 197#endif 198 199static uint32_t csr_read_4(struct sf_softc *, int); 200static void csr_write_4(struct sf_softc *, int, uint32_t); 201static void sf_txthresh_adjust(struct sf_softc *); 202static int sf_sysctl_stats(SYSCTL_HANDLER_ARGS); 203static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 204static int sysctl_hw_sf_int_mod(SYSCTL_HANDLER_ARGS); 205 206static device_method_t sf_methods[] = { 207 /* Device interface */ 208 DEVMETHOD(device_probe, sf_probe), 209 DEVMETHOD(device_attach, sf_attach), 210 DEVMETHOD(device_detach, sf_detach), 211 DEVMETHOD(device_shutdown, sf_shutdown), 212 DEVMETHOD(device_suspend, sf_suspend), 213 DEVMETHOD(device_resume, sf_resume), 214 215 /* MII interface */ 216 DEVMETHOD(miibus_readreg, sf_miibus_readreg), 217 DEVMETHOD(miibus_writereg, sf_miibus_writereg), 218 DEVMETHOD(miibus_statchg, sf_miibus_statchg), 219 220 DEVMETHOD_END 221}; 222 223static driver_t sf_driver = { 224 "sf", 225 sf_methods, 226 sizeof(struct sf_softc), 227}; 228 229static devclass_t sf_devclass; 230 231DRIVER_MODULE(sf, pci, sf_driver, sf_devclass, 0, 0); 232DRIVER_MODULE(miibus, sf, miibus_driver, miibus_devclass, 0, 0); 233 234#define SF_SETBIT(sc, reg, x) \ 235 csr_write_4(sc, reg, csr_read_4(sc, reg) | (x)) 236 237#define SF_CLRBIT(sc, reg, x) \ 238 csr_write_4(sc, reg, csr_read_4(sc, reg) & ~(x)) 239 240static uint32_t 241csr_read_4(struct sf_softc *sc, int reg) 242{ 243 uint32_t val; 244 245 if (sc->sf_restype == SYS_RES_MEMORY) 246 val = CSR_READ_4(sc, (reg + SF_RMAP_INTREG_BASE)); 247 else { 248 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); 249 val = CSR_READ_4(sc, SF_INDIRECTIO_DATA); 250 } 251 252 return (val); 253} 254 255static uint8_t 256sf_read_eeprom(struct sf_softc *sc, int reg) 257{ 258 uint8_t val; 259 260 val = (csr_read_4(sc, SF_EEADDR_BASE + 261 (reg & 0xFFFFFFFC)) >> (8 * (reg & 3))) & 0xFF; 262 263 return (val); 264} 265 266static void 267csr_write_4(struct sf_softc *sc, int reg, uint32_t val) 268{ 269 270 if (sc->sf_restype == SYS_RES_MEMORY) 271 CSR_WRITE_4(sc, (reg + SF_RMAP_INTREG_BASE), val); 272 else { 273 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); 274 CSR_WRITE_4(sc, SF_INDIRECTIO_DATA, val); 275 } 276} 277 278/* 279 * Copy the address 'mac' into the perfect RX filter entry at 280 * offset 'idx.' The perfect filter only has 16 entries so do 281 * some sanity tests. 282 */ 283static int 284sf_setperf(struct sf_softc *sc, int idx, uint8_t *mac) 285{ 286 287 if (idx < 0 || idx > SF_RXFILT_PERFECT_CNT) 288 return (EINVAL); 289 290 if (mac == NULL) 291 return (EINVAL); 292 293 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 294 (idx * SF_RXFILT_PERFECT_SKIP) + 0, mac[5] | (mac[4] << 8)); 295 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 296 (idx * SF_RXFILT_PERFECT_SKIP) + 4, mac[3] | (mac[2] << 8)); 297 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 298 (idx * SF_RXFILT_PERFECT_SKIP) + 8, mac[1] | (mac[0] << 8)); 299 300 return (0); 301} 302 303/* 304 * Set the bit in the 512-bit hash table that corresponds to the 305 * specified mac address 'mac.' If 'prio' is nonzero, update the 306 * priority hash table instead of the filter hash table. 307 */ 308static int 309sf_sethash(struct sf_softc *sc, caddr_t mac, int prio) 310{ 311 uint32_t h; 312 313 if (mac == NULL) 314 return (EINVAL); 315 316 h = ether_crc32_be(mac, ETHER_ADDR_LEN) >> 23; 317 318 if (prio) { 319 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_PRIOOFF + 320 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); 321 } else { 322 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_ADDROFF + 323 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); 324 } 325 326 return (0); 327} 328 329#ifdef notdef 330/* 331 * Set a VLAN tag in the receive filter. 332 */ 333static int 334sf_setvlan(struct sf_softc *sc, int idx, uint32_t vlan) 335{ 336 337 if (idx < 0 || idx >> SF_RXFILT_HASH_CNT) 338 return (EINVAL); 339 340 csr_write_4(sc, SF_RXFILT_HASH_BASE + 341 (idx * SF_RXFILT_HASH_SKIP) + SF_RXFILT_HASH_VLANOFF, vlan); 342 343 return (0); 344} 345#endif 346 347static int 348sf_miibus_readreg(device_t dev, int phy, int reg) 349{ 350 struct sf_softc *sc; 351 int i; 352 uint32_t val = 0; 353 354 sc = device_get_softc(dev); 355 356 for (i = 0; i < SF_TIMEOUT; i++) { 357 val = csr_read_4(sc, SF_PHY_REG(phy, reg)); 358 if ((val & SF_MII_DATAVALID) != 0) 359 break; 360 } 361 362 if (i == SF_TIMEOUT) 363 return (0); 364 365 val &= SF_MII_DATAPORT; 366 if (val == 0xffff) 367 return (0); 368 369 return (val); 370} 371 372static int 373sf_miibus_writereg(device_t dev, int phy, int reg, int val) 374{ 375 struct sf_softc *sc; 376 int i; 377 int busy; 378 379 sc = device_get_softc(dev); 380 381 csr_write_4(sc, SF_PHY_REG(phy, reg), val); 382 383 for (i = 0; i < SF_TIMEOUT; i++) { 384 busy = csr_read_4(sc, SF_PHY_REG(phy, reg)); 385 if ((busy & SF_MII_BUSY) == 0) 386 break; 387 } 388 389 return (0); 390} 391 392static void 393sf_miibus_statchg(device_t dev) 394{ 395 struct sf_softc *sc; 396 struct mii_data *mii; 397 struct ifnet *ifp; 398 uint32_t val; 399 400 sc = device_get_softc(dev); 401 mii = device_get_softc(sc->sf_miibus); 402 ifp = sc->sf_ifp; 403 if (mii == NULL || ifp == NULL || 404 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 405 return; 406 407 sc->sf_link = 0; 408 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 409 (IFM_ACTIVE | IFM_AVALID)) { 410 switch (IFM_SUBTYPE(mii->mii_media_active)) { 411 case IFM_10_T: 412 case IFM_100_TX: 413 case IFM_100_FX: 414 sc->sf_link = 1; 415 break; 416 } 417 } 418 if (sc->sf_link == 0) 419 return; 420 421 val = csr_read_4(sc, SF_MACCFG_1); 422 val &= ~SF_MACCFG1_FULLDUPLEX; 423 val &= ~(SF_MACCFG1_RX_FLOWENB | SF_MACCFG1_TX_FLOWENB); 424 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 425 val |= SF_MACCFG1_FULLDUPLEX; 426 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_FDX); 427#ifdef notyet 428 /* Configure flow-control bits. */ 429 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & 430 IFM_ETH_RXPAUSE) != 0) 431 val |= SF_MACCFG1_RX_FLOWENB; 432 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & 433 IFM_ETH_TXPAUSE) != 0) 434 val |= SF_MACCFG1_TX_FLOWENB; 435#endif 436 } else 437 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_HDX); 438 439 /* Make sure to reset MAC to take changes effect. */ 440 csr_write_4(sc, SF_MACCFG_1, val | SF_MACCFG1_SOFTRESET); 441 DELAY(1000); 442 csr_write_4(sc, SF_MACCFG_1, val); 443 444 val = csr_read_4(sc, SF_TIMER_CTL); 445 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) 446 val |= SF_TIMER_TIMES_TEN; 447 else 448 val &= ~SF_TIMER_TIMES_TEN; 449 csr_write_4(sc, SF_TIMER_CTL, val); 450} 451 452static void 453sf_rxfilter(struct sf_softc *sc) 454{ 455 struct ifnet *ifp; 456 int i; 457 struct ifmultiaddr *ifma; 458 uint8_t dummy[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 }; 459 uint32_t rxfilt; 460 461 ifp = sc->sf_ifp; 462 463 /* First zot all the existing filters. */ 464 for (i = 1; i < SF_RXFILT_PERFECT_CNT; i++) 465 sf_setperf(sc, i, dummy); 466 for (i = SF_RXFILT_HASH_BASE; i < (SF_RXFILT_HASH_MAX + 1); 467 i += sizeof(uint32_t)) 468 csr_write_4(sc, i, 0); 469 470 rxfilt = csr_read_4(sc, SF_RXFILT); 471 rxfilt &= ~(SF_RXFILT_PROMISC | SF_RXFILT_ALLMULTI | SF_RXFILT_BROAD); 472 if ((ifp->if_flags & IFF_BROADCAST) != 0) 473 rxfilt |= SF_RXFILT_BROAD; 474 if ((ifp->if_flags & IFF_ALLMULTI) != 0 || 475 (ifp->if_flags & IFF_PROMISC) != 0) { 476 if ((ifp->if_flags & IFF_PROMISC) != 0) 477 rxfilt |= SF_RXFILT_PROMISC; 478 if ((ifp->if_flags & IFF_ALLMULTI) != 0) 479 rxfilt |= SF_RXFILT_ALLMULTI; 480 goto done; 481 } 482 483 /* Now program new ones. */ 484 i = 1; 485 if_maddr_rlock(ifp); 486 TAILQ_FOREACH_REVERSE(ifma, &ifp->if_multiaddrs, ifmultihead, 487 ifma_link) { 488 if (ifma->ifma_addr->sa_family != AF_LINK) 489 continue; 490 /* 491 * Program the first 15 multicast groups 492 * into the perfect filter. For all others, 493 * use the hash table. 494 */ 495 if (i < SF_RXFILT_PERFECT_CNT) { 496 sf_setperf(sc, i, 497 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 498 i++; 499 continue; 500 } 501 502 sf_sethash(sc, 503 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 0); 504 } 505 if_maddr_runlock(ifp); 506 507done: 508 csr_write_4(sc, SF_RXFILT, rxfilt); 509} 510 511/* 512 * Set media options. 513 */ 514static int 515sf_ifmedia_upd(struct ifnet *ifp) 516{ 517 struct sf_softc *sc; 518 int error; 519 520 sc = ifp->if_softc; 521 SF_LOCK(sc); 522 error = sf_ifmedia_upd_locked(ifp); 523 SF_UNLOCK(sc); 524 return (error); 525} 526 527static int 528sf_ifmedia_upd_locked(struct ifnet *ifp) 529{ 530 struct sf_softc *sc; 531 struct mii_data *mii; 532 struct mii_softc *miisc; 533 534 sc = ifp->if_softc; 535 mii = device_get_softc(sc->sf_miibus); 536 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 537 PHY_RESET(miisc); 538 return (mii_mediachg(mii)); 539} 540 541/* 542 * Report current media status. 543 */ 544static void 545sf_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 546{ 547 struct sf_softc *sc; 548 struct mii_data *mii; 549 550 sc = ifp->if_softc; 551 SF_LOCK(sc); 552 if ((ifp->if_flags & IFF_UP) == 0) { 553 SF_UNLOCK(sc); 554 return; 555 } 556 557 mii = device_get_softc(sc->sf_miibus); 558 mii_pollstat(mii); 559 ifmr->ifm_active = mii->mii_media_active; 560 ifmr->ifm_status = mii->mii_media_status; 561 SF_UNLOCK(sc); 562} 563 564static int 565sf_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 566{ 567 struct sf_softc *sc; 568 struct ifreq *ifr; 569 struct mii_data *mii; 570 int error, mask; 571 572 sc = ifp->if_softc; 573 ifr = (struct ifreq *)data; 574 error = 0; 575 576 switch (command) { 577 case SIOCSIFFLAGS: 578 SF_LOCK(sc); 579 if (ifp->if_flags & IFF_UP) { 580 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 581 if ((ifp->if_flags ^ sc->sf_if_flags) & 582 (IFF_PROMISC | IFF_ALLMULTI)) 583 sf_rxfilter(sc); 584 } else { 585 if (sc->sf_detach == 0) 586 sf_init_locked(sc); 587 } 588 } else { 589 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 590 sf_stop(sc); 591 } 592 sc->sf_if_flags = ifp->if_flags; 593 SF_UNLOCK(sc); 594 break; 595 case SIOCADDMULTI: 596 case SIOCDELMULTI: 597 SF_LOCK(sc); 598 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 599 sf_rxfilter(sc); 600 SF_UNLOCK(sc); 601 break; 602 case SIOCGIFMEDIA: 603 case SIOCSIFMEDIA: 604 mii = device_get_softc(sc->sf_miibus); 605 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 606 break; 607 case SIOCSIFCAP: 608 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 609#ifdef DEVICE_POLLING 610 if ((mask & IFCAP_POLLING) != 0) { 611 if ((ifr->ifr_reqcap & IFCAP_POLLING) != 0) { 612 error = ether_poll_register(sf_poll, ifp); 613 if (error != 0) 614 break; 615 SF_LOCK(sc); 616 /* Disable interrupts. */ 617 csr_write_4(sc, SF_IMR, 0); 618 ifp->if_capenable |= IFCAP_POLLING; 619 SF_UNLOCK(sc); 620 } else { 621 error = ether_poll_deregister(ifp); 622 /* Enable interrupts. */ 623 SF_LOCK(sc); 624 csr_write_4(sc, SF_IMR, SF_INTRS); 625 ifp->if_capenable &= ~IFCAP_POLLING; 626 SF_UNLOCK(sc); 627 } 628 } 629#endif /* DEVICE_POLLING */ 630 if ((mask & IFCAP_TXCSUM) != 0) { 631 if ((IFCAP_TXCSUM & ifp->if_capabilities) != 0) { 632 SF_LOCK(sc); 633 ifp->if_capenable ^= IFCAP_TXCSUM; 634 if ((IFCAP_TXCSUM & ifp->if_capenable) != 0) { 635 ifp->if_hwassist |= SF_CSUM_FEATURES; 636 SF_SETBIT(sc, SF_GEN_ETH_CTL, 637 SF_ETHCTL_TXGFP_ENB); 638 } else { 639 ifp->if_hwassist &= ~SF_CSUM_FEATURES; 640 SF_CLRBIT(sc, SF_GEN_ETH_CTL, 641 SF_ETHCTL_TXGFP_ENB); 642 } 643 SF_UNLOCK(sc); 644 } 645 } 646 if ((mask & IFCAP_RXCSUM) != 0) { 647 if ((IFCAP_RXCSUM & ifp->if_capabilities) != 0) { 648 SF_LOCK(sc); 649 ifp->if_capenable ^= IFCAP_RXCSUM; 650 if ((IFCAP_RXCSUM & ifp->if_capenable) != 0) 651 SF_SETBIT(sc, SF_GEN_ETH_CTL, 652 SF_ETHCTL_RXGFP_ENB); 653 else 654 SF_CLRBIT(sc, SF_GEN_ETH_CTL, 655 SF_ETHCTL_RXGFP_ENB); 656 SF_UNLOCK(sc); 657 } 658 } 659 break; 660 default: 661 error = ether_ioctl(ifp, command, data); 662 break; 663 } 664 665 return (error); 666} 667 668static void 669sf_reset(struct sf_softc *sc) 670{ 671 int i; 672 673 csr_write_4(sc, SF_GEN_ETH_CTL, 0); 674 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 675 DELAY(1000); 676 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 677 678 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_RESET); 679 680 for (i = 0; i < SF_TIMEOUT; i++) { 681 DELAY(10); 682 if (!(csr_read_4(sc, SF_PCI_DEVCFG) & SF_PCIDEVCFG_RESET)) 683 break; 684 } 685 686 if (i == SF_TIMEOUT) 687 device_printf(sc->sf_dev, "reset never completed!\n"); 688 689 /* Wait a little while for the chip to get its brains in order. */ 690 DELAY(1000); 691} 692 693/* 694 * Probe for an Adaptec AIC-6915 chip. Check the PCI vendor and device 695 * IDs against our list and return a device name if we find a match. 696 * We also check the subsystem ID so that we can identify exactly which 697 * NIC has been found, if possible. 698 */ 699static int 700sf_probe(device_t dev) 701{ 702 struct sf_type *t; 703 uint16_t vid; 704 uint16_t did; 705 uint16_t sdid; 706 int i; 707 708 vid = pci_get_vendor(dev); 709 did = pci_get_device(dev); 710 sdid = pci_get_subdevice(dev); 711 712 t = sf_devs; 713 for (i = 0; i < nitems(sf_devs); i++, t++) { 714 if (vid == t->sf_vid && did == t->sf_did) { 715 if (sdid == t->sf_sdid) { 716 device_set_desc(dev, t->sf_sname); 717 return (BUS_PROBE_DEFAULT); 718 } 719 } 720 } 721 722 if (vid == AD_VENDORID && did == AD_DEVICEID_STARFIRE) { 723 /* unknown subdevice */ 724 device_set_desc(dev, sf_devs[0].sf_name); 725 return (BUS_PROBE_DEFAULT); 726 } 727 728 return (ENXIO); 729} 730 731/* 732 * Attach the interface. Allocate softc structures, do ifmedia 733 * setup and ethernet/BPF attach. 734 */ 735static int 736sf_attach(device_t dev) 737{ 738 int i; 739 struct sf_softc *sc; 740 struct ifnet *ifp; 741 uint32_t reg; 742 int rid, error = 0; 743 uint8_t eaddr[ETHER_ADDR_LEN]; 744 745 sc = device_get_softc(dev); 746 sc->sf_dev = dev; 747 748 mtx_init(&sc->sf_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 749 MTX_DEF); 750 callout_init_mtx(&sc->sf_co, &sc->sf_mtx, 0); 751 752 /* 753 * Map control/status registers. 754 */ 755 pci_enable_busmaster(dev); 756 757 /* 758 * Prefer memory space register mapping over I/O space as the 759 * hardware requires lots of register access to get various 760 * producer/consumer index during Tx/Rx operation. However this 761 * requires large memory space(512K) to map the entire register 762 * space. 763 */ 764 sc->sf_rid = PCIR_BAR(0); 765 sc->sf_restype = SYS_RES_MEMORY; 766 sc->sf_res = bus_alloc_resource_any(dev, sc->sf_restype, &sc->sf_rid, 767 RF_ACTIVE); 768 if (sc->sf_res == NULL) { 769 reg = pci_read_config(dev, PCIR_BAR(0), 4); 770 if ((reg & PCIM_BAR_MEM_64) == PCIM_BAR_MEM_64) 771 sc->sf_rid = PCIR_BAR(2); 772 else 773 sc->sf_rid = PCIR_BAR(1); 774 sc->sf_restype = SYS_RES_IOPORT; 775 sc->sf_res = bus_alloc_resource_any(dev, sc->sf_restype, 776 &sc->sf_rid, RF_ACTIVE); 777 if (sc->sf_res == NULL) { 778 device_printf(dev, "couldn't allocate resources\n"); 779 mtx_destroy(&sc->sf_mtx); 780 return (ENXIO); 781 } 782 } 783 if (bootverbose) 784 device_printf(dev, "using %s space register mapping\n", 785 sc->sf_restype == SYS_RES_MEMORY ? "memory" : "I/O"); 786 787 reg = pci_read_config(dev, PCIR_CACHELNSZ, 1); 788 if (reg == 0) { 789 /* 790 * If cache line size is 0, MWI is not used at all, so set 791 * reasonable default. AIC-6915 supports 0, 4, 8, 16, 32 792 * and 64. 793 */ 794 reg = 16; 795 device_printf(dev, "setting PCI cache line size to %u\n", reg); 796 pci_write_config(dev, PCIR_CACHELNSZ, reg, 1); 797 } else { 798 if (bootverbose) 799 device_printf(dev, "PCI cache line size : %u\n", reg); 800 } 801 /* Enable MWI. */ 802 reg = pci_read_config(dev, PCIR_COMMAND, 2); 803 reg |= PCIM_CMD_MWRICEN; 804 pci_write_config(dev, PCIR_COMMAND, reg, 2); 805 806 /* Allocate interrupt. */ 807 rid = 0; 808 sc->sf_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 809 RF_SHAREABLE | RF_ACTIVE); 810 811 if (sc->sf_irq == NULL) { 812 device_printf(dev, "couldn't map interrupt\n"); 813 error = ENXIO; 814 goto fail; 815 } 816 817 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 818 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 819 OID_AUTO, "stats", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 820 sf_sysctl_stats, "I", "Statistics"); 821 822 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 823 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 824 OID_AUTO, "int_mod", CTLTYPE_INT | CTLFLAG_RW, 825 &sc->sf_int_mod, 0, sysctl_hw_sf_int_mod, "I", 826 "sf interrupt moderation"); 827 /* Pull in device tunables. */ 828 sc->sf_int_mod = SF_IM_DEFAULT; 829 error = resource_int_value(device_get_name(dev), device_get_unit(dev), 830 "int_mod", &sc->sf_int_mod); 831 if (error == 0) { 832 if (sc->sf_int_mod < SF_IM_MIN || 833 sc->sf_int_mod > SF_IM_MAX) { 834 device_printf(dev, "int_mod value out of range; " 835 "using default: %d\n", SF_IM_DEFAULT); 836 sc->sf_int_mod = SF_IM_DEFAULT; 837 } 838 } 839 840 /* Reset the adapter. */ 841 sf_reset(sc); 842 843 /* 844 * Get station address from the EEPROM. 845 */ 846 for (i = 0; i < ETHER_ADDR_LEN; i++) 847 eaddr[i] = 848 sf_read_eeprom(sc, SF_EE_NODEADDR + ETHER_ADDR_LEN - i); 849 850 /* Allocate DMA resources. */ 851 if (sf_dma_alloc(sc) != 0) { 852 error = ENOSPC; 853 goto fail; 854 } 855 856 sc->sf_txthresh = SF_MIN_TX_THRESHOLD; 857 858 ifp = sc->sf_ifp = if_alloc(IFT_ETHER); 859 if (ifp == NULL) { 860 device_printf(dev, "can not allocate ifnet structure\n"); 861 error = ENOSPC; 862 goto fail; 863 } 864 865 /* Do MII setup. */ 866 error = mii_attach(dev, &sc->sf_miibus, ifp, sf_ifmedia_upd, 867 sf_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0); 868 if (error != 0) { 869 device_printf(dev, "attaching PHYs failed\n"); 870 goto fail; 871 } 872 873 ifp->if_softc = sc; 874 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 875 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 876 ifp->if_ioctl = sf_ioctl; 877 ifp->if_start = sf_start; 878 ifp->if_init = sf_init; 879 IFQ_SET_MAXLEN(&ifp->if_snd, SF_TX_DLIST_CNT - 1); 880 ifp->if_snd.ifq_drv_maxlen = SF_TX_DLIST_CNT - 1; 881 IFQ_SET_READY(&ifp->if_snd); 882 /* 883 * With the help of firmware, AIC-6915 supports 884 * Tx/Rx TCP/UDP checksum offload. 885 */ 886 ifp->if_hwassist = SF_CSUM_FEATURES; 887 ifp->if_capabilities = IFCAP_HWCSUM; 888 889 /* 890 * Call MI attach routine. 891 */ 892 ether_ifattach(ifp, eaddr); 893 894 /* VLAN capability setup. */ 895 ifp->if_capabilities |= IFCAP_VLAN_MTU; 896 ifp->if_capenable = ifp->if_capabilities; 897#ifdef DEVICE_POLLING 898 ifp->if_capabilities |= IFCAP_POLLING; 899#endif 900 /* 901 * Tell the upper layer(s) we support long frames. 902 * Must appear after the call to ether_ifattach() because 903 * ether_ifattach() sets ifi_hdrlen to the default value. 904 */ 905 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 906 907 /* Hook interrupt last to avoid having to lock softc */ 908 error = bus_setup_intr(dev, sc->sf_irq, INTR_TYPE_NET | INTR_MPSAFE, 909 NULL, sf_intr, sc, &sc->sf_intrhand); 910 911 if (error) { 912 device_printf(dev, "couldn't set up irq\n"); 913 ether_ifdetach(ifp); 914 goto fail; 915 } 916 917 gone_by_fcp101_dev(dev); 918 919fail: 920 if (error) 921 sf_detach(dev); 922 923 return (error); 924} 925 926/* 927 * Shutdown hardware and free up resources. This can be called any 928 * time after the mutex has been initialized. It is called in both 929 * the error case in attach and the normal detach case so it needs 930 * to be careful about only freeing resources that have actually been 931 * allocated. 932 */ 933static int 934sf_detach(device_t dev) 935{ 936 struct sf_softc *sc; 937 struct ifnet *ifp; 938 939 sc = device_get_softc(dev); 940 ifp = sc->sf_ifp; 941 942#ifdef DEVICE_POLLING 943 if (ifp != NULL && ifp->if_capenable & IFCAP_POLLING) 944 ether_poll_deregister(ifp); 945#endif 946 947 /* These should only be active if attach succeeded */ 948 if (device_is_attached(dev)) { 949 SF_LOCK(sc); 950 sc->sf_detach = 1; 951 sf_stop(sc); 952 SF_UNLOCK(sc); 953 callout_drain(&sc->sf_co); 954 if (ifp != NULL) 955 ether_ifdetach(ifp); 956 } 957 if (sc->sf_miibus) { 958 device_delete_child(dev, sc->sf_miibus); 959 sc->sf_miibus = NULL; 960 } 961 bus_generic_detach(dev); 962 963 if (sc->sf_intrhand != NULL) 964 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand); 965 if (sc->sf_irq != NULL) 966 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq); 967 if (sc->sf_res != NULL) 968 bus_release_resource(dev, sc->sf_restype, sc->sf_rid, 969 sc->sf_res); 970 971 sf_dma_free(sc); 972 if (ifp != NULL) 973 if_free(ifp); 974 975 mtx_destroy(&sc->sf_mtx); 976 977 return (0); 978} 979 980struct sf_dmamap_arg { 981 bus_addr_t sf_busaddr; 982}; 983 984static void 985sf_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 986{ 987 struct sf_dmamap_arg *ctx; 988 989 if (error != 0) 990 return; 991 ctx = arg; 992 ctx->sf_busaddr = segs[0].ds_addr; 993} 994 995static int 996sf_dma_alloc(struct sf_softc *sc) 997{ 998 struct sf_dmamap_arg ctx; 999 struct sf_txdesc *txd; 1000 struct sf_rxdesc *rxd; 1001 bus_addr_t lowaddr; 1002 bus_addr_t rx_ring_end, rx_cring_end; 1003 bus_addr_t tx_ring_end, tx_cring_end; 1004 int error, i; 1005 1006 lowaddr = BUS_SPACE_MAXADDR; 1007 1008again: 1009 /* Create parent DMA tag. */ 1010 error = bus_dma_tag_create( 1011 bus_get_dma_tag(sc->sf_dev), /* parent */ 1012 1, 0, /* alignment, boundary */ 1013 lowaddr, /* lowaddr */ 1014 BUS_SPACE_MAXADDR, /* highaddr */ 1015 NULL, NULL, /* filter, filterarg */ 1016 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1017 0, /* nsegments */ 1018 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1019 0, /* flags */ 1020 NULL, NULL, /* lockfunc, lockarg */ 1021 &sc->sf_cdata.sf_parent_tag); 1022 if (error != 0) { 1023 device_printf(sc->sf_dev, "failed to create parent DMA tag\n"); 1024 goto fail; 1025 } 1026 /* Create tag for Tx ring. */ 1027 error = bus_dma_tag_create(sc->sf_cdata.sf_parent_tag,/* parent */ 1028 SF_RING_ALIGN, 0, /* alignment, boundary */ 1029 BUS_SPACE_MAXADDR, /* lowaddr */ 1030 BUS_SPACE_MAXADDR, /* highaddr */ 1031 NULL, NULL, /* filter, filterarg */ 1032 SF_TX_DLIST_SIZE, /* maxsize */ 1033 1, /* nsegments */ 1034 SF_TX_DLIST_SIZE, /* maxsegsize */ 1035 0, /* flags */ 1036 NULL, NULL, /* lockfunc, lockarg */ 1037 &sc->sf_cdata.sf_tx_ring_tag); 1038 if (error != 0) { 1039 device_printf(sc->sf_dev, "failed to create Tx ring DMA tag\n"); 1040 goto fail; 1041 } 1042 1043 /* Create tag for Tx completion ring. */ 1044 error = bus_dma_tag_create(sc->sf_cdata.sf_parent_tag,/* parent */ 1045 SF_RING_ALIGN, 0, /* alignment, boundary */ 1046 BUS_SPACE_MAXADDR, /* lowaddr */ 1047 BUS_SPACE_MAXADDR, /* highaddr */ 1048 NULL, NULL, /* filter, filterarg */ 1049 SF_TX_CLIST_SIZE, /* maxsize */ 1050 1, /* nsegments */ 1051 SF_TX_CLIST_SIZE, /* maxsegsize */ 1052 0, /* flags */ 1053 NULL, NULL, /* lockfunc, lockarg */ 1054 &sc->sf_cdata.sf_tx_cring_tag); 1055 if (error != 0) { 1056 device_printf(sc->sf_dev, 1057 "failed to create Tx completion ring DMA tag\n"); 1058 goto fail; 1059 } 1060 1061 /* Create tag for Rx ring. */ 1062 error = bus_dma_tag_create(sc->sf_cdata.sf_parent_tag,/* parent */ 1063 SF_RING_ALIGN, 0, /* alignment, boundary */ 1064 BUS_SPACE_MAXADDR, /* lowaddr */ 1065 BUS_SPACE_MAXADDR, /* highaddr */ 1066 NULL, NULL, /* filter, filterarg */ 1067 SF_RX_DLIST_SIZE, /* maxsize */ 1068 1, /* nsegments */ 1069 SF_RX_DLIST_SIZE, /* maxsegsize */ 1070 0, /* flags */ 1071 NULL, NULL, /* lockfunc, lockarg */ 1072 &sc->sf_cdata.sf_rx_ring_tag); 1073 if (error != 0) { 1074 device_printf(sc->sf_dev, 1075 "failed to create Rx ring DMA tag\n"); 1076 goto fail; 1077 } 1078 1079 /* Create tag for Rx completion ring. */ 1080 error = bus_dma_tag_create(sc->sf_cdata.sf_parent_tag,/* parent */ 1081 SF_RING_ALIGN, 0, /* alignment, boundary */ 1082 BUS_SPACE_MAXADDR, /* lowaddr */ 1083 BUS_SPACE_MAXADDR, /* highaddr */ 1084 NULL, NULL, /* filter, filterarg */ 1085 SF_RX_CLIST_SIZE, /* maxsize */ 1086 1, /* nsegments */ 1087 SF_RX_CLIST_SIZE, /* maxsegsize */ 1088 0, /* flags */ 1089 NULL, NULL, /* lockfunc, lockarg */ 1090 &sc->sf_cdata.sf_rx_cring_tag); 1091 if (error != 0) { 1092 device_printf(sc->sf_dev, 1093 "failed to create Rx completion ring DMA tag\n"); 1094 goto fail; 1095 } 1096 1097 /* Create tag for Tx buffers. */ 1098 error = bus_dma_tag_create(sc->sf_cdata.sf_parent_tag,/* parent */ 1099 1, 0, /* alignment, boundary */ 1100 BUS_SPACE_MAXADDR, /* lowaddr */ 1101 BUS_SPACE_MAXADDR, /* highaddr */ 1102 NULL, NULL, /* filter, filterarg */ 1103 MCLBYTES * SF_MAXTXSEGS, /* maxsize */ 1104 SF_MAXTXSEGS, /* nsegments */ 1105 MCLBYTES, /* maxsegsize */ 1106 0, /* flags */ 1107 NULL, NULL, /* lockfunc, lockarg */ 1108 &sc->sf_cdata.sf_tx_tag); 1109 if (error != 0) { 1110 device_printf(sc->sf_dev, "failed to create Tx DMA tag\n"); 1111 goto fail; 1112 } 1113 1114 /* Create tag for Rx buffers. */ 1115 error = bus_dma_tag_create(sc->sf_cdata.sf_parent_tag,/* parent */ 1116 SF_RX_ALIGN, 0, /* alignment, boundary */ 1117 BUS_SPACE_MAXADDR, /* lowaddr */ 1118 BUS_SPACE_MAXADDR, /* highaddr */ 1119 NULL, NULL, /* filter, filterarg */ 1120 MCLBYTES, /* maxsize */ 1121 1, /* nsegments */ 1122 MCLBYTES, /* maxsegsize */ 1123 0, /* flags */ 1124 NULL, NULL, /* lockfunc, lockarg */ 1125 &sc->sf_cdata.sf_rx_tag); 1126 if (error != 0) { 1127 device_printf(sc->sf_dev, "failed to create Rx DMA tag\n"); 1128 goto fail; 1129 } 1130 1131 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 1132 error = bus_dmamem_alloc(sc->sf_cdata.sf_tx_ring_tag, 1133 (void **)&sc->sf_rdata.sf_tx_ring, BUS_DMA_WAITOK | 1134 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->sf_cdata.sf_tx_ring_map); 1135 if (error != 0) { 1136 device_printf(sc->sf_dev, 1137 "failed to allocate DMA'able memory for Tx ring\n"); 1138 goto fail; 1139 } 1140 1141 ctx.sf_busaddr = 0; 1142 error = bus_dmamap_load(sc->sf_cdata.sf_tx_ring_tag, 1143 sc->sf_cdata.sf_tx_ring_map, sc->sf_rdata.sf_tx_ring, 1144 SF_TX_DLIST_SIZE, sf_dmamap_cb, &ctx, 0); 1145 if (error != 0 || ctx.sf_busaddr == 0) { 1146 device_printf(sc->sf_dev, 1147 "failed to load DMA'able memory for Tx ring\n"); 1148 goto fail; 1149 } 1150 sc->sf_rdata.sf_tx_ring_paddr = ctx.sf_busaddr; 1151 1152 /* 1153 * Allocate DMA'able memory and load the DMA map for Tx completion ring. 1154 */ 1155 error = bus_dmamem_alloc(sc->sf_cdata.sf_tx_cring_tag, 1156 (void **)&sc->sf_rdata.sf_tx_cring, BUS_DMA_WAITOK | 1157 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->sf_cdata.sf_tx_cring_map); 1158 if (error != 0) { 1159 device_printf(sc->sf_dev, 1160 "failed to allocate DMA'able memory for " 1161 "Tx completion ring\n"); 1162 goto fail; 1163 } 1164 1165 ctx.sf_busaddr = 0; 1166 error = bus_dmamap_load(sc->sf_cdata.sf_tx_cring_tag, 1167 sc->sf_cdata.sf_tx_cring_map, sc->sf_rdata.sf_tx_cring, 1168 SF_TX_CLIST_SIZE, sf_dmamap_cb, &ctx, 0); 1169 if (error != 0 || ctx.sf_busaddr == 0) { 1170 device_printf(sc->sf_dev, 1171 "failed to load DMA'able memory for Tx completion ring\n"); 1172 goto fail; 1173 } 1174 sc->sf_rdata.sf_tx_cring_paddr = ctx.sf_busaddr; 1175 1176 /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 1177 error = bus_dmamem_alloc(sc->sf_cdata.sf_rx_ring_tag, 1178 (void **)&sc->sf_rdata.sf_rx_ring, BUS_DMA_WAITOK | 1179 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->sf_cdata.sf_rx_ring_map); 1180 if (error != 0) { 1181 device_printf(sc->sf_dev, 1182 "failed to allocate DMA'able memory for Rx ring\n"); 1183 goto fail; 1184 } 1185 1186 ctx.sf_busaddr = 0; 1187 error = bus_dmamap_load(sc->sf_cdata.sf_rx_ring_tag, 1188 sc->sf_cdata.sf_rx_ring_map, sc->sf_rdata.sf_rx_ring, 1189 SF_RX_DLIST_SIZE, sf_dmamap_cb, &ctx, 0); 1190 if (error != 0 || ctx.sf_busaddr == 0) { 1191 device_printf(sc->sf_dev, 1192 "failed to load DMA'able memory for Rx ring\n"); 1193 goto fail; 1194 } 1195 sc->sf_rdata.sf_rx_ring_paddr = ctx.sf_busaddr; 1196 1197 /* 1198 * Allocate DMA'able memory and load the DMA map for Rx completion ring. 1199 */ 1200 error = bus_dmamem_alloc(sc->sf_cdata.sf_rx_cring_tag, 1201 (void **)&sc->sf_rdata.sf_rx_cring, BUS_DMA_WAITOK | 1202 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->sf_cdata.sf_rx_cring_map); 1203 if (error != 0) { 1204 device_printf(sc->sf_dev, 1205 "failed to allocate DMA'able memory for " 1206 "Rx completion ring\n"); 1207 goto fail; 1208 } 1209 1210 ctx.sf_busaddr = 0; 1211 error = bus_dmamap_load(sc->sf_cdata.sf_rx_cring_tag, 1212 sc->sf_cdata.sf_rx_cring_map, sc->sf_rdata.sf_rx_cring, 1213 SF_RX_CLIST_SIZE, sf_dmamap_cb, &ctx, 0); 1214 if (error != 0 || ctx.sf_busaddr == 0) { 1215 device_printf(sc->sf_dev, 1216 "failed to load DMA'able memory for Rx completion ring\n"); 1217 goto fail; 1218 } 1219 sc->sf_rdata.sf_rx_cring_paddr = ctx.sf_busaddr; 1220 1221 /* 1222 * Tx desciptor ring and Tx completion ring should be addressed in 1223 * the same 4GB space. The same rule applys to Rx ring and Rx 1224 * completion ring. Unfortunately there is no way to specify this 1225 * boundary restriction with bus_dma(9). So just try to allocate 1226 * without the restriction and check the restriction was satisfied. 1227 * If not, fall back to 32bit dma addressing mode which always 1228 * guarantees the restriction. 1229 */ 1230 tx_ring_end = sc->sf_rdata.sf_tx_ring_paddr + SF_TX_DLIST_SIZE; 1231 tx_cring_end = sc->sf_rdata.sf_tx_cring_paddr + SF_TX_CLIST_SIZE; 1232 rx_ring_end = sc->sf_rdata.sf_rx_ring_paddr + SF_RX_DLIST_SIZE; 1233 rx_cring_end = sc->sf_rdata.sf_rx_cring_paddr + SF_RX_CLIST_SIZE; 1234 if ((SF_ADDR_HI(sc->sf_rdata.sf_tx_ring_paddr) != 1235 SF_ADDR_HI(tx_cring_end)) || 1236 (SF_ADDR_HI(sc->sf_rdata.sf_tx_cring_paddr) != 1237 SF_ADDR_HI(tx_ring_end)) || 1238 (SF_ADDR_HI(sc->sf_rdata.sf_rx_ring_paddr) != 1239 SF_ADDR_HI(rx_cring_end)) || 1240 (SF_ADDR_HI(sc->sf_rdata.sf_rx_cring_paddr) != 1241 SF_ADDR_HI(rx_ring_end))) { 1242 device_printf(sc->sf_dev, 1243 "switching to 32bit DMA mode\n"); 1244 sf_dma_free(sc); 1245 /* Limit DMA address space to 32bit and try again. */ 1246 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1247 goto again; 1248 } 1249 1250 /* Create DMA maps for Tx buffers. */ 1251 for (i = 0; i < SF_TX_DLIST_CNT; i++) { 1252 txd = &sc->sf_cdata.sf_txdesc[i]; 1253 txd->tx_m = NULL; 1254 txd->ndesc = 0; 1255 txd->tx_dmamap = NULL; 1256 error = bus_dmamap_create(sc->sf_cdata.sf_tx_tag, 0, 1257 &txd->tx_dmamap); 1258 if (error != 0) { 1259 device_printf(sc->sf_dev, 1260 "failed to create Tx dmamap\n"); 1261 goto fail; 1262 } 1263 } 1264 /* Create DMA maps for Rx buffers. */ 1265 if ((error = bus_dmamap_create(sc->sf_cdata.sf_rx_tag, 0, 1266 &sc->sf_cdata.sf_rx_sparemap)) != 0) { 1267 device_printf(sc->sf_dev, 1268 "failed to create spare Rx dmamap\n"); 1269 goto fail; 1270 } 1271 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 1272 rxd = &sc->sf_cdata.sf_rxdesc[i]; 1273 rxd->rx_m = NULL; 1274 rxd->rx_dmamap = NULL; 1275 error = bus_dmamap_create(sc->sf_cdata.sf_rx_tag, 0, 1276 &rxd->rx_dmamap); 1277 if (error != 0) { 1278 device_printf(sc->sf_dev, 1279 "failed to create Rx dmamap\n"); 1280 goto fail; 1281 } 1282 } 1283 1284fail: 1285 return (error); 1286} 1287 1288static void 1289sf_dma_free(struct sf_softc *sc) 1290{ 1291 struct sf_txdesc *txd; 1292 struct sf_rxdesc *rxd; 1293 int i; 1294 1295 /* Tx ring. */ 1296 if (sc->sf_cdata.sf_tx_ring_tag) { 1297 if (sc->sf_rdata.sf_tx_ring_paddr) 1298 bus_dmamap_unload(sc->sf_cdata.sf_tx_ring_tag, 1299 sc->sf_cdata.sf_tx_ring_map); 1300 if (sc->sf_rdata.sf_tx_ring) 1301 bus_dmamem_free(sc->sf_cdata.sf_tx_ring_tag, 1302 sc->sf_rdata.sf_tx_ring, 1303 sc->sf_cdata.sf_tx_ring_map); 1304 sc->sf_rdata.sf_tx_ring = NULL; 1305 sc->sf_rdata.sf_tx_ring_paddr = 0; 1306 bus_dma_tag_destroy(sc->sf_cdata.sf_tx_ring_tag); 1307 sc->sf_cdata.sf_tx_ring_tag = NULL; 1308 } 1309 /* Tx completion ring. */ 1310 if (sc->sf_cdata.sf_tx_cring_tag) { 1311 if (sc->sf_rdata.sf_tx_cring_paddr) 1312 bus_dmamap_unload(sc->sf_cdata.sf_tx_cring_tag, 1313 sc->sf_cdata.sf_tx_cring_map); 1314 if (sc->sf_rdata.sf_tx_cring) 1315 bus_dmamem_free(sc->sf_cdata.sf_tx_cring_tag, 1316 sc->sf_rdata.sf_tx_cring, 1317 sc->sf_cdata.sf_tx_cring_map); 1318 sc->sf_rdata.sf_tx_cring = NULL; 1319 sc->sf_rdata.sf_tx_cring_paddr = 0; 1320 bus_dma_tag_destroy(sc->sf_cdata.sf_tx_cring_tag); 1321 sc->sf_cdata.sf_tx_cring_tag = NULL; 1322 } 1323 /* Rx ring. */ 1324 if (sc->sf_cdata.sf_rx_ring_tag) { 1325 if (sc->sf_rdata.sf_rx_ring_paddr) 1326 bus_dmamap_unload(sc->sf_cdata.sf_rx_ring_tag, 1327 sc->sf_cdata.sf_rx_ring_map); 1328 if (sc->sf_rdata.sf_rx_ring) 1329 bus_dmamem_free(sc->sf_cdata.sf_rx_ring_tag, 1330 sc->sf_rdata.sf_rx_ring, 1331 sc->sf_cdata.sf_rx_ring_map); 1332 sc->sf_rdata.sf_rx_ring = NULL; 1333 sc->sf_rdata.sf_rx_ring_paddr = 0; 1334 bus_dma_tag_destroy(sc->sf_cdata.sf_rx_ring_tag); 1335 sc->sf_cdata.sf_rx_ring_tag = NULL; 1336 } 1337 /* Rx completion ring. */ 1338 if (sc->sf_cdata.sf_rx_cring_tag) { 1339 if (sc->sf_rdata.sf_rx_cring_paddr) 1340 bus_dmamap_unload(sc->sf_cdata.sf_rx_cring_tag, 1341 sc->sf_cdata.sf_rx_cring_map); 1342 if (sc->sf_rdata.sf_rx_cring) 1343 bus_dmamem_free(sc->sf_cdata.sf_rx_cring_tag, 1344 sc->sf_rdata.sf_rx_cring, 1345 sc->sf_cdata.sf_rx_cring_map); 1346 sc->sf_rdata.sf_rx_cring = NULL; 1347 sc->sf_rdata.sf_rx_cring_paddr = 0; 1348 bus_dma_tag_destroy(sc->sf_cdata.sf_rx_cring_tag); 1349 sc->sf_cdata.sf_rx_cring_tag = NULL; 1350 } 1351 /* Tx buffers. */ 1352 if (sc->sf_cdata.sf_tx_tag) { 1353 for (i = 0; i < SF_TX_DLIST_CNT; i++) { 1354 txd = &sc->sf_cdata.sf_txdesc[i]; 1355 if (txd->tx_dmamap) { 1356 bus_dmamap_destroy(sc->sf_cdata.sf_tx_tag, 1357 txd->tx_dmamap); 1358 txd->tx_dmamap = NULL; 1359 } 1360 } 1361 bus_dma_tag_destroy(sc->sf_cdata.sf_tx_tag); 1362 sc->sf_cdata.sf_tx_tag = NULL; 1363 } 1364 /* Rx buffers. */ 1365 if (sc->sf_cdata.sf_rx_tag) { 1366 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 1367 rxd = &sc->sf_cdata.sf_rxdesc[i]; 1368 if (rxd->rx_dmamap) { 1369 bus_dmamap_destroy(sc->sf_cdata.sf_rx_tag, 1370 rxd->rx_dmamap); 1371 rxd->rx_dmamap = NULL; 1372 } 1373 } 1374 if (sc->sf_cdata.sf_rx_sparemap) { 1375 bus_dmamap_destroy(sc->sf_cdata.sf_rx_tag, 1376 sc->sf_cdata.sf_rx_sparemap); 1377 sc->sf_cdata.sf_rx_sparemap = 0; 1378 } 1379 bus_dma_tag_destroy(sc->sf_cdata.sf_rx_tag); 1380 sc->sf_cdata.sf_rx_tag = NULL; 1381 } 1382 1383 if (sc->sf_cdata.sf_parent_tag) { 1384 bus_dma_tag_destroy(sc->sf_cdata.sf_parent_tag); 1385 sc->sf_cdata.sf_parent_tag = NULL; 1386 } 1387} 1388 1389static int 1390sf_init_rx_ring(struct sf_softc *sc) 1391{ 1392 struct sf_ring_data *rd; 1393 int i; 1394 1395 sc->sf_cdata.sf_rxc_cons = 0; 1396 1397 rd = &sc->sf_rdata; 1398 bzero(rd->sf_rx_ring, SF_RX_DLIST_SIZE); 1399 bzero(rd->sf_rx_cring, SF_RX_CLIST_SIZE); 1400 1401 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 1402 if (sf_newbuf(sc, i) != 0) 1403 return (ENOBUFS); 1404 } 1405 1406 bus_dmamap_sync(sc->sf_cdata.sf_rx_cring_tag, 1407 sc->sf_cdata.sf_rx_cring_map, 1408 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1409 bus_dmamap_sync(sc->sf_cdata.sf_rx_ring_tag, 1410 sc->sf_cdata.sf_rx_ring_map, 1411 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1412 1413 return (0); 1414} 1415 1416static void 1417sf_init_tx_ring(struct sf_softc *sc) 1418{ 1419 struct sf_ring_data *rd; 1420 int i; 1421 1422 sc->sf_cdata.sf_tx_prod = 0; 1423 sc->sf_cdata.sf_tx_cnt = 0; 1424 sc->sf_cdata.sf_txc_cons = 0; 1425 1426 rd = &sc->sf_rdata; 1427 bzero(rd->sf_tx_ring, SF_TX_DLIST_SIZE); 1428 bzero(rd->sf_tx_cring, SF_TX_CLIST_SIZE); 1429 for (i = 0; i < SF_TX_DLIST_CNT; i++) { 1430 rd->sf_tx_ring[i].sf_tx_ctrl = htole32(SF_TX_DESC_ID); 1431 sc->sf_cdata.sf_txdesc[i].tx_m = NULL; 1432 sc->sf_cdata.sf_txdesc[i].ndesc = 0; 1433 } 1434 rd->sf_tx_ring[i].sf_tx_ctrl |= htole32(SF_TX_DESC_END); 1435 1436 bus_dmamap_sync(sc->sf_cdata.sf_tx_ring_tag, 1437 sc->sf_cdata.sf_tx_ring_map, 1438 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1439 bus_dmamap_sync(sc->sf_cdata.sf_tx_cring_tag, 1440 sc->sf_cdata.sf_tx_cring_map, 1441 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1442} 1443 1444/* 1445 * Initialize an RX descriptor and attach an MBUF cluster. 1446 */ 1447static int 1448sf_newbuf(struct sf_softc *sc, int idx) 1449{ 1450 struct sf_rx_rdesc *desc; 1451 struct sf_rxdesc *rxd; 1452 struct mbuf *m; 1453 bus_dma_segment_t segs[1]; 1454 bus_dmamap_t map; 1455 int nsegs; 1456 1457 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1458 if (m == NULL) 1459 return (ENOBUFS); 1460 m->m_len = m->m_pkthdr.len = MCLBYTES; 1461 m_adj(m, sizeof(uint32_t)); 1462 1463 if (bus_dmamap_load_mbuf_sg(sc->sf_cdata.sf_rx_tag, 1464 sc->sf_cdata.sf_rx_sparemap, m, segs, &nsegs, 0) != 0) { 1465 m_freem(m); 1466 return (ENOBUFS); 1467 } 1468 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1469 1470 rxd = &sc->sf_cdata.sf_rxdesc[idx]; 1471 if (rxd->rx_m != NULL) { 1472 bus_dmamap_sync(sc->sf_cdata.sf_rx_tag, rxd->rx_dmamap, 1473 BUS_DMASYNC_POSTREAD); 1474 bus_dmamap_unload(sc->sf_cdata.sf_rx_tag, rxd->rx_dmamap); 1475 } 1476 map = rxd->rx_dmamap; 1477 rxd->rx_dmamap = sc->sf_cdata.sf_rx_sparemap; 1478 sc->sf_cdata.sf_rx_sparemap = map; 1479 bus_dmamap_sync(sc->sf_cdata.sf_rx_tag, rxd->rx_dmamap, 1480 BUS_DMASYNC_PREREAD); 1481 rxd->rx_m = m; 1482 desc = &sc->sf_rdata.sf_rx_ring[idx]; 1483 desc->sf_addr = htole64(segs[0].ds_addr); 1484 1485 return (0); 1486} 1487 1488#ifndef __NO_STRICT_ALIGNMENT 1489static __inline void 1490sf_fixup_rx(struct mbuf *m) 1491{ 1492 int i; 1493 uint16_t *src, *dst; 1494 1495 src = mtod(m, uint16_t *); 1496 dst = src - 1; 1497 1498 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1499 *dst++ = *src++; 1500 1501 m->m_data -= ETHER_ALIGN; 1502} 1503#endif 1504 1505/* 1506 * The starfire is programmed to use 'normal' mode for packet reception, 1507 * which means we use the consumer/producer model for both the buffer 1508 * descriptor queue and the completion descriptor queue. The only problem 1509 * with this is that it involves a lot of register accesses: we have to 1510 * read the RX completion consumer and producer indexes and the RX buffer 1511 * producer index, plus the RX completion consumer and RX buffer producer 1512 * indexes have to be updated. It would have been easier if Adaptec had 1513 * put each index in a separate register, especially given that the damn 1514 * NIC has a 512K register space. 1515 * 1516 * In spite of all the lovely features that Adaptec crammed into the 6915, 1517 * it is marred by one truly stupid design flaw, which is that receive 1518 * buffer addresses must be aligned on a longword boundary. This forces 1519 * the packet payload to be unaligned, which is suboptimal on the x86 and 1520 * completely unusable on the Alpha. Our only recourse is to copy received 1521 * packets into properly aligned buffers before handing them off. 1522 */ 1523static int 1524sf_rxeof(struct sf_softc *sc) 1525{ 1526 struct mbuf *m; 1527 struct ifnet *ifp; 1528 struct sf_rxdesc *rxd; 1529 struct sf_rx_rcdesc *cur_cmp; 1530 int cons, eidx, prog, rx_npkts; 1531 uint32_t status, status2; 1532 1533 SF_LOCK_ASSERT(sc); 1534 1535 ifp = sc->sf_ifp; 1536 rx_npkts = 0; 1537 1538 bus_dmamap_sync(sc->sf_cdata.sf_rx_ring_tag, 1539 sc->sf_cdata.sf_rx_ring_map, 1540 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1541 bus_dmamap_sync(sc->sf_cdata.sf_rx_cring_tag, 1542 sc->sf_cdata.sf_rx_cring_map, 1543 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1544 1545 /* 1546 * To reduce register access, directly read Receive completion 1547 * queue entry. 1548 */ 1549 eidx = 0; 1550 prog = 0; 1551 for (cons = sc->sf_cdata.sf_rxc_cons; 1552 (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0; 1553 SF_INC(cons, SF_RX_CLIST_CNT)) { 1554 cur_cmp = &sc->sf_rdata.sf_rx_cring[cons]; 1555 status = le32toh(cur_cmp->sf_rx_status1); 1556 if (status == 0) 1557 break; 1558#ifdef DEVICE_POLLING 1559 if ((ifp->if_capenable & IFCAP_POLLING) != 0) { 1560 if (sc->rxcycles <= 0) 1561 break; 1562 sc->rxcycles--; 1563 } 1564#endif 1565 prog++; 1566 eidx = (status & SF_RX_CMPDESC_EIDX) >> 16; 1567 rxd = &sc->sf_cdata.sf_rxdesc[eidx]; 1568 m = rxd->rx_m; 1569 1570 /* 1571 * Note, IFCOUNTER_IPACKETS and IFCOUNTER_IERRORS 1572 * are handled in sf_stats_update(). 1573 */ 1574 if ((status & SF_RXSTAT1_OK) == 0) { 1575 cur_cmp->sf_rx_status1 = 0; 1576 continue; 1577 } 1578 1579 if (sf_newbuf(sc, eidx) != 0) { 1580 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 1581 cur_cmp->sf_rx_status1 = 0; 1582 continue; 1583 } 1584 1585 /* AIC-6915 supports TCP/UDP checksum offload. */ 1586 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) { 1587 status2 = le32toh(cur_cmp->sf_rx_status2); 1588 /* 1589 * Sometimes AIC-6915 generates an interrupt to 1590 * warn RxGFP stall with bad checksum bit set 1591 * in status word. I'm not sure what conditioan 1592 * triggers it but recevied packet's checksum 1593 * was correct even though AIC-6915 does not 1594 * agree on this. This may be an indication of 1595 * firmware bug. To fix the issue, do not rely 1596 * on bad checksum bit in status word and let 1597 * upper layer verify integrity of received 1598 * frame. 1599 * Another nice feature of AIC-6915 is hardware 1600 * assistance of checksum calculation by 1601 * providing partial checksum value for received 1602 * frame. The partial checksum value can be used 1603 * to accelerate checksum computation for 1604 * fragmented TCP/UDP packets. Upper network 1605 * stack already takes advantage of the partial 1606 * checksum value in IP reassembly stage. But 1607 * I'm not sure the correctness of the partial 1608 * hardware checksum assistance as frequent 1609 * RxGFP stalls are seen on non-fragmented 1610 * frames. Due to the nature of the complexity 1611 * of checksum computation code in firmware it's 1612 * possible to see another bug in RxGFP so 1613 * ignore checksum assistance for fragmented 1614 * frames. This can be changed in future. 1615 */ 1616 if ((status2 & SF_RXSTAT2_FRAG) == 0) { 1617 if ((status2 & (SF_RXSTAT2_TCP | 1618 SF_RXSTAT2_UDP)) != 0) { 1619 if ((status2 & SF_RXSTAT2_CSUM_OK)) { 1620 m->m_pkthdr.csum_flags = 1621 CSUM_DATA_VALID | 1622 CSUM_PSEUDO_HDR; 1623 m->m_pkthdr.csum_data = 0xffff; 1624 } 1625 } 1626 } 1627#ifdef SF_PARTIAL_CSUM_SUPPORT 1628 else if ((status2 & SF_RXSTAT2_FRAG) != 0) { 1629 if ((status2 & (SF_RXSTAT2_TCP | 1630 SF_RXSTAT2_UDP)) != 0) { 1631 if ((status2 & SF_RXSTAT2_PCSUM_OK)) { 1632 m->m_pkthdr.csum_flags = 1633 CSUM_DATA_VALID; 1634 m->m_pkthdr.csum_data = 1635 (status & 1636 SF_RX_CMPDESC_CSUM2); 1637 } 1638 } 1639 } 1640#endif 1641 } 1642 1643 m->m_pkthdr.len = m->m_len = status & SF_RX_CMPDESC_LEN; 1644#ifndef __NO_STRICT_ALIGNMENT 1645 sf_fixup_rx(m); 1646#endif 1647 m->m_pkthdr.rcvif = ifp; 1648 1649 SF_UNLOCK(sc); 1650 (*ifp->if_input)(ifp, m); 1651 SF_LOCK(sc); 1652 rx_npkts++; 1653 1654 /* Clear completion status. */ 1655 cur_cmp->sf_rx_status1 = 0; 1656 } 1657 1658 if (prog > 0) { 1659 sc->sf_cdata.sf_rxc_cons = cons; 1660 bus_dmamap_sync(sc->sf_cdata.sf_rx_ring_tag, 1661 sc->sf_cdata.sf_rx_ring_map, 1662 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1663 bus_dmamap_sync(sc->sf_cdata.sf_rx_cring_tag, 1664 sc->sf_cdata.sf_rx_cring_map, 1665 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1666 1667 /* Update Rx completion Q1 consumer index. */ 1668 csr_write_4(sc, SF_CQ_CONSIDX, 1669 (csr_read_4(sc, SF_CQ_CONSIDX) & ~SF_CQ_CONSIDX_RXQ1) | 1670 (cons & SF_CQ_CONSIDX_RXQ1)); 1671 /* Update Rx descriptor Q1 ptr. */ 1672 csr_write_4(sc, SF_RXDQ_PTR_Q1, 1673 (csr_read_4(sc, SF_RXDQ_PTR_Q1) & ~SF_RXDQ_PRODIDX) | 1674 (eidx & SF_RXDQ_PRODIDX)); 1675 } 1676 return (rx_npkts); 1677} 1678 1679/* 1680 * Read the transmit status from the completion queue and release 1681 * mbufs. Note that the buffer descriptor index in the completion 1682 * descriptor is an offset from the start of the transmit buffer 1683 * descriptor list in bytes. This is important because the manual 1684 * gives the impression that it should match the producer/consumer 1685 * index, which is the offset in 8 byte blocks. 1686 */ 1687static void 1688sf_txeof(struct sf_softc *sc) 1689{ 1690 struct sf_txdesc *txd; 1691 struct sf_tx_rcdesc *cur_cmp; 1692 struct ifnet *ifp; 1693 uint32_t status; 1694 int cons, idx, prod; 1695 1696 SF_LOCK_ASSERT(sc); 1697 1698 ifp = sc->sf_ifp; 1699 1700 bus_dmamap_sync(sc->sf_cdata.sf_tx_cring_tag, 1701 sc->sf_cdata.sf_tx_cring_map, 1702 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1703 1704 cons = sc->sf_cdata.sf_txc_cons; 1705 prod = (csr_read_4(sc, SF_CQ_PRODIDX) & SF_TXDQ_PRODIDX_HIPRIO) >> 16; 1706 if (prod == cons) 1707 return; 1708 1709 for (; cons != prod; SF_INC(cons, SF_TX_CLIST_CNT)) { 1710 cur_cmp = &sc->sf_rdata.sf_tx_cring[cons]; 1711 status = le32toh(cur_cmp->sf_tx_status1); 1712 if (status == 0) 1713 break; 1714 switch (status & SF_TX_CMPDESC_TYPE) { 1715 case SF_TXCMPTYPE_TX: 1716 /* Tx complete entry. */ 1717 break; 1718 case SF_TXCMPTYPE_DMA: 1719 /* DMA complete entry. */ 1720 idx = status & SF_TX_CMPDESC_IDX; 1721 idx = idx / sizeof(struct sf_tx_rdesc); 1722 /* 1723 * We don't need to check Tx status here. 1724 * SF_ISR_TX_LOFIFO intr would handle this. 1725 * Note, IFCOUNTER_OPACKETS, IFCOUNTER_COLLISIONS 1726 * and IFCOUNTER_OERROR are handled in 1727 * sf_stats_update(). 1728 */ 1729 txd = &sc->sf_cdata.sf_txdesc[idx]; 1730 if (txd->tx_m != NULL) { 1731 bus_dmamap_sync(sc->sf_cdata.sf_tx_tag, 1732 txd->tx_dmamap, 1733 BUS_DMASYNC_POSTWRITE); 1734 bus_dmamap_unload(sc->sf_cdata.sf_tx_tag, 1735 txd->tx_dmamap); 1736 m_freem(txd->tx_m); 1737 txd->tx_m = NULL; 1738 } 1739 sc->sf_cdata.sf_tx_cnt -= txd->ndesc; 1740 KASSERT(sc->sf_cdata.sf_tx_cnt >= 0, 1741 ("%s: Active Tx desc counter was garbled\n", 1742 __func__)); 1743 txd->ndesc = 0; 1744 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1745 break; 1746 default: 1747 /* It should not happen. */ 1748 device_printf(sc->sf_dev, 1749 "unknown Tx completion type : 0x%08x : %d : %d\n", 1750 status, cons, prod); 1751 break; 1752 } 1753 cur_cmp->sf_tx_status1 = 0; 1754 } 1755 1756 sc->sf_cdata.sf_txc_cons = cons; 1757 bus_dmamap_sync(sc->sf_cdata.sf_tx_cring_tag, 1758 sc->sf_cdata.sf_tx_cring_map, 1759 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1760 1761 if (sc->sf_cdata.sf_tx_cnt == 0) 1762 sc->sf_watchdog_timer = 0; 1763 1764 /* Update Tx completion consumer index. */ 1765 csr_write_4(sc, SF_CQ_CONSIDX, 1766 (csr_read_4(sc, SF_CQ_CONSIDX) & 0xffff) | 1767 ((cons << 16) & 0xffff0000)); 1768} 1769 1770static void 1771sf_txthresh_adjust(struct sf_softc *sc) 1772{ 1773 uint32_t txfctl; 1774 1775 device_printf(sc->sf_dev, "Tx underrun -- "); 1776 if (sc->sf_txthresh < SF_MAX_TX_THRESHOLD) { 1777 txfctl = csr_read_4(sc, SF_TX_FRAMCTL); 1778 /* Increase Tx threshold 256 bytes. */ 1779 sc->sf_txthresh += 16; 1780 if (sc->sf_txthresh > SF_MAX_TX_THRESHOLD) 1781 sc->sf_txthresh = SF_MAX_TX_THRESHOLD; 1782 txfctl &= ~SF_TXFRMCTL_TXTHRESH; 1783 txfctl |= sc->sf_txthresh; 1784 printf("increasing Tx threshold to %d bytes\n", 1785 sc->sf_txthresh * SF_TX_THRESHOLD_UNIT); 1786 csr_write_4(sc, SF_TX_FRAMCTL, txfctl); 1787 } else 1788 printf("\n"); 1789} 1790 1791#ifdef DEVICE_POLLING 1792static int 1793sf_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1794{ 1795 struct sf_softc *sc; 1796 uint32_t status; 1797 int rx_npkts; 1798 1799 sc = ifp->if_softc; 1800 rx_npkts = 0; 1801 SF_LOCK(sc); 1802 1803 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1804 SF_UNLOCK(sc); 1805 return (rx_npkts); 1806 } 1807 1808 sc->rxcycles = count; 1809 rx_npkts = sf_rxeof(sc); 1810 sf_txeof(sc); 1811 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1812 sf_start_locked(ifp); 1813 1814 if (cmd == POLL_AND_CHECK_STATUS) { 1815 /* Reading the ISR register clears all interrrupts. */ 1816 status = csr_read_4(sc, SF_ISR); 1817 1818 if ((status & SF_ISR_ABNORMALINTR) != 0) { 1819 if ((status & SF_ISR_STATSOFLOW) != 0) 1820 sf_stats_update(sc); 1821 else if ((status & SF_ISR_TX_LOFIFO) != 0) 1822 sf_txthresh_adjust(sc); 1823 else if ((status & SF_ISR_DMAERR) != 0) { 1824 device_printf(sc->sf_dev, 1825 "DMA error, resetting\n"); 1826 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1827 sf_init_locked(sc); 1828 SF_UNLOCK(sc); 1829 return (rx_npkts); 1830 } else if ((status & SF_ISR_NO_TX_CSUM) != 0) { 1831 sc->sf_statistics.sf_tx_gfp_stall++; 1832#ifdef SF_GFP_DEBUG 1833 device_printf(sc->sf_dev, 1834 "TxGFP is not responding!\n"); 1835#endif 1836 } else if ((status & SF_ISR_RXGFP_NORESP) != 0) { 1837 sc->sf_statistics.sf_rx_gfp_stall++; 1838#ifdef SF_GFP_DEBUG 1839 device_printf(sc->sf_dev, 1840 "RxGFP is not responding!\n"); 1841#endif 1842 } 1843 } 1844 } 1845 1846 SF_UNLOCK(sc); 1847 return (rx_npkts); 1848} 1849#endif /* DEVICE_POLLING */ 1850 1851static void 1852sf_intr(void *arg) 1853{ 1854 struct sf_softc *sc; 1855 struct ifnet *ifp; 1856 uint32_t status; 1857 int cnt; 1858 1859 sc = (struct sf_softc *)arg; 1860 SF_LOCK(sc); 1861 1862 if (sc->sf_suspended != 0) 1863 goto done_locked; 1864 1865 /* Reading the ISR register clears all interrrupts. */ 1866 status = csr_read_4(sc, SF_ISR); 1867 if (status == 0 || status == 0xffffffff || 1868 (status & SF_ISR_PCIINT_ASSERTED) == 0) 1869 goto done_locked; 1870 1871 ifp = sc->sf_ifp; 1872#ifdef DEVICE_POLLING 1873 if ((ifp->if_capenable & IFCAP_POLLING) != 0) 1874 goto done_locked; 1875#endif 1876 1877 /* Disable interrupts. */ 1878 csr_write_4(sc, SF_IMR, 0x00000000); 1879 1880 for (cnt = 32; (status & SF_INTRS) != 0;) { 1881 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1882 break; 1883 if ((status & SF_ISR_RXDQ1_DMADONE) != 0) 1884 sf_rxeof(sc); 1885 1886 if ((status & (SF_ISR_TX_TXDONE | SF_ISR_TX_DMADONE | 1887 SF_ISR_TX_QUEUEDONE)) != 0) 1888 sf_txeof(sc); 1889 1890 if ((status & SF_ISR_ABNORMALINTR) != 0) { 1891 if ((status & SF_ISR_STATSOFLOW) != 0) 1892 sf_stats_update(sc); 1893 else if ((status & SF_ISR_TX_LOFIFO) != 0) 1894 sf_txthresh_adjust(sc); 1895 else if ((status & SF_ISR_DMAERR) != 0) { 1896 device_printf(sc->sf_dev, 1897 "DMA error, resetting\n"); 1898 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1899 sf_init_locked(sc); 1900 SF_UNLOCK(sc); 1901 return; 1902 } else if ((status & SF_ISR_NO_TX_CSUM) != 0) { 1903 sc->sf_statistics.sf_tx_gfp_stall++; 1904#ifdef SF_GFP_DEBUG 1905 device_printf(sc->sf_dev, 1906 "TxGFP is not responding!\n"); 1907#endif 1908 } 1909 else if ((status & SF_ISR_RXGFP_NORESP) != 0) { 1910 sc->sf_statistics.sf_rx_gfp_stall++; 1911#ifdef SF_GFP_DEBUG 1912 device_printf(sc->sf_dev, 1913 "RxGFP is not responding!\n"); 1914#endif 1915 } 1916 } 1917 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1918 sf_start_locked(ifp); 1919 if (--cnt <= 0) 1920 break; 1921 /* Reading the ISR register clears all interrrupts. */ 1922 status = csr_read_4(sc, SF_ISR); 1923 } 1924 1925 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1926 /* Re-enable interrupts. */ 1927 csr_write_4(sc, SF_IMR, SF_INTRS); 1928 } 1929 1930done_locked: 1931 SF_UNLOCK(sc); 1932} 1933 1934static void 1935sf_download_fw(struct sf_softc *sc) 1936{ 1937 uint32_t gfpinst; 1938 int i, ndx; 1939 uint8_t *p; 1940 1941 /* 1942 * A FP instruction is composed of 48bits so we have to 1943 * write it with two parts. 1944 */ 1945 p = txfwdata; 1946 ndx = 0; 1947 for (i = 0; i < sizeof(txfwdata) / SF_GFP_INST_BYTES; i++) { 1948 gfpinst = p[2] << 24 | p[3] << 16 | p[4] << 8 | p[5]; 1949 csr_write_4(sc, SF_TXGFP_MEM_BASE + ndx * 4, gfpinst); 1950 gfpinst = p[0] << 8 | p[1]; 1951 csr_write_4(sc, SF_TXGFP_MEM_BASE + (ndx + 1) * 4, gfpinst); 1952 p += SF_GFP_INST_BYTES; 1953 ndx += 2; 1954 } 1955 if (bootverbose) 1956 device_printf(sc->sf_dev, "%d Tx instructions downloaded\n", i); 1957 1958 p = rxfwdata; 1959 ndx = 0; 1960 for (i = 0; i < sizeof(rxfwdata) / SF_GFP_INST_BYTES; i++) { 1961 gfpinst = p[2] << 24 | p[3] << 16 | p[4] << 8 | p[5]; 1962 csr_write_4(sc, SF_RXGFP_MEM_BASE + (ndx * 4), gfpinst); 1963 gfpinst = p[0] << 8 | p[1]; 1964 csr_write_4(sc, SF_RXGFP_MEM_BASE + (ndx + 1) * 4, gfpinst); 1965 p += SF_GFP_INST_BYTES; 1966 ndx += 2; 1967 } 1968 if (bootverbose) 1969 device_printf(sc->sf_dev, "%d Rx instructions downloaded\n", i); 1970} 1971 1972static void 1973sf_init(void *xsc) 1974{ 1975 struct sf_softc *sc; 1976 1977 sc = (struct sf_softc *)xsc; 1978 SF_LOCK(sc); 1979 sf_init_locked(sc); 1980 SF_UNLOCK(sc); 1981} 1982 1983static void 1984sf_init_locked(struct sf_softc *sc) 1985{ 1986 struct ifnet *ifp; 1987 uint8_t eaddr[ETHER_ADDR_LEN]; 1988 bus_addr_t addr; 1989 int i; 1990 1991 SF_LOCK_ASSERT(sc); 1992 ifp = sc->sf_ifp; 1993 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1994 return; 1995 1996 sf_stop(sc); 1997 /* Reset the hardware to a known state. */ 1998 sf_reset(sc); 1999 2000 /* Init all the receive filter registers */ 2001 for (i = SF_RXFILT_PERFECT_BASE; 2002 i < (SF_RXFILT_HASH_MAX + 1); i += sizeof(uint32_t)) 2003 csr_write_4(sc, i, 0); 2004 2005 /* Empty stats counter registers. */ 2006 for (i = SF_STATS_BASE; i < (SF_STATS_END + 1); i += sizeof(uint32_t)) 2007 csr_write_4(sc, i, 0); 2008 2009 /* Init our MAC address. */ 2010 bcopy(IF_LLADDR(sc->sf_ifp), eaddr, sizeof(eaddr)); 2011 csr_write_4(sc, SF_PAR0, 2012 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 2013 csr_write_4(sc, SF_PAR1, eaddr[0] << 8 | eaddr[1]); 2014 sf_setperf(sc, 0, eaddr); 2015 2016 if (sf_init_rx_ring(sc) == ENOBUFS) { 2017 device_printf(sc->sf_dev, 2018 "initialization failed: no memory for rx buffers\n"); 2019 sf_stop(sc); 2020 return; 2021 } 2022 2023 sf_init_tx_ring(sc); 2024 2025 /* 2026 * 16 perfect address filtering. 2027 * Hash only multicast destination address, Accept matching 2028 * frames regardless of VLAN ID. 2029 */ 2030 csr_write_4(sc, SF_RXFILT, SF_PERFMODE_NORMAL | SF_HASHMODE_ANYVLAN); 2031 2032 /* 2033 * Set Rx filter. 2034 */ 2035 sf_rxfilter(sc); 2036 2037 /* Init the completion queue indexes. */ 2038 csr_write_4(sc, SF_CQ_CONSIDX, 0); 2039 csr_write_4(sc, SF_CQ_PRODIDX, 0); 2040 2041 /* Init the RX completion queue. */ 2042 addr = sc->sf_rdata.sf_rx_cring_paddr; 2043 csr_write_4(sc, SF_CQ_ADDR_HI, SF_ADDR_HI(addr)); 2044 csr_write_4(sc, SF_RXCQ_CTL_1, SF_ADDR_LO(addr) & SF_RXCQ_ADDR); 2045 if (SF_ADDR_HI(addr) != 0) 2046 SF_SETBIT(sc, SF_RXCQ_CTL_1, SF_RXCQ_USE_64BIT); 2047 /* Set RX completion queue type 2. */ 2048 SF_SETBIT(sc, SF_RXCQ_CTL_1, SF_RXCQTYPE_2); 2049 csr_write_4(sc, SF_RXCQ_CTL_2, 0); 2050 2051 /* 2052 * Init RX DMA control. 2053 * default RxHighPriority Threshold, 2054 * default RxBurstSize, 128bytes. 2055 */ 2056 SF_SETBIT(sc, SF_RXDMA_CTL, 2057 SF_RXDMA_REPORTBADPKTS | 2058 (SF_RXDMA_HIGHPRIO_THRESH << 8) | 2059 SF_RXDMA_BURST); 2060 2061 /* Init the RX buffer descriptor queue. */ 2062 addr = sc->sf_rdata.sf_rx_ring_paddr; 2063 csr_write_4(sc, SF_RXDQ_ADDR_HI, SF_ADDR_HI(addr)); 2064 csr_write_4(sc, SF_RXDQ_ADDR_Q1, SF_ADDR_LO(addr)); 2065 2066 /* Set RX queue buffer length. */ 2067 csr_write_4(sc, SF_RXDQ_CTL_1, 2068 ((MCLBYTES - sizeof(uint32_t)) << 16) | 2069 SF_RXDQCTL_64BITBADDR | SF_RXDQCTL_VARIABLE); 2070 2071 if (SF_ADDR_HI(addr) != 0) 2072 SF_SETBIT(sc, SF_RXDQ_CTL_1, SF_RXDQCTL_64BITDADDR); 2073 csr_write_4(sc, SF_RXDQ_PTR_Q1, SF_RX_DLIST_CNT - 1); 2074 csr_write_4(sc, SF_RXDQ_CTL_2, 0); 2075 2076 /* Init the TX completion queue */ 2077 addr = sc->sf_rdata.sf_tx_cring_paddr; 2078 csr_write_4(sc, SF_TXCQ_CTL, SF_ADDR_LO(addr) & SF_TXCQ_ADDR); 2079 if (SF_ADDR_HI(addr) != 0) 2080 SF_SETBIT(sc, SF_TXCQ_CTL, SF_TXCQ_USE_64BIT); 2081 2082 /* Init the TX buffer descriptor queue. */ 2083 addr = sc->sf_rdata.sf_tx_ring_paddr; 2084 csr_write_4(sc, SF_TXDQ_ADDR_HI, SF_ADDR_HI(addr)); 2085 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 0); 2086 csr_write_4(sc, SF_TXDQ_ADDR_LOPRIO, SF_ADDR_LO(addr)); 2087 csr_write_4(sc, SF_TX_FRAMCTL, 2088 SF_TXFRMCTL_CPLAFTERTX | sc->sf_txthresh); 2089 csr_write_4(sc, SF_TXDQ_CTL, 2090 SF_TXDMA_HIPRIO_THRESH << 24 | 2091 SF_TXSKIPLEN_0BYTES << 16 | 2092 SF_TXDDMA_BURST << 8 | 2093 SF_TXBUFDESC_TYPE2 | SF_TXMINSPACE_UNLIMIT); 2094 if (SF_ADDR_HI(addr) != 0) 2095 SF_SETBIT(sc, SF_TXDQ_CTL, SF_TXDQCTL_64BITADDR); 2096 2097 /* Set VLAN Type register. */ 2098 csr_write_4(sc, SF_VLANTYPE, ETHERTYPE_VLAN); 2099 2100 /* Set TxPause Timer. */ 2101 csr_write_4(sc, SF_TXPAUSETIMER, 0xffff); 2102 2103 /* Enable autopadding of short TX frames. */ 2104 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_AUTOPAD); 2105 SF_SETBIT(sc, SF_MACCFG_2, SF_MACCFG2_AUTOVLANPAD); 2106 /* Make sure to reset MAC to take changes effect. */ 2107 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 2108 DELAY(1000); 2109 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 2110 2111 /* Enable PCI bus master. */ 2112 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_PCIMEN); 2113 2114 /* Load StarFire firmware. */ 2115 sf_download_fw(sc); 2116 2117 /* Intialize interrupt moderation. */ 2118 csr_write_4(sc, SF_TIMER_CTL, SF_TIMER_IMASK_MODE | SF_TIMER_TIMES_TEN | 2119 (sc->sf_int_mod & SF_TIMER_IMASK_INTERVAL)); 2120 2121#ifdef DEVICE_POLLING 2122 /* Disable interrupts if we are polling. */ 2123 if ((ifp->if_capenable & IFCAP_POLLING) != 0) 2124 csr_write_4(sc, SF_IMR, 0x00000000); 2125 else 2126#endif 2127 /* Enable interrupts. */ 2128 csr_write_4(sc, SF_IMR, SF_INTRS); 2129 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_INTR_ENB); 2130 2131 /* Enable the RX and TX engines. */ 2132 csr_write_4(sc, SF_GEN_ETH_CTL, 2133 SF_ETHCTL_RX_ENB | SF_ETHCTL_RXDMA_ENB | 2134 SF_ETHCTL_TX_ENB | SF_ETHCTL_TXDMA_ENB); 2135 2136 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 2137 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_TXGFP_ENB); 2138 else 2139 SF_CLRBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_TXGFP_ENB); 2140 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 2141 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_RXGFP_ENB); 2142 else 2143 SF_CLRBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_RXGFP_ENB); 2144 2145 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2146 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2147 2148 sc->sf_link = 0; 2149 sf_ifmedia_upd_locked(ifp); 2150 2151 callout_reset(&sc->sf_co, hz, sf_tick, sc); 2152} 2153 2154static int 2155sf_encap(struct sf_softc *sc, struct mbuf **m_head) 2156{ 2157 struct sf_txdesc *txd; 2158 struct sf_tx_rdesc *desc; 2159 struct mbuf *m; 2160 bus_dmamap_t map; 2161 bus_dma_segment_t txsegs[SF_MAXTXSEGS]; 2162 int error, i, nsegs, prod, si; 2163 int avail, nskip; 2164 2165 SF_LOCK_ASSERT(sc); 2166 2167 m = *m_head; 2168 prod = sc->sf_cdata.sf_tx_prod; 2169 txd = &sc->sf_cdata.sf_txdesc[prod]; 2170 map = txd->tx_dmamap; 2171 error = bus_dmamap_load_mbuf_sg(sc->sf_cdata.sf_tx_tag, map, 2172 *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT); 2173 if (error == EFBIG) { 2174 m = m_collapse(*m_head, M_NOWAIT, SF_MAXTXSEGS); 2175 if (m == NULL) { 2176 m_freem(*m_head); 2177 *m_head = NULL; 2178 return (ENOBUFS); 2179 } 2180 *m_head = m; 2181 error = bus_dmamap_load_mbuf_sg(sc->sf_cdata.sf_tx_tag, 2182 map, *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT); 2183 if (error != 0) { 2184 m_freem(*m_head); 2185 *m_head = NULL; 2186 return (error); 2187 } 2188 } else if (error != 0) 2189 return (error); 2190 if (nsegs == 0) { 2191 m_freem(*m_head); 2192 *m_head = NULL; 2193 return (EIO); 2194 } 2195 2196 /* Check number of available descriptors. */ 2197 avail = (SF_TX_DLIST_CNT - 1) - sc->sf_cdata.sf_tx_cnt; 2198 if (avail < nsegs) { 2199 bus_dmamap_unload(sc->sf_cdata.sf_tx_tag, map); 2200 return (ENOBUFS); 2201 } 2202 nskip = 0; 2203 if (prod + nsegs >= SF_TX_DLIST_CNT) { 2204 nskip = SF_TX_DLIST_CNT - prod - 1; 2205 if (avail < nsegs + nskip) { 2206 bus_dmamap_unload(sc->sf_cdata.sf_tx_tag, map); 2207 return (ENOBUFS); 2208 } 2209 } 2210 2211 bus_dmamap_sync(sc->sf_cdata.sf_tx_tag, map, BUS_DMASYNC_PREWRITE); 2212 2213 si = prod; 2214 for (i = 0; i < nsegs; i++) { 2215 desc = &sc->sf_rdata.sf_tx_ring[prod]; 2216 desc->sf_tx_ctrl = htole32(SF_TX_DESC_ID | 2217 (txsegs[i].ds_len & SF_TX_DESC_FRAGLEN)); 2218 desc->sf_tx_reserved = 0; 2219 desc->sf_addr = htole64(txsegs[i].ds_addr); 2220 if (i == 0 && prod + nsegs >= SF_TX_DLIST_CNT) { 2221 /* Queue wraps! */ 2222 desc->sf_tx_ctrl |= htole32(SF_TX_DESC_END); 2223 prod = 0; 2224 } else 2225 SF_INC(prod, SF_TX_DLIST_CNT); 2226 } 2227 /* Update producer index. */ 2228 sc->sf_cdata.sf_tx_prod = prod; 2229 sc->sf_cdata.sf_tx_cnt += nsegs + nskip; 2230 2231 desc = &sc->sf_rdata.sf_tx_ring[si]; 2232 /* Check TDP/UDP checksum offload request. */ 2233 if ((m->m_pkthdr.csum_flags & SF_CSUM_FEATURES) != 0) 2234 desc->sf_tx_ctrl |= htole32(SF_TX_DESC_CALTCP); 2235 desc->sf_tx_ctrl |= 2236 htole32(SF_TX_DESC_CRCEN | SF_TX_DESC_INTR | (nsegs << 16)); 2237 2238 txd->tx_dmamap = map; 2239 txd->tx_m = m; 2240 txd->ndesc = nsegs + nskip; 2241 2242 return (0); 2243} 2244 2245static void 2246sf_start(struct ifnet *ifp) 2247{ 2248 struct sf_softc *sc; 2249 2250 sc = ifp->if_softc; 2251 SF_LOCK(sc); 2252 sf_start_locked(ifp); 2253 SF_UNLOCK(sc); 2254} 2255 2256static void 2257sf_start_locked(struct ifnet *ifp) 2258{ 2259 struct sf_softc *sc; 2260 struct mbuf *m_head; 2261 int enq; 2262 2263 sc = ifp->if_softc; 2264 SF_LOCK_ASSERT(sc); 2265 2266 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2267 IFF_DRV_RUNNING || sc->sf_link == 0) 2268 return; 2269 2270 /* 2271 * Since we don't know when descriptor wrap occurrs in advance 2272 * limit available number of active Tx descriptor counter to be 2273 * higher than maximum number of DMA segments allowed in driver. 2274 */ 2275 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2276 sc->sf_cdata.sf_tx_cnt < SF_TX_DLIST_CNT - SF_MAXTXSEGS; ) { 2277 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2278 if (m_head == NULL) 2279 break; 2280 /* 2281 * Pack the data into the transmit ring. If we 2282 * don't have room, set the OACTIVE flag and wait 2283 * for the NIC to drain the ring. 2284 */ 2285 if (sf_encap(sc, &m_head)) { 2286 if (m_head == NULL) 2287 break; 2288 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2289 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2290 break; 2291 } 2292 2293 enq++; 2294 /* 2295 * If there's a BPF listener, bounce a copy of this frame 2296 * to him. 2297 */ 2298 ETHER_BPF_MTAP(ifp, m_head); 2299 } 2300 2301 if (enq > 0) { 2302 bus_dmamap_sync(sc->sf_cdata.sf_tx_ring_tag, 2303 sc->sf_cdata.sf_tx_ring_map, 2304 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2305 /* Kick transmit. */ 2306 csr_write_4(sc, SF_TXDQ_PRODIDX, 2307 sc->sf_cdata.sf_tx_prod * (sizeof(struct sf_tx_rdesc) / 8)); 2308 2309 /* Set a timeout in case the chip goes out to lunch. */ 2310 sc->sf_watchdog_timer = 5; 2311 } 2312} 2313 2314static void 2315sf_stop(struct sf_softc *sc) 2316{ 2317 struct sf_txdesc *txd; 2318 struct sf_rxdesc *rxd; 2319 struct ifnet *ifp; 2320 int i; 2321 2322 SF_LOCK_ASSERT(sc); 2323 2324 ifp = sc->sf_ifp; 2325 2326 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2327 sc->sf_link = 0; 2328 callout_stop(&sc->sf_co); 2329 sc->sf_watchdog_timer = 0; 2330 2331 /* Reading the ISR register clears all interrrupts. */ 2332 csr_read_4(sc, SF_ISR); 2333 /* Disable further interrupts. */ 2334 csr_write_4(sc, SF_IMR, 0); 2335 2336 /* Disable Tx/Rx egine. */ 2337 csr_write_4(sc, SF_GEN_ETH_CTL, 0); 2338 2339 /* Give hardware chance to drain active DMA cycles. */ 2340 DELAY(1000); 2341 2342 csr_write_4(sc, SF_CQ_CONSIDX, 0); 2343 csr_write_4(sc, SF_CQ_PRODIDX, 0); 2344 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 0); 2345 csr_write_4(sc, SF_RXDQ_CTL_1, 0); 2346 csr_write_4(sc, SF_RXDQ_PTR_Q1, 0); 2347 csr_write_4(sc, SF_TXCQ_CTL, 0); 2348 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 0); 2349 csr_write_4(sc, SF_TXDQ_CTL, 0); 2350 2351 /* 2352 * Free RX and TX mbufs still in the queues. 2353 */ 2354 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 2355 rxd = &sc->sf_cdata.sf_rxdesc[i]; 2356 if (rxd->rx_m != NULL) { 2357 bus_dmamap_sync(sc->sf_cdata.sf_rx_tag, 2358 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 2359 bus_dmamap_unload(sc->sf_cdata.sf_rx_tag, 2360 rxd->rx_dmamap); 2361 m_freem(rxd->rx_m); 2362 rxd->rx_m = NULL; 2363 } 2364 } 2365 for (i = 0; i < SF_TX_DLIST_CNT; i++) { 2366 txd = &sc->sf_cdata.sf_txdesc[i]; 2367 if (txd->tx_m != NULL) { 2368 bus_dmamap_sync(sc->sf_cdata.sf_tx_tag, 2369 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2370 bus_dmamap_unload(sc->sf_cdata.sf_tx_tag, 2371 txd->tx_dmamap); 2372 m_freem(txd->tx_m); 2373 txd->tx_m = NULL; 2374 txd->ndesc = 0; 2375 } 2376 } 2377} 2378 2379static void 2380sf_tick(void *xsc) 2381{ 2382 struct sf_softc *sc; 2383 struct mii_data *mii; 2384 2385 sc = xsc; 2386 SF_LOCK_ASSERT(sc); 2387 mii = device_get_softc(sc->sf_miibus); 2388 mii_tick(mii); 2389 sf_stats_update(sc); 2390 sf_watchdog(sc); 2391 callout_reset(&sc->sf_co, hz, sf_tick, sc); 2392} 2393 2394/* 2395 * Note: it is important that this function not be interrupted. We 2396 * use a two-stage register access scheme: if we are interrupted in 2397 * between setting the indirect address register and reading from the 2398 * indirect data register, the contents of the address register could 2399 * be changed out from under us. 2400 */ 2401static void 2402sf_stats_update(struct sf_softc *sc) 2403{ 2404 struct ifnet *ifp; 2405 struct sf_stats now, *stats, *nstats; 2406 int i; 2407 2408 SF_LOCK_ASSERT(sc); 2409 2410 ifp = sc->sf_ifp; 2411 stats = &now; 2412 2413 stats->sf_tx_frames = 2414 csr_read_4(sc, SF_STATS_BASE + SF_STATS_TX_FRAMES); 2415 stats->sf_tx_single_colls = 2416 csr_read_4(sc, SF_STATS_BASE + SF_STATS_TX_SINGLE_COL); 2417 stats->sf_tx_multi_colls = 2418 csr_read_4(sc, SF_STATS_BASE + SF_STATS_TX_MULTI_COL); 2419 stats->sf_tx_crcerrs = 2420 csr_read_4(sc, SF_STATS_BASE + SF_STATS_TX_CRC_ERRS); 2421 stats->sf_tx_bytes = 2422 csr_read_4(sc, SF_STATS_BASE + SF_STATS_TX_BYTES); 2423 stats->sf_tx_deferred = 2424 csr_read_4(sc, SF_STATS_BASE + SF_STATS_TX_DEFERRED); 2425 stats->sf_tx_late_colls = 2426 csr_read_4(sc, SF_STATS_BASE + SF_STATS_TX_LATE_COL); 2427 stats->sf_tx_pause_frames = 2428 csr_read_4(sc, SF_STATS_BASE + SF_STATS_TX_PAUSE); 2429 stats->sf_tx_control_frames = 2430 csr_read_4(sc, SF_STATS_BASE + SF_STATS_TX_CTL_FRAME); 2431 stats->sf_tx_excess_colls = 2432 csr_read_4(sc, SF_STATS_BASE + SF_STATS_TX_EXCESS_COL); 2433 stats->sf_tx_excess_defer = 2434 csr_read_4(sc, SF_STATS_BASE + SF_STATS_TX_EXCESS_DEF); 2435 stats->sf_tx_mcast_frames = 2436 csr_read_4(sc, SF_STATS_BASE + SF_STATS_TX_MULTI); 2437 stats->sf_tx_bcast_frames = 2438 csr_read_4(sc, SF_STATS_BASE + SF_STATS_TX_BCAST); 2439 stats->sf_tx_frames_lost = 2440 csr_read_4(sc, SF_STATS_BASE + SF_STATS_TX_FRAME_LOST); 2441 stats->sf_rx_frames = 2442 csr_read_4(sc, SF_STATS_BASE + SF_STATS_RX_FRAMES); 2443 stats->sf_rx_crcerrs = 2444 csr_read_4(sc, SF_STATS_BASE + SF_STATS_RX_CRC_ERRS); 2445 stats->sf_rx_alignerrs = 2446 csr_read_4(sc, SF_STATS_BASE + SF_STATS_RX_ALIGN_ERRS); 2447 stats->sf_rx_bytes = 2448 csr_read_4(sc, SF_STATS_BASE + SF_STATS_RX_BYTES); 2449 stats->sf_rx_pause_frames = 2450 csr_read_4(sc, SF_STATS_BASE + SF_STATS_RX_PAUSE); 2451 stats->sf_rx_control_frames = 2452 csr_read_4(sc, SF_STATS_BASE + SF_STATS_RX_CTL_FRAME); 2453 stats->sf_rx_unsup_control_frames = 2454 csr_read_4(sc, SF_STATS_BASE + SF_STATS_RX_UNSUP_FRAME); 2455 stats->sf_rx_giants = 2456 csr_read_4(sc, SF_STATS_BASE + SF_STATS_RX_GIANTS); 2457 stats->sf_rx_runts = 2458 csr_read_4(sc, SF_STATS_BASE + SF_STATS_RX_RUNTS); 2459 stats->sf_rx_jabbererrs = 2460 csr_read_4(sc, SF_STATS_BASE + SF_STATS_RX_JABBER); 2461 stats->sf_rx_fragments = 2462 csr_read_4(sc, SF_STATS_BASE + SF_STATS_RX_FRAGMENTS); 2463 stats->sf_rx_pkts_64 = 2464 csr_read_4(sc, SF_STATS_BASE + SF_STATS_RX_64); 2465 stats->sf_rx_pkts_65_127 = 2466 csr_read_4(sc, SF_STATS_BASE + SF_STATS_RX_65_127); 2467 stats->sf_rx_pkts_128_255 = 2468 csr_read_4(sc, SF_STATS_BASE + SF_STATS_RX_128_255); 2469 stats->sf_rx_pkts_256_511 = 2470 csr_read_4(sc, SF_STATS_BASE + SF_STATS_RX_256_511); 2471 stats->sf_rx_pkts_512_1023 = 2472 csr_read_4(sc, SF_STATS_BASE + SF_STATS_RX_512_1023); 2473 stats->sf_rx_pkts_1024_1518 = 2474 csr_read_4(sc, SF_STATS_BASE + SF_STATS_RX_1024_1518); 2475 stats->sf_rx_frames_lost = 2476 csr_read_4(sc, SF_STATS_BASE + SF_STATS_RX_FRAME_LOST); 2477 /* Lower 16bits are valid. */ 2478 stats->sf_tx_underruns = 2479 (csr_read_4(sc, SF_STATS_BASE + SF_STATS_TX_UNDERRUN) & 0xffff); 2480 2481 /* Empty stats counter registers. */ 2482 for (i = SF_STATS_BASE; i < (SF_STATS_END + 1); i += sizeof(uint32_t)) 2483 csr_write_4(sc, i, 0); 2484 2485 if_inc_counter(ifp, IFCOUNTER_OPACKETS, (u_long)stats->sf_tx_frames); 2486 2487 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 2488 (u_long)stats->sf_tx_single_colls + 2489 (u_long)stats->sf_tx_multi_colls); 2490 2491 if_inc_counter(ifp, IFCOUNTER_OERRORS, 2492 (u_long)stats->sf_tx_excess_colls + 2493 (u_long)stats->sf_tx_excess_defer + 2494 (u_long)stats->sf_tx_frames_lost); 2495 2496 if_inc_counter(ifp, IFCOUNTER_IPACKETS, (u_long)stats->sf_rx_frames); 2497 2498 if_inc_counter(ifp, IFCOUNTER_IERRORS, 2499 (u_long)stats->sf_rx_crcerrs + 2500 (u_long)stats->sf_rx_alignerrs + 2501 (u_long)stats->sf_rx_giants + 2502 (u_long)stats->sf_rx_runts + 2503 (u_long)stats->sf_rx_jabbererrs + 2504 (u_long)stats->sf_rx_frames_lost); 2505 2506 nstats = &sc->sf_statistics; 2507 2508 nstats->sf_tx_frames += stats->sf_tx_frames; 2509 nstats->sf_tx_single_colls += stats->sf_tx_single_colls; 2510 nstats->sf_tx_multi_colls += stats->sf_tx_multi_colls; 2511 nstats->sf_tx_crcerrs += stats->sf_tx_crcerrs; 2512 nstats->sf_tx_bytes += stats->sf_tx_bytes; 2513 nstats->sf_tx_deferred += stats->sf_tx_deferred; 2514 nstats->sf_tx_late_colls += stats->sf_tx_late_colls; 2515 nstats->sf_tx_pause_frames += stats->sf_tx_pause_frames; 2516 nstats->sf_tx_control_frames += stats->sf_tx_control_frames; 2517 nstats->sf_tx_excess_colls += stats->sf_tx_excess_colls; 2518 nstats->sf_tx_excess_defer += stats->sf_tx_excess_defer; 2519 nstats->sf_tx_mcast_frames += stats->sf_tx_mcast_frames; 2520 nstats->sf_tx_bcast_frames += stats->sf_tx_bcast_frames; 2521 nstats->sf_tx_frames_lost += stats->sf_tx_frames_lost; 2522 nstats->sf_rx_frames += stats->sf_rx_frames; 2523 nstats->sf_rx_crcerrs += stats->sf_rx_crcerrs; 2524 nstats->sf_rx_alignerrs += stats->sf_rx_alignerrs; 2525 nstats->sf_rx_bytes += stats->sf_rx_bytes; 2526 nstats->sf_rx_pause_frames += stats->sf_rx_pause_frames; 2527 nstats->sf_rx_control_frames += stats->sf_rx_control_frames; 2528 nstats->sf_rx_unsup_control_frames += stats->sf_rx_unsup_control_frames; 2529 nstats->sf_rx_giants += stats->sf_rx_giants; 2530 nstats->sf_rx_runts += stats->sf_rx_runts; 2531 nstats->sf_rx_jabbererrs += stats->sf_rx_jabbererrs; 2532 nstats->sf_rx_fragments += stats->sf_rx_fragments; 2533 nstats->sf_rx_pkts_64 += stats->sf_rx_pkts_64; 2534 nstats->sf_rx_pkts_65_127 += stats->sf_rx_pkts_65_127; 2535 nstats->sf_rx_pkts_128_255 += stats->sf_rx_pkts_128_255; 2536 nstats->sf_rx_pkts_256_511 += stats->sf_rx_pkts_256_511; 2537 nstats->sf_rx_pkts_512_1023 += stats->sf_rx_pkts_512_1023; 2538 nstats->sf_rx_pkts_1024_1518 += stats->sf_rx_pkts_1024_1518; 2539 nstats->sf_rx_frames_lost += stats->sf_rx_frames_lost; 2540 nstats->sf_tx_underruns += stats->sf_tx_underruns; 2541} 2542 2543static void 2544sf_watchdog(struct sf_softc *sc) 2545{ 2546 struct ifnet *ifp; 2547 2548 SF_LOCK_ASSERT(sc); 2549 2550 if (sc->sf_watchdog_timer == 0 || --sc->sf_watchdog_timer) 2551 return; 2552 2553 ifp = sc->sf_ifp; 2554 2555 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 2556 if (sc->sf_link == 0) { 2557 if (bootverbose) 2558 if_printf(sc->sf_ifp, "watchdog timeout " 2559 "(missed link)\n"); 2560 } else 2561 if_printf(ifp, "watchdog timeout, %d Tx descs are active\n", 2562 sc->sf_cdata.sf_tx_cnt); 2563 2564 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2565 sf_init_locked(sc); 2566 2567 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2568 sf_start_locked(ifp); 2569} 2570 2571static int 2572sf_shutdown(device_t dev) 2573{ 2574 struct sf_softc *sc; 2575 2576 sc = device_get_softc(dev); 2577 2578 SF_LOCK(sc); 2579 sf_stop(sc); 2580 SF_UNLOCK(sc); 2581 2582 return (0); 2583} 2584 2585static int 2586sf_suspend(device_t dev) 2587{ 2588 struct sf_softc *sc; 2589 2590 sc = device_get_softc(dev); 2591 2592 SF_LOCK(sc); 2593 sf_stop(sc); 2594 sc->sf_suspended = 1; 2595 bus_generic_suspend(dev); 2596 SF_UNLOCK(sc); 2597 2598 return (0); 2599} 2600 2601static int 2602sf_resume(device_t dev) 2603{ 2604 struct sf_softc *sc; 2605 struct ifnet *ifp; 2606 2607 sc = device_get_softc(dev); 2608 2609 SF_LOCK(sc); 2610 bus_generic_resume(dev); 2611 ifp = sc->sf_ifp; 2612 if ((ifp->if_flags & IFF_UP) != 0) 2613 sf_init_locked(sc); 2614 2615 sc->sf_suspended = 0; 2616 SF_UNLOCK(sc); 2617 2618 return (0); 2619} 2620 2621static int 2622sf_sysctl_stats(SYSCTL_HANDLER_ARGS) 2623{ 2624 struct sf_softc *sc; 2625 struct sf_stats *stats; 2626 int error; 2627 int result; 2628 2629 result = -1; 2630 error = sysctl_handle_int(oidp, &result, 0, req); 2631 2632 if (error != 0 || req->newptr == NULL) 2633 return (error); 2634 2635 if (result != 1) 2636 return (error); 2637 2638 sc = (struct sf_softc *)arg1; 2639 stats = &sc->sf_statistics; 2640 2641 printf("%s statistics:\n", device_get_nameunit(sc->sf_dev)); 2642 printf("Transmit good frames : %ju\n", 2643 (uintmax_t)stats->sf_tx_frames); 2644 printf("Transmit good octets : %ju\n", 2645 (uintmax_t)stats->sf_tx_bytes); 2646 printf("Transmit single collisions : %u\n", 2647 stats->sf_tx_single_colls); 2648 printf("Transmit multiple collisions : %u\n", 2649 stats->sf_tx_multi_colls); 2650 printf("Transmit late collisions : %u\n", 2651 stats->sf_tx_late_colls); 2652 printf("Transmit abort due to excessive collisions : %u\n", 2653 stats->sf_tx_excess_colls); 2654 printf("Transmit CRC errors : %u\n", 2655 stats->sf_tx_crcerrs); 2656 printf("Transmit deferrals : %u\n", 2657 stats->sf_tx_deferred); 2658 printf("Transmit abort due to excessive deferrals : %u\n", 2659 stats->sf_tx_excess_defer); 2660 printf("Transmit pause control frames : %u\n", 2661 stats->sf_tx_pause_frames); 2662 printf("Transmit control frames : %u\n", 2663 stats->sf_tx_control_frames); 2664 printf("Transmit good multicast frames : %u\n", 2665 stats->sf_tx_mcast_frames); 2666 printf("Transmit good broadcast frames : %u\n", 2667 stats->sf_tx_bcast_frames); 2668 printf("Transmit frames lost due to internal transmit errors : %u\n", 2669 stats->sf_tx_frames_lost); 2670 printf("Transmit FIFO underflows : %u\n", 2671 stats->sf_tx_underruns); 2672 printf("Transmit GFP stalls : %u\n", stats->sf_tx_gfp_stall); 2673 printf("Receive good frames : %ju\n", 2674 (uint64_t)stats->sf_rx_frames); 2675 printf("Receive good octets : %ju\n", 2676 (uint64_t)stats->sf_rx_bytes); 2677 printf("Receive CRC errors : %u\n", 2678 stats->sf_rx_crcerrs); 2679 printf("Receive alignment errors : %u\n", 2680 stats->sf_rx_alignerrs); 2681 printf("Receive pause frames : %u\n", 2682 stats->sf_rx_pause_frames); 2683 printf("Receive control frames : %u\n", 2684 stats->sf_rx_control_frames); 2685 printf("Receive control frames with unsupported opcode : %u\n", 2686 stats->sf_rx_unsup_control_frames); 2687 printf("Receive frames too long : %u\n", 2688 stats->sf_rx_giants); 2689 printf("Receive frames too short : %u\n", 2690 stats->sf_rx_runts); 2691 printf("Receive frames jabber errors : %u\n", 2692 stats->sf_rx_jabbererrs); 2693 printf("Receive frames fragments : %u\n", 2694 stats->sf_rx_fragments); 2695 printf("Receive packets 64 bytes : %ju\n", 2696 (uint64_t)stats->sf_rx_pkts_64); 2697 printf("Receive packets 65 to 127 bytes : %ju\n", 2698 (uint64_t)stats->sf_rx_pkts_65_127); 2699 printf("Receive packets 128 to 255 bytes : %ju\n", 2700 (uint64_t)stats->sf_rx_pkts_128_255); 2701 printf("Receive packets 256 to 511 bytes : %ju\n", 2702 (uint64_t)stats->sf_rx_pkts_256_511); 2703 printf("Receive packets 512 to 1023 bytes : %ju\n", 2704 (uint64_t)stats->sf_rx_pkts_512_1023); 2705 printf("Receive packets 1024 to 1518 bytes : %ju\n", 2706 (uint64_t)stats->sf_rx_pkts_1024_1518); 2707 printf("Receive frames lost due to internal receive errors : %u\n", 2708 stats->sf_rx_frames_lost); 2709 printf("Receive GFP stalls : %u\n", stats->sf_rx_gfp_stall); 2710 2711 return (error); 2712} 2713 2714static int 2715sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 2716{ 2717 int error, value; 2718 2719 if (!arg1) 2720 return (EINVAL); 2721 value = *(int *)arg1; 2722 error = sysctl_handle_int(oidp, &value, 0, req); 2723 if (error || !req->newptr) 2724 return (error); 2725 if (value < low || value > high) 2726 return (EINVAL); 2727 *(int *)arg1 = value; 2728 2729 return (0); 2730} 2731 2732static int 2733sysctl_hw_sf_int_mod(SYSCTL_HANDLER_ARGS) 2734{ 2735 2736 return (sysctl_int_range(oidp, arg1, arg2, req, SF_IM_MIN, SF_IM_MAX)); 2737} 2738