if_sf.c revision 84147
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/dev/sf/if_sf.c 84147 2001-09-29 19:28:31Z jlemon $ 33 */ 34 35/* 36 * Adaptec AIC-6915 "Starfire" PCI fast ethernet driver for FreeBSD. 37 * Programming manual is available from: 38 * ftp.adaptec.com:/pub/BBS/userguides/aic6915_pg.pdf. 39 * 40 * Written by Bill Paul <wpaul@ctr.columbia.edu> 41 * Department of Electical Engineering 42 * Columbia University, New York City 43 */ 44 45/* 46 * The Adaptec AIC-6915 "Starfire" is a 64-bit 10/100 PCI ethernet 47 * controller designed with flexibility and reducing CPU load in mind. 48 * The Starfire offers high and low priority buffer queues, a 49 * producer/consumer index mechanism and several different buffer 50 * queue and completion queue descriptor types. Any one of a number 51 * of different driver designs can be used, depending on system and 52 * OS requirements. This driver makes use of type0 transmit frame 53 * descriptors (since BSD fragments packets across an mbuf chain) 54 * and two RX buffer queues prioritized on size (one queue for small 55 * frames that will fit into a single mbuf, another with full size 56 * mbuf clusters for everything else). The producer/consumer indexes 57 * and completion queues are also used. 58 * 59 * One downside to the Starfire has to do with alignment: buffer 60 * queues must be aligned on 256-byte boundaries, and receive buffers 61 * must be aligned on longword boundaries. The receive buffer alignment 62 * causes problems on the Alpha platform, where the packet payload 63 * should be longword aligned. There is no simple way around this. 64 * 65 * For receive filtering, the Starfire offers 16 perfect filter slots 66 * and a 512-bit hash table. 67 * 68 * The Starfire has no internal transceiver, relying instead on an 69 * external MII-based transceiver. Accessing registers on external 70 * PHYs is done through a special register map rather than with the 71 * usual bitbang MDIO method. 72 * 73 * Acesssing the registers on the Starfire is a little tricky. The 74 * Starfire has a 512K internal register space. When programmed for 75 * PCI memory mapped mode, the entire register space can be accessed 76 * directly. However in I/O space mode, only 256 bytes are directly 77 * mapped into PCI I/O space. The other registers can be accessed 78 * indirectly using the SF_INDIRECTIO_ADDR and SF_INDIRECTIO_DATA 79 * registers inside the 256-byte I/O window. 80 */ 81 82#include <sys/param.h> 83#include <sys/systm.h> 84#include <sys/sockio.h> 85#include <sys/mbuf.h> 86#include <sys/malloc.h> 87#include <sys/kernel.h> 88#include <sys/socket.h> 89 90#include <net/if.h> 91#include <net/if_arp.h> 92#include <net/ethernet.h> 93#include <net/if_dl.h> 94#include <net/if_media.h> 95 96#include <net/bpf.h> 97 98#include <vm/vm.h> /* for vtophys */ 99#include <vm/pmap.h> /* for vtophys */ 100#include <machine/bus_pio.h> 101#include <machine/bus_memio.h> 102#include <machine/bus.h> 103#include <machine/resource.h> 104#include <sys/bus.h> 105#include <sys/rman.h> 106 107#include <dev/mii/mii.h> 108#include <dev/mii/miivar.h> 109 110/* "controller miibus0" required. See GENERIC if you get errors here. */ 111#include "miibus_if.h" 112 113#include <pci/pcireg.h> 114#include <pci/pcivar.h> 115 116#define SF_USEIOSPACE 117 118#include <pci/if_sfreg.h> 119 120MODULE_DEPEND(sf, miibus, 1, 1, 1); 121 122#ifndef lint 123static const char rcsid[] = 124 "$FreeBSD: head/sys/dev/sf/if_sf.c 84147 2001-09-29 19:28:31Z jlemon $"; 125#endif 126 127static struct sf_type sf_devs[] = { 128 { AD_VENDORID, AD_DEVICEID_STARFIRE, 129 "Adaptec AIC-6915 10/100BaseTX" }, 130 { 0, 0, NULL } 131}; 132 133static int sf_probe __P((device_t)); 134static int sf_attach __P((device_t)); 135static int sf_detach __P((device_t)); 136static void sf_intr __P((void *)); 137static void sf_stats_update __P((void *)); 138static void sf_rxeof __P((struct sf_softc *)); 139static void sf_txeof __P((struct sf_softc *)); 140static int sf_encap __P((struct sf_softc *, 141 struct sf_tx_bufdesc_type0 *, 142 struct mbuf *)); 143static void sf_start __P((struct ifnet *)); 144static int sf_ioctl __P((struct ifnet *, u_long, caddr_t)); 145static void sf_init __P((void *)); 146static void sf_stop __P((struct sf_softc *)); 147static void sf_watchdog __P((struct ifnet *)); 148static void sf_shutdown __P((device_t)); 149static int sf_ifmedia_upd __P((struct ifnet *)); 150static void sf_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 151static void sf_reset __P((struct sf_softc *)); 152static int sf_init_rx_ring __P((struct sf_softc *)); 153static void sf_init_tx_ring __P((struct sf_softc *)); 154static int sf_newbuf __P((struct sf_softc *, 155 struct sf_rx_bufdesc_type0 *, 156 struct mbuf *)); 157static void sf_setmulti __P((struct sf_softc *)); 158static int sf_setperf __P((struct sf_softc *, int, caddr_t)); 159static int sf_sethash __P((struct sf_softc *, caddr_t, int)); 160#ifdef notdef 161static int sf_setvlan __P((struct sf_softc *, int, u_int32_t)); 162#endif 163 164static u_int8_t sf_read_eeprom __P((struct sf_softc *, int)); 165static u_int32_t sf_calchash __P((caddr_t)); 166 167static int sf_miibus_readreg __P((device_t, int, int)); 168static int sf_miibus_writereg __P((device_t, int, int, int)); 169static void sf_miibus_statchg __P((device_t)); 170 171static u_int32_t csr_read_4 __P((struct sf_softc *, int)); 172static void csr_write_4 __P((struct sf_softc *, int, u_int32_t)); 173static void sf_txthresh_adjust __P((struct sf_softc *)); 174 175#ifdef SF_USEIOSPACE 176#define SF_RES SYS_RES_IOPORT 177#define SF_RID SF_PCI_LOIO 178#else 179#define SF_RES SYS_RES_MEMORY 180#define SF_RID SF_PCI_LOMEM 181#endif 182 183static device_method_t sf_methods[] = { 184 /* Device interface */ 185 DEVMETHOD(device_probe, sf_probe), 186 DEVMETHOD(device_attach, sf_attach), 187 DEVMETHOD(device_detach, sf_detach), 188 DEVMETHOD(device_shutdown, sf_shutdown), 189 190 /* bus interface */ 191 DEVMETHOD(bus_print_child, bus_generic_print_child), 192 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 193 194 /* MII interface */ 195 DEVMETHOD(miibus_readreg, sf_miibus_readreg), 196 DEVMETHOD(miibus_writereg, sf_miibus_writereg), 197 DEVMETHOD(miibus_statchg, sf_miibus_statchg), 198 199 { 0, 0 } 200}; 201 202static driver_t sf_driver = { 203 "sf", 204 sf_methods, 205 sizeof(struct sf_softc), 206}; 207 208static devclass_t sf_devclass; 209 210DRIVER_MODULE(if_sf, pci, sf_driver, sf_devclass, 0, 0); 211DRIVER_MODULE(miibus, sf, miibus_driver, miibus_devclass, 0, 0); 212 213#define SF_SETBIT(sc, reg, x) \ 214 csr_write_4(sc, reg, csr_read_4(sc, reg) | x) 215 216#define SF_CLRBIT(sc, reg, x) \ 217 csr_write_4(sc, reg, csr_read_4(sc, reg) & ~x) 218 219static u_int32_t csr_read_4(sc, reg) 220 struct sf_softc *sc; 221 int reg; 222{ 223 u_int32_t val; 224 225#ifdef SF_USEIOSPACE 226 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); 227 val = CSR_READ_4(sc, SF_INDIRECTIO_DATA); 228#else 229 val = CSR_READ_4(sc, (reg + SF_RMAP_INTREG_BASE)); 230#endif 231 232 return(val); 233} 234 235static u_int8_t sf_read_eeprom(sc, reg) 236 struct sf_softc *sc; 237 int reg; 238{ 239 u_int8_t val; 240 241 val = (csr_read_4(sc, SF_EEADDR_BASE + 242 (reg & 0xFFFFFFFC)) >> (8 * (reg & 3))) & 0xFF; 243 244 return(val); 245} 246 247static void csr_write_4(sc, reg, val) 248 struct sf_softc *sc; 249 int reg; 250 u_int32_t val; 251{ 252#ifdef SF_USEIOSPACE 253 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); 254 CSR_WRITE_4(sc, SF_INDIRECTIO_DATA, val); 255#else 256 CSR_WRITE_4(sc, (reg + SF_RMAP_INTREG_BASE), val); 257#endif 258 return; 259} 260 261static u_int32_t sf_calchash(addr) 262 caddr_t addr; 263{ 264 u_int32_t crc, carry; 265 int i, j; 266 u_int8_t c; 267 268 /* Compute CRC for the address value. */ 269 crc = 0xFFFFFFFF; /* initial value */ 270 271 for (i = 0; i < 6; i++) { 272 c = *(addr + i); 273 for (j = 0; j < 8; j++) { 274 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 275 crc <<= 1; 276 c >>= 1; 277 if (carry) 278 crc = (crc ^ 0x04c11db6) | carry; 279 } 280 } 281 282 /* return the filter bit position */ 283 return(crc >> 23 & 0x1FF); 284} 285 286/* 287 * Copy the address 'mac' into the perfect RX filter entry at 288 * offset 'idx.' The perfect filter only has 16 entries so do 289 * some sanity tests. 290 */ 291static int sf_setperf(sc, idx, mac) 292 struct sf_softc *sc; 293 int idx; 294 caddr_t mac; 295{ 296 u_int16_t *p; 297 298 if (idx < 0 || idx > SF_RXFILT_PERFECT_CNT) 299 return(EINVAL); 300 301 if (mac == NULL) 302 return(EINVAL); 303 304 p = (u_int16_t *)mac; 305 306 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 307 (idx * SF_RXFILT_PERFECT_SKIP), htons(p[2])); 308 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 309 (idx * SF_RXFILT_PERFECT_SKIP) + 4, htons(p[1])); 310 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 311 (idx * SF_RXFILT_PERFECT_SKIP) + 8, htons(p[0])); 312 313 return(0); 314} 315 316/* 317 * Set the bit in the 512-bit hash table that corresponds to the 318 * specified mac address 'mac.' If 'prio' is nonzero, update the 319 * priority hash table instead of the filter hash table. 320 */ 321static int sf_sethash(sc, mac, prio) 322 struct sf_softc *sc; 323 caddr_t mac; 324 int prio; 325{ 326 u_int32_t h = 0; 327 328 if (mac == NULL) 329 return(EINVAL); 330 331 h = sf_calchash(mac); 332 333 if (prio) { 334 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_PRIOOFF + 335 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); 336 } else { 337 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_ADDROFF + 338 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); 339 } 340 341 return(0); 342} 343 344#ifdef notdef 345/* 346 * Set a VLAN tag in the receive filter. 347 */ 348static int sf_setvlan(sc, idx, vlan) 349 struct sf_softc *sc; 350 int idx; 351 u_int32_t vlan; 352{ 353 if (idx < 0 || idx >> SF_RXFILT_HASH_CNT) 354 return(EINVAL); 355 356 csr_write_4(sc, SF_RXFILT_HASH_BASE + 357 (idx * SF_RXFILT_HASH_SKIP) + SF_RXFILT_HASH_VLANOFF, vlan); 358 359 return(0); 360} 361#endif 362 363static int sf_miibus_readreg(dev, phy, reg) 364 device_t dev; 365 int phy, reg; 366{ 367 struct sf_softc *sc; 368 int i; 369 u_int32_t val = 0; 370 371 sc = device_get_softc(dev); 372 373 for (i = 0; i < SF_TIMEOUT; i++) { 374 val = csr_read_4(sc, SF_PHY_REG(phy, reg)); 375 if (val & SF_MII_DATAVALID) 376 break; 377 } 378 379 if (i == SF_TIMEOUT) 380 return(0); 381 382 if ((val & 0x0000FFFF) == 0xFFFF) 383 return(0); 384 385 return(val & 0x0000FFFF); 386} 387 388static int sf_miibus_writereg(dev, phy, reg, val) 389 device_t dev; 390 int phy, reg, val; 391{ 392 struct sf_softc *sc; 393 int i; 394 int busy; 395 396 sc = device_get_softc(dev); 397 398 csr_write_4(sc, SF_PHY_REG(phy, reg), val); 399 400 for (i = 0; i < SF_TIMEOUT; i++) { 401 busy = csr_read_4(sc, SF_PHY_REG(phy, reg)); 402 if (!(busy & SF_MII_BUSY)) 403 break; 404 } 405 406 return(0); 407} 408 409static void sf_miibus_statchg(dev) 410 device_t dev; 411{ 412 struct sf_softc *sc; 413 struct mii_data *mii; 414 415 sc = device_get_softc(dev); 416 mii = device_get_softc(sc->sf_miibus); 417 418 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 419 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 420 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_FDX); 421 } else { 422 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 423 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_HDX); 424 } 425 426 return; 427} 428 429static void sf_setmulti(sc) 430 struct sf_softc *sc; 431{ 432 struct ifnet *ifp; 433 int i; 434 struct ifmultiaddr *ifma; 435 u_int8_t dummy[] = { 0, 0, 0, 0, 0, 0 }; 436 437 ifp = &sc->arpcom.ac_if; 438 439 /* First zot all the existing filters. */ 440 for (i = 1; i < SF_RXFILT_PERFECT_CNT; i++) 441 sf_setperf(sc, i, (char *)&dummy); 442 for (i = SF_RXFILT_HASH_BASE; 443 i < (SF_RXFILT_HASH_MAX + 1); i += 4) 444 csr_write_4(sc, i, 0); 445 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI); 446 447 /* Now program new ones. */ 448 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 449 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI); 450 } else { 451 i = 1; 452 TAILQ_FOREACH_REVERSE(ifma, &ifp->if_multiaddrs, ifmultihead, ifma_link) { 453 if (ifma->ifma_addr->sa_family != AF_LINK) 454 continue; 455 /* 456 * Program the first 15 multicast groups 457 * into the perfect filter. For all others, 458 * use the hash table. 459 */ 460 if (i < SF_RXFILT_PERFECT_CNT) { 461 sf_setperf(sc, i, 462 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 463 i++; 464 continue; 465 } 466 467 sf_sethash(sc, 468 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 0); 469 } 470 } 471 472 return; 473} 474 475/* 476 * Set media options. 477 */ 478static int sf_ifmedia_upd(ifp) 479 struct ifnet *ifp; 480{ 481 struct sf_softc *sc; 482 struct mii_data *mii; 483 484 sc = ifp->if_softc; 485 mii = device_get_softc(sc->sf_miibus); 486 sc->sf_link = 0; 487 if (mii->mii_instance) { 488 struct mii_softc *miisc; 489 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 490 mii_phy_reset(miisc); 491 } 492 mii_mediachg(mii); 493 494 return(0); 495} 496 497/* 498 * Report current media status. 499 */ 500static void sf_ifmedia_sts(ifp, ifmr) 501 struct ifnet *ifp; 502 struct ifmediareq *ifmr; 503{ 504 struct sf_softc *sc; 505 struct mii_data *mii; 506 507 sc = ifp->if_softc; 508 mii = device_get_softc(sc->sf_miibus); 509 510 mii_pollstat(mii); 511 ifmr->ifm_active = mii->mii_media_active; 512 ifmr->ifm_status = mii->mii_media_status; 513 514 return; 515} 516 517static int sf_ioctl(ifp, command, data) 518 struct ifnet *ifp; 519 u_long command; 520 caddr_t data; 521{ 522 struct sf_softc *sc = ifp->if_softc; 523 struct ifreq *ifr = (struct ifreq *) data; 524 struct mii_data *mii; 525 int error = 0; 526 527 SF_LOCK(sc); 528 529 switch(command) { 530 case SIOCSIFADDR: 531 case SIOCGIFADDR: 532 case SIOCSIFMTU: 533 error = ether_ioctl(ifp, command, data); 534 break; 535 case SIOCSIFFLAGS: 536 if (ifp->if_flags & IFF_UP) { 537 if (ifp->if_flags & IFF_RUNNING && 538 ifp->if_flags & IFF_PROMISC && 539 !(sc->sf_if_flags & IFF_PROMISC)) { 540 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 541 } else if (ifp->if_flags & IFF_RUNNING && 542 !(ifp->if_flags & IFF_PROMISC) && 543 sc->sf_if_flags & IFF_PROMISC) { 544 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 545 } else if (!(ifp->if_flags & IFF_RUNNING)) 546 sf_init(sc); 547 } else { 548 if (ifp->if_flags & IFF_RUNNING) 549 sf_stop(sc); 550 } 551 sc->sf_if_flags = ifp->if_flags; 552 error = 0; 553 break; 554 case SIOCADDMULTI: 555 case SIOCDELMULTI: 556 sf_setmulti(sc); 557 error = 0; 558 break; 559 case SIOCGIFMEDIA: 560 case SIOCSIFMEDIA: 561 mii = device_get_softc(sc->sf_miibus); 562 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 563 break; 564 default: 565 error = EINVAL; 566 break; 567 } 568 569 SF_UNLOCK(sc); 570 571 return(error); 572} 573 574static void sf_reset(sc) 575 struct sf_softc *sc; 576{ 577 register int i; 578 579 csr_write_4(sc, SF_GEN_ETH_CTL, 0); 580 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 581 DELAY(1000); 582 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 583 584 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_RESET); 585 586 for (i = 0; i < SF_TIMEOUT; i++) { 587 DELAY(10); 588 if (!(csr_read_4(sc, SF_PCI_DEVCFG) & SF_PCIDEVCFG_RESET)) 589 break; 590 } 591 592 if (i == SF_TIMEOUT) 593 printf("sf%d: reset never completed!\n", sc->sf_unit); 594 595 /* Wait a little while for the chip to get its brains in order. */ 596 DELAY(1000); 597 return; 598} 599 600/* 601 * Probe for an Adaptec AIC-6915 chip. Check the PCI vendor and device 602 * IDs against our list and return a device name if we find a match. 603 * We also check the subsystem ID so that we can identify exactly which 604 * NIC has been found, if possible. 605 */ 606static int sf_probe(dev) 607 device_t dev; 608{ 609 struct sf_type *t; 610 611 t = sf_devs; 612 613 while(t->sf_name != NULL) { 614 if ((pci_get_vendor(dev) == t->sf_vid) && 615 (pci_get_device(dev) == t->sf_did)) { 616 switch((pci_read_config(dev, 617 SF_PCI_SUBVEN_ID, 4) >> 16) & 0xFFFF) { 618 case AD_SUBSYSID_62011_REV0: 619 case AD_SUBSYSID_62011_REV1: 620 device_set_desc(dev, 621 "Adaptec ANA-62011 10/100BaseTX"); 622 return(0); 623 break; 624 case AD_SUBSYSID_62022: 625 device_set_desc(dev, 626 "Adaptec ANA-62022 10/100BaseTX"); 627 return(0); 628 break; 629 case AD_SUBSYSID_62044_REV0: 630 case AD_SUBSYSID_62044_REV1: 631 device_set_desc(dev, 632 "Adaptec ANA-62044 10/100BaseTX"); 633 return(0); 634 break; 635 case AD_SUBSYSID_62020: 636 device_set_desc(dev, 637 "Adaptec ANA-62020 10/100BaseFX"); 638 return(0); 639 break; 640 case AD_SUBSYSID_69011: 641 device_set_desc(dev, 642 "Adaptec ANA-69011 10/100BaseTX"); 643 return(0); 644 break; 645 default: 646 device_set_desc(dev, t->sf_name); 647 return(0); 648 break; 649 } 650 } 651 t++; 652 } 653 654 return(ENXIO); 655} 656 657/* 658 * Attach the interface. Allocate softc structures, do ifmedia 659 * setup and ethernet/BPF attach. 660 */ 661static int sf_attach(dev) 662 device_t dev; 663{ 664 int i; 665 u_int32_t command; 666 struct sf_softc *sc; 667 struct ifnet *ifp; 668 int unit, rid, error = 0; 669 670 sc = device_get_softc(dev); 671 unit = device_get_unit(dev); 672 bzero(sc, sizeof(struct sf_softc)); 673 674 mtx_init(&sc->sf_mtx, device_get_nameunit(dev), MTX_DEF | MTX_RECURSE); 675 SF_LOCK(sc); 676 /* 677 * Handle power management nonsense. 678 */ 679 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 680 u_int32_t iobase, membase, irq; 681 682 /* Save important PCI config data. */ 683 iobase = pci_read_config(dev, SF_PCI_LOIO, 4); 684 membase = pci_read_config(dev, SF_PCI_LOMEM, 4); 685 irq = pci_read_config(dev, SF_PCI_INTLINE, 4); 686 687 /* Reset the power state. */ 688 printf("sf%d: chip is in D%d power mode " 689 "-- setting to D0\n", unit, 690 pci_get_powerstate(dev)); 691 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 692 693 /* Restore PCI config data. */ 694 pci_write_config(dev, SF_PCI_LOIO, iobase, 4); 695 pci_write_config(dev, SF_PCI_LOMEM, membase, 4); 696 pci_write_config(dev, SF_PCI_INTLINE, irq, 4); 697 } 698 699 /* 700 * Map control/status registers. 701 */ 702 pci_enable_busmaster(dev); 703 pci_enable_io(dev, SYS_RES_IOPORT); 704 pci_enable_io(dev, SYS_RES_MEMORY); 705 command = pci_read_config(dev, PCIR_COMMAND, 4); 706 707#ifdef SF_USEIOSPACE 708 if (!(command & PCIM_CMD_PORTEN)) { 709 printf("sf%d: failed to enable I/O ports!\n", unit); 710 error = ENXIO; 711 goto fail; 712 } 713#else 714 if (!(command & PCIM_CMD_MEMEN)) { 715 printf("sf%d: failed to enable memory mapping!\n", unit); 716 error = ENXIO; 717 goto fail; 718 } 719#endif 720 721 rid = SF_RID; 722 sc->sf_res = bus_alloc_resource(dev, SF_RES, &rid, 723 0, ~0, 1, RF_ACTIVE); 724 725 if (sc->sf_res == NULL) { 726 printf ("sf%d: couldn't map ports\n", unit); 727 error = ENXIO; 728 goto fail; 729 } 730 731 sc->sf_btag = rman_get_bustag(sc->sf_res); 732 sc->sf_bhandle = rman_get_bushandle(sc->sf_res); 733 734 /* Allocate interrupt */ 735 rid = 0; 736 sc->sf_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 737 RF_SHAREABLE | RF_ACTIVE); 738 739 if (sc->sf_irq == NULL) { 740 printf("sf%d: couldn't map interrupt\n", unit); 741 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 742 error = ENXIO; 743 goto fail; 744 } 745 746 error = bus_setup_intr(dev, sc->sf_irq, INTR_TYPE_NET, 747 sf_intr, sc, &sc->sf_intrhand); 748 749 if (error) { 750 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_res); 751 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 752 printf("sf%d: couldn't set up irq\n", unit); 753 goto fail; 754 } 755 756 callout_handle_init(&sc->sf_stat_ch); 757 /* Reset the adapter. */ 758 sf_reset(sc); 759 760 /* 761 * Get station address from the EEPROM. 762 */ 763 for (i = 0; i < ETHER_ADDR_LEN; i++) 764 sc->arpcom.ac_enaddr[i] = 765 sf_read_eeprom(sc, SF_EE_NODEADDR + ETHER_ADDR_LEN - i); 766 767 /* 768 * An Adaptec chip was detected. Inform the world. 769 */ 770 printf("sf%d: Ethernet address: %6D\n", unit, 771 sc->arpcom.ac_enaddr, ":"); 772 773 sc->sf_unit = unit; 774 775 /* Allocate the descriptor queues. */ 776 sc->sf_ldata = contigmalloc(sizeof(struct sf_list_data), M_DEVBUF, 777 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 778 779 if (sc->sf_ldata == NULL) { 780 printf("sf%d: no memory for list buffers!\n", unit); 781 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand); 782 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq); 783 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 784 error = ENXIO; 785 goto fail; 786 } 787 788 bzero(sc->sf_ldata, sizeof(struct sf_list_data)); 789 790 /* Do MII setup. */ 791 if (mii_phy_probe(dev, &sc->sf_miibus, 792 sf_ifmedia_upd, sf_ifmedia_sts)) { 793 printf("sf%d: MII without any phy!\n", sc->sf_unit); 794 contigfree(sc->sf_ldata,sizeof(struct sf_list_data),M_DEVBUF); 795 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand); 796 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq); 797 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 798 error = ENXIO; 799 goto fail; 800 } 801 802 ifp = &sc->arpcom.ac_if; 803 ifp->if_softc = sc; 804 ifp->if_unit = unit; 805 ifp->if_name = "sf"; 806 ifp->if_mtu = ETHERMTU; 807 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 808 ifp->if_ioctl = sf_ioctl; 809 ifp->if_output = ether_output; 810 ifp->if_start = sf_start; 811 ifp->if_watchdog = sf_watchdog; 812 ifp->if_init = sf_init; 813 ifp->if_baudrate = 10000000; 814 ifp->if_snd.ifq_maxlen = SF_TX_DLIST_CNT - 1; 815 816 /* 817 * Call MI attach routine. 818 */ 819 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 820 SF_UNLOCK(sc); 821 return(0); 822 823fail: 824 SF_UNLOCK(sc); 825 mtx_destroy(&sc->sf_mtx); 826 return(error); 827} 828 829static int sf_detach(dev) 830 device_t dev; 831{ 832 struct sf_softc *sc; 833 struct ifnet *ifp; 834 835 sc = device_get_softc(dev); 836 SF_LOCK(sc); 837 ifp = &sc->arpcom.ac_if; 838 839 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 840 sf_stop(sc); 841 842 bus_generic_detach(dev); 843 device_delete_child(dev, sc->sf_miibus); 844 845 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand); 846 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq); 847 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 848 849 contigfree(sc->sf_ldata, sizeof(struct sf_list_data), M_DEVBUF); 850 851 SF_UNLOCK(sc); 852 mtx_destroy(&sc->sf_mtx); 853 854 return(0); 855} 856 857static int sf_init_rx_ring(sc) 858 struct sf_softc *sc; 859{ 860 struct sf_list_data *ld; 861 int i; 862 863 ld = sc->sf_ldata; 864 865 bzero((char *)ld->sf_rx_dlist_big, 866 sizeof(struct sf_rx_bufdesc_type0) * SF_RX_DLIST_CNT); 867 bzero((char *)ld->sf_rx_clist, 868 sizeof(struct sf_rx_cmpdesc_type3) * SF_RX_CLIST_CNT); 869 870 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 871 if (sf_newbuf(sc, &ld->sf_rx_dlist_big[i], NULL) == ENOBUFS) 872 return(ENOBUFS); 873 } 874 875 return(0); 876} 877 878static void sf_init_tx_ring(sc) 879 struct sf_softc *sc; 880{ 881 struct sf_list_data *ld; 882 int i; 883 884 ld = sc->sf_ldata; 885 886 bzero((char *)ld->sf_tx_dlist, 887 sizeof(struct sf_tx_bufdesc_type0) * SF_TX_DLIST_CNT); 888 bzero((char *)ld->sf_tx_clist, 889 sizeof(struct sf_tx_cmpdesc_type0) * SF_TX_CLIST_CNT); 890 891 for (i = 0; i < SF_TX_DLIST_CNT; i++) 892 ld->sf_tx_dlist[i].sf_id = SF_TX_BUFDESC_ID; 893 for (i = 0; i < SF_TX_CLIST_CNT; i++) 894 ld->sf_tx_clist[i].sf_type = SF_TXCMPTYPE_TX; 895 896 ld->sf_tx_dlist[SF_TX_DLIST_CNT - 1].sf_end = 1; 897 sc->sf_tx_cnt = 0; 898 899 return; 900} 901 902static int sf_newbuf(sc, c, m) 903 struct sf_softc *sc; 904 struct sf_rx_bufdesc_type0 *c; 905 struct mbuf *m; 906{ 907 struct mbuf *m_new = NULL; 908 909 if (m == NULL) { 910 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 911 if (m_new == NULL) { 912 printf("sf%d: no memory for rx list -- " 913 "packet dropped!\n", sc->sf_unit); 914 return(ENOBUFS); 915 } 916 917 MCLGET(m_new, M_DONTWAIT); 918 if (!(m_new->m_flags & M_EXT)) { 919 printf("sf%d: no memory for rx list -- " 920 "packet dropped!\n", sc->sf_unit); 921 m_freem(m_new); 922 return(ENOBUFS); 923 } 924 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 925 } else { 926 m_new = m; 927 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 928 m_new->m_data = m_new->m_ext.ext_buf; 929 } 930 931 m_adj(m_new, sizeof(u_int64_t)); 932 933 c->sf_mbuf = m_new; 934 c->sf_addrlo = SF_RX_HOSTADDR(vtophys(mtod(m_new, caddr_t))); 935 c->sf_valid = 1; 936 937 return(0); 938} 939 940/* 941 * The starfire is programmed to use 'normal' mode for packet reception, 942 * which means we use the consumer/producer model for both the buffer 943 * descriptor queue and the completion descriptor queue. The only problem 944 * with this is that it involves a lot of register accesses: we have to 945 * read the RX completion consumer and producer indexes and the RX buffer 946 * producer index, plus the RX completion consumer and RX buffer producer 947 * indexes have to be updated. It would have been easier if Adaptec had 948 * put each index in a separate register, especially given that the damn 949 * NIC has a 512K register space. 950 * 951 * In spite of all the lovely features that Adaptec crammed into the 6915, 952 * it is marred by one truly stupid design flaw, which is that receive 953 * buffer addresses must be aligned on a longword boundary. This forces 954 * the packet payload to be unaligned, which is suboptimal on the x86 and 955 * completely unuseable on the Alpha. Our only recourse is to copy received 956 * packets into properly aligned buffers before handing them off. 957 */ 958 959static void sf_rxeof(sc) 960 struct sf_softc *sc; 961{ 962 struct ether_header *eh; 963 struct mbuf *m; 964 struct ifnet *ifp; 965 struct sf_rx_bufdesc_type0 *desc; 966 struct sf_rx_cmpdesc_type3 *cur_rx; 967 u_int32_t rxcons, rxprod; 968 int cmpprodidx, cmpconsidx, bufprodidx; 969 970 ifp = &sc->arpcom.ac_if; 971 972 rxcons = csr_read_4(sc, SF_CQ_CONSIDX); 973 rxprod = csr_read_4(sc, SF_RXDQ_PTR_Q1); 974 cmpprodidx = SF_IDX_LO(csr_read_4(sc, SF_CQ_PRODIDX)); 975 cmpconsidx = SF_IDX_LO(rxcons); 976 bufprodidx = SF_IDX_LO(rxprod); 977 978 while (cmpconsidx != cmpprodidx) { 979 struct mbuf *m0; 980 981 cur_rx = &sc->sf_ldata->sf_rx_clist[cmpconsidx]; 982 desc = &sc->sf_ldata->sf_rx_dlist_big[cur_rx->sf_endidx]; 983 m = desc->sf_mbuf; 984 SF_INC(cmpconsidx, SF_RX_CLIST_CNT); 985 SF_INC(bufprodidx, SF_RX_DLIST_CNT); 986 987 if (!(cur_rx->sf_status1 & SF_RXSTAT1_OK)) { 988 ifp->if_ierrors++; 989 sf_newbuf(sc, desc, m); 990 continue; 991 } 992 993 m0 = m_devget(mtod(m, char *), cur_rx->sf_len, ETHER_ALIGN, 994 ifp, NULL); 995 sf_newbuf(sc, desc, m); 996 if (m0 == NULL) { 997 ifp->if_ierrors++; 998 continue; 999 } 1000 m = m0; 1001 1002 eh = mtod(m, struct ether_header *); 1003 ifp->if_ipackets++; 1004 1005 /* Remove header from mbuf and pass it on. */ 1006 m_adj(m, sizeof(struct ether_header)); 1007 ether_input(ifp, eh, m); 1008 } 1009 1010 csr_write_4(sc, SF_CQ_CONSIDX, 1011 (rxcons & ~SF_CQ_CONSIDX_RXQ1) | cmpconsidx); 1012 csr_write_4(sc, SF_RXDQ_PTR_Q1, 1013 (rxprod & ~SF_RXDQ_PRODIDX) | bufprodidx); 1014 1015 return; 1016} 1017 1018/* 1019 * Read the transmit status from the completion queue and release 1020 * mbufs. Note that the buffer descriptor index in the completion 1021 * descriptor is an offset from the start of the transmit buffer 1022 * descriptor list in bytes. This is important because the manual 1023 * gives the impression that it should match the producer/consumer 1024 * index, which is the offset in 8 byte blocks. 1025 */ 1026static void sf_txeof(sc) 1027 struct sf_softc *sc; 1028{ 1029 int txcons, cmpprodidx, cmpconsidx; 1030 struct sf_tx_cmpdesc_type1 *cur_cmp; 1031 struct sf_tx_bufdesc_type0 *cur_tx; 1032 struct ifnet *ifp; 1033 1034 ifp = &sc->arpcom.ac_if; 1035 1036 txcons = csr_read_4(sc, SF_CQ_CONSIDX); 1037 cmpprodidx = SF_IDX_HI(csr_read_4(sc, SF_CQ_PRODIDX)); 1038 cmpconsidx = SF_IDX_HI(txcons); 1039 1040 while (cmpconsidx != cmpprodidx) { 1041 cur_cmp = &sc->sf_ldata->sf_tx_clist[cmpconsidx]; 1042 cur_tx = &sc->sf_ldata->sf_tx_dlist[cur_cmp->sf_index >> 7]; 1043 1044 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_OK) 1045 ifp->if_opackets++; 1046 else { 1047 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_UNDERRUN) 1048 sf_txthresh_adjust(sc); 1049 ifp->if_oerrors++; 1050 } 1051 1052 sc->sf_tx_cnt--; 1053 if (cur_tx->sf_mbuf != NULL) { 1054 m_freem(cur_tx->sf_mbuf); 1055 cur_tx->sf_mbuf = NULL; 1056 } else 1057 break; 1058 SF_INC(cmpconsidx, SF_TX_CLIST_CNT); 1059 } 1060 1061 ifp->if_timer = 0; 1062 ifp->if_flags &= ~IFF_OACTIVE; 1063 1064 csr_write_4(sc, SF_CQ_CONSIDX, 1065 (txcons & ~SF_CQ_CONSIDX_TXQ) | 1066 ((cmpconsidx << 16) & 0xFFFF0000)); 1067 1068 return; 1069} 1070 1071static void sf_txthresh_adjust(sc) 1072 struct sf_softc *sc; 1073{ 1074 u_int32_t txfctl; 1075 u_int8_t txthresh; 1076 1077 txfctl = csr_read_4(sc, SF_TX_FRAMCTL); 1078 txthresh = txfctl & SF_TXFRMCTL_TXTHRESH; 1079 if (txthresh < 0xFF) { 1080 txthresh++; 1081 txfctl &= ~SF_TXFRMCTL_TXTHRESH; 1082 txfctl |= txthresh; 1083#ifdef DIAGNOSTIC 1084 printf("sf%d: tx underrun, increasing " 1085 "tx threshold to %d bytes\n", 1086 sc->sf_unit, txthresh * 4); 1087#endif 1088 csr_write_4(sc, SF_TX_FRAMCTL, txfctl); 1089 } 1090 1091 return; 1092} 1093 1094static void sf_intr(arg) 1095 void *arg; 1096{ 1097 struct sf_softc *sc; 1098 struct ifnet *ifp; 1099 u_int32_t status; 1100 1101 sc = arg; 1102 SF_LOCK(sc); 1103 1104 ifp = &sc->arpcom.ac_if; 1105 1106 if (!(csr_read_4(sc, SF_ISR_SHADOW) & SF_ISR_PCIINT_ASSERTED)) { 1107 SF_UNLOCK(sc); 1108 return; 1109 } 1110 1111 /* Disable interrupts. */ 1112 csr_write_4(sc, SF_IMR, 0x00000000); 1113 1114 for (;;) { 1115 status = csr_read_4(sc, SF_ISR); 1116 if (status) 1117 csr_write_4(sc, SF_ISR, status); 1118 1119 if (!(status & SF_INTRS)) 1120 break; 1121 1122 if (status & SF_ISR_RXDQ1_DMADONE) 1123 sf_rxeof(sc); 1124 1125 if (status & SF_ISR_TX_TXDONE || 1126 status & SF_ISR_TX_DMADONE || 1127 status & SF_ISR_TX_QUEUEDONE) 1128 sf_txeof(sc); 1129 1130 if (status & SF_ISR_TX_LOFIFO) 1131 sf_txthresh_adjust(sc); 1132 1133 if (status & SF_ISR_ABNORMALINTR) { 1134 if (status & SF_ISR_STATSOFLOW) { 1135 untimeout(sf_stats_update, sc, 1136 sc->sf_stat_ch); 1137 sf_stats_update(sc); 1138 } else 1139 sf_init(sc); 1140 } 1141 } 1142 1143 /* Re-enable interrupts. */ 1144 csr_write_4(sc, SF_IMR, SF_INTRS); 1145 1146 if (ifp->if_snd.ifq_head != NULL) 1147 sf_start(ifp); 1148 1149 SF_UNLOCK(sc); 1150 return; 1151} 1152 1153static void sf_init(xsc) 1154 void *xsc; 1155{ 1156 struct sf_softc *sc; 1157 struct ifnet *ifp; 1158 struct mii_data *mii; 1159 int i; 1160 1161 sc = xsc; 1162 SF_LOCK(sc); 1163 ifp = &sc->arpcom.ac_if; 1164 mii = device_get_softc(sc->sf_miibus); 1165 1166 sf_stop(sc); 1167 sf_reset(sc); 1168 1169 /* Init all the receive filter registers */ 1170 for (i = SF_RXFILT_PERFECT_BASE; 1171 i < (SF_RXFILT_HASH_MAX + 1); i += 4) 1172 csr_write_4(sc, i, 0); 1173 1174 /* Empty stats counter registers. */ 1175 for (i = 0; i < sizeof(struct sf_stats)/sizeof(u_int32_t); i++) 1176 csr_write_4(sc, SF_STATS_BASE + 1177 (i + sizeof(u_int32_t)), 0); 1178 1179 /* Init our MAC address */ 1180 csr_write_4(sc, SF_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1181 csr_write_4(sc, SF_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1182 sf_setperf(sc, 0, (caddr_t)&sc->arpcom.ac_enaddr); 1183 1184 if (sf_init_rx_ring(sc) == ENOBUFS) { 1185 printf("sf%d: initialization failed: no " 1186 "memory for rx buffers\n", sc->sf_unit); 1187 SF_UNLOCK(sc); 1188 return; 1189 } 1190 1191 sf_init_tx_ring(sc); 1192 1193 csr_write_4(sc, SF_RXFILT, SF_PERFMODE_NORMAL|SF_HASHMODE_WITHVLAN); 1194 1195 /* If we want promiscuous mode, set the allframes bit. */ 1196 if (ifp->if_flags & IFF_PROMISC) { 1197 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 1198 } else { 1199 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 1200 } 1201 1202 if (ifp->if_flags & IFF_BROADCAST) { 1203 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_BROAD); 1204 } else { 1205 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_BROAD); 1206 } 1207 1208 /* 1209 * Load the multicast filter. 1210 */ 1211 sf_setmulti(sc); 1212 1213 /* Init the completion queue indexes */ 1214 csr_write_4(sc, SF_CQ_CONSIDX, 0); 1215 csr_write_4(sc, SF_CQ_PRODIDX, 0); 1216 1217 /* Init the RX completion queue */ 1218 csr_write_4(sc, SF_RXCQ_CTL_1, 1219 vtophys(sc->sf_ldata->sf_rx_clist) & SF_RXCQ_ADDR); 1220 SF_SETBIT(sc, SF_RXCQ_CTL_1, SF_RXCQTYPE_3); 1221 1222 /* Init RX DMA control. */ 1223 SF_SETBIT(sc, SF_RXDMA_CTL, SF_RXDMA_REPORTBADPKTS); 1224 1225 /* Init the RX buffer descriptor queue. */ 1226 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 1227 vtophys(sc->sf_ldata->sf_rx_dlist_big)); 1228 csr_write_4(sc, SF_RXDQ_CTL_1, (MCLBYTES << 16) | SF_DESCSPACE_16BYTES); 1229 csr_write_4(sc, SF_RXDQ_PTR_Q1, SF_RX_DLIST_CNT - 1); 1230 1231 /* Init the TX completion queue */ 1232 csr_write_4(sc, SF_TXCQ_CTL, 1233 vtophys(sc->sf_ldata->sf_tx_clist) & SF_RXCQ_ADDR); 1234 1235 /* Init the TX buffer descriptor queue. */ 1236 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 1237 vtophys(sc->sf_ldata->sf_tx_dlist)); 1238 SF_SETBIT(sc, SF_TX_FRAMCTL, SF_TXFRMCTL_CPLAFTERTX); 1239 csr_write_4(sc, SF_TXDQ_CTL, 1240 SF_TXBUFDESC_TYPE0|SF_TXMINSPACE_128BYTES|SF_TXSKIPLEN_8BYTES); 1241 SF_SETBIT(sc, SF_TXDQ_CTL, SF_TXDQCTL_NODMACMP); 1242 1243 /* Enable autopadding of short TX frames. */ 1244 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_AUTOPAD); 1245 1246 /* Enable interrupts. */ 1247 csr_write_4(sc, SF_IMR, SF_INTRS); 1248 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_INTR_ENB); 1249 1250 /* Enable the RX and TX engines. */ 1251 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_RX_ENB|SF_ETHCTL_RXDMA_ENB); 1252 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_TX_ENB|SF_ETHCTL_TXDMA_ENB); 1253 1254 /*mii_mediachg(mii);*/ 1255 sf_ifmedia_upd(ifp); 1256 1257 ifp->if_flags |= IFF_RUNNING; 1258 ifp->if_flags &= ~IFF_OACTIVE; 1259 1260 sc->sf_stat_ch = timeout(sf_stats_update, sc, hz); 1261 1262 SF_UNLOCK(sc); 1263 1264 return; 1265} 1266 1267static int sf_encap(sc, c, m_head) 1268 struct sf_softc *sc; 1269 struct sf_tx_bufdesc_type0 *c; 1270 struct mbuf *m_head; 1271{ 1272 int frag = 0; 1273 struct sf_frag *f = NULL; 1274 struct mbuf *m; 1275 1276 m = m_head; 1277 1278 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1279 if (m->m_len != 0) { 1280 if (frag == SF_MAXFRAGS) 1281 break; 1282 f = &c->sf_frags[frag]; 1283 if (frag == 0) 1284 f->sf_pktlen = m_head->m_pkthdr.len; 1285 f->sf_fraglen = m->m_len; 1286 f->sf_addr = vtophys(mtod(m, vm_offset_t)); 1287 frag++; 1288 } 1289 } 1290 1291 if (m != NULL) { 1292 struct mbuf *m_new = NULL; 1293 1294 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1295 if (m_new == NULL) { 1296 printf("sf%d: no memory for tx list", sc->sf_unit); 1297 return(1); 1298 } 1299 1300 if (m_head->m_pkthdr.len > MHLEN) { 1301 MCLGET(m_new, M_DONTWAIT); 1302 if (!(m_new->m_flags & M_EXT)) { 1303 m_freem(m_new); 1304 printf("sf%d: no memory for tx list", 1305 sc->sf_unit); 1306 return(1); 1307 } 1308 } 1309 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1310 mtod(m_new, caddr_t)); 1311 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1312 m_freem(m_head); 1313 m_head = m_new; 1314 f = &c->sf_frags[0]; 1315 f->sf_fraglen = f->sf_pktlen = m_head->m_pkthdr.len; 1316 f->sf_addr = vtophys(mtod(m_head, caddr_t)); 1317 frag = 1; 1318 } 1319 1320 c->sf_mbuf = m_head; 1321 c->sf_id = SF_TX_BUFDESC_ID; 1322 c->sf_fragcnt = frag; 1323 c->sf_intr = 1; 1324 c->sf_caltcp = 0; 1325 c->sf_crcen = 1; 1326 1327 return(0); 1328} 1329 1330static void sf_start(ifp) 1331 struct ifnet *ifp; 1332{ 1333 struct sf_softc *sc; 1334 struct sf_tx_bufdesc_type0 *cur_tx = NULL; 1335 struct mbuf *m_head = NULL; 1336 int i, txprod; 1337 1338 sc = ifp->if_softc; 1339 SF_LOCK(sc); 1340 1341 if (!sc->sf_link && ifp->if_snd.ifq_len < 10) { 1342 SF_UNLOCK(sc); 1343 return; 1344 } 1345 1346 if (ifp->if_flags & IFF_OACTIVE) { 1347 SF_UNLOCK(sc); 1348 return; 1349 } 1350 1351 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX); 1352 i = SF_IDX_HI(txprod) >> 4; 1353 1354 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) { 1355 printf("sf%d: TX ring full, resetting\n", sc->sf_unit); 1356 sf_init(sc); 1357 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX); 1358 i = SF_IDX_HI(txprod) >> 4; 1359 } 1360 1361 while(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf == NULL) { 1362 if (sc->sf_tx_cnt >= (SF_TX_DLIST_CNT - 5)) { 1363 ifp->if_flags |= IFF_OACTIVE; 1364 cur_tx = NULL; 1365 break; 1366 } 1367 IF_DEQUEUE(&ifp->if_snd, m_head); 1368 if (m_head == NULL) 1369 break; 1370 1371 cur_tx = &sc->sf_ldata->sf_tx_dlist[i]; 1372 if (sf_encap(sc, cur_tx, m_head)) { 1373 IF_PREPEND(&ifp->if_snd, m_head); 1374 ifp->if_flags |= IFF_OACTIVE; 1375 cur_tx = NULL; 1376 break; 1377 } 1378 1379 /* 1380 * If there's a BPF listener, bounce a copy of this frame 1381 * to him. 1382 */ 1383 if (ifp->if_bpf) 1384 bpf_mtap(ifp, m_head); 1385 1386 SF_INC(i, SF_TX_DLIST_CNT); 1387 sc->sf_tx_cnt++; 1388 /* 1389 * Don't get the TX DMA queue get too full. 1390 */ 1391 if (sc->sf_tx_cnt > 64) 1392 break; 1393 } 1394 1395 if (cur_tx == NULL) { 1396 SF_UNLOCK(sc); 1397 return; 1398 } 1399 1400 /* Transmit */ 1401 csr_write_4(sc, SF_TXDQ_PRODIDX, 1402 (txprod & ~SF_TXDQ_PRODIDX_HIPRIO) | 1403 ((i << 20) & 0xFFFF0000)); 1404 1405 ifp->if_timer = 5; 1406 1407 SF_UNLOCK(sc); 1408 1409 return; 1410} 1411 1412static void sf_stop(sc) 1413 struct sf_softc *sc; 1414{ 1415 int i; 1416 struct ifnet *ifp; 1417 1418 SF_LOCK(sc); 1419 1420 ifp = &sc->arpcom.ac_if; 1421 1422 untimeout(sf_stats_update, sc, sc->sf_stat_ch); 1423 1424 csr_write_4(sc, SF_GEN_ETH_CTL, 0); 1425 csr_write_4(sc, SF_CQ_CONSIDX, 0); 1426 csr_write_4(sc, SF_CQ_PRODIDX, 0); 1427 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 0); 1428 csr_write_4(sc, SF_RXDQ_CTL_1, 0); 1429 csr_write_4(sc, SF_RXDQ_PTR_Q1, 0); 1430 csr_write_4(sc, SF_TXCQ_CTL, 0); 1431 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 0); 1432 csr_write_4(sc, SF_TXDQ_CTL, 0); 1433 sf_reset(sc); 1434 1435 sc->sf_link = 0; 1436 1437 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 1438 if (sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf != NULL) { 1439 m_freem(sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf); 1440 sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf = NULL; 1441 } 1442 } 1443 1444 for (i = 0; i < SF_TX_DLIST_CNT; i++) { 1445 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) { 1446 m_freem(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf); 1447 sc->sf_ldata->sf_tx_dlist[i].sf_mbuf = NULL; 1448 } 1449 } 1450 1451 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 1452 SF_UNLOCK(sc); 1453 1454 return; 1455} 1456 1457/* 1458 * Note: it is important that this function not be interrupted. We 1459 * use a two-stage register access scheme: if we are interrupted in 1460 * between setting the indirect address register and reading from the 1461 * indirect data register, the contents of the address register could 1462 * be changed out from under us. 1463 */ 1464static void sf_stats_update(xsc) 1465 void *xsc; 1466{ 1467 struct sf_softc *sc; 1468 struct ifnet *ifp; 1469 struct mii_data *mii; 1470 struct sf_stats stats; 1471 u_int32_t *ptr; 1472 int i; 1473 1474 sc = xsc; 1475 SF_LOCK(sc); 1476 ifp = &sc->arpcom.ac_if; 1477 mii = device_get_softc(sc->sf_miibus); 1478 1479 ptr = (u_int32_t *)&stats; 1480 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++) 1481 ptr[i] = csr_read_4(sc, SF_STATS_BASE + 1482 (i + sizeof(u_int32_t))); 1483 1484 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++) 1485 csr_write_4(sc, SF_STATS_BASE + 1486 (i + sizeof(u_int32_t)), 0); 1487 1488 ifp->if_collisions += stats.sf_tx_single_colls + 1489 stats.sf_tx_multi_colls + stats.sf_tx_excess_colls; 1490 1491 mii_tick(mii); 1492 1493 if (!sc->sf_link && mii->mii_media_status & IFM_ACTIVE && 1494 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1495 sc->sf_link++; 1496 if (ifp->if_snd.ifq_head != NULL) 1497 sf_start(ifp); 1498 } 1499 1500 sc->sf_stat_ch = timeout(sf_stats_update, sc, hz); 1501 1502 SF_UNLOCK(sc); 1503 1504 return; 1505} 1506 1507static void sf_watchdog(ifp) 1508 struct ifnet *ifp; 1509{ 1510 struct sf_softc *sc; 1511 1512 sc = ifp->if_softc; 1513 1514 SF_LOCK(sc); 1515 1516 ifp->if_oerrors++; 1517 printf("sf%d: watchdog timeout\n", sc->sf_unit); 1518 1519 sf_stop(sc); 1520 sf_reset(sc); 1521 sf_init(sc); 1522 1523 if (ifp->if_snd.ifq_head != NULL) 1524 sf_start(ifp); 1525 1526 SF_UNLOCK(sc); 1527 1528 return; 1529} 1530 1531static void sf_shutdown(dev) 1532 device_t dev; 1533{ 1534 struct sf_softc *sc; 1535 1536 sc = device_get_softc(dev); 1537 1538 sf_stop(sc); 1539 1540 return; 1541} 1542