if_sf.c revision 71962
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/dev/sf/if_sf.c 71962 2001-02-03 16:29:10Z phk $ 33 */ 34 35/* 36 * Adaptec AIC-6915 "Starfire" PCI fast ethernet driver for FreeBSD. 37 * Programming manual is available from: 38 * ftp.adaptec.com:/pub/BBS/userguides/aic6915_pg.pdf. 39 * 40 * Written by Bill Paul <wpaul@ctr.columbia.edu> 41 * Department of Electical Engineering 42 * Columbia University, New York City 43 */ 44 45/* 46 * The Adaptec AIC-6915 "Starfire" is a 64-bit 10/100 PCI ethernet 47 * controller designed with flexibility and reducing CPU load in mind. 48 * The Starfire offers high and low priority buffer queues, a 49 * producer/consumer index mechanism and several different buffer 50 * queue and completion queue descriptor types. Any one of a number 51 * of different driver designs can be used, depending on system and 52 * OS requirements. This driver makes use of type0 transmit frame 53 * descriptors (since BSD fragments packets across an mbuf chain) 54 * and two RX buffer queues prioritized on size (one queue for small 55 * frames that will fit into a single mbuf, another with full size 56 * mbuf clusters for everything else). The producer/consumer indexes 57 * and completion queues are also used. 58 * 59 * One downside to the Starfire has to do with alignment: buffer 60 * queues must be aligned on 256-byte boundaries, and receive buffers 61 * must be aligned on longword boundaries. The receive buffer alignment 62 * causes problems on the Alpha platform, where the packet payload 63 * should be longword aligned. There is no simple way around this. 64 * 65 * For receive filtering, the Starfire offers 16 perfect filter slots 66 * and a 512-bit hash table. 67 * 68 * The Starfire has no internal transceiver, relying instead on an 69 * external MII-based transceiver. Accessing registers on external 70 * PHYs is done through a special register map rather than with the 71 * usual bitbang MDIO method. 72 * 73 * Acesssing the registers on the Starfire is a little tricky. The 74 * Starfire has a 512K internal register space. When programmed for 75 * PCI memory mapped mode, the entire register space can be accessed 76 * directly. However in I/O space mode, only 256 bytes are directly 77 * mapped into PCI I/O space. The other registers can be accessed 78 * indirectly using the SF_INDIRECTIO_ADDR and SF_INDIRECTIO_DATA 79 * registers inside the 256-byte I/O window. 80 */ 81 82#include <sys/param.h> 83#include <sys/systm.h> 84#include <sys/sockio.h> 85#include <sys/mbuf.h> 86#include <sys/malloc.h> 87#include <sys/kernel.h> 88#include <sys/socket.h> 89 90#include <net/if.h> 91#include <net/if_arp.h> 92#include <net/ethernet.h> 93#include <net/if_dl.h> 94#include <net/if_media.h> 95 96#include <net/bpf.h> 97 98#include <vm/vm.h> /* for vtophys */ 99#include <vm/pmap.h> /* for vtophys */ 100#include <machine/bus_pio.h> 101#include <machine/bus_memio.h> 102#include <machine/bus.h> 103#include <machine/resource.h> 104#include <sys/bus.h> 105#include <sys/rman.h> 106 107#include <dev/mii/mii.h> 108#include <dev/mii/miivar.h> 109 110/* "controller miibus0" required. See GENERIC if you get errors here. */ 111#include "miibus_if.h" 112 113#include <pci/pcireg.h> 114#include <pci/pcivar.h> 115 116#define SF_USEIOSPACE 117 118#include <pci/if_sfreg.h> 119 120MODULE_DEPEND(sf, miibus, 1, 1, 1); 121 122#ifndef lint 123static const char rcsid[] = 124 "$FreeBSD: head/sys/dev/sf/if_sf.c 71962 2001-02-03 16:29:10Z phk $"; 125#endif 126 127static struct sf_type sf_devs[] = { 128 { AD_VENDORID, AD_DEVICEID_STARFIRE, 129 "Adaptec AIC-6915 10/100BaseTX" }, 130 { 0, 0, NULL } 131}; 132 133static int sf_probe __P((device_t)); 134static int sf_attach __P((device_t)); 135static int sf_detach __P((device_t)); 136static void sf_intr __P((void *)); 137static void sf_stats_update __P((void *)); 138static void sf_rxeof __P((struct sf_softc *)); 139static void sf_txeof __P((struct sf_softc *)); 140static int sf_encap __P((struct sf_softc *, 141 struct sf_tx_bufdesc_type0 *, 142 struct mbuf *)); 143static void sf_start __P((struct ifnet *)); 144static int sf_ioctl __P((struct ifnet *, u_long, caddr_t)); 145static void sf_init __P((void *)); 146static void sf_stop __P((struct sf_softc *)); 147static void sf_watchdog __P((struct ifnet *)); 148static void sf_shutdown __P((device_t)); 149static int sf_ifmedia_upd __P((struct ifnet *)); 150static void sf_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 151static void sf_reset __P((struct sf_softc *)); 152static int sf_init_rx_ring __P((struct sf_softc *)); 153static void sf_init_tx_ring __P((struct sf_softc *)); 154static int sf_newbuf __P((struct sf_softc *, 155 struct sf_rx_bufdesc_type0 *, 156 struct mbuf *)); 157static void sf_setmulti __P((struct sf_softc *)); 158static int sf_setperf __P((struct sf_softc *, int, caddr_t)); 159static int sf_sethash __P((struct sf_softc *, caddr_t, int)); 160#ifdef notdef 161static int sf_setvlan __P((struct sf_softc *, int, u_int32_t)); 162#endif 163 164static u_int8_t sf_read_eeprom __P((struct sf_softc *, int)); 165static u_int32_t sf_calchash __P((caddr_t)); 166 167static int sf_miibus_readreg __P((device_t, int, int)); 168static int sf_miibus_writereg __P((device_t, int, int, int)); 169static void sf_miibus_statchg __P((device_t)); 170 171static u_int32_t csr_read_4 __P((struct sf_softc *, int)); 172static void csr_write_4 __P((struct sf_softc *, int, u_int32_t)); 173 174#ifdef SF_USEIOSPACE 175#define SF_RES SYS_RES_IOPORT 176#define SF_RID SF_PCI_LOIO 177#else 178#define SF_RES SYS_RES_MEMORY 179#define SF_RID SF_PCI_LOMEM 180#endif 181 182static device_method_t sf_methods[] = { 183 /* Device interface */ 184 DEVMETHOD(device_probe, sf_probe), 185 DEVMETHOD(device_attach, sf_attach), 186 DEVMETHOD(device_detach, sf_detach), 187 DEVMETHOD(device_shutdown, sf_shutdown), 188 189 /* bus interface */ 190 DEVMETHOD(bus_print_child, bus_generic_print_child), 191 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 192 193 /* MII interface */ 194 DEVMETHOD(miibus_readreg, sf_miibus_readreg), 195 DEVMETHOD(miibus_writereg, sf_miibus_writereg), 196 DEVMETHOD(miibus_statchg, sf_miibus_statchg), 197 198 { 0, 0 } 199}; 200 201static driver_t sf_driver = { 202 "sf", 203 sf_methods, 204 sizeof(struct sf_softc), 205}; 206 207static devclass_t sf_devclass; 208 209DRIVER_MODULE(if_sf, pci, sf_driver, sf_devclass, 0, 0); 210DRIVER_MODULE(miibus, sf, miibus_driver, miibus_devclass, 0, 0); 211 212#define SF_SETBIT(sc, reg, x) \ 213 csr_write_4(sc, reg, csr_read_4(sc, reg) | x) 214 215#define SF_CLRBIT(sc, reg, x) \ 216 csr_write_4(sc, reg, csr_read_4(sc, reg) & ~x) 217 218static u_int32_t csr_read_4(sc, reg) 219 struct sf_softc *sc; 220 int reg; 221{ 222 u_int32_t val; 223 224#ifdef SF_USEIOSPACE 225 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); 226 val = CSR_READ_4(sc, SF_INDIRECTIO_DATA); 227#else 228 val = CSR_READ_4(sc, (reg + SF_RMAP_INTREG_BASE)); 229#endif 230 231 return(val); 232} 233 234static u_int8_t sf_read_eeprom(sc, reg) 235 struct sf_softc *sc; 236 int reg; 237{ 238 u_int8_t val; 239 240 val = (csr_read_4(sc, SF_EEADDR_BASE + 241 (reg & 0xFFFFFFFC)) >> (8 * (reg & 3))) & 0xFF; 242 243 return(val); 244} 245 246static void csr_write_4(sc, reg, val) 247 struct sf_softc *sc; 248 int reg; 249 u_int32_t val; 250{ 251#ifdef SF_USEIOSPACE 252 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); 253 CSR_WRITE_4(sc, SF_INDIRECTIO_DATA, val); 254#else 255 CSR_WRITE_4(sc, (reg + SF_RMAP_INTREG_BASE), val); 256#endif 257 return; 258} 259 260static u_int32_t sf_calchash(addr) 261 caddr_t addr; 262{ 263 u_int32_t crc, carry; 264 int i, j; 265 u_int8_t c; 266 267 /* Compute CRC for the address value. */ 268 crc = 0xFFFFFFFF; /* initial value */ 269 270 for (i = 0; i < 6; i++) { 271 c = *(addr + i); 272 for (j = 0; j < 8; j++) { 273 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 274 crc <<= 1; 275 c >>= 1; 276 if (carry) 277 crc = (crc ^ 0x04c11db6) | carry; 278 } 279 } 280 281 /* return the filter bit position */ 282 return(crc >> 23 & 0x1FF); 283} 284 285/* 286 * Copy the address 'mac' into the perfect RX filter entry at 287 * offset 'idx.' The perfect filter only has 16 entries so do 288 * some sanity tests. 289 */ 290static int sf_setperf(sc, idx, mac) 291 struct sf_softc *sc; 292 int idx; 293 caddr_t mac; 294{ 295 u_int16_t *p; 296 297 if (idx < 0 || idx > SF_RXFILT_PERFECT_CNT) 298 return(EINVAL); 299 300 if (mac == NULL) 301 return(EINVAL); 302 303 p = (u_int16_t *)mac; 304 305 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 306 (idx * SF_RXFILT_PERFECT_SKIP), htons(p[2])); 307 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 308 (idx * SF_RXFILT_PERFECT_SKIP) + 4, htons(p[1])); 309 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 310 (idx * SF_RXFILT_PERFECT_SKIP) + 8, htons(p[0])); 311 312 return(0); 313} 314 315/* 316 * Set the bit in the 512-bit hash table that corresponds to the 317 * specified mac address 'mac.' If 'prio' is nonzero, update the 318 * priority hash table instead of the filter hash table. 319 */ 320static int sf_sethash(sc, mac, prio) 321 struct sf_softc *sc; 322 caddr_t mac; 323 int prio; 324{ 325 u_int32_t h = 0; 326 327 if (mac == NULL) 328 return(EINVAL); 329 330 h = sf_calchash(mac); 331 332 if (prio) { 333 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_PRIOOFF + 334 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); 335 } else { 336 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_ADDROFF + 337 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); 338 } 339 340 return(0); 341} 342 343#ifdef notdef 344/* 345 * Set a VLAN tag in the receive filter. 346 */ 347static int sf_setvlan(sc, idx, vlan) 348 struct sf_softc *sc; 349 int idx; 350 u_int32_t vlan; 351{ 352 if (idx < 0 || idx >> SF_RXFILT_HASH_CNT) 353 return(EINVAL); 354 355 csr_write_4(sc, SF_RXFILT_HASH_BASE + 356 (idx * SF_RXFILT_HASH_SKIP) + SF_RXFILT_HASH_VLANOFF, vlan); 357 358 return(0); 359} 360#endif 361 362static int sf_miibus_readreg(dev, phy, reg) 363 device_t dev; 364 int phy, reg; 365{ 366 struct sf_softc *sc; 367 int i; 368 u_int32_t val = 0; 369 370 sc = device_get_softc(dev); 371 372 for (i = 0; i < SF_TIMEOUT; i++) { 373 val = csr_read_4(sc, SF_PHY_REG(phy, reg)); 374 if (val & SF_MII_DATAVALID) 375 break; 376 } 377 378 if (i == SF_TIMEOUT) 379 return(0); 380 381 if ((val & 0x0000FFFF) == 0xFFFF) 382 return(0); 383 384 return(val & 0x0000FFFF); 385} 386 387static int sf_miibus_writereg(dev, phy, reg, val) 388 device_t dev; 389 int phy, reg, val; 390{ 391 struct sf_softc *sc; 392 int i; 393 int busy; 394 395 sc = device_get_softc(dev); 396 397 csr_write_4(sc, SF_PHY_REG(phy, reg), val); 398 399 for (i = 0; i < SF_TIMEOUT; i++) { 400 busy = csr_read_4(sc, SF_PHY_REG(phy, reg)); 401 if (!(busy & SF_MII_BUSY)) 402 break; 403 } 404 405 return(0); 406} 407 408static void sf_miibus_statchg(dev) 409 device_t dev; 410{ 411 struct sf_softc *sc; 412 struct mii_data *mii; 413 414 sc = device_get_softc(dev); 415 mii = device_get_softc(sc->sf_miibus); 416 417 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 418 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 419 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_FDX); 420 } else { 421 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 422 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_HDX); 423 } 424 425 return; 426} 427 428static void sf_setmulti(sc) 429 struct sf_softc *sc; 430{ 431 struct ifnet *ifp; 432 int i; 433 struct ifmultiaddr *ifma; 434 u_int8_t dummy[] = { 0, 0, 0, 0, 0, 0 }; 435 436 ifp = &sc->arpcom.ac_if; 437 438 /* First zot all the existing filters. */ 439 for (i = 1; i < SF_RXFILT_PERFECT_CNT; i++) 440 sf_setperf(sc, i, (char *)&dummy); 441 for (i = SF_RXFILT_HASH_BASE; 442 i < (SF_RXFILT_HASH_MAX + 1); i += 4) 443 csr_write_4(sc, i, 0); 444 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI); 445 446 /* Now program new ones. */ 447 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 448 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI); 449 } else { 450 i = 1; 451 /* First find the tail of the list. */ 452 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 453 if (ifma->ifma_link.le_next == NULL) 454 break; 455 } 456 /* Now traverse the list backwards. */ 457 for (; ifma != NULL && ifma != (void *)&ifp->if_multiaddrs; 458 ifma = (struct ifmultiaddr *)ifma->ifma_link.le_prev) { 459 if (ifma->ifma_addr->sa_family != AF_LINK) 460 continue; 461 /* 462 * Program the first 15 multicast groups 463 * into the perfect filter. For all others, 464 * use the hash table. 465 */ 466 if (i < SF_RXFILT_PERFECT_CNT) { 467 sf_setperf(sc, i, 468 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 469 i++; 470 continue; 471 } 472 473 sf_sethash(sc, 474 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 0); 475 } 476 } 477 478 return; 479} 480 481/* 482 * Set media options. 483 */ 484static int sf_ifmedia_upd(ifp) 485 struct ifnet *ifp; 486{ 487 struct sf_softc *sc; 488 struct mii_data *mii; 489 490 sc = ifp->if_softc; 491 mii = device_get_softc(sc->sf_miibus); 492 sc->sf_link = 0; 493 if (mii->mii_instance) { 494 struct mii_softc *miisc; 495 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 496 miisc = LIST_NEXT(miisc, mii_list)) 497 mii_phy_reset(miisc); 498 } 499 mii_mediachg(mii); 500 501 return(0); 502} 503 504/* 505 * Report current media status. 506 */ 507static void sf_ifmedia_sts(ifp, ifmr) 508 struct ifnet *ifp; 509 struct ifmediareq *ifmr; 510{ 511 struct sf_softc *sc; 512 struct mii_data *mii; 513 514 sc = ifp->if_softc; 515 mii = device_get_softc(sc->sf_miibus); 516 517 mii_pollstat(mii); 518 ifmr->ifm_active = mii->mii_media_active; 519 ifmr->ifm_status = mii->mii_media_status; 520 521 return; 522} 523 524static int sf_ioctl(ifp, command, data) 525 struct ifnet *ifp; 526 u_long command; 527 caddr_t data; 528{ 529 struct sf_softc *sc = ifp->if_softc; 530 struct ifreq *ifr = (struct ifreq *) data; 531 struct mii_data *mii; 532 int error = 0; 533 534 SF_LOCK(sc); 535 536 switch(command) { 537 case SIOCSIFADDR: 538 case SIOCGIFADDR: 539 case SIOCSIFMTU: 540 error = ether_ioctl(ifp, command, data); 541 break; 542 case SIOCSIFFLAGS: 543 if (ifp->if_flags & IFF_UP) { 544 if (ifp->if_flags & IFF_RUNNING && 545 ifp->if_flags & IFF_PROMISC && 546 !(sc->sf_if_flags & IFF_PROMISC)) { 547 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 548 } else if (ifp->if_flags & IFF_RUNNING && 549 !(ifp->if_flags & IFF_PROMISC) && 550 sc->sf_if_flags & IFF_PROMISC) { 551 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 552 } else if (!(ifp->if_flags & IFF_RUNNING)) 553 sf_init(sc); 554 } else { 555 if (ifp->if_flags & IFF_RUNNING) 556 sf_stop(sc); 557 } 558 sc->sf_if_flags = ifp->if_flags; 559 error = 0; 560 break; 561 case SIOCADDMULTI: 562 case SIOCDELMULTI: 563 sf_setmulti(sc); 564 error = 0; 565 break; 566 case SIOCGIFMEDIA: 567 case SIOCSIFMEDIA: 568 mii = device_get_softc(sc->sf_miibus); 569 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 570 break; 571 default: 572 error = EINVAL; 573 break; 574 } 575 576 SF_UNLOCK(sc); 577 578 return(error); 579} 580 581static void sf_reset(sc) 582 struct sf_softc *sc; 583{ 584 register int i; 585 586 csr_write_4(sc, SF_GEN_ETH_CTL, 0); 587 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 588 DELAY(1000); 589 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 590 591 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_RESET); 592 593 for (i = 0; i < SF_TIMEOUT; i++) { 594 DELAY(10); 595 if (!(csr_read_4(sc, SF_PCI_DEVCFG) & SF_PCIDEVCFG_RESET)) 596 break; 597 } 598 599 if (i == SF_TIMEOUT) 600 printf("sf%d: reset never completed!\n", sc->sf_unit); 601 602 /* Wait a little while for the chip to get its brains in order. */ 603 DELAY(1000); 604 return; 605} 606 607/* 608 * Probe for an Adaptec AIC-6915 chip. Check the PCI vendor and device 609 * IDs against our list and return a device name if we find a match. 610 * We also check the subsystem ID so that we can identify exactly which 611 * NIC has been found, if possible. 612 */ 613static int sf_probe(dev) 614 device_t dev; 615{ 616 struct sf_type *t; 617 618 t = sf_devs; 619 620 while(t->sf_name != NULL) { 621 if ((pci_get_vendor(dev) == t->sf_vid) && 622 (pci_get_device(dev) == t->sf_did)) { 623 switch((pci_read_config(dev, 624 SF_PCI_SUBVEN_ID, 4) >> 16) & 0xFFFF) { 625 case AD_SUBSYSID_62011_REV0: 626 case AD_SUBSYSID_62011_REV1: 627 device_set_desc(dev, 628 "Adaptec ANA-62011 10/100BaseTX"); 629 return(0); 630 break; 631 case AD_SUBSYSID_62022: 632 device_set_desc(dev, 633 "Adaptec ANA-62022 10/100BaseTX"); 634 return(0); 635 break; 636 case AD_SUBSYSID_62044_REV0: 637 case AD_SUBSYSID_62044_REV1: 638 device_set_desc(dev, 639 "Adaptec ANA-62044 10/100BaseTX"); 640 return(0); 641 break; 642 case AD_SUBSYSID_62020: 643 device_set_desc(dev, 644 "Adaptec ANA-62020 10/100BaseFX"); 645 return(0); 646 break; 647 case AD_SUBSYSID_69011: 648 device_set_desc(dev, 649 "Adaptec ANA-69011 10/100BaseTX"); 650 return(0); 651 break; 652 default: 653 device_set_desc(dev, t->sf_name); 654 return(0); 655 break; 656 } 657 } 658 t++; 659 } 660 661 return(ENXIO); 662} 663 664/* 665 * Attach the interface. Allocate softc structures, do ifmedia 666 * setup and ethernet/BPF attach. 667 */ 668static int sf_attach(dev) 669 device_t dev; 670{ 671 int i; 672 u_int32_t command; 673 struct sf_softc *sc; 674 struct ifnet *ifp; 675 int unit, rid, error = 0; 676 677 sc = device_get_softc(dev); 678 unit = device_get_unit(dev); 679 bzero(sc, sizeof(struct sf_softc)); 680 681 mtx_init(&sc->sf_mtx, device_get_nameunit(dev), MTX_DEF | MTX_RECURSE); 682 SF_LOCK(sc); 683 /* 684 * Handle power management nonsense. 685 */ 686 command = pci_read_config(dev, SF_PCI_CAPID, 4) & 0x000000FF; 687 if (command == 0x01) { 688 689 command = pci_read_config(dev, SF_PCI_PWRMGMTCTRL, 4); 690 if (command & SF_PSTATE_MASK) { 691 u_int32_t iobase, membase, irq; 692 693 /* Save important PCI config data. */ 694 iobase = pci_read_config(dev, SF_PCI_LOIO, 4); 695 membase = pci_read_config(dev, SF_PCI_LOMEM, 4); 696 irq = pci_read_config(dev, SF_PCI_INTLINE, 4); 697 698 /* Reset the power state. */ 699 printf("sf%d: chip is in D%d power mode " 700 "-- setting to D0\n", unit, command & SF_PSTATE_MASK); 701 command &= 0xFFFFFFFC; 702 pci_write_config(dev, SF_PCI_PWRMGMTCTRL, command, 4); 703 704 /* Restore PCI config data. */ 705 pci_write_config(dev, SF_PCI_LOIO, iobase, 4); 706 pci_write_config(dev, SF_PCI_LOMEM, membase, 4); 707 pci_write_config(dev, SF_PCI_INTLINE, irq, 4); 708 } 709 } 710 711 /* 712 * Map control/status registers. 713 */ 714 command = pci_read_config(dev, PCIR_COMMAND, 4); 715 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 716 pci_write_config(dev, PCIR_COMMAND, command, 4); 717 command = pci_read_config(dev, PCIR_COMMAND, 4); 718 719#ifdef SF_USEIOSPACE 720 if (!(command & PCIM_CMD_PORTEN)) { 721 printf("sf%d: failed to enable I/O ports!\n", unit); 722 error = ENXIO; 723 goto fail; 724 } 725#else 726 if (!(command & PCIM_CMD_MEMEN)) { 727 printf("sf%d: failed to enable memory mapping!\n", unit); 728 error = ENXIO; 729 goto fail; 730 } 731#endif 732 733 rid = SF_RID; 734 sc->sf_res = bus_alloc_resource(dev, SF_RES, &rid, 735 0, ~0, 1, RF_ACTIVE); 736 737 if (sc->sf_res == NULL) { 738 printf ("sf%d: couldn't map ports\n", unit); 739 error = ENXIO; 740 goto fail; 741 } 742 743 sc->sf_btag = rman_get_bustag(sc->sf_res); 744 sc->sf_bhandle = rman_get_bushandle(sc->sf_res); 745 746 /* Allocate interrupt */ 747 rid = 0; 748 sc->sf_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 749 RF_SHAREABLE | RF_ACTIVE); 750 751 if (sc->sf_irq == NULL) { 752 printf("sf%d: couldn't map interrupt\n", unit); 753 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 754 error = ENXIO; 755 goto fail; 756 } 757 758 error = bus_setup_intr(dev, sc->sf_irq, INTR_TYPE_NET, 759 sf_intr, sc, &sc->sf_intrhand); 760 761 if (error) { 762 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_res); 763 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 764 printf("sf%d: couldn't set up irq\n", unit); 765 goto fail; 766 } 767 768 callout_handle_init(&sc->sf_stat_ch); 769 /* Reset the adapter. */ 770 sf_reset(sc); 771 772 /* 773 * Get station address from the EEPROM. 774 */ 775 for (i = 0; i < ETHER_ADDR_LEN; i++) 776 sc->arpcom.ac_enaddr[i] = 777 sf_read_eeprom(sc, SF_EE_NODEADDR + ETHER_ADDR_LEN - i); 778 779 /* 780 * An Adaptec chip was detected. Inform the world. 781 */ 782 printf("sf%d: Ethernet address: %6D\n", unit, 783 sc->arpcom.ac_enaddr, ":"); 784 785 sc->sf_unit = unit; 786 787 /* Allocate the descriptor queues. */ 788 sc->sf_ldata = contigmalloc(sizeof(struct sf_list_data), M_DEVBUF, 789 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 790 791 if (sc->sf_ldata == NULL) { 792 printf("sf%d: no memory for list buffers!\n", unit); 793 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand); 794 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq); 795 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 796 error = ENXIO; 797 goto fail; 798 } 799 800 bzero(sc->sf_ldata, sizeof(struct sf_list_data)); 801 802 /* Do MII setup. */ 803 if (mii_phy_probe(dev, &sc->sf_miibus, 804 sf_ifmedia_upd, sf_ifmedia_sts)) { 805 printf("sf%d: MII without any phy!\n", sc->sf_unit); 806 contigfree(sc->sf_ldata,sizeof(struct sf_list_data),M_DEVBUF); 807 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand); 808 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq); 809 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 810 error = ENXIO; 811 goto fail; 812 } 813 814 ifp = &sc->arpcom.ac_if; 815 ifp->if_softc = sc; 816 ifp->if_unit = unit; 817 ifp->if_name = "sf"; 818 ifp->if_mtu = ETHERMTU; 819 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 820 ifp->if_ioctl = sf_ioctl; 821 ifp->if_output = ether_output; 822 ifp->if_start = sf_start; 823 ifp->if_watchdog = sf_watchdog; 824 ifp->if_init = sf_init; 825 ifp->if_baudrate = 10000000; 826 ifp->if_snd.ifq_maxlen = SF_TX_DLIST_CNT - 1; 827 828 /* 829 * Call MI attach routine. 830 */ 831 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 832 SF_UNLOCK(sc); 833 return(0); 834 835fail: 836 SF_UNLOCK(sc); 837 mtx_destroy(&sc->sf_mtx); 838 return(error); 839} 840 841static int sf_detach(dev) 842 device_t dev; 843{ 844 struct sf_softc *sc; 845 struct ifnet *ifp; 846 847 sc = device_get_softc(dev); 848 SF_LOCK(sc); 849 ifp = &sc->arpcom.ac_if; 850 851 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 852 sf_stop(sc); 853 854 bus_generic_detach(dev); 855 device_delete_child(dev, sc->sf_miibus); 856 857 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand); 858 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq); 859 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 860 861 contigfree(sc->sf_ldata, sizeof(struct sf_list_data), M_DEVBUF); 862 863 SF_UNLOCK(sc); 864 mtx_destroy(&sc->sf_mtx); 865 866 return(0); 867} 868 869static int sf_init_rx_ring(sc) 870 struct sf_softc *sc; 871{ 872 struct sf_list_data *ld; 873 int i; 874 875 ld = sc->sf_ldata; 876 877 bzero((char *)ld->sf_rx_dlist_big, 878 sizeof(struct sf_rx_bufdesc_type0) * SF_RX_DLIST_CNT); 879 bzero((char *)ld->sf_rx_clist, 880 sizeof(struct sf_rx_cmpdesc_type3) * SF_RX_CLIST_CNT); 881 882 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 883 if (sf_newbuf(sc, &ld->sf_rx_dlist_big[i], NULL) == ENOBUFS) 884 return(ENOBUFS); 885 } 886 887 return(0); 888} 889 890static void sf_init_tx_ring(sc) 891 struct sf_softc *sc; 892{ 893 struct sf_list_data *ld; 894 int i; 895 896 ld = sc->sf_ldata; 897 898 bzero((char *)ld->sf_tx_dlist, 899 sizeof(struct sf_tx_bufdesc_type0) * SF_TX_DLIST_CNT); 900 bzero((char *)ld->sf_tx_clist, 901 sizeof(struct sf_tx_cmpdesc_type0) * SF_TX_CLIST_CNT); 902 903 for (i = 0; i < SF_TX_DLIST_CNT; i++) 904 ld->sf_tx_dlist[i].sf_id = SF_TX_BUFDESC_ID; 905 for (i = 0; i < SF_TX_CLIST_CNT; i++) 906 ld->sf_tx_clist[i].sf_type = SF_TXCMPTYPE_TX; 907 908 ld->sf_tx_dlist[SF_TX_DLIST_CNT - 1].sf_end = 1; 909 sc->sf_tx_cnt = 0; 910 911 return; 912} 913 914static int sf_newbuf(sc, c, m) 915 struct sf_softc *sc; 916 struct sf_rx_bufdesc_type0 *c; 917 struct mbuf *m; 918{ 919 struct mbuf *m_new = NULL; 920 921 if (m == NULL) { 922 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 923 if (m_new == NULL) { 924 printf("sf%d: no memory for rx list -- " 925 "packet dropped!\n", sc->sf_unit); 926 return(ENOBUFS); 927 } 928 929 MCLGET(m_new, M_DONTWAIT); 930 if (!(m_new->m_flags & M_EXT)) { 931 printf("sf%d: no memory for rx list -- " 932 "packet dropped!\n", sc->sf_unit); 933 m_freem(m_new); 934 return(ENOBUFS); 935 } 936 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 937 } else { 938 m_new = m; 939 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 940 m_new->m_data = m_new->m_ext.ext_buf; 941 } 942 943 m_adj(m_new, sizeof(u_int64_t)); 944 945 c->sf_mbuf = m_new; 946 c->sf_addrlo = SF_RX_HOSTADDR(vtophys(mtod(m_new, caddr_t))); 947 c->sf_valid = 1; 948 949 return(0); 950} 951 952/* 953 * The starfire is programmed to use 'normal' mode for packet reception, 954 * which means we use the consumer/producer model for both the buffer 955 * descriptor queue and the completion descriptor queue. The only problem 956 * with this is that it involves a lot of register accesses: we have to 957 * read the RX completion consumer and producer indexes and the RX buffer 958 * producer index, plus the RX completion consumer and RX buffer producer 959 * indexes have to be updated. It would have been easier if Adaptec had 960 * put each index in a separate register, especially given that the damn 961 * NIC has a 512K register space. 962 * 963 * In spite of all the lovely features that Adaptec crammed into the 6915, 964 * it is marred by one truly stupid design flaw, which is that receive 965 * buffer addresses must be aligned on a longword boundary. This forces 966 * the packet payload to be unaligned, which is suboptimal on the x86 and 967 * completely unuseable on the Alpha. Our only recourse is to copy received 968 * packets into properly aligned buffers before handing them off. 969 */ 970 971static void sf_rxeof(sc) 972 struct sf_softc *sc; 973{ 974 struct ether_header *eh; 975 struct mbuf *m; 976 struct ifnet *ifp; 977 struct sf_rx_bufdesc_type0 *desc; 978 struct sf_rx_cmpdesc_type3 *cur_rx; 979 u_int32_t rxcons, rxprod; 980 int cmpprodidx, cmpconsidx, bufprodidx; 981 982 ifp = &sc->arpcom.ac_if; 983 984 rxcons = csr_read_4(sc, SF_CQ_CONSIDX); 985 rxprod = csr_read_4(sc, SF_RXDQ_PTR_Q1); 986 cmpprodidx = SF_IDX_LO(csr_read_4(sc, SF_CQ_PRODIDX)); 987 cmpconsidx = SF_IDX_LO(rxcons); 988 bufprodidx = SF_IDX_LO(rxprod); 989 990 while (cmpconsidx != cmpprodidx) { 991 struct mbuf *m0; 992 993 cur_rx = &sc->sf_ldata->sf_rx_clist[cmpconsidx]; 994 desc = &sc->sf_ldata->sf_rx_dlist_big[cur_rx->sf_endidx]; 995 m = desc->sf_mbuf; 996 SF_INC(cmpconsidx, SF_RX_CLIST_CNT); 997 SF_INC(bufprodidx, SF_RX_DLIST_CNT); 998 999 if (!(cur_rx->sf_status1 & SF_RXSTAT1_OK)) { 1000 ifp->if_ierrors++; 1001 sf_newbuf(sc, desc, m); 1002 continue; 1003 } 1004 1005 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1006 cur_rx->sf_len + ETHER_ALIGN, 0, ifp, NULL); 1007 sf_newbuf(sc, desc, m); 1008 if (m0 == NULL) { 1009 ifp->if_ierrors++; 1010 continue; 1011 } 1012 m_adj(m0, ETHER_ALIGN); 1013 m = m0; 1014 1015 eh = mtod(m, struct ether_header *); 1016 ifp->if_ipackets++; 1017 1018 /* Remove header from mbuf and pass it on. */ 1019 m_adj(m, sizeof(struct ether_header)); 1020 ether_input(ifp, eh, m); 1021 } 1022 1023 csr_write_4(sc, SF_CQ_CONSIDX, 1024 (rxcons & ~SF_CQ_CONSIDX_RXQ1) | cmpconsidx); 1025 csr_write_4(sc, SF_RXDQ_PTR_Q1, 1026 (rxprod & ~SF_RXDQ_PRODIDX) | bufprodidx); 1027 1028 return; 1029} 1030 1031/* 1032 * Read the transmit status from the completion queue and release 1033 * mbufs. Note that the buffer descriptor index in the completion 1034 * descriptor is an offset from the start of the transmit buffer 1035 * descriptor list in bytes. This is important because the manual 1036 * gives the impression that it should match the producer/consumer 1037 * index, which is the offset in 8 byte blocks. 1038 */ 1039static void sf_txeof(sc) 1040 struct sf_softc *sc; 1041{ 1042 int txcons, cmpprodidx, cmpconsidx; 1043 struct sf_tx_cmpdesc_type1 *cur_cmp; 1044 struct sf_tx_bufdesc_type0 *cur_tx; 1045 struct ifnet *ifp; 1046 1047 ifp = &sc->arpcom.ac_if; 1048 1049 txcons = csr_read_4(sc, SF_CQ_CONSIDX); 1050 cmpprodidx = SF_IDX_HI(csr_read_4(sc, SF_CQ_PRODIDX)); 1051 cmpconsidx = SF_IDX_HI(txcons); 1052 1053 while (cmpconsidx != cmpprodidx) { 1054 cur_cmp = &sc->sf_ldata->sf_tx_clist[cmpconsidx]; 1055 cur_tx = &sc->sf_ldata->sf_tx_dlist[cur_cmp->sf_index >> 7]; 1056 SF_INC(cmpconsidx, SF_TX_CLIST_CNT); 1057 1058 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_OK) 1059 ifp->if_opackets++; 1060 else 1061 ifp->if_oerrors++; 1062 1063 sc->sf_tx_cnt--; 1064 if (cur_tx->sf_mbuf != NULL) { 1065 m_freem(cur_tx->sf_mbuf); 1066 cur_tx->sf_mbuf = NULL; 1067 } 1068 } 1069 1070 ifp->if_timer = 0; 1071 ifp->if_flags &= ~IFF_OACTIVE; 1072 1073 csr_write_4(sc, SF_CQ_CONSIDX, 1074 (txcons & ~SF_CQ_CONSIDX_TXQ) | 1075 ((cmpconsidx << 16) & 0xFFFF0000)); 1076 1077 return; 1078} 1079 1080static void sf_intr(arg) 1081 void *arg; 1082{ 1083 struct sf_softc *sc; 1084 struct ifnet *ifp; 1085 u_int32_t status; 1086 1087 sc = arg; 1088 SF_LOCK(sc); 1089 1090 ifp = &sc->arpcom.ac_if; 1091 1092 if (!(csr_read_4(sc, SF_ISR_SHADOW) & SF_ISR_PCIINT_ASSERTED)) { 1093 SF_UNLOCK(sc); 1094 return; 1095 } 1096 1097 /* Disable interrupts. */ 1098 csr_write_4(sc, SF_IMR, 0x00000000); 1099 1100 for (;;) { 1101 status = csr_read_4(sc, SF_ISR); 1102 if (status) 1103 csr_write_4(sc, SF_ISR, status); 1104 1105 if (!(status & SF_INTRS)) 1106 break; 1107 1108 if (status & SF_ISR_RXDQ1_DMADONE) 1109 sf_rxeof(sc); 1110 1111 if (status & SF_ISR_TX_TXDONE) 1112 sf_txeof(sc); 1113 1114 if (status & SF_ISR_ABNORMALINTR) { 1115 if (status & SF_ISR_STATSOFLOW) { 1116 untimeout(sf_stats_update, sc, 1117 sc->sf_stat_ch); 1118 sf_stats_update(sc); 1119 } else 1120 sf_init(sc); 1121 } 1122 } 1123 1124 /* Re-enable interrupts. */ 1125 csr_write_4(sc, SF_IMR, SF_INTRS); 1126 1127 if (ifp->if_snd.ifq_head != NULL) 1128 sf_start(ifp); 1129 1130 SF_UNLOCK(sc); 1131 return; 1132} 1133 1134static void sf_init(xsc) 1135 void *xsc; 1136{ 1137 struct sf_softc *sc; 1138 struct ifnet *ifp; 1139 struct mii_data *mii; 1140 int i; 1141 1142 sc = xsc; 1143 SF_LOCK(sc); 1144 ifp = &sc->arpcom.ac_if; 1145 mii = device_get_softc(sc->sf_miibus); 1146 1147 sf_stop(sc); 1148 sf_reset(sc); 1149 1150 /* Init all the receive filter registers */ 1151 for (i = SF_RXFILT_PERFECT_BASE; 1152 i < (SF_RXFILT_HASH_MAX + 1); i += 4) 1153 csr_write_4(sc, i, 0); 1154 1155 /* Empty stats counter registers. */ 1156 for (i = 0; i < sizeof(struct sf_stats)/sizeof(u_int32_t); i++) 1157 csr_write_4(sc, SF_STATS_BASE + 1158 (i + sizeof(u_int32_t)), 0); 1159 1160 /* Init our MAC address */ 1161 csr_write_4(sc, SF_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1162 csr_write_4(sc, SF_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1163 sf_setperf(sc, 0, (caddr_t)&sc->arpcom.ac_enaddr); 1164 1165 if (sf_init_rx_ring(sc) == ENOBUFS) { 1166 printf("sf%d: initialization failed: no " 1167 "memory for rx buffers\n", sc->sf_unit); 1168 SF_UNLOCK(sc); 1169 return; 1170 } 1171 1172 sf_init_tx_ring(sc); 1173 1174 csr_write_4(sc, SF_RXFILT, SF_PERFMODE_NORMAL|SF_HASHMODE_WITHVLAN); 1175 1176 /* If we want promiscuous mode, set the allframes bit. */ 1177 if (ifp->if_flags & IFF_PROMISC) { 1178 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 1179 } else { 1180 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 1181 } 1182 1183 if (ifp->if_flags & IFF_BROADCAST) { 1184 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_BROAD); 1185 } else { 1186 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_BROAD); 1187 } 1188 1189 /* 1190 * Load the multicast filter. 1191 */ 1192 sf_setmulti(sc); 1193 1194 /* Init the completion queue indexes */ 1195 csr_write_4(sc, SF_CQ_CONSIDX, 0); 1196 csr_write_4(sc, SF_CQ_PRODIDX, 0); 1197 1198 /* Init the RX completion queue */ 1199 csr_write_4(sc, SF_RXCQ_CTL_1, 1200 vtophys(sc->sf_ldata->sf_rx_clist) & SF_RXCQ_ADDR); 1201 SF_SETBIT(sc, SF_RXCQ_CTL_1, SF_RXCQTYPE_3); 1202 1203 /* Init RX DMA control. */ 1204 SF_SETBIT(sc, SF_RXDMA_CTL, SF_RXDMA_REPORTBADPKTS); 1205 1206 /* Init the RX buffer descriptor queue. */ 1207 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 1208 vtophys(sc->sf_ldata->sf_rx_dlist_big)); 1209 csr_write_4(sc, SF_RXDQ_CTL_1, (MCLBYTES << 16) | SF_DESCSPACE_16BYTES); 1210 csr_write_4(sc, SF_RXDQ_PTR_Q1, SF_RX_DLIST_CNT - 1); 1211 1212 /* Init the TX completion queue */ 1213 csr_write_4(sc, SF_TXCQ_CTL, 1214 vtophys(sc->sf_ldata->sf_tx_clist) & SF_RXCQ_ADDR); 1215 1216 /* Init the TX buffer descriptor queue. */ 1217 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 1218 vtophys(sc->sf_ldata->sf_tx_dlist)); 1219 SF_SETBIT(sc, SF_TX_FRAMCTL, SF_TXFRMCTL_CPLAFTERTX); 1220 csr_write_4(sc, SF_TXDQ_CTL, 1221 SF_TXBUFDESC_TYPE0|SF_TXMINSPACE_128BYTES|SF_TXSKIPLEN_8BYTES); 1222 SF_SETBIT(sc, SF_TXDQ_CTL, SF_TXDQCTL_NODMACMP); 1223 1224 /* Enable autopadding of short TX frames. */ 1225 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_AUTOPAD); 1226 1227 /* Enable interrupts. */ 1228 csr_write_4(sc, SF_IMR, SF_INTRS); 1229 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_INTR_ENB); 1230 1231 /* Enable the RX and TX engines. */ 1232 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_RX_ENB|SF_ETHCTL_RXDMA_ENB); 1233 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_TX_ENB|SF_ETHCTL_TXDMA_ENB); 1234 1235 /*mii_mediachg(mii);*/ 1236 sf_ifmedia_upd(ifp); 1237 1238 ifp->if_flags |= IFF_RUNNING; 1239 ifp->if_flags &= ~IFF_OACTIVE; 1240 1241 sc->sf_stat_ch = timeout(sf_stats_update, sc, hz); 1242 1243 SF_UNLOCK(sc); 1244 1245 return; 1246} 1247 1248static int sf_encap(sc, c, m_head) 1249 struct sf_softc *sc; 1250 struct sf_tx_bufdesc_type0 *c; 1251 struct mbuf *m_head; 1252{ 1253 int frag = 0; 1254 struct sf_frag *f = NULL; 1255 struct mbuf *m; 1256 1257 m = m_head; 1258 1259 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1260 if (m->m_len != 0) { 1261 if (frag == SF_MAXFRAGS) 1262 break; 1263 f = &c->sf_frags[frag]; 1264 if (frag == 0) 1265 f->sf_pktlen = m_head->m_pkthdr.len; 1266 f->sf_fraglen = m->m_len; 1267 f->sf_addr = vtophys(mtod(m, vm_offset_t)); 1268 frag++; 1269 } 1270 } 1271 1272 if (m != NULL) { 1273 struct mbuf *m_new = NULL; 1274 1275 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1276 if (m_new == NULL) { 1277 printf("sf%d: no memory for tx list", sc->sf_unit); 1278 return(1); 1279 } 1280 1281 if (m_head->m_pkthdr.len > MHLEN) { 1282 MCLGET(m_new, M_DONTWAIT); 1283 if (!(m_new->m_flags & M_EXT)) { 1284 m_freem(m_new); 1285 printf("sf%d: no memory for tx list", 1286 sc->sf_unit); 1287 return(1); 1288 } 1289 } 1290 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1291 mtod(m_new, caddr_t)); 1292 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1293 m_freem(m_head); 1294 m_head = m_new; 1295 f = &c->sf_frags[0]; 1296 f->sf_fraglen = f->sf_pktlen = m_head->m_pkthdr.len; 1297 f->sf_addr = vtophys(mtod(m_head, caddr_t)); 1298 frag = 1; 1299 } 1300 1301 c->sf_mbuf = m_head; 1302 c->sf_id = SF_TX_BUFDESC_ID; 1303 c->sf_fragcnt = frag; 1304 c->sf_intr = 1; 1305 c->sf_caltcp = 0; 1306 c->sf_crcen = 1; 1307 1308 return(0); 1309} 1310 1311static void sf_start(ifp) 1312 struct ifnet *ifp; 1313{ 1314 struct sf_softc *sc; 1315 struct sf_tx_bufdesc_type0 *cur_tx = NULL; 1316 struct mbuf *m_head = NULL; 1317 int i, txprod; 1318 1319 sc = ifp->if_softc; 1320 SF_LOCK(sc); 1321 1322 if (!sc->sf_link) { 1323 SF_UNLOCK(sc); 1324 return; 1325 } 1326 1327 if (ifp->if_flags & IFF_OACTIVE) { 1328 SF_UNLOCK(sc); 1329 return; 1330 } 1331 1332 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX); 1333 i = SF_IDX_HI(txprod) >> 4; 1334 1335 while(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf == NULL) { 1336 if (sc->sf_tx_cnt == (SF_TX_DLIST_CNT - 2)) { 1337 ifp->if_flags |= IFF_OACTIVE; 1338 cur_tx = NULL; 1339 break; 1340 } 1341 IF_DEQUEUE(&ifp->if_snd, m_head); 1342 if (m_head == NULL) 1343 break; 1344 1345 cur_tx = &sc->sf_ldata->sf_tx_dlist[i]; 1346 if (sf_encap(sc, cur_tx, m_head)) { 1347 IF_PREPEND(&ifp->if_snd, m_head); 1348 ifp->if_flags |= IFF_OACTIVE; 1349 cur_tx = NULL; 1350 break; 1351 } 1352 1353 /* 1354 * If there's a BPF listener, bounce a copy of this frame 1355 * to him. 1356 */ 1357 if (ifp->if_bpf) 1358 bpf_mtap(ifp, m_head); 1359 1360 SF_INC(i, SF_TX_DLIST_CNT); 1361 sc->sf_tx_cnt++; 1362 } 1363 1364 if (cur_tx == NULL) { 1365 SF_UNLOCK(sc); 1366 return; 1367 } 1368 1369 /* Transmit */ 1370 csr_write_4(sc, SF_TXDQ_PRODIDX, 1371 (txprod & ~SF_TXDQ_PRODIDX_HIPRIO) | 1372 ((i << 20) & 0xFFFF0000)); 1373 1374 ifp->if_timer = 5; 1375 1376 SF_UNLOCK(sc); 1377 1378 return; 1379} 1380 1381static void sf_stop(sc) 1382 struct sf_softc *sc; 1383{ 1384 int i; 1385 struct ifnet *ifp; 1386 1387 SF_LOCK(sc); 1388 1389 ifp = &sc->arpcom.ac_if; 1390 1391 untimeout(sf_stats_update, sc, sc->sf_stat_ch); 1392 1393 csr_write_4(sc, SF_GEN_ETH_CTL, 0); 1394 csr_write_4(sc, SF_CQ_CONSIDX, 0); 1395 csr_write_4(sc, SF_CQ_PRODIDX, 0); 1396 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 0); 1397 csr_write_4(sc, SF_RXDQ_CTL_1, 0); 1398 csr_write_4(sc, SF_RXDQ_PTR_Q1, 0); 1399 csr_write_4(sc, SF_TXCQ_CTL, 0); 1400 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 0); 1401 csr_write_4(sc, SF_TXDQ_CTL, 0); 1402 sf_reset(sc); 1403 1404 sc->sf_link = 0; 1405 1406 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 1407 if (sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf != NULL) { 1408 m_freem(sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf); 1409 sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf = NULL; 1410 } 1411 } 1412 1413 for (i = 0; i < SF_TX_DLIST_CNT; i++) { 1414 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) { 1415 m_freem(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf); 1416 sc->sf_ldata->sf_tx_dlist[i].sf_mbuf = NULL; 1417 } 1418 } 1419 1420 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 1421 SF_UNLOCK(sc); 1422 1423 return; 1424} 1425 1426/* 1427 * Note: it is important that this function not be interrupted. We 1428 * use a two-stage register access scheme: if we are interrupted in 1429 * between setting the indirect address register and reading from the 1430 * indirect data register, the contents of the address register could 1431 * be changed out from under us. 1432 */ 1433static void sf_stats_update(xsc) 1434 void *xsc; 1435{ 1436 struct sf_softc *sc; 1437 struct ifnet *ifp; 1438 struct mii_data *mii; 1439 struct sf_stats stats; 1440 u_int32_t *ptr; 1441 int i; 1442 1443 sc = xsc; 1444 SF_LOCK(sc); 1445 ifp = &sc->arpcom.ac_if; 1446 mii = device_get_softc(sc->sf_miibus); 1447 1448 ptr = (u_int32_t *)&stats; 1449 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++) 1450 ptr[i] = csr_read_4(sc, SF_STATS_BASE + 1451 (i + sizeof(u_int32_t))); 1452 1453 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++) 1454 csr_write_4(sc, SF_STATS_BASE + 1455 (i + sizeof(u_int32_t)), 0); 1456 1457 ifp->if_collisions += stats.sf_tx_single_colls + 1458 stats.sf_tx_multi_colls + stats.sf_tx_excess_colls; 1459 1460 mii_tick(mii); 1461 if (!sc->sf_link) { 1462 mii_pollstat(mii); 1463 if (mii->mii_media_status & IFM_ACTIVE && 1464 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1465 sc->sf_link++; 1466 if (ifp->if_snd.ifq_head != NULL) 1467 sf_start(ifp); 1468 } 1469 1470 sc->sf_stat_ch = timeout(sf_stats_update, sc, hz); 1471 1472 SF_UNLOCK(sc); 1473 1474 return; 1475} 1476 1477static void sf_watchdog(ifp) 1478 struct ifnet *ifp; 1479{ 1480 struct sf_softc *sc; 1481 1482 sc = ifp->if_softc; 1483 1484 SF_LOCK(sc); 1485 1486 ifp->if_oerrors++; 1487 printf("sf%d: watchdog timeout\n", sc->sf_unit); 1488 1489 sf_stop(sc); 1490 sf_reset(sc); 1491 sf_init(sc); 1492 1493 if (ifp->if_snd.ifq_head != NULL) 1494 sf_start(ifp); 1495 1496 SF_UNLOCK(sc); 1497 1498 return; 1499} 1500 1501static void sf_shutdown(dev) 1502 device_t dev; 1503{ 1504 struct sf_softc *sc; 1505 1506 sc = device_get_softc(dev); 1507 1508 sf_stop(sc); 1509 1510 return; 1511} 1512