if_sf.c revision 71228
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/dev/sf/if_sf.c 71228 2001-01-19 01:59:14Z bmilekic $ 33 */ 34 35/* 36 * Adaptec AIC-6915 "Starfire" PCI fast ethernet driver for FreeBSD. 37 * Programming manual is available from: 38 * ftp.adaptec.com:/pub/BBS/userguides/aic6915_pg.pdf. 39 * 40 * Written by Bill Paul <wpaul@ctr.columbia.edu> 41 * Department of Electical Engineering 42 * Columbia University, New York City 43 */ 44 45/* 46 * The Adaptec AIC-6915 "Starfire" is a 64-bit 10/100 PCI ethernet 47 * controller designed with flexibility and reducing CPU load in mind. 48 * The Starfire offers high and low priority buffer queues, a 49 * producer/consumer index mechanism and several different buffer 50 * queue and completion queue descriptor types. Any one of a number 51 * of different driver designs can be used, depending on system and 52 * OS requirements. This driver makes use of type0 transmit frame 53 * descriptors (since BSD fragments packets across an mbuf chain) 54 * and two RX buffer queues prioritized on size (one queue for small 55 * frames that will fit into a single mbuf, another with full size 56 * mbuf clusters for everything else). The producer/consumer indexes 57 * and completion queues are also used. 58 * 59 * One downside to the Starfire has to do with alignment: buffer 60 * queues must be aligned on 256-byte boundaries, and receive buffers 61 * must be aligned on longword boundaries. The receive buffer alignment 62 * causes problems on the Alpha platform, where the packet payload 63 * should be longword aligned. There is no simple way around this. 64 * 65 * For receive filtering, the Starfire offers 16 perfect filter slots 66 * and a 512-bit hash table. 67 * 68 * The Starfire has no internal transceiver, relying instead on an 69 * external MII-based transceiver. Accessing registers on external 70 * PHYs is done through a special register map rather than with the 71 * usual bitbang MDIO method. 72 * 73 * Acesssing the registers on the Starfire is a little tricky. The 74 * Starfire has a 512K internal register space. When programmed for 75 * PCI memory mapped mode, the entire register space can be accessed 76 * directly. However in I/O space mode, only 256 bytes are directly 77 * mapped into PCI I/O space. The other registers can be accessed 78 * indirectly using the SF_INDIRECTIO_ADDR and SF_INDIRECTIO_DATA 79 * registers inside the 256-byte I/O window. 80 */ 81 82#include <sys/param.h> 83#include <sys/systm.h> 84#include <sys/sockio.h> 85#include <sys/mbuf.h> 86#include <sys/malloc.h> 87#include <sys/kernel.h> 88#include <sys/socket.h> 89 90#include <net/if.h> 91#include <net/if_arp.h> 92#include <net/ethernet.h> 93#include <net/if_dl.h> 94#include <net/if_media.h> 95 96#include <net/bpf.h> 97 98#include <vm/vm.h> /* for vtophys */ 99#include <vm/pmap.h> /* for vtophys */ 100#include <machine/bus_pio.h> 101#include <machine/bus_memio.h> 102#include <machine/bus.h> 103#include <machine/resource.h> 104#include <sys/bus.h> 105#include <sys/rman.h> 106 107#include <dev/mii/mii.h> 108#include <dev/mii/miivar.h> 109 110/* "controller miibus0" required. See GENERIC if you get errors here. */ 111#include "miibus_if.h" 112 113#include <pci/pcireg.h> 114#include <pci/pcivar.h> 115 116#define SF_USEIOSPACE 117 118#include <pci/if_sfreg.h> 119 120MODULE_DEPEND(sf, miibus, 1, 1, 1); 121 122#ifndef lint 123static const char rcsid[] = 124 "$FreeBSD: head/sys/dev/sf/if_sf.c 71228 2001-01-19 01:59:14Z bmilekic $"; 125#endif 126 127static struct sf_type sf_devs[] = { 128 { AD_VENDORID, AD_DEVICEID_STARFIRE, 129 "Adaptec AIC-6915 10/100BaseTX" }, 130 { 0, 0, NULL } 131}; 132 133static int sf_probe __P((device_t)); 134static int sf_attach __P((device_t)); 135static int sf_detach __P((device_t)); 136static void sf_intr __P((void *)); 137static void sf_stats_update __P((void *)); 138static void sf_rxeof __P((struct sf_softc *)); 139static void sf_txeof __P((struct sf_softc *)); 140static int sf_encap __P((struct sf_softc *, 141 struct sf_tx_bufdesc_type0 *, 142 struct mbuf *)); 143static void sf_start __P((struct ifnet *)); 144static int sf_ioctl __P((struct ifnet *, u_long, caddr_t)); 145static void sf_init __P((void *)); 146static void sf_stop __P((struct sf_softc *)); 147static void sf_watchdog __P((struct ifnet *)); 148static void sf_shutdown __P((device_t)); 149static int sf_ifmedia_upd __P((struct ifnet *)); 150static void sf_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 151static void sf_reset __P((struct sf_softc *)); 152static int sf_init_rx_ring __P((struct sf_softc *)); 153static void sf_init_tx_ring __P((struct sf_softc *)); 154static int sf_newbuf __P((struct sf_softc *, 155 struct sf_rx_bufdesc_type0 *, 156 struct mbuf *)); 157static void sf_setmulti __P((struct sf_softc *)); 158static int sf_setperf __P((struct sf_softc *, int, caddr_t)); 159static int sf_sethash __P((struct sf_softc *, caddr_t, int)); 160#ifdef notdef 161static int sf_setvlan __P((struct sf_softc *, int, u_int32_t)); 162#endif 163 164static u_int8_t sf_read_eeprom __P((struct sf_softc *, int)); 165static u_int32_t sf_calchash __P((caddr_t)); 166 167static int sf_miibus_readreg __P((device_t, int, int)); 168static int sf_miibus_writereg __P((device_t, int, int, int)); 169static void sf_miibus_statchg __P((device_t)); 170 171static u_int32_t csr_read_4 __P((struct sf_softc *, int)); 172static void csr_write_4 __P((struct sf_softc *, int, u_int32_t)); 173 174#ifdef SF_USEIOSPACE 175#define SF_RES SYS_RES_IOPORT 176#define SF_RID SF_PCI_LOIO 177#else 178#define SF_RES SYS_RES_MEMORY 179#define SF_RID SF_PCI_LOMEM 180#endif 181 182static device_method_t sf_methods[] = { 183 /* Device interface */ 184 DEVMETHOD(device_probe, sf_probe), 185 DEVMETHOD(device_attach, sf_attach), 186 DEVMETHOD(device_detach, sf_detach), 187 DEVMETHOD(device_shutdown, sf_shutdown), 188 189 /* bus interface */ 190 DEVMETHOD(bus_print_child, bus_generic_print_child), 191 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 192 193 /* MII interface */ 194 DEVMETHOD(miibus_readreg, sf_miibus_readreg), 195 DEVMETHOD(miibus_writereg, sf_miibus_writereg), 196 DEVMETHOD(miibus_statchg, sf_miibus_statchg), 197 198 { 0, 0 } 199}; 200 201static driver_t sf_driver = { 202 "sf", 203 sf_methods, 204 sizeof(struct sf_softc), 205}; 206 207static devclass_t sf_devclass; 208 209DRIVER_MODULE(if_sf, pci, sf_driver, sf_devclass, 0, 0); 210DRIVER_MODULE(miibus, sf, miibus_driver, miibus_devclass, 0, 0); 211 212#define SF_SETBIT(sc, reg, x) \ 213 csr_write_4(sc, reg, csr_read_4(sc, reg) | x) 214 215#define SF_CLRBIT(sc, reg, x) \ 216 csr_write_4(sc, reg, csr_read_4(sc, reg) & ~x) 217 218static u_int32_t csr_read_4(sc, reg) 219 struct sf_softc *sc; 220 int reg; 221{ 222 u_int32_t val; 223 224#ifdef SF_USEIOSPACE 225 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); 226 val = CSR_READ_4(sc, SF_INDIRECTIO_DATA); 227#else 228 val = CSR_READ_4(sc, (reg + SF_RMAP_INTREG_BASE)); 229#endif 230 231 return(val); 232} 233 234static u_int8_t sf_read_eeprom(sc, reg) 235 struct sf_softc *sc; 236 int reg; 237{ 238 u_int8_t val; 239 240 val = (csr_read_4(sc, SF_EEADDR_BASE + 241 (reg & 0xFFFFFFFC)) >> (8 * (reg & 3))) & 0xFF; 242 243 return(val); 244} 245 246static void csr_write_4(sc, reg, val) 247 struct sf_softc *sc; 248 int reg; 249 u_int32_t val; 250{ 251#ifdef SF_USEIOSPACE 252 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); 253 CSR_WRITE_4(sc, SF_INDIRECTIO_DATA, val); 254#else 255 CSR_WRITE_4(sc, (reg + SF_RMAP_INTREG_BASE), val); 256#endif 257 return; 258} 259 260static u_int32_t sf_calchash(addr) 261 caddr_t addr; 262{ 263 u_int32_t crc, carry; 264 int i, j; 265 u_int8_t c; 266 267 /* Compute CRC for the address value. */ 268 crc = 0xFFFFFFFF; /* initial value */ 269 270 for (i = 0; i < 6; i++) { 271 c = *(addr + i); 272 for (j = 0; j < 8; j++) { 273 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 274 crc <<= 1; 275 c >>= 1; 276 if (carry) 277 crc = (crc ^ 0x04c11db6) | carry; 278 } 279 } 280 281 /* return the filter bit position */ 282 return(crc >> 23 & 0x1FF); 283} 284 285/* 286 * Copy the address 'mac' into the perfect RX filter entry at 287 * offset 'idx.' The perfect filter only has 16 entries so do 288 * some sanity tests. 289 */ 290static int sf_setperf(sc, idx, mac) 291 struct sf_softc *sc; 292 int idx; 293 caddr_t mac; 294{ 295 u_int16_t *p; 296 297 if (idx < 0 || idx > SF_RXFILT_PERFECT_CNT) 298 return(EINVAL); 299 300 if (mac == NULL) 301 return(EINVAL); 302 303 p = (u_int16_t *)mac; 304 305 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 306 (idx * SF_RXFILT_PERFECT_SKIP), htons(p[2])); 307 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 308 (idx * SF_RXFILT_PERFECT_SKIP) + 4, htons(p[1])); 309 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 310 (idx * SF_RXFILT_PERFECT_SKIP) + 8, htons(p[0])); 311 312 return(0); 313} 314 315/* 316 * Set the bit in the 512-bit hash table that corresponds to the 317 * specified mac address 'mac.' If 'prio' is nonzero, update the 318 * priority hash table instead of the filter hash table. 319 */ 320static int sf_sethash(sc, mac, prio) 321 struct sf_softc *sc; 322 caddr_t mac; 323 int prio; 324{ 325 u_int32_t h = 0; 326 327 if (mac == NULL) 328 return(EINVAL); 329 330 h = sf_calchash(mac); 331 332 if (prio) { 333 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_PRIOOFF + 334 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); 335 } else { 336 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_ADDROFF + 337 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); 338 } 339 340 return(0); 341} 342 343#ifdef notdef 344/* 345 * Set a VLAN tag in the receive filter. 346 */ 347static int sf_setvlan(sc, idx, vlan) 348 struct sf_softc *sc; 349 int idx; 350 u_int32_t vlan; 351{ 352 if (idx < 0 || idx >> SF_RXFILT_HASH_CNT) 353 return(EINVAL); 354 355 csr_write_4(sc, SF_RXFILT_HASH_BASE + 356 (idx * SF_RXFILT_HASH_SKIP) + SF_RXFILT_HASH_VLANOFF, vlan); 357 358 return(0); 359} 360#endif 361 362static int sf_miibus_readreg(dev, phy, reg) 363 device_t dev; 364 int phy, reg; 365{ 366 struct sf_softc *sc; 367 int i; 368 u_int32_t val = 0; 369 370 sc = device_get_softc(dev); 371 372 for (i = 0; i < SF_TIMEOUT; i++) { 373 val = csr_read_4(sc, SF_PHY_REG(phy, reg)); 374 if (val & SF_MII_DATAVALID) 375 break; 376 } 377 378 if (i == SF_TIMEOUT) 379 return(0); 380 381 if ((val & 0x0000FFFF) == 0xFFFF) 382 return(0); 383 384 return(val & 0x0000FFFF); 385} 386 387static int sf_miibus_writereg(dev, phy, reg, val) 388 device_t dev; 389 int phy, reg, val; 390{ 391 struct sf_softc *sc; 392 int i; 393 int busy; 394 395 sc = device_get_softc(dev); 396 397 csr_write_4(sc, SF_PHY_REG(phy, reg), val); 398 399 for (i = 0; i < SF_TIMEOUT; i++) { 400 busy = csr_read_4(sc, SF_PHY_REG(phy, reg)); 401 if (!(busy & SF_MII_BUSY)) 402 break; 403 } 404 405 return(0); 406} 407 408static void sf_miibus_statchg(dev) 409 device_t dev; 410{ 411 struct sf_softc *sc; 412 struct mii_data *mii; 413 414 sc = device_get_softc(dev); 415 mii = device_get_softc(sc->sf_miibus); 416 417 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 418 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 419 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_FDX); 420 } else { 421 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 422 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_HDX); 423 } 424 425 return; 426} 427 428static void sf_setmulti(sc) 429 struct sf_softc *sc; 430{ 431 struct ifnet *ifp; 432 int i; 433 struct ifmultiaddr *ifma; 434 u_int8_t dummy[] = { 0, 0, 0, 0, 0, 0 }; 435 436 ifp = &sc->arpcom.ac_if; 437 438 /* First zot all the existing filters. */ 439 for (i = 1; i < SF_RXFILT_PERFECT_CNT; i++) 440 sf_setperf(sc, i, (char *)&dummy); 441 for (i = SF_RXFILT_HASH_BASE; 442 i < (SF_RXFILT_HASH_MAX + 1); i += 4) 443 csr_write_4(sc, i, 0); 444 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI); 445 446 /* Now program new ones. */ 447 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 448 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI); 449 } else { 450 i = 1; 451 /* First find the tail of the list. */ 452 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 453 ifma = ifma->ifma_link.le_next) { 454 if (ifma->ifma_link.le_next == NULL) 455 break; 456 } 457 /* Now traverse the list backwards. */ 458 for (; ifma != NULL && ifma != (void *)&ifp->if_multiaddrs; 459 ifma = (struct ifmultiaddr *)ifma->ifma_link.le_prev) { 460 if (ifma->ifma_addr->sa_family != AF_LINK) 461 continue; 462 /* 463 * Program the first 15 multicast groups 464 * into the perfect filter. For all others, 465 * use the hash table. 466 */ 467 if (i < SF_RXFILT_PERFECT_CNT) { 468 sf_setperf(sc, i, 469 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 470 i++; 471 continue; 472 } 473 474 sf_sethash(sc, 475 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 0); 476 } 477 } 478 479 return; 480} 481 482/* 483 * Set media options. 484 */ 485static int sf_ifmedia_upd(ifp) 486 struct ifnet *ifp; 487{ 488 struct sf_softc *sc; 489 struct mii_data *mii; 490 491 sc = ifp->if_softc; 492 mii = device_get_softc(sc->sf_miibus); 493 sc->sf_link = 0; 494 if (mii->mii_instance) { 495 struct mii_softc *miisc; 496 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 497 miisc = LIST_NEXT(miisc, mii_list)) 498 mii_phy_reset(miisc); 499 } 500 mii_mediachg(mii); 501 502 return(0); 503} 504 505/* 506 * Report current media status. 507 */ 508static void sf_ifmedia_sts(ifp, ifmr) 509 struct ifnet *ifp; 510 struct ifmediareq *ifmr; 511{ 512 struct sf_softc *sc; 513 struct mii_data *mii; 514 515 sc = ifp->if_softc; 516 mii = device_get_softc(sc->sf_miibus); 517 518 mii_pollstat(mii); 519 ifmr->ifm_active = mii->mii_media_active; 520 ifmr->ifm_status = mii->mii_media_status; 521 522 return; 523} 524 525static int sf_ioctl(ifp, command, data) 526 struct ifnet *ifp; 527 u_long command; 528 caddr_t data; 529{ 530 struct sf_softc *sc = ifp->if_softc; 531 struct ifreq *ifr = (struct ifreq *) data; 532 struct mii_data *mii; 533 int error = 0; 534 535 SF_LOCK(sc); 536 537 switch(command) { 538 case SIOCSIFADDR: 539 case SIOCGIFADDR: 540 case SIOCSIFMTU: 541 error = ether_ioctl(ifp, command, data); 542 break; 543 case SIOCSIFFLAGS: 544 if (ifp->if_flags & IFF_UP) { 545 if (ifp->if_flags & IFF_RUNNING && 546 ifp->if_flags & IFF_PROMISC && 547 !(sc->sf_if_flags & IFF_PROMISC)) { 548 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 549 } else if (ifp->if_flags & IFF_RUNNING && 550 !(ifp->if_flags & IFF_PROMISC) && 551 sc->sf_if_flags & IFF_PROMISC) { 552 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 553 } else if (!(ifp->if_flags & IFF_RUNNING)) 554 sf_init(sc); 555 } else { 556 if (ifp->if_flags & IFF_RUNNING) 557 sf_stop(sc); 558 } 559 sc->sf_if_flags = ifp->if_flags; 560 error = 0; 561 break; 562 case SIOCADDMULTI: 563 case SIOCDELMULTI: 564 sf_setmulti(sc); 565 error = 0; 566 break; 567 case SIOCGIFMEDIA: 568 case SIOCSIFMEDIA: 569 mii = device_get_softc(sc->sf_miibus); 570 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 571 break; 572 default: 573 error = EINVAL; 574 break; 575 } 576 577 SF_UNLOCK(sc); 578 579 return(error); 580} 581 582static void sf_reset(sc) 583 struct sf_softc *sc; 584{ 585 register int i; 586 587 csr_write_4(sc, SF_GEN_ETH_CTL, 0); 588 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 589 DELAY(1000); 590 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 591 592 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_RESET); 593 594 for (i = 0; i < SF_TIMEOUT; i++) { 595 DELAY(10); 596 if (!(csr_read_4(sc, SF_PCI_DEVCFG) & SF_PCIDEVCFG_RESET)) 597 break; 598 } 599 600 if (i == SF_TIMEOUT) 601 printf("sf%d: reset never completed!\n", sc->sf_unit); 602 603 /* Wait a little while for the chip to get its brains in order. */ 604 DELAY(1000); 605 return; 606} 607 608/* 609 * Probe for an Adaptec AIC-6915 chip. Check the PCI vendor and device 610 * IDs against our list and return a device name if we find a match. 611 * We also check the subsystem ID so that we can identify exactly which 612 * NIC has been found, if possible. 613 */ 614static int sf_probe(dev) 615 device_t dev; 616{ 617 struct sf_type *t; 618 619 t = sf_devs; 620 621 while(t->sf_name != NULL) { 622 if ((pci_get_vendor(dev) == t->sf_vid) && 623 (pci_get_device(dev) == t->sf_did)) { 624 switch((pci_read_config(dev, 625 SF_PCI_SUBVEN_ID, 4) >> 16) & 0xFFFF) { 626 case AD_SUBSYSID_62011_REV0: 627 case AD_SUBSYSID_62011_REV1: 628 device_set_desc(dev, 629 "Adaptec ANA-62011 10/100BaseTX"); 630 return(0); 631 break; 632 case AD_SUBSYSID_62022: 633 device_set_desc(dev, 634 "Adaptec ANA-62022 10/100BaseTX"); 635 return(0); 636 break; 637 case AD_SUBSYSID_62044_REV0: 638 case AD_SUBSYSID_62044_REV1: 639 device_set_desc(dev, 640 "Adaptec ANA-62044 10/100BaseTX"); 641 return(0); 642 break; 643 case AD_SUBSYSID_62020: 644 device_set_desc(dev, 645 "Adaptec ANA-62020 10/100BaseFX"); 646 return(0); 647 break; 648 case AD_SUBSYSID_69011: 649 device_set_desc(dev, 650 "Adaptec ANA-69011 10/100BaseTX"); 651 return(0); 652 break; 653 default: 654 device_set_desc(dev, t->sf_name); 655 return(0); 656 break; 657 } 658 } 659 t++; 660 } 661 662 return(ENXIO); 663} 664 665/* 666 * Attach the interface. Allocate softc structures, do ifmedia 667 * setup and ethernet/BPF attach. 668 */ 669static int sf_attach(dev) 670 device_t dev; 671{ 672 int i; 673 u_int32_t command; 674 struct sf_softc *sc; 675 struct ifnet *ifp; 676 int unit, rid, error = 0; 677 678 sc = device_get_softc(dev); 679 unit = device_get_unit(dev); 680 bzero(sc, sizeof(struct sf_softc)); 681 682 mtx_init(&sc->sf_mtx, device_get_nameunit(dev), MTX_DEF | MTX_RECURSE); 683 SF_LOCK(sc); 684 /* 685 * Handle power management nonsense. 686 */ 687 command = pci_read_config(dev, SF_PCI_CAPID, 4) & 0x000000FF; 688 if (command == 0x01) { 689 690 command = pci_read_config(dev, SF_PCI_PWRMGMTCTRL, 4); 691 if (command & SF_PSTATE_MASK) { 692 u_int32_t iobase, membase, irq; 693 694 /* Save important PCI config data. */ 695 iobase = pci_read_config(dev, SF_PCI_LOIO, 4); 696 membase = pci_read_config(dev, SF_PCI_LOMEM, 4); 697 irq = pci_read_config(dev, SF_PCI_INTLINE, 4); 698 699 /* Reset the power state. */ 700 printf("sf%d: chip is in D%d power mode " 701 "-- setting to D0\n", unit, command & SF_PSTATE_MASK); 702 command &= 0xFFFFFFFC; 703 pci_write_config(dev, SF_PCI_PWRMGMTCTRL, command, 4); 704 705 /* Restore PCI config data. */ 706 pci_write_config(dev, SF_PCI_LOIO, iobase, 4); 707 pci_write_config(dev, SF_PCI_LOMEM, membase, 4); 708 pci_write_config(dev, SF_PCI_INTLINE, irq, 4); 709 } 710 } 711 712 /* 713 * Map control/status registers. 714 */ 715 command = pci_read_config(dev, PCIR_COMMAND, 4); 716 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 717 pci_write_config(dev, PCIR_COMMAND, command, 4); 718 command = pci_read_config(dev, PCIR_COMMAND, 4); 719 720#ifdef SF_USEIOSPACE 721 if (!(command & PCIM_CMD_PORTEN)) { 722 printf("sf%d: failed to enable I/O ports!\n", unit); 723 error = ENXIO; 724 goto fail; 725 } 726#else 727 if (!(command & PCIM_CMD_MEMEN)) { 728 printf("sf%d: failed to enable memory mapping!\n", unit); 729 error = ENXIO; 730 goto fail; 731 } 732#endif 733 734 rid = SF_RID; 735 sc->sf_res = bus_alloc_resource(dev, SF_RES, &rid, 736 0, ~0, 1, RF_ACTIVE); 737 738 if (sc->sf_res == NULL) { 739 printf ("sf%d: couldn't map ports\n", unit); 740 error = ENXIO; 741 goto fail; 742 } 743 744 sc->sf_btag = rman_get_bustag(sc->sf_res); 745 sc->sf_bhandle = rman_get_bushandle(sc->sf_res); 746 747 /* Allocate interrupt */ 748 rid = 0; 749 sc->sf_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 750 RF_SHAREABLE | RF_ACTIVE); 751 752 if (sc->sf_irq == NULL) { 753 printf("sf%d: couldn't map interrupt\n", unit); 754 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 755 error = ENXIO; 756 goto fail; 757 } 758 759 error = bus_setup_intr(dev, sc->sf_irq, INTR_TYPE_NET, 760 sf_intr, sc, &sc->sf_intrhand); 761 762 if (error) { 763 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_res); 764 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 765 printf("sf%d: couldn't set up irq\n", unit); 766 goto fail; 767 } 768 769 callout_handle_init(&sc->sf_stat_ch); 770 /* Reset the adapter. */ 771 sf_reset(sc); 772 773 /* 774 * Get station address from the EEPROM. 775 */ 776 for (i = 0; i < ETHER_ADDR_LEN; i++) 777 sc->arpcom.ac_enaddr[i] = 778 sf_read_eeprom(sc, SF_EE_NODEADDR + ETHER_ADDR_LEN - i); 779 780 /* 781 * An Adaptec chip was detected. Inform the world. 782 */ 783 printf("sf%d: Ethernet address: %6D\n", unit, 784 sc->arpcom.ac_enaddr, ":"); 785 786 sc->sf_unit = unit; 787 788 /* Allocate the descriptor queues. */ 789 sc->sf_ldata = contigmalloc(sizeof(struct sf_list_data), M_DEVBUF, 790 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 791 792 if (sc->sf_ldata == NULL) { 793 printf("sf%d: no memory for list buffers!\n", unit); 794 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand); 795 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq); 796 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 797 error = ENXIO; 798 goto fail; 799 } 800 801 bzero(sc->sf_ldata, sizeof(struct sf_list_data)); 802 803 /* Do MII setup. */ 804 if (mii_phy_probe(dev, &sc->sf_miibus, 805 sf_ifmedia_upd, sf_ifmedia_sts)) { 806 printf("sf%d: MII without any phy!\n", sc->sf_unit); 807 contigfree(sc->sf_ldata,sizeof(struct sf_list_data),M_DEVBUF); 808 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand); 809 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq); 810 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 811 error = ENXIO; 812 goto fail; 813 } 814 815 ifp = &sc->arpcom.ac_if; 816 ifp->if_softc = sc; 817 ifp->if_unit = unit; 818 ifp->if_name = "sf"; 819 ifp->if_mtu = ETHERMTU; 820 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 821 ifp->if_ioctl = sf_ioctl; 822 ifp->if_output = ether_output; 823 ifp->if_start = sf_start; 824 ifp->if_watchdog = sf_watchdog; 825 ifp->if_init = sf_init; 826 ifp->if_baudrate = 10000000; 827 ifp->if_snd.ifq_maxlen = SF_TX_DLIST_CNT - 1; 828 829 /* 830 * Call MI attach routine. 831 */ 832 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 833 SF_UNLOCK(sc); 834 return(0); 835 836fail: 837 SF_UNLOCK(sc); 838 mtx_destroy(&sc->sf_mtx); 839 return(error); 840} 841 842static int sf_detach(dev) 843 device_t dev; 844{ 845 struct sf_softc *sc; 846 struct ifnet *ifp; 847 848 sc = device_get_softc(dev); 849 SF_LOCK(sc); 850 ifp = &sc->arpcom.ac_if; 851 852 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 853 sf_stop(sc); 854 855 bus_generic_detach(dev); 856 device_delete_child(dev, sc->sf_miibus); 857 858 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand); 859 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq); 860 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 861 862 contigfree(sc->sf_ldata, sizeof(struct sf_list_data), M_DEVBUF); 863 864 SF_UNLOCK(sc); 865 mtx_destroy(&sc->sf_mtx); 866 867 return(0); 868} 869 870static int sf_init_rx_ring(sc) 871 struct sf_softc *sc; 872{ 873 struct sf_list_data *ld; 874 int i; 875 876 ld = sc->sf_ldata; 877 878 bzero((char *)ld->sf_rx_dlist_big, 879 sizeof(struct sf_rx_bufdesc_type0) * SF_RX_DLIST_CNT); 880 bzero((char *)ld->sf_rx_clist, 881 sizeof(struct sf_rx_cmpdesc_type3) * SF_RX_CLIST_CNT); 882 883 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 884 if (sf_newbuf(sc, &ld->sf_rx_dlist_big[i], NULL) == ENOBUFS) 885 return(ENOBUFS); 886 } 887 888 return(0); 889} 890 891static void sf_init_tx_ring(sc) 892 struct sf_softc *sc; 893{ 894 struct sf_list_data *ld; 895 int i; 896 897 ld = sc->sf_ldata; 898 899 bzero((char *)ld->sf_tx_dlist, 900 sizeof(struct sf_tx_bufdesc_type0) * SF_TX_DLIST_CNT); 901 bzero((char *)ld->sf_tx_clist, 902 sizeof(struct sf_tx_cmpdesc_type0) * SF_TX_CLIST_CNT); 903 904 for (i = 0; i < SF_TX_DLIST_CNT; i++) 905 ld->sf_tx_dlist[i].sf_id = SF_TX_BUFDESC_ID; 906 for (i = 0; i < SF_TX_CLIST_CNT; i++) 907 ld->sf_tx_clist[i].sf_type = SF_TXCMPTYPE_TX; 908 909 ld->sf_tx_dlist[SF_TX_DLIST_CNT - 1].sf_end = 1; 910 sc->sf_tx_cnt = 0; 911 912 return; 913} 914 915static int sf_newbuf(sc, c, m) 916 struct sf_softc *sc; 917 struct sf_rx_bufdesc_type0 *c; 918 struct mbuf *m; 919{ 920 struct mbuf *m_new = NULL; 921 922 if (m == NULL) { 923 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 924 if (m_new == NULL) { 925 printf("sf%d: no memory for rx list -- " 926 "packet dropped!\n", sc->sf_unit); 927 return(ENOBUFS); 928 } 929 930 MCLGET(m_new, M_DONTWAIT); 931 if (!(m_new->m_flags & M_EXT)) { 932 printf("sf%d: no memory for rx list -- " 933 "packet dropped!\n", sc->sf_unit); 934 m_freem(m_new); 935 return(ENOBUFS); 936 } 937 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 938 } else { 939 m_new = m; 940 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 941 m_new->m_data = m_new->m_ext.ext_buf; 942 } 943 944 m_adj(m_new, sizeof(u_int64_t)); 945 946 c->sf_mbuf = m_new; 947 c->sf_addrlo = SF_RX_HOSTADDR(vtophys(mtod(m_new, caddr_t))); 948 c->sf_valid = 1; 949 950 return(0); 951} 952 953/* 954 * The starfire is programmed to use 'normal' mode for packet reception, 955 * which means we use the consumer/producer model for both the buffer 956 * descriptor queue and the completion descriptor queue. The only problem 957 * with this is that it involves a lot of register accesses: we have to 958 * read the RX completion consumer and producer indexes and the RX buffer 959 * producer index, plus the RX completion consumer and RX buffer producer 960 * indexes have to be updated. It would have been easier if Adaptec had 961 * put each index in a separate register, especially given that the damn 962 * NIC has a 512K register space. 963 * 964 * In spite of all the lovely features that Adaptec crammed into the 6915, 965 * it is marred by one truly stupid design flaw, which is that receive 966 * buffer addresses must be aligned on a longword boundary. This forces 967 * the packet payload to be unaligned, which is suboptimal on the x86 and 968 * completely unuseable on the Alpha. Our only recourse is to copy received 969 * packets into properly aligned buffers before handing them off. 970 */ 971 972static void sf_rxeof(sc) 973 struct sf_softc *sc; 974{ 975 struct ether_header *eh; 976 struct mbuf *m; 977 struct ifnet *ifp; 978 struct sf_rx_bufdesc_type0 *desc; 979 struct sf_rx_cmpdesc_type3 *cur_rx; 980 u_int32_t rxcons, rxprod; 981 int cmpprodidx, cmpconsidx, bufprodidx; 982 983 ifp = &sc->arpcom.ac_if; 984 985 rxcons = csr_read_4(sc, SF_CQ_CONSIDX); 986 rxprod = csr_read_4(sc, SF_RXDQ_PTR_Q1); 987 cmpprodidx = SF_IDX_LO(csr_read_4(sc, SF_CQ_PRODIDX)); 988 cmpconsidx = SF_IDX_LO(rxcons); 989 bufprodidx = SF_IDX_LO(rxprod); 990 991 while (cmpconsidx != cmpprodidx) { 992 struct mbuf *m0; 993 994 cur_rx = &sc->sf_ldata->sf_rx_clist[cmpconsidx]; 995 desc = &sc->sf_ldata->sf_rx_dlist_big[cur_rx->sf_endidx]; 996 m = desc->sf_mbuf; 997 SF_INC(cmpconsidx, SF_RX_CLIST_CNT); 998 SF_INC(bufprodidx, SF_RX_DLIST_CNT); 999 1000 if (!(cur_rx->sf_status1 & SF_RXSTAT1_OK)) { 1001 ifp->if_ierrors++; 1002 sf_newbuf(sc, desc, m); 1003 continue; 1004 } 1005 1006 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1007 cur_rx->sf_len + ETHER_ALIGN, 0, ifp, NULL); 1008 sf_newbuf(sc, desc, m); 1009 if (m0 == NULL) { 1010 ifp->if_ierrors++; 1011 continue; 1012 } 1013 m_adj(m0, ETHER_ALIGN); 1014 m = m0; 1015 1016 eh = mtod(m, struct ether_header *); 1017 ifp->if_ipackets++; 1018 1019 /* Remove header from mbuf and pass it on. */ 1020 m_adj(m, sizeof(struct ether_header)); 1021 ether_input(ifp, eh, m); 1022 } 1023 1024 csr_write_4(sc, SF_CQ_CONSIDX, 1025 (rxcons & ~SF_CQ_CONSIDX_RXQ1) | cmpconsidx); 1026 csr_write_4(sc, SF_RXDQ_PTR_Q1, 1027 (rxprod & ~SF_RXDQ_PRODIDX) | bufprodidx); 1028 1029 return; 1030} 1031 1032/* 1033 * Read the transmit status from the completion queue and release 1034 * mbufs. Note that the buffer descriptor index in the completion 1035 * descriptor is an offset from the start of the transmit buffer 1036 * descriptor list in bytes. This is important because the manual 1037 * gives the impression that it should match the producer/consumer 1038 * index, which is the offset in 8 byte blocks. 1039 */ 1040static void sf_txeof(sc) 1041 struct sf_softc *sc; 1042{ 1043 int txcons, cmpprodidx, cmpconsidx; 1044 struct sf_tx_cmpdesc_type1 *cur_cmp; 1045 struct sf_tx_bufdesc_type0 *cur_tx; 1046 struct ifnet *ifp; 1047 1048 ifp = &sc->arpcom.ac_if; 1049 1050 txcons = csr_read_4(sc, SF_CQ_CONSIDX); 1051 cmpprodidx = SF_IDX_HI(csr_read_4(sc, SF_CQ_PRODIDX)); 1052 cmpconsidx = SF_IDX_HI(txcons); 1053 1054 while (cmpconsidx != cmpprodidx) { 1055 cur_cmp = &sc->sf_ldata->sf_tx_clist[cmpconsidx]; 1056 cur_tx = &sc->sf_ldata->sf_tx_dlist[cur_cmp->sf_index >> 7]; 1057 SF_INC(cmpconsidx, SF_TX_CLIST_CNT); 1058 1059 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_OK) 1060 ifp->if_opackets++; 1061 else 1062 ifp->if_oerrors++; 1063 1064 sc->sf_tx_cnt--; 1065 if (cur_tx->sf_mbuf != NULL) { 1066 m_freem(cur_tx->sf_mbuf); 1067 cur_tx->sf_mbuf = NULL; 1068 } 1069 } 1070 1071 ifp->if_timer = 0; 1072 ifp->if_flags &= ~IFF_OACTIVE; 1073 1074 csr_write_4(sc, SF_CQ_CONSIDX, 1075 (txcons & ~SF_CQ_CONSIDX_TXQ) | 1076 ((cmpconsidx << 16) & 0xFFFF0000)); 1077 1078 return; 1079} 1080 1081static void sf_intr(arg) 1082 void *arg; 1083{ 1084 struct sf_softc *sc; 1085 struct ifnet *ifp; 1086 u_int32_t status; 1087 1088 sc = arg; 1089 SF_LOCK(sc); 1090 1091 ifp = &sc->arpcom.ac_if; 1092 1093 if (!(csr_read_4(sc, SF_ISR_SHADOW) & SF_ISR_PCIINT_ASSERTED)) { 1094 SF_UNLOCK(sc); 1095 return; 1096 } 1097 1098 /* Disable interrupts. */ 1099 csr_write_4(sc, SF_IMR, 0x00000000); 1100 1101 for (;;) { 1102 status = csr_read_4(sc, SF_ISR); 1103 if (status) 1104 csr_write_4(sc, SF_ISR, status); 1105 1106 if (!(status & SF_INTRS)) 1107 break; 1108 1109 if (status & SF_ISR_RXDQ1_DMADONE) 1110 sf_rxeof(sc); 1111 1112 if (status & SF_ISR_TX_TXDONE) 1113 sf_txeof(sc); 1114 1115 if (status & SF_ISR_ABNORMALINTR) { 1116 if (status & SF_ISR_STATSOFLOW) { 1117 untimeout(sf_stats_update, sc, 1118 sc->sf_stat_ch); 1119 sf_stats_update(sc); 1120 } else 1121 sf_init(sc); 1122 } 1123 } 1124 1125 /* Re-enable interrupts. */ 1126 csr_write_4(sc, SF_IMR, SF_INTRS); 1127 1128 if (ifp->if_snd.ifq_head != NULL) 1129 sf_start(ifp); 1130 1131 SF_UNLOCK(sc); 1132 return; 1133} 1134 1135static void sf_init(xsc) 1136 void *xsc; 1137{ 1138 struct sf_softc *sc; 1139 struct ifnet *ifp; 1140 struct mii_data *mii; 1141 int i; 1142 1143 sc = xsc; 1144 SF_LOCK(sc); 1145 ifp = &sc->arpcom.ac_if; 1146 mii = device_get_softc(sc->sf_miibus); 1147 1148 sf_stop(sc); 1149 sf_reset(sc); 1150 1151 /* Init all the receive filter registers */ 1152 for (i = SF_RXFILT_PERFECT_BASE; 1153 i < (SF_RXFILT_HASH_MAX + 1); i += 4) 1154 csr_write_4(sc, i, 0); 1155 1156 /* Empty stats counter registers. */ 1157 for (i = 0; i < sizeof(struct sf_stats)/sizeof(u_int32_t); i++) 1158 csr_write_4(sc, SF_STATS_BASE + 1159 (i + sizeof(u_int32_t)), 0); 1160 1161 /* Init our MAC address */ 1162 csr_write_4(sc, SF_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1163 csr_write_4(sc, SF_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1164 sf_setperf(sc, 0, (caddr_t)&sc->arpcom.ac_enaddr); 1165 1166 if (sf_init_rx_ring(sc) == ENOBUFS) { 1167 printf("sf%d: initialization failed: no " 1168 "memory for rx buffers\n", sc->sf_unit); 1169 SF_UNLOCK(sc); 1170 return; 1171 } 1172 1173 sf_init_tx_ring(sc); 1174 1175 csr_write_4(sc, SF_RXFILT, SF_PERFMODE_NORMAL|SF_HASHMODE_WITHVLAN); 1176 1177 /* If we want promiscuous mode, set the allframes bit. */ 1178 if (ifp->if_flags & IFF_PROMISC) { 1179 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 1180 } else { 1181 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 1182 } 1183 1184 if (ifp->if_flags & IFF_BROADCAST) { 1185 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_BROAD); 1186 } else { 1187 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_BROAD); 1188 } 1189 1190 /* 1191 * Load the multicast filter. 1192 */ 1193 sf_setmulti(sc); 1194 1195 /* Init the completion queue indexes */ 1196 csr_write_4(sc, SF_CQ_CONSIDX, 0); 1197 csr_write_4(sc, SF_CQ_PRODIDX, 0); 1198 1199 /* Init the RX completion queue */ 1200 csr_write_4(sc, SF_RXCQ_CTL_1, 1201 vtophys(sc->sf_ldata->sf_rx_clist) & SF_RXCQ_ADDR); 1202 SF_SETBIT(sc, SF_RXCQ_CTL_1, SF_RXCQTYPE_3); 1203 1204 /* Init RX DMA control. */ 1205 SF_SETBIT(sc, SF_RXDMA_CTL, SF_RXDMA_REPORTBADPKTS); 1206 1207 /* Init the RX buffer descriptor queue. */ 1208 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 1209 vtophys(sc->sf_ldata->sf_rx_dlist_big)); 1210 csr_write_4(sc, SF_RXDQ_CTL_1, (MCLBYTES << 16) | SF_DESCSPACE_16BYTES); 1211 csr_write_4(sc, SF_RXDQ_PTR_Q1, SF_RX_DLIST_CNT - 1); 1212 1213 /* Init the TX completion queue */ 1214 csr_write_4(sc, SF_TXCQ_CTL, 1215 vtophys(sc->sf_ldata->sf_tx_clist) & SF_RXCQ_ADDR); 1216 1217 /* Init the TX buffer descriptor queue. */ 1218 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 1219 vtophys(sc->sf_ldata->sf_tx_dlist)); 1220 SF_SETBIT(sc, SF_TX_FRAMCTL, SF_TXFRMCTL_CPLAFTERTX); 1221 csr_write_4(sc, SF_TXDQ_CTL, 1222 SF_TXBUFDESC_TYPE0|SF_TXMINSPACE_128BYTES|SF_TXSKIPLEN_8BYTES); 1223 SF_SETBIT(sc, SF_TXDQ_CTL, SF_TXDQCTL_NODMACMP); 1224 1225 /* Enable autopadding of short TX frames. */ 1226 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_AUTOPAD); 1227 1228 /* Enable interrupts. */ 1229 csr_write_4(sc, SF_IMR, SF_INTRS); 1230 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_INTR_ENB); 1231 1232 /* Enable the RX and TX engines. */ 1233 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_RX_ENB|SF_ETHCTL_RXDMA_ENB); 1234 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_TX_ENB|SF_ETHCTL_TXDMA_ENB); 1235 1236 /*mii_mediachg(mii);*/ 1237 sf_ifmedia_upd(ifp); 1238 1239 ifp->if_flags |= IFF_RUNNING; 1240 ifp->if_flags &= ~IFF_OACTIVE; 1241 1242 sc->sf_stat_ch = timeout(sf_stats_update, sc, hz); 1243 1244 SF_UNLOCK(sc); 1245 1246 return; 1247} 1248 1249static int sf_encap(sc, c, m_head) 1250 struct sf_softc *sc; 1251 struct sf_tx_bufdesc_type0 *c; 1252 struct mbuf *m_head; 1253{ 1254 int frag = 0; 1255 struct sf_frag *f = NULL; 1256 struct mbuf *m; 1257 1258 m = m_head; 1259 1260 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1261 if (m->m_len != 0) { 1262 if (frag == SF_MAXFRAGS) 1263 break; 1264 f = &c->sf_frags[frag]; 1265 if (frag == 0) 1266 f->sf_pktlen = m_head->m_pkthdr.len; 1267 f->sf_fraglen = m->m_len; 1268 f->sf_addr = vtophys(mtod(m, vm_offset_t)); 1269 frag++; 1270 } 1271 } 1272 1273 if (m != NULL) { 1274 struct mbuf *m_new = NULL; 1275 1276 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1277 if (m_new == NULL) { 1278 printf("sf%d: no memory for tx list", sc->sf_unit); 1279 return(1); 1280 } 1281 1282 if (m_head->m_pkthdr.len > MHLEN) { 1283 MCLGET(m_new, M_DONTWAIT); 1284 if (!(m_new->m_flags & M_EXT)) { 1285 m_freem(m_new); 1286 printf("sf%d: no memory for tx list", 1287 sc->sf_unit); 1288 return(1); 1289 } 1290 } 1291 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1292 mtod(m_new, caddr_t)); 1293 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1294 m_freem(m_head); 1295 m_head = m_new; 1296 f = &c->sf_frags[0]; 1297 f->sf_fraglen = f->sf_pktlen = m_head->m_pkthdr.len; 1298 f->sf_addr = vtophys(mtod(m_head, caddr_t)); 1299 frag = 1; 1300 } 1301 1302 c->sf_mbuf = m_head; 1303 c->sf_id = SF_TX_BUFDESC_ID; 1304 c->sf_fragcnt = frag; 1305 c->sf_intr = 1; 1306 c->sf_caltcp = 0; 1307 c->sf_crcen = 1; 1308 1309 return(0); 1310} 1311 1312static void sf_start(ifp) 1313 struct ifnet *ifp; 1314{ 1315 struct sf_softc *sc; 1316 struct sf_tx_bufdesc_type0 *cur_tx = NULL; 1317 struct mbuf *m_head = NULL; 1318 int i, txprod; 1319 1320 sc = ifp->if_softc; 1321 SF_LOCK(sc); 1322 1323 if (!sc->sf_link) { 1324 SF_UNLOCK(sc); 1325 return; 1326 } 1327 1328 if (ifp->if_flags & IFF_OACTIVE) { 1329 SF_UNLOCK(sc); 1330 return; 1331 } 1332 1333 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX); 1334 i = SF_IDX_HI(txprod) >> 4; 1335 1336 while(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf == NULL) { 1337 IF_DEQUEUE(&ifp->if_snd, m_head); 1338 if (m_head == NULL) 1339 break; 1340 1341 cur_tx = &sc->sf_ldata->sf_tx_dlist[i]; 1342 sf_encap(sc, cur_tx, m_head); 1343 1344 /* 1345 * If there's a BPF listener, bounce a copy of this frame 1346 * to him. 1347 */ 1348 if (ifp->if_bpf) 1349 bpf_mtap(ifp, m_head); 1350 1351 SF_INC(i, SF_TX_DLIST_CNT); 1352 sc->sf_tx_cnt++; 1353 if (sc->sf_tx_cnt == (SF_TX_DLIST_CNT - 2)) 1354 break; 1355 } 1356 1357 if (cur_tx == NULL) { 1358 SF_UNLOCK(sc); 1359 return; 1360 } 1361 1362 /* Transmit */ 1363 csr_write_4(sc, SF_TXDQ_PRODIDX, 1364 (txprod & ~SF_TXDQ_PRODIDX_HIPRIO) | 1365 ((i << 20) & 0xFFFF0000)); 1366 1367 ifp->if_timer = 5; 1368 1369 SF_UNLOCK(sc); 1370 1371 return; 1372} 1373 1374static void sf_stop(sc) 1375 struct sf_softc *sc; 1376{ 1377 int i; 1378 struct ifnet *ifp; 1379 1380 SF_LOCK(sc); 1381 1382 ifp = &sc->arpcom.ac_if; 1383 1384 untimeout(sf_stats_update, sc, sc->sf_stat_ch); 1385 1386 csr_write_4(sc, SF_GEN_ETH_CTL, 0); 1387 csr_write_4(sc, SF_CQ_CONSIDX, 0); 1388 csr_write_4(sc, SF_CQ_PRODIDX, 0); 1389 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 0); 1390 csr_write_4(sc, SF_RXDQ_CTL_1, 0); 1391 csr_write_4(sc, SF_RXDQ_PTR_Q1, 0); 1392 csr_write_4(sc, SF_TXCQ_CTL, 0); 1393 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 0); 1394 csr_write_4(sc, SF_TXDQ_CTL, 0); 1395 sf_reset(sc); 1396 1397 sc->sf_link = 0; 1398 1399 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 1400 if (sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf != NULL) { 1401 m_freem(sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf); 1402 sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf = NULL; 1403 } 1404 } 1405 1406 for (i = 0; i < SF_TX_DLIST_CNT; i++) { 1407 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) { 1408 m_freem(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf); 1409 sc->sf_ldata->sf_tx_dlist[i].sf_mbuf = NULL; 1410 } 1411 } 1412 1413 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 1414 SF_UNLOCK(sc); 1415 1416 return; 1417} 1418 1419/* 1420 * Note: it is important that this function not be interrupted. We 1421 * use a two-stage register access scheme: if we are interrupted in 1422 * between setting the indirect address register and reading from the 1423 * indirect data register, the contents of the address register could 1424 * be changed out from under us. 1425 */ 1426static void sf_stats_update(xsc) 1427 void *xsc; 1428{ 1429 struct sf_softc *sc; 1430 struct ifnet *ifp; 1431 struct mii_data *mii; 1432 struct sf_stats stats; 1433 u_int32_t *ptr; 1434 int i; 1435 1436 sc = xsc; 1437 SF_LOCK(sc); 1438 ifp = &sc->arpcom.ac_if; 1439 mii = device_get_softc(sc->sf_miibus); 1440 1441 ptr = (u_int32_t *)&stats; 1442 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++) 1443 ptr[i] = csr_read_4(sc, SF_STATS_BASE + 1444 (i + sizeof(u_int32_t))); 1445 1446 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++) 1447 csr_write_4(sc, SF_STATS_BASE + 1448 (i + sizeof(u_int32_t)), 0); 1449 1450 ifp->if_collisions += stats.sf_tx_single_colls + 1451 stats.sf_tx_multi_colls + stats.sf_tx_excess_colls; 1452 1453 mii_tick(mii); 1454 if (!sc->sf_link) { 1455 mii_pollstat(mii); 1456 if (mii->mii_media_status & IFM_ACTIVE && 1457 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1458 sc->sf_link++; 1459 if (ifp->if_snd.ifq_head != NULL) 1460 sf_start(ifp); 1461 } 1462 1463 sc->sf_stat_ch = timeout(sf_stats_update, sc, hz); 1464 1465 SF_UNLOCK(sc); 1466 1467 return; 1468} 1469 1470static void sf_watchdog(ifp) 1471 struct ifnet *ifp; 1472{ 1473 struct sf_softc *sc; 1474 1475 sc = ifp->if_softc; 1476 1477 SF_LOCK(sc); 1478 1479 ifp->if_oerrors++; 1480 printf("sf%d: watchdog timeout\n", sc->sf_unit); 1481 1482 sf_stop(sc); 1483 sf_reset(sc); 1484 sf_init(sc); 1485 1486 if (ifp->if_snd.ifq_head != NULL) 1487 sf_start(ifp); 1488 1489 SF_UNLOCK(sc); 1490 1491 return; 1492} 1493 1494static void sf_shutdown(dev) 1495 device_t dev; 1496{ 1497 struct sf_softc *sc; 1498 1499 sc = device_get_softc(dev); 1500 1501 sf_stop(sc); 1502 1503 return; 1504} 1505