if_sf.c revision 67087
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/dev/sf/if_sf.c 67087 2000-10-13 17:54:19Z wpaul $ 33 */ 34 35/* 36 * Adaptec AIC-6915 "Starfire" PCI fast ethernet driver for FreeBSD. 37 * Programming manual is available from: 38 * ftp.adaptec.com:/pub/BBS/userguides/aic6915_pg.pdf. 39 * 40 * Written by Bill Paul <wpaul@ctr.columbia.edu> 41 * Department of Electical Engineering 42 * Columbia University, New York City 43 */ 44 45/* 46 * The Adaptec AIC-6915 "Starfire" is a 64-bit 10/100 PCI ethernet 47 * controller designed with flexibility and reducing CPU load in mind. 48 * The Starfire offers high and low priority buffer queues, a 49 * producer/consumer index mechanism and several different buffer 50 * queue and completion queue descriptor types. Any one of a number 51 * of different driver designs can be used, depending on system and 52 * OS requirements. This driver makes use of type0 transmit frame 53 * descriptors (since BSD fragments packets across an mbuf chain) 54 * and two RX buffer queues prioritized on size (one queue for small 55 * frames that will fit into a single mbuf, another with full size 56 * mbuf clusters for everything else). The producer/consumer indexes 57 * and completion queues are also used. 58 * 59 * One downside to the Starfire has to do with alignment: buffer 60 * queues must be aligned on 256-byte boundaries, and receive buffers 61 * must be aligned on longword boundaries. The receive buffer alignment 62 * causes problems on the Alpha platform, where the packet payload 63 * should be longword aligned. There is no simple way around this. 64 * 65 * For receive filtering, the Starfire offers 16 perfect filter slots 66 * and a 512-bit hash table. 67 * 68 * The Starfire has no internal transceiver, relying instead on an 69 * external MII-based transceiver. Accessing registers on external 70 * PHYs is done through a special register map rather than with the 71 * usual bitbang MDIO method. 72 * 73 * Acesssing the registers on the Starfire is a little tricky. The 74 * Starfire has a 512K internal register space. When programmed for 75 * PCI memory mapped mode, the entire register space can be accessed 76 * directly. However in I/O space mode, only 256 bytes are directly 77 * mapped into PCI I/O space. The other registers can be accessed 78 * indirectly using the SF_INDIRECTIO_ADDR and SF_INDIRECTIO_DATA 79 * registers inside the 256-byte I/O window. 80 */ 81 82#include <sys/param.h> 83#include <sys/systm.h> 84#include <sys/sockio.h> 85#include <sys/mbuf.h> 86#include <sys/malloc.h> 87#include <sys/kernel.h> 88#include <sys/socket.h> 89 90#include <net/if.h> 91#include <net/if_arp.h> 92#include <net/ethernet.h> 93#include <net/if_dl.h> 94#include <net/if_media.h> 95 96#include <net/bpf.h> 97 98#include <vm/vm.h> /* for vtophys */ 99#include <vm/pmap.h> /* for vtophys */ 100#include <machine/clock.h> /* for DELAY */ 101#include <machine/bus_pio.h> 102#include <machine/bus_memio.h> 103#include <machine/bus.h> 104#include <machine/resource.h> 105#include <sys/bus.h> 106#include <sys/rman.h> 107 108#include <dev/mii/mii.h> 109#include <dev/mii/miivar.h> 110 111/* "controller miibus0" required. See GENERIC if you get errors here. */ 112#include "miibus_if.h" 113 114#include <pci/pcireg.h> 115#include <pci/pcivar.h> 116 117#define SF_USEIOSPACE 118 119#include <pci/if_sfreg.h> 120 121MODULE_DEPEND(sf, miibus, 1, 1, 1); 122 123#ifndef lint 124static const char rcsid[] = 125 "$FreeBSD: head/sys/dev/sf/if_sf.c 67087 2000-10-13 17:54:19Z wpaul $"; 126#endif 127 128static struct sf_type sf_devs[] = { 129 { AD_VENDORID, AD_DEVICEID_STARFIRE, 130 "Adaptec AIC-6915 10/100BaseTX" }, 131 { 0, 0, NULL } 132}; 133 134static int sf_probe __P((device_t)); 135static int sf_attach __P((device_t)); 136static int sf_detach __P((device_t)); 137static void sf_intr __P((void *)); 138static void sf_stats_update __P((void *)); 139static void sf_rxeof __P((struct sf_softc *)); 140static void sf_txeof __P((struct sf_softc *)); 141static int sf_encap __P((struct sf_softc *, 142 struct sf_tx_bufdesc_type0 *, 143 struct mbuf *)); 144static void sf_start __P((struct ifnet *)); 145static int sf_ioctl __P((struct ifnet *, u_long, caddr_t)); 146static void sf_init __P((void *)); 147static void sf_stop __P((struct sf_softc *)); 148static void sf_watchdog __P((struct ifnet *)); 149static void sf_shutdown __P((device_t)); 150static int sf_ifmedia_upd __P((struct ifnet *)); 151static void sf_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 152static void sf_reset __P((struct sf_softc *)); 153static int sf_init_rx_ring __P((struct sf_softc *)); 154static void sf_init_tx_ring __P((struct sf_softc *)); 155static int sf_newbuf __P((struct sf_softc *, 156 struct sf_rx_bufdesc_type0 *, 157 struct mbuf *)); 158static void sf_setmulti __P((struct sf_softc *)); 159static int sf_setperf __P((struct sf_softc *, int, caddr_t)); 160static int sf_sethash __P((struct sf_softc *, caddr_t, int)); 161#ifdef notdef 162static int sf_setvlan __P((struct sf_softc *, int, u_int32_t)); 163#endif 164 165static u_int8_t sf_read_eeprom __P((struct sf_softc *, int)); 166static u_int32_t sf_calchash __P((caddr_t)); 167 168static int sf_miibus_readreg __P((device_t, int, int)); 169static int sf_miibus_writereg __P((device_t, int, int, int)); 170static void sf_miibus_statchg __P((device_t)); 171 172static u_int32_t csr_read_4 __P((struct sf_softc *, int)); 173static void csr_write_4 __P((struct sf_softc *, int, u_int32_t)); 174 175#ifdef SF_USEIOSPACE 176#define SF_RES SYS_RES_IOPORT 177#define SF_RID SF_PCI_LOIO 178#else 179#define SF_RES SYS_RES_MEMORY 180#define SF_RID SF_PCI_LOMEM 181#endif 182 183static device_method_t sf_methods[] = { 184 /* Device interface */ 185 DEVMETHOD(device_probe, sf_probe), 186 DEVMETHOD(device_attach, sf_attach), 187 DEVMETHOD(device_detach, sf_detach), 188 DEVMETHOD(device_shutdown, sf_shutdown), 189 190 /* bus interface */ 191 DEVMETHOD(bus_print_child, bus_generic_print_child), 192 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 193 194 /* MII interface */ 195 DEVMETHOD(miibus_readreg, sf_miibus_readreg), 196 DEVMETHOD(miibus_writereg, sf_miibus_writereg), 197 DEVMETHOD(miibus_statchg, sf_miibus_statchg), 198 199 { 0, 0 } 200}; 201 202static driver_t sf_driver = { 203 "sf", 204 sf_methods, 205 sizeof(struct sf_softc), 206}; 207 208static devclass_t sf_devclass; 209 210DRIVER_MODULE(if_sf, pci, sf_driver, sf_devclass, 0, 0); 211DRIVER_MODULE(miibus, sf, miibus_driver, miibus_devclass, 0, 0); 212 213#define SF_SETBIT(sc, reg, x) \ 214 csr_write_4(sc, reg, csr_read_4(sc, reg) | x) 215 216#define SF_CLRBIT(sc, reg, x) \ 217 csr_write_4(sc, reg, csr_read_4(sc, reg) & ~x) 218 219static u_int32_t csr_read_4(sc, reg) 220 struct sf_softc *sc; 221 int reg; 222{ 223 u_int32_t val; 224 225#ifdef SF_USEIOSPACE 226 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); 227 val = CSR_READ_4(sc, SF_INDIRECTIO_DATA); 228#else 229 val = CSR_READ_4(sc, (reg + SF_RMAP_INTREG_BASE)); 230#endif 231 232 return(val); 233} 234 235static u_int8_t sf_read_eeprom(sc, reg) 236 struct sf_softc *sc; 237 int reg; 238{ 239 u_int8_t val; 240 241 val = (csr_read_4(sc, SF_EEADDR_BASE + 242 (reg & 0xFFFFFFFC)) >> (8 * (reg & 3))) & 0xFF; 243 244 return(val); 245} 246 247static void csr_write_4(sc, reg, val) 248 struct sf_softc *sc; 249 int reg; 250 u_int32_t val; 251{ 252#ifdef SF_USEIOSPACE 253 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); 254 CSR_WRITE_4(sc, SF_INDIRECTIO_DATA, val); 255#else 256 CSR_WRITE_4(sc, (reg + SF_RMAP_INTREG_BASE), val); 257#endif 258 return; 259} 260 261static u_int32_t sf_calchash(addr) 262 caddr_t addr; 263{ 264 u_int32_t crc, carry; 265 int i, j; 266 u_int8_t c; 267 268 /* Compute CRC for the address value. */ 269 crc = 0xFFFFFFFF; /* initial value */ 270 271 for (i = 0; i < 6; i++) { 272 c = *(addr + i); 273 for (j = 0; j < 8; j++) { 274 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 275 crc <<= 1; 276 c >>= 1; 277 if (carry) 278 crc = (crc ^ 0x04c11db6) | carry; 279 } 280 } 281 282 /* return the filter bit position */ 283 return(crc >> 23 & 0x1FF); 284} 285 286/* 287 * Copy the address 'mac' into the perfect RX filter entry at 288 * offset 'idx.' The perfect filter only has 16 entries so do 289 * some sanity tests. 290 */ 291static int sf_setperf(sc, idx, mac) 292 struct sf_softc *sc; 293 int idx; 294 caddr_t mac; 295{ 296 u_int16_t *p; 297 298 if (idx < 0 || idx > SF_RXFILT_PERFECT_CNT) 299 return(EINVAL); 300 301 if (mac == NULL) 302 return(EINVAL); 303 304 p = (u_int16_t *)mac; 305 306 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 307 (idx * SF_RXFILT_PERFECT_SKIP), htons(p[2])); 308 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 309 (idx * SF_RXFILT_PERFECT_SKIP) + 4, htons(p[1])); 310 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 311 (idx * SF_RXFILT_PERFECT_SKIP) + 8, htons(p[0])); 312 313 return(0); 314} 315 316/* 317 * Set the bit in the 512-bit hash table that corresponds to the 318 * specified mac address 'mac.' If 'prio' is nonzero, update the 319 * priority hash table instead of the filter hash table. 320 */ 321static int sf_sethash(sc, mac, prio) 322 struct sf_softc *sc; 323 caddr_t mac; 324 int prio; 325{ 326 u_int32_t h = 0; 327 328 if (mac == NULL) 329 return(EINVAL); 330 331 h = sf_calchash(mac); 332 333 if (prio) { 334 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_PRIOOFF + 335 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); 336 } else { 337 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_ADDROFF + 338 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); 339 } 340 341 return(0); 342} 343 344#ifdef notdef 345/* 346 * Set a VLAN tag in the receive filter. 347 */ 348static int sf_setvlan(sc, idx, vlan) 349 struct sf_softc *sc; 350 int idx; 351 u_int32_t vlan; 352{ 353 if (idx < 0 || idx >> SF_RXFILT_HASH_CNT) 354 return(EINVAL); 355 356 csr_write_4(sc, SF_RXFILT_HASH_BASE + 357 (idx * SF_RXFILT_HASH_SKIP) + SF_RXFILT_HASH_VLANOFF, vlan); 358 359 return(0); 360} 361#endif 362 363static int sf_miibus_readreg(dev, phy, reg) 364 device_t dev; 365 int phy, reg; 366{ 367 struct sf_softc *sc; 368 int i; 369 u_int32_t val = 0; 370 371 sc = device_get_softc(dev); 372 373 for (i = 0; i < SF_TIMEOUT; i++) { 374 val = csr_read_4(sc, SF_PHY_REG(phy, reg)); 375 if (val & SF_MII_DATAVALID) 376 break; 377 } 378 379 if (i == SF_TIMEOUT) 380 return(0); 381 382 if ((val & 0x0000FFFF) == 0xFFFF) 383 return(0); 384 385 return(val & 0x0000FFFF); 386} 387 388static int sf_miibus_writereg(dev, phy, reg, val) 389 device_t dev; 390 int phy, reg, val; 391{ 392 struct sf_softc *sc; 393 int i; 394 int busy; 395 396 sc = device_get_softc(dev); 397 398 csr_write_4(sc, SF_PHY_REG(phy, reg), val); 399 400 for (i = 0; i < SF_TIMEOUT; i++) { 401 busy = csr_read_4(sc, SF_PHY_REG(phy, reg)); 402 if (!(busy & SF_MII_BUSY)) 403 break; 404 } 405 406 return(0); 407} 408 409static void sf_miibus_statchg(dev) 410 device_t dev; 411{ 412 struct sf_softc *sc; 413 struct mii_data *mii; 414 415 sc = device_get_softc(dev); 416 mii = device_get_softc(sc->sf_miibus); 417 418 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 419 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 420 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_FDX); 421 } else { 422 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 423 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_HDX); 424 } 425 426 return; 427} 428 429static void sf_setmulti(sc) 430 struct sf_softc *sc; 431{ 432 struct ifnet *ifp; 433 int i; 434 struct ifmultiaddr *ifma; 435 u_int8_t dummy[] = { 0, 0, 0, 0, 0, 0 }; 436 437 ifp = &sc->arpcom.ac_if; 438 439 /* First zot all the existing filters. */ 440 for (i = 1; i < SF_RXFILT_PERFECT_CNT; i++) 441 sf_setperf(sc, i, (char *)&dummy); 442 for (i = SF_RXFILT_HASH_BASE; 443 i < (SF_RXFILT_HASH_MAX + 1); i += 4) 444 csr_write_4(sc, i, 0); 445 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI); 446 447 /* Now program new ones. */ 448 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 449 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI); 450 } else { 451 i = 1; 452 /* First find the tail of the list. */ 453 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 454 ifma = ifma->ifma_link.le_next) { 455 if (ifma->ifma_link.le_next == NULL) 456 break; 457 } 458 /* Now traverse the list backwards. */ 459 for (; ifma != NULL && ifma != (void *)&ifp->if_multiaddrs; 460 ifma = (struct ifmultiaddr *)ifma->ifma_link.le_prev) { 461 if (ifma->ifma_addr->sa_family != AF_LINK) 462 continue; 463 /* 464 * Program the first 15 multicast groups 465 * into the perfect filter. For all others, 466 * use the hash table. 467 */ 468 if (i < SF_RXFILT_PERFECT_CNT) { 469 sf_setperf(sc, i, 470 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 471 i++; 472 continue; 473 } 474 475 sf_sethash(sc, 476 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 0); 477 } 478 } 479 480 return; 481} 482 483/* 484 * Set media options. 485 */ 486static int sf_ifmedia_upd(ifp) 487 struct ifnet *ifp; 488{ 489 struct sf_softc *sc; 490 struct mii_data *mii; 491 492 sc = ifp->if_softc; 493 mii = device_get_softc(sc->sf_miibus); 494 sc->sf_link = 0; 495 if (mii->mii_instance) { 496 struct mii_softc *miisc; 497 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 498 miisc = LIST_NEXT(miisc, mii_list)) 499 mii_phy_reset(miisc); 500 } 501 mii_mediachg(mii); 502 503 return(0); 504} 505 506/* 507 * Report current media status. 508 */ 509static void sf_ifmedia_sts(ifp, ifmr) 510 struct ifnet *ifp; 511 struct ifmediareq *ifmr; 512{ 513 struct sf_softc *sc; 514 struct mii_data *mii; 515 516 sc = ifp->if_softc; 517 mii = device_get_softc(sc->sf_miibus); 518 519 mii_pollstat(mii); 520 ifmr->ifm_active = mii->mii_media_active; 521 ifmr->ifm_status = mii->mii_media_status; 522 523 return; 524} 525 526static int sf_ioctl(ifp, command, data) 527 struct ifnet *ifp; 528 u_long command; 529 caddr_t data; 530{ 531 struct sf_softc *sc = ifp->if_softc; 532 struct ifreq *ifr = (struct ifreq *) data; 533 struct mii_data *mii; 534 int error = 0; 535 536 SF_LOCK(sc); 537 538 switch(command) { 539 case SIOCSIFADDR: 540 case SIOCGIFADDR: 541 case SIOCSIFMTU: 542 error = ether_ioctl(ifp, command, data); 543 break; 544 case SIOCSIFFLAGS: 545 if (ifp->if_flags & IFF_UP) { 546 if (ifp->if_flags & IFF_RUNNING && 547 ifp->if_flags & IFF_PROMISC && 548 !(sc->sf_if_flags & IFF_PROMISC)) { 549 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 550 } else if (ifp->if_flags & IFF_RUNNING && 551 !(ifp->if_flags & IFF_PROMISC) && 552 sc->sf_if_flags & IFF_PROMISC) { 553 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 554 } else if (!(ifp->if_flags & IFF_RUNNING)) 555 sf_init(sc); 556 } else { 557 if (ifp->if_flags & IFF_RUNNING) 558 sf_stop(sc); 559 } 560 sc->sf_if_flags = ifp->if_flags; 561 error = 0; 562 break; 563 case SIOCADDMULTI: 564 case SIOCDELMULTI: 565 sf_setmulti(sc); 566 error = 0; 567 break; 568 case SIOCGIFMEDIA: 569 case SIOCSIFMEDIA: 570 mii = device_get_softc(sc->sf_miibus); 571 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 572 break; 573 default: 574 error = EINVAL; 575 break; 576 } 577 578 SF_UNLOCK(sc); 579 580 return(error); 581} 582 583static void sf_reset(sc) 584 struct sf_softc *sc; 585{ 586 register int i; 587 588 csr_write_4(sc, SF_GEN_ETH_CTL, 0); 589 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 590 DELAY(1000); 591 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 592 593 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_RESET); 594 595 for (i = 0; i < SF_TIMEOUT; i++) { 596 DELAY(10); 597 if (!(csr_read_4(sc, SF_PCI_DEVCFG) & SF_PCIDEVCFG_RESET)) 598 break; 599 } 600 601 if (i == SF_TIMEOUT) 602 printf("sf%d: reset never completed!\n", sc->sf_unit); 603 604 /* Wait a little while for the chip to get its brains in order. */ 605 DELAY(1000); 606 return; 607} 608 609/* 610 * Probe for an Adaptec AIC-6915 chip. Check the PCI vendor and device 611 * IDs against our list and return a device name if we find a match. 612 * We also check the subsystem ID so that we can identify exactly which 613 * NIC has been found, if possible. 614 */ 615static int sf_probe(dev) 616 device_t dev; 617{ 618 struct sf_type *t; 619 620 t = sf_devs; 621 622 while(t->sf_name != NULL) { 623 if ((pci_get_vendor(dev) == t->sf_vid) && 624 (pci_get_device(dev) == t->sf_did)) { 625 switch((pci_read_config(dev, 626 SF_PCI_SUBVEN_ID, 4) >> 16) & 0xFFFF) { 627 case AD_SUBSYSID_62011_REV0: 628 case AD_SUBSYSID_62011_REV1: 629 device_set_desc(dev, 630 "Adaptec ANA-62011 10/100BaseTX"); 631 return(0); 632 break; 633 case AD_SUBSYSID_62022: 634 device_set_desc(dev, 635 "Adaptec ANA-62022 10/100BaseTX"); 636 return(0); 637 break; 638 case AD_SUBSYSID_62044_REV0: 639 case AD_SUBSYSID_62044_REV1: 640 device_set_desc(dev, 641 "Adaptec ANA-62044 10/100BaseTX"); 642 return(0); 643 break; 644 case AD_SUBSYSID_62020: 645 device_set_desc(dev, 646 "Adaptec ANA-62020 10/100BaseFX"); 647 return(0); 648 break; 649 case AD_SUBSYSID_69011: 650 device_set_desc(dev, 651 "Adaptec ANA-69011 10/100BaseTX"); 652 return(0); 653 break; 654 default: 655 device_set_desc(dev, t->sf_name); 656 return(0); 657 break; 658 } 659 } 660 t++; 661 } 662 663 return(ENXIO); 664} 665 666/* 667 * Attach the interface. Allocate softc structures, do ifmedia 668 * setup and ethernet/BPF attach. 669 */ 670static int sf_attach(dev) 671 device_t dev; 672{ 673 int i; 674 u_int32_t command; 675 struct sf_softc *sc; 676 struct ifnet *ifp; 677 int unit, rid, error = 0; 678 679 sc = device_get_softc(dev); 680 unit = device_get_unit(dev); 681 bzero(sc, sizeof(struct sf_softc)); 682 683 /* 684 * Handle power management nonsense. 685 */ 686 command = pci_read_config(dev, SF_PCI_CAPID, 4) & 0x000000FF; 687 if (command == 0x01) { 688 689 command = pci_read_config(dev, SF_PCI_PWRMGMTCTRL, 4); 690 if (command & SF_PSTATE_MASK) { 691 u_int32_t iobase, membase, irq; 692 693 /* Save important PCI config data. */ 694 iobase = pci_read_config(dev, SF_PCI_LOIO, 4); 695 membase = pci_read_config(dev, SF_PCI_LOMEM, 4); 696 irq = pci_read_config(dev, SF_PCI_INTLINE, 4); 697 698 /* Reset the power state. */ 699 printf("sf%d: chip is in D%d power mode " 700 "-- setting to D0\n", unit, command & SF_PSTATE_MASK); 701 command &= 0xFFFFFFFC; 702 pci_write_config(dev, SF_PCI_PWRMGMTCTRL, command, 4); 703 704 /* Restore PCI config data. */ 705 pci_write_config(dev, SF_PCI_LOIO, iobase, 4); 706 pci_write_config(dev, SF_PCI_LOMEM, membase, 4); 707 pci_write_config(dev, SF_PCI_INTLINE, irq, 4); 708 } 709 } 710 711 /* 712 * Map control/status registers. 713 */ 714 command = pci_read_config(dev, PCIR_COMMAND, 4); 715 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 716 pci_write_config(dev, PCIR_COMMAND, command, 4); 717 command = pci_read_config(dev, PCIR_COMMAND, 4); 718 719#ifdef SF_USEIOSPACE 720 if (!(command & PCIM_CMD_PORTEN)) { 721 printf("sf%d: failed to enable I/O ports!\n", unit); 722 error = ENXIO; 723 goto fail; 724 } 725#else 726 if (!(command & PCIM_CMD_MEMEN)) { 727 printf("sf%d: failed to enable memory mapping!\n", unit); 728 error = ENXIO; 729 goto fail; 730 } 731#endif 732 733 rid = SF_RID; 734 sc->sf_res = bus_alloc_resource(dev, SF_RES, &rid, 735 0, ~0, 1, RF_ACTIVE); 736 737 if (sc->sf_res == NULL) { 738 printf ("sf%d: couldn't map ports\n", unit); 739 error = ENXIO; 740 goto fail; 741 } 742 743 sc->sf_btag = rman_get_bustag(sc->sf_res); 744 sc->sf_bhandle = rman_get_bushandle(sc->sf_res); 745 746 /* Allocate interrupt */ 747 rid = 0; 748 sc->sf_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 749 RF_SHAREABLE | RF_ACTIVE); 750 751 if (sc->sf_irq == NULL) { 752 printf("sf%d: couldn't map interrupt\n", unit); 753 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 754 error = ENXIO; 755 goto fail; 756 } 757 758 error = bus_setup_intr(dev, sc->sf_irq, INTR_TYPE_NET, 759 sf_intr, sc, &sc->sf_intrhand); 760 761 if (error) { 762 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_res); 763 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 764 printf("sf%d: couldn't set up irq\n", unit); 765 goto fail; 766 } 767 768 callout_handle_init(&sc->sf_stat_ch); 769 mtx_init(&sc->sf_mtx, "sf", MTX_DEF); 770 SF_LOCK(sc); 771 /* Reset the adapter. */ 772 sf_reset(sc); 773 774 /* 775 * Get station address from the EEPROM. 776 */ 777 for (i = 0; i < ETHER_ADDR_LEN; i++) 778 sc->arpcom.ac_enaddr[i] = 779 sf_read_eeprom(sc, SF_EE_NODEADDR + ETHER_ADDR_LEN - i); 780 781 /* 782 * An Adaptec chip was detected. Inform the world. 783 */ 784 printf("sf%d: Ethernet address: %6D\n", unit, 785 sc->arpcom.ac_enaddr, ":"); 786 787 sc->sf_unit = unit; 788 789 /* Allocate the descriptor queues. */ 790 sc->sf_ldata = contigmalloc(sizeof(struct sf_list_data), M_DEVBUF, 791 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 792 793 if (sc->sf_ldata == NULL) { 794 printf("sf%d: no memory for list buffers!\n", unit); 795 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand); 796 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq); 797 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 798 error = ENXIO; 799 goto fail; 800 } 801 802 bzero(sc->sf_ldata, sizeof(struct sf_list_data)); 803 804 /* Do MII setup. */ 805 if (mii_phy_probe(dev, &sc->sf_miibus, 806 sf_ifmedia_upd, sf_ifmedia_sts)) { 807 printf("sf%d: MII without any phy!\n", sc->sf_unit); 808 contigfree(sc->sf_ldata,sizeof(struct sf_list_data),M_DEVBUF); 809 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand); 810 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq); 811 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 812 error = ENXIO; 813 goto fail; 814 } 815 816 ifp = &sc->arpcom.ac_if; 817 ifp->if_softc = sc; 818 ifp->if_unit = unit; 819 ifp->if_name = "sf"; 820 ifp->if_mtu = ETHERMTU; 821 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 822 ifp->if_ioctl = sf_ioctl; 823 ifp->if_output = ether_output; 824 ifp->if_start = sf_start; 825 ifp->if_watchdog = sf_watchdog; 826 ifp->if_init = sf_init; 827 ifp->if_baudrate = 10000000; 828 ifp->if_snd.ifq_maxlen = SF_TX_DLIST_CNT - 1; 829 830 /* 831 * Call MI attach routine. 832 */ 833 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 834 SF_UNLOCK(sc); 835 return(0); 836 837fail: 838 SF_UNLOCK(sc); 839 mtx_destroy(&sc->sf_mtx); 840 return(error); 841} 842 843static int sf_detach(dev) 844 device_t dev; 845{ 846 struct sf_softc *sc; 847 struct ifnet *ifp; 848 849 sc = device_get_softc(dev); 850 SF_LOCK(sc); 851 ifp = &sc->arpcom.ac_if; 852 853 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 854 sf_stop(sc); 855 856 bus_generic_detach(dev); 857 device_delete_child(dev, sc->sf_miibus); 858 859 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand); 860 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq); 861 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 862 863 contigfree(sc->sf_ldata, sizeof(struct sf_list_data), M_DEVBUF); 864 865 SF_UNLOCK(sc); 866 mtx_destroy(&sc->sf_mtx); 867 868 return(0); 869} 870 871static int sf_init_rx_ring(sc) 872 struct sf_softc *sc; 873{ 874 struct sf_list_data *ld; 875 int i; 876 877 ld = sc->sf_ldata; 878 879 bzero((char *)ld->sf_rx_dlist_big, 880 sizeof(struct sf_rx_bufdesc_type0) * SF_RX_DLIST_CNT); 881 bzero((char *)ld->sf_rx_clist, 882 sizeof(struct sf_rx_cmpdesc_type3) * SF_RX_CLIST_CNT); 883 884 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 885 if (sf_newbuf(sc, &ld->sf_rx_dlist_big[i], NULL) == ENOBUFS) 886 return(ENOBUFS); 887 } 888 889 return(0); 890} 891 892static void sf_init_tx_ring(sc) 893 struct sf_softc *sc; 894{ 895 struct sf_list_data *ld; 896 int i; 897 898 ld = sc->sf_ldata; 899 900 bzero((char *)ld->sf_tx_dlist, 901 sizeof(struct sf_tx_bufdesc_type0) * SF_TX_DLIST_CNT); 902 bzero((char *)ld->sf_tx_clist, 903 sizeof(struct sf_tx_cmpdesc_type0) * SF_TX_CLIST_CNT); 904 905 for (i = 0; i < SF_TX_DLIST_CNT; i++) 906 ld->sf_tx_dlist[i].sf_id = SF_TX_BUFDESC_ID; 907 for (i = 0; i < SF_TX_CLIST_CNT; i++) 908 ld->sf_tx_clist[i].sf_type = SF_TXCMPTYPE_TX; 909 910 ld->sf_tx_dlist[SF_TX_DLIST_CNT - 1].sf_end = 1; 911 sc->sf_tx_cnt = 0; 912 913 return; 914} 915 916static int sf_newbuf(sc, c, m) 917 struct sf_softc *sc; 918 struct sf_rx_bufdesc_type0 *c; 919 struct mbuf *m; 920{ 921 struct mbuf *m_new = NULL; 922 923 if (m == NULL) { 924 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 925 if (m_new == NULL) { 926 printf("sf%d: no memory for rx list -- " 927 "packet dropped!\n", sc->sf_unit); 928 return(ENOBUFS); 929 } 930 931 MCLGET(m_new, M_DONTWAIT); 932 if (!(m_new->m_flags & M_EXT)) { 933 printf("sf%d: no memory for rx list -- " 934 "packet dropped!\n", sc->sf_unit); 935 m_freem(m_new); 936 return(ENOBUFS); 937 } 938 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 939 } else { 940 m_new = m; 941 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 942 m_new->m_data = m_new->m_ext.ext_buf; 943 } 944 945 m_adj(m_new, sizeof(u_int64_t)); 946 947 c->sf_mbuf = m_new; 948 c->sf_addrlo = SF_RX_HOSTADDR(vtophys(mtod(m_new, caddr_t))); 949 c->sf_valid = 1; 950 951 return(0); 952} 953 954/* 955 * The starfire is programmed to use 'normal' mode for packet reception, 956 * which means we use the consumer/producer model for both the buffer 957 * descriptor queue and the completion descriptor queue. The only problem 958 * with this is that it involves a lot of register accesses: we have to 959 * read the RX completion consumer and producer indexes and the RX buffer 960 * producer index, plus the RX completion consumer and RX buffer producer 961 * indexes have to be updated. It would have been easier if Adaptec had 962 * put each index in a separate register, especially given that the damn 963 * NIC has a 512K register space. 964 * 965 * In spite of all the lovely features that Adaptec crammed into the 6915, 966 * it is marred by one truly stupid design flaw, which is that receive 967 * buffer addresses must be aligned on a longword boundary. This forces 968 * the packet payload to be unaligned, which is suboptimal on the x86 and 969 * completely unuseable on the Alpha. Our only recourse is to copy received 970 * packets into properly aligned buffers before handing them off. 971 */ 972 973static void sf_rxeof(sc) 974 struct sf_softc *sc; 975{ 976 struct ether_header *eh; 977 struct mbuf *m; 978 struct ifnet *ifp; 979 struct sf_rx_bufdesc_type0 *desc; 980 struct sf_rx_cmpdesc_type3 *cur_rx; 981 u_int32_t rxcons, rxprod; 982 int cmpprodidx, cmpconsidx, bufprodidx; 983 984 ifp = &sc->arpcom.ac_if; 985 986 rxcons = csr_read_4(sc, SF_CQ_CONSIDX); 987 rxprod = csr_read_4(sc, SF_RXDQ_PTR_Q1); 988 cmpprodidx = SF_IDX_LO(csr_read_4(sc, SF_CQ_PRODIDX)); 989 cmpconsidx = SF_IDX_LO(rxcons); 990 bufprodidx = SF_IDX_LO(rxprod); 991 992 while (cmpconsidx != cmpprodidx) { 993 struct mbuf *m0; 994 995 cur_rx = &sc->sf_ldata->sf_rx_clist[cmpconsidx]; 996 desc = &sc->sf_ldata->sf_rx_dlist_big[cur_rx->sf_endidx]; 997 m = desc->sf_mbuf; 998 SF_INC(cmpconsidx, SF_RX_CLIST_CNT); 999 SF_INC(bufprodidx, SF_RX_DLIST_CNT); 1000 1001 if (!(cur_rx->sf_status1 & SF_RXSTAT1_OK)) { 1002 ifp->if_ierrors++; 1003 sf_newbuf(sc, desc, m); 1004 continue; 1005 } 1006 1007 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1008 cur_rx->sf_len + ETHER_ALIGN, 0, ifp, NULL); 1009 sf_newbuf(sc, desc, m); 1010 if (m0 == NULL) { 1011 ifp->if_ierrors++; 1012 continue; 1013 } 1014 m_adj(m0, ETHER_ALIGN); 1015 m = m0; 1016 1017 eh = mtod(m, struct ether_header *); 1018 ifp->if_ipackets++; 1019 1020 /* Remove header from mbuf and pass it on. */ 1021 m_adj(m, sizeof(struct ether_header)); 1022 ether_input(ifp, eh, m); 1023 } 1024 1025 csr_write_4(sc, SF_CQ_CONSIDX, 1026 (rxcons & ~SF_CQ_CONSIDX_RXQ1) | cmpconsidx); 1027 csr_write_4(sc, SF_RXDQ_PTR_Q1, 1028 (rxprod & ~SF_RXDQ_PRODIDX) | bufprodidx); 1029 1030 return; 1031} 1032 1033/* 1034 * Read the transmit status from the completion queue and release 1035 * mbufs. Note that the buffer descriptor index in the completion 1036 * descriptor is an offset from the start of the transmit buffer 1037 * descriptor list in bytes. This is important because the manual 1038 * gives the impression that it should match the producer/consumer 1039 * index, which is the offset in 8 byte blocks. 1040 */ 1041static void sf_txeof(sc) 1042 struct sf_softc *sc; 1043{ 1044 int txcons, cmpprodidx, cmpconsidx; 1045 struct sf_tx_cmpdesc_type1 *cur_cmp; 1046 struct sf_tx_bufdesc_type0 *cur_tx; 1047 struct ifnet *ifp; 1048 1049 ifp = &sc->arpcom.ac_if; 1050 1051 txcons = csr_read_4(sc, SF_CQ_CONSIDX); 1052 cmpprodidx = SF_IDX_HI(csr_read_4(sc, SF_CQ_PRODIDX)); 1053 cmpconsidx = SF_IDX_HI(txcons); 1054 1055 while (cmpconsidx != cmpprodidx) { 1056 cur_cmp = &sc->sf_ldata->sf_tx_clist[cmpconsidx]; 1057 cur_tx = &sc->sf_ldata->sf_tx_dlist[cur_cmp->sf_index >> 7]; 1058 SF_INC(cmpconsidx, SF_TX_CLIST_CNT); 1059 1060 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_OK) 1061 ifp->if_opackets++; 1062 else 1063 ifp->if_oerrors++; 1064 1065 sc->sf_tx_cnt--; 1066 if (cur_tx->sf_mbuf != NULL) { 1067 m_freem(cur_tx->sf_mbuf); 1068 cur_tx->sf_mbuf = NULL; 1069 } 1070 } 1071 1072 ifp->if_timer = 0; 1073 ifp->if_flags &= ~IFF_OACTIVE; 1074 1075 csr_write_4(sc, SF_CQ_CONSIDX, 1076 (txcons & ~SF_CQ_CONSIDX_TXQ) | 1077 ((cmpconsidx << 16) & 0xFFFF0000)); 1078 1079 return; 1080} 1081 1082static void sf_intr(arg) 1083 void *arg; 1084{ 1085 struct sf_softc *sc; 1086 struct ifnet *ifp; 1087 u_int32_t status; 1088 1089 sc = arg; 1090 SF_LOCK(sc); 1091 1092 ifp = &sc->arpcom.ac_if; 1093 1094 if (!(csr_read_4(sc, SF_ISR_SHADOW) & SF_ISR_PCIINT_ASSERTED)) { 1095 SF_UNLOCK(sc); 1096 return; 1097 } 1098 1099 /* Disable interrupts. */ 1100 csr_write_4(sc, SF_IMR, 0x00000000); 1101 1102 for (;;) { 1103 status = csr_read_4(sc, SF_ISR); 1104 if (status) 1105 csr_write_4(sc, SF_ISR, status); 1106 1107 if (!(status & SF_INTRS)) 1108 break; 1109 1110 if (status & SF_ISR_RXDQ1_DMADONE) 1111 sf_rxeof(sc); 1112 1113 if (status & SF_ISR_TX_TXDONE) 1114 sf_txeof(sc); 1115 1116 if (status & SF_ISR_ABNORMALINTR) { 1117 if (status & SF_ISR_STATSOFLOW) { 1118 untimeout(sf_stats_update, sc, 1119 sc->sf_stat_ch); 1120 sf_stats_update(sc); 1121 } else 1122 sf_init(sc); 1123 } 1124 } 1125 1126 /* Re-enable interrupts. */ 1127 csr_write_4(sc, SF_IMR, SF_INTRS); 1128 1129 if (ifp->if_snd.ifq_head != NULL) 1130 sf_start(ifp); 1131 1132 SF_UNLOCK(sc); 1133 return; 1134} 1135 1136static void sf_init(xsc) 1137 void *xsc; 1138{ 1139 struct sf_softc *sc; 1140 struct ifnet *ifp; 1141 struct mii_data *mii; 1142 int i; 1143 1144 sc = xsc; 1145 SF_LOCK(sc); 1146 ifp = &sc->arpcom.ac_if; 1147 mii = device_get_softc(sc->sf_miibus); 1148 1149 sf_stop(sc); 1150 sf_reset(sc); 1151 1152 /* Init all the receive filter registers */ 1153 for (i = SF_RXFILT_PERFECT_BASE; 1154 i < (SF_RXFILT_HASH_MAX + 1); i += 4) 1155 csr_write_4(sc, i, 0); 1156 1157 /* Empty stats counter registers. */ 1158 for (i = 0; i < sizeof(struct sf_stats)/sizeof(u_int32_t); i++) 1159 csr_write_4(sc, SF_STATS_BASE + 1160 (i + sizeof(u_int32_t)), 0); 1161 1162 /* Init our MAC address */ 1163 csr_write_4(sc, SF_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1164 csr_write_4(sc, SF_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1165 sf_setperf(sc, 0, (caddr_t)&sc->arpcom.ac_enaddr); 1166 1167 if (sf_init_rx_ring(sc) == ENOBUFS) { 1168 printf("sf%d: initialization failed: no " 1169 "memory for rx buffers\n", sc->sf_unit); 1170 SF_UNLOCK(sc); 1171 return; 1172 } 1173 1174 sf_init_tx_ring(sc); 1175 1176 csr_write_4(sc, SF_RXFILT, SF_PERFMODE_NORMAL|SF_HASHMODE_WITHVLAN); 1177 1178 /* If we want promiscuous mode, set the allframes bit. */ 1179 if (ifp->if_flags & IFF_PROMISC) { 1180 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 1181 } else { 1182 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 1183 } 1184 1185 if (ifp->if_flags & IFF_BROADCAST) { 1186 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_BROAD); 1187 } else { 1188 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_BROAD); 1189 } 1190 1191 /* 1192 * Load the multicast filter. 1193 */ 1194 sf_setmulti(sc); 1195 1196 /* Init the completion queue indexes */ 1197 csr_write_4(sc, SF_CQ_CONSIDX, 0); 1198 csr_write_4(sc, SF_CQ_PRODIDX, 0); 1199 1200 /* Init the RX completion queue */ 1201 csr_write_4(sc, SF_RXCQ_CTL_1, 1202 vtophys(sc->sf_ldata->sf_rx_clist) & SF_RXCQ_ADDR); 1203 SF_SETBIT(sc, SF_RXCQ_CTL_1, SF_RXCQTYPE_3); 1204 1205 /* Init RX DMA control. */ 1206 SF_SETBIT(sc, SF_RXDMA_CTL, SF_RXDMA_REPORTBADPKTS); 1207 1208 /* Init the RX buffer descriptor queue. */ 1209 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 1210 vtophys(sc->sf_ldata->sf_rx_dlist_big)); 1211 csr_write_4(sc, SF_RXDQ_CTL_1, (MCLBYTES << 16) | SF_DESCSPACE_16BYTES); 1212 csr_write_4(sc, SF_RXDQ_PTR_Q1, SF_RX_DLIST_CNT - 1); 1213 1214 /* Init the TX completion queue */ 1215 csr_write_4(sc, SF_TXCQ_CTL, 1216 vtophys(sc->sf_ldata->sf_tx_clist) & SF_RXCQ_ADDR); 1217 1218 /* Init the TX buffer descriptor queue. */ 1219 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 1220 vtophys(sc->sf_ldata->sf_tx_dlist)); 1221 SF_SETBIT(sc, SF_TX_FRAMCTL, SF_TXFRMCTL_CPLAFTERTX); 1222 csr_write_4(sc, SF_TXDQ_CTL, 1223 SF_TXBUFDESC_TYPE0|SF_TXMINSPACE_128BYTES|SF_TXSKIPLEN_8BYTES); 1224 SF_SETBIT(sc, SF_TXDQ_CTL, SF_TXDQCTL_NODMACMP); 1225 1226 /* Enable autopadding of short TX frames. */ 1227 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_AUTOPAD); 1228 1229 /* Enable interrupts. */ 1230 csr_write_4(sc, SF_IMR, SF_INTRS); 1231 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_INTR_ENB); 1232 1233 /* Enable the RX and TX engines. */ 1234 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_RX_ENB|SF_ETHCTL_RXDMA_ENB); 1235 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_TX_ENB|SF_ETHCTL_TXDMA_ENB); 1236 1237 /*mii_mediachg(mii);*/ 1238 sf_ifmedia_upd(ifp); 1239 1240 ifp->if_flags |= IFF_RUNNING; 1241 ifp->if_flags &= ~IFF_OACTIVE; 1242 1243 sc->sf_stat_ch = timeout(sf_stats_update, sc, hz); 1244 1245 SF_UNLOCK(sc); 1246 1247 return; 1248} 1249 1250static int sf_encap(sc, c, m_head) 1251 struct sf_softc *sc; 1252 struct sf_tx_bufdesc_type0 *c; 1253 struct mbuf *m_head; 1254{ 1255 int frag = 0; 1256 struct sf_frag *f = NULL; 1257 struct mbuf *m; 1258 1259 m = m_head; 1260 1261 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1262 if (m->m_len != 0) { 1263 if (frag == SF_MAXFRAGS) 1264 break; 1265 f = &c->sf_frags[frag]; 1266 if (frag == 0) 1267 f->sf_pktlen = m_head->m_pkthdr.len; 1268 f->sf_fraglen = m->m_len; 1269 f->sf_addr = vtophys(mtod(m, vm_offset_t)); 1270 frag++; 1271 } 1272 } 1273 1274 if (m != NULL) { 1275 struct mbuf *m_new = NULL; 1276 1277 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1278 if (m_new == NULL) { 1279 printf("sf%d: no memory for tx list", sc->sf_unit); 1280 return(1); 1281 } 1282 1283 if (m_head->m_pkthdr.len > MHLEN) { 1284 MCLGET(m_new, M_DONTWAIT); 1285 if (!(m_new->m_flags & M_EXT)) { 1286 m_freem(m_new); 1287 printf("sf%d: no memory for tx list", 1288 sc->sf_unit); 1289 return(1); 1290 } 1291 } 1292 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1293 mtod(m_new, caddr_t)); 1294 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1295 m_freem(m_head); 1296 m_head = m_new; 1297 f = &c->sf_frags[0]; 1298 f->sf_fraglen = f->sf_pktlen = m_head->m_pkthdr.len; 1299 f->sf_addr = vtophys(mtod(m_head, caddr_t)); 1300 frag = 1; 1301 } 1302 1303 c->sf_mbuf = m_head; 1304 c->sf_id = SF_TX_BUFDESC_ID; 1305 c->sf_fragcnt = frag; 1306 c->sf_intr = 1; 1307 c->sf_caltcp = 0; 1308 c->sf_crcen = 1; 1309 1310 return(0); 1311} 1312 1313static void sf_start(ifp) 1314 struct ifnet *ifp; 1315{ 1316 struct sf_softc *sc; 1317 struct sf_tx_bufdesc_type0 *cur_tx = NULL; 1318 struct mbuf *m_head = NULL; 1319 int i, txprod; 1320 1321 sc = ifp->if_softc; 1322 SF_LOCK(sc); 1323 1324 if (!sc->sf_link) { 1325 SF_UNLOCK(sc); 1326 return; 1327 } 1328 1329 if (ifp->if_flags & IFF_OACTIVE) { 1330 SF_UNLOCK(sc); 1331 return; 1332 } 1333 1334 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX); 1335 i = SF_IDX_HI(txprod) >> 4; 1336 1337 while(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf == NULL) { 1338 IF_DEQUEUE(&ifp->if_snd, m_head); 1339 if (m_head == NULL) 1340 break; 1341 1342 cur_tx = &sc->sf_ldata->sf_tx_dlist[i]; 1343 sf_encap(sc, cur_tx, m_head); 1344 1345 /* 1346 * If there's a BPF listener, bounce a copy of this frame 1347 * to him. 1348 */ 1349 if (ifp->if_bpf) 1350 bpf_mtap(ifp, m_head); 1351 1352 SF_INC(i, SF_TX_DLIST_CNT); 1353 sc->sf_tx_cnt++; 1354 if (sc->sf_tx_cnt == (SF_TX_DLIST_CNT - 2)) 1355 break; 1356 } 1357 1358 if (cur_tx == NULL) { 1359 SF_UNLOCK(sc); 1360 return; 1361 } 1362 1363 /* Transmit */ 1364 csr_write_4(sc, SF_TXDQ_PRODIDX, 1365 (txprod & ~SF_TXDQ_PRODIDX_HIPRIO) | 1366 ((i << 20) & 0xFFFF0000)); 1367 1368 ifp->if_timer = 5; 1369 1370 SF_UNLOCK(sc); 1371 1372 return; 1373} 1374 1375static void sf_stop(sc) 1376 struct sf_softc *sc; 1377{ 1378 int i; 1379 struct ifnet *ifp; 1380 1381 SF_LOCK(sc); 1382 1383 ifp = &sc->arpcom.ac_if; 1384 1385 untimeout(sf_stats_update, sc, sc->sf_stat_ch); 1386 1387 csr_write_4(sc, SF_GEN_ETH_CTL, 0); 1388 csr_write_4(sc, SF_CQ_CONSIDX, 0); 1389 csr_write_4(sc, SF_CQ_PRODIDX, 0); 1390 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 0); 1391 csr_write_4(sc, SF_RXDQ_CTL_1, 0); 1392 csr_write_4(sc, SF_RXDQ_PTR_Q1, 0); 1393 csr_write_4(sc, SF_TXCQ_CTL, 0); 1394 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 0); 1395 csr_write_4(sc, SF_TXDQ_CTL, 0); 1396 sf_reset(sc); 1397 1398 sc->sf_link = 0; 1399 1400 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 1401 if (sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf != NULL) { 1402 m_freem(sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf); 1403 sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf = NULL; 1404 } 1405 } 1406 1407 for (i = 0; i < SF_TX_DLIST_CNT; i++) { 1408 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) { 1409 m_freem(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf); 1410 sc->sf_ldata->sf_tx_dlist[i].sf_mbuf = NULL; 1411 } 1412 } 1413 1414 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 1415 SF_UNLOCK(sc); 1416 1417 return; 1418} 1419 1420/* 1421 * Note: it is important that this function not be interrupted. We 1422 * use a two-stage register access scheme: if we are interrupted in 1423 * between setting the indirect address register and reading from the 1424 * indirect data register, the contents of the address register could 1425 * be changed out from under us. 1426 */ 1427static void sf_stats_update(xsc) 1428 void *xsc; 1429{ 1430 struct sf_softc *sc; 1431 struct ifnet *ifp; 1432 struct mii_data *mii; 1433 struct sf_stats stats; 1434 u_int32_t *ptr; 1435 int i; 1436 1437 sc = xsc; 1438 SF_LOCK(sc); 1439 ifp = &sc->arpcom.ac_if; 1440 mii = device_get_softc(sc->sf_miibus); 1441 1442 ptr = (u_int32_t *)&stats; 1443 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++) 1444 ptr[i] = csr_read_4(sc, SF_STATS_BASE + 1445 (i + sizeof(u_int32_t))); 1446 1447 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++) 1448 csr_write_4(sc, SF_STATS_BASE + 1449 (i + sizeof(u_int32_t)), 0); 1450 1451 ifp->if_collisions += stats.sf_tx_single_colls + 1452 stats.sf_tx_multi_colls + stats.sf_tx_excess_colls; 1453 1454 mii_tick(mii); 1455 if (!sc->sf_link) { 1456 mii_pollstat(mii); 1457 if (mii->mii_media_status & IFM_ACTIVE && 1458 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1459 sc->sf_link++; 1460 if (ifp->if_snd.ifq_head != NULL) 1461 sf_start(ifp); 1462 } 1463 1464 sc->sf_stat_ch = timeout(sf_stats_update, sc, hz); 1465 1466 SF_UNLOCK(sc); 1467 1468 return; 1469} 1470 1471static void sf_watchdog(ifp) 1472 struct ifnet *ifp; 1473{ 1474 struct sf_softc *sc; 1475 1476 sc = ifp->if_softc; 1477 1478 SF_LOCK(sc); 1479 1480 ifp->if_oerrors++; 1481 printf("sf%d: watchdog timeout\n", sc->sf_unit); 1482 1483 sf_stop(sc); 1484 sf_reset(sc); 1485 sf_init(sc); 1486 1487 if (ifp->if_snd.ifq_head != NULL) 1488 sf_start(ifp); 1489 1490 SF_UNLOCK(sc); 1491 1492 return; 1493} 1494 1495static void sf_shutdown(dev) 1496 device_t dev; 1497{ 1498 struct sf_softc *sc; 1499 1500 sc = device_get_softc(dev); 1501 1502 sf_stop(sc); 1503 1504 return; 1505} 1506