if_sf.c revision 60536
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/dev/sf/if_sf.c 60536 2000-05-14 02:18:43Z archie $ 33 */ 34 35/* 36 * Adaptec AIC-6915 "Starfire" PCI fast ethernet driver for FreeBSD. 37 * Programming manual is available from: 38 * ftp.adaptec.com:/pub/BBS/userguides/aic6915_pg.pdf. 39 * 40 * Written by Bill Paul <wpaul@ctr.columbia.edu> 41 * Department of Electical Engineering 42 * Columbia University, New York City 43 */ 44 45/* 46 * The Adaptec AIC-6915 "Starfire" is a 64-bit 10/100 PCI ethernet 47 * controller designed with flexibility and reducing CPU load in mind. 48 * The Starfire offers high and low priority buffer queues, a 49 * producer/consumer index mechanism and several different buffer 50 * queue and completion queue descriptor types. Any one of a number 51 * of different driver designs can be used, depending on system and 52 * OS requirements. This driver makes use of type0 transmit frame 53 * descriptors (since BSD fragments packets across an mbuf chain) 54 * and two RX buffer queues prioritized on size (one queue for small 55 * frames that will fit into a single mbuf, another with full size 56 * mbuf clusters for everything else). The producer/consumer indexes 57 * and completion queues are also used. 58 * 59 * One downside to the Starfire has to do with alignment: buffer 60 * queues must be aligned on 256-byte boundaries, and receive buffers 61 * must be aligned on longword boundaries. The receive buffer alignment 62 * causes problems on the Alpha platform, where the packet payload 63 * should be longword aligned. There is no simple way around this. 64 * 65 * For receive filtering, the Starfire offers 16 perfect filter slots 66 * and a 512-bit hash table. 67 * 68 * The Starfire has no internal transceiver, relying instead on an 69 * external MII-based transceiver. Accessing registers on external 70 * PHYs is done through a special register map rather than with the 71 * usual bitbang MDIO method. 72 * 73 * Acesssing the registers on the Starfire is a little tricky. The 74 * Starfire has a 512K internal register space. When programmed for 75 * PCI memory mapped mode, the entire register space can be accessed 76 * directly. However in I/O space mode, only 256 bytes are directly 77 * mapped into PCI I/O space. The other registers can be accessed 78 * indirectly using the SF_INDIRECTIO_ADDR and SF_INDIRECTIO_DATA 79 * registers inside the 256-byte I/O window. 80 */ 81 82#include <sys/param.h> 83#include <sys/systm.h> 84#include <sys/sockio.h> 85#include <sys/mbuf.h> 86#include <sys/malloc.h> 87#include <sys/kernel.h> 88#include <sys/socket.h> 89 90#include <net/if.h> 91#include <net/if_arp.h> 92#include <net/ethernet.h> 93#include <net/if_dl.h> 94#include <net/if_media.h> 95 96#include <net/bpf.h> 97 98#include <vm/vm.h> /* for vtophys */ 99#include <vm/pmap.h> /* for vtophys */ 100#include <machine/clock.h> /* for DELAY */ 101#include <machine/bus_pio.h> 102#include <machine/bus_memio.h> 103#include <machine/bus.h> 104#include <machine/resource.h> 105#include <sys/bus.h> 106#include <sys/rman.h> 107 108#include <dev/mii/mii.h> 109#include <dev/mii/miivar.h> 110 111/* "controller miibus0" required. See GENERIC if you get errors here. */ 112#include "miibus_if.h" 113 114#include <pci/pcireg.h> 115#include <pci/pcivar.h> 116 117#define SF_USEIOSPACE 118 119#include <pci/if_sfreg.h> 120 121MODULE_DEPEND(sf, miibus, 1, 1, 1); 122 123#ifndef lint 124static const char rcsid[] = 125 "$FreeBSD: head/sys/dev/sf/if_sf.c 60536 2000-05-14 02:18:43Z archie $"; 126#endif 127 128static struct sf_type sf_devs[] = { 129 { AD_VENDORID, AD_DEVICEID_STARFIRE, 130 "Adaptec AIC-6915 10/100BaseTX" }, 131 { 0, 0, NULL } 132}; 133 134static int sf_probe __P((device_t)); 135static int sf_attach __P((device_t)); 136static int sf_detach __P((device_t)); 137static void sf_intr __P((void *)); 138static void sf_stats_update __P((void *)); 139static void sf_rxeof __P((struct sf_softc *)); 140static void sf_txeof __P((struct sf_softc *)); 141static int sf_encap __P((struct sf_softc *, 142 struct sf_tx_bufdesc_type0 *, 143 struct mbuf *)); 144static void sf_start __P((struct ifnet *)); 145static int sf_ioctl __P((struct ifnet *, u_long, caddr_t)); 146static void sf_init __P((void *)); 147static void sf_stop __P((struct sf_softc *)); 148static void sf_watchdog __P((struct ifnet *)); 149static void sf_shutdown __P((device_t)); 150static int sf_ifmedia_upd __P((struct ifnet *)); 151static void sf_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 152static void sf_reset __P((struct sf_softc *)); 153static int sf_init_rx_ring __P((struct sf_softc *)); 154static void sf_init_tx_ring __P((struct sf_softc *)); 155static int sf_newbuf __P((struct sf_softc *, 156 struct sf_rx_bufdesc_type0 *, 157 struct mbuf *)); 158static void sf_setmulti __P((struct sf_softc *)); 159static int sf_setperf __P((struct sf_softc *, int, caddr_t)); 160static int sf_sethash __P((struct sf_softc *, caddr_t, int)); 161#ifdef notdef 162static int sf_setvlan __P((struct sf_softc *, int, u_int32_t)); 163#endif 164 165static u_int8_t sf_read_eeprom __P((struct sf_softc *, int)); 166static u_int32_t sf_calchash __P((caddr_t)); 167 168static int sf_miibus_readreg __P((device_t, int, int)); 169static int sf_miibus_writereg __P((device_t, int, int, int)); 170static void sf_miibus_statchg __P((device_t)); 171 172static u_int32_t csr_read_4 __P((struct sf_softc *, int)); 173static void csr_write_4 __P((struct sf_softc *, int, u_int32_t)); 174 175#ifdef SF_USEIOSPACE 176#define SF_RES SYS_RES_IOPORT 177#define SF_RID SF_PCI_LOIO 178#else 179#define SF_RES SYS_RES_MEMORY 180#define SF_RID SF_PCI_LOMEM 181#endif 182 183static device_method_t sf_methods[] = { 184 /* Device interface */ 185 DEVMETHOD(device_probe, sf_probe), 186 DEVMETHOD(device_attach, sf_attach), 187 DEVMETHOD(device_detach, sf_detach), 188 DEVMETHOD(device_shutdown, sf_shutdown), 189 190 /* bus interface */ 191 DEVMETHOD(bus_print_child, bus_generic_print_child), 192 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 193 194 /* MII interface */ 195 DEVMETHOD(miibus_readreg, sf_miibus_readreg), 196 DEVMETHOD(miibus_writereg, sf_miibus_writereg), 197 DEVMETHOD(miibus_statchg, sf_miibus_statchg), 198 199 { 0, 0 } 200}; 201 202static driver_t sf_driver = { 203 "sf", 204 sf_methods, 205 sizeof(struct sf_softc), 206}; 207 208static devclass_t sf_devclass; 209 210DRIVER_MODULE(if_sf, pci, sf_driver, sf_devclass, 0, 0); 211DRIVER_MODULE(miibus, sf, miibus_driver, miibus_devclass, 0, 0); 212 213#define SF_SETBIT(sc, reg, x) \ 214 csr_write_4(sc, reg, csr_read_4(sc, reg) | x) 215 216#define SF_CLRBIT(sc, reg, x) \ 217 csr_write_4(sc, reg, csr_read_4(sc, reg) & ~x) 218 219static u_int32_t csr_read_4(sc, reg) 220 struct sf_softc *sc; 221 int reg; 222{ 223 u_int32_t val; 224 225#ifdef SF_USEIOSPACE 226 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); 227 val = CSR_READ_4(sc, SF_INDIRECTIO_DATA); 228#else 229 val = CSR_READ_4(sc, (reg + SF_RMAP_INTREG_BASE)); 230#endif 231 232 return(val); 233} 234 235static u_int8_t sf_read_eeprom(sc, reg) 236 struct sf_softc *sc; 237 int reg; 238{ 239 u_int8_t val; 240 241 val = (csr_read_4(sc, SF_EEADDR_BASE + 242 (reg & 0xFFFFFFFC)) >> (8 * (reg & 3))) & 0xFF; 243 244 return(val); 245} 246 247static void csr_write_4(sc, reg, val) 248 struct sf_softc *sc; 249 int reg; 250 u_int32_t val; 251{ 252#ifdef SF_USEIOSPACE 253 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); 254 CSR_WRITE_4(sc, SF_INDIRECTIO_DATA, val); 255#else 256 CSR_WRITE_4(sc, (reg + SF_RMAP_INTREG_BASE), val); 257#endif 258 return; 259} 260 261static u_int32_t sf_calchash(addr) 262 caddr_t addr; 263{ 264 u_int32_t crc, carry; 265 int i, j; 266 u_int8_t c; 267 268 /* Compute CRC for the address value. */ 269 crc = 0xFFFFFFFF; /* initial value */ 270 271 for (i = 0; i < 6; i++) { 272 c = *(addr + i); 273 for (j = 0; j < 8; j++) { 274 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 275 crc <<= 1; 276 c >>= 1; 277 if (carry) 278 crc = (crc ^ 0x04c11db6) | carry; 279 } 280 } 281 282 /* return the filter bit position */ 283 return(crc >> 23 & 0x1FF); 284} 285 286/* 287 * Copy the address 'mac' into the perfect RX filter entry at 288 * offset 'idx.' The perfect filter only has 16 entries so do 289 * some sanity tests. 290 */ 291static int sf_setperf(sc, idx, mac) 292 struct sf_softc *sc; 293 int idx; 294 caddr_t mac; 295{ 296 u_int16_t *p; 297 298 if (idx < 0 || idx > SF_RXFILT_PERFECT_CNT) 299 return(EINVAL); 300 301 if (mac == NULL) 302 return(EINVAL); 303 304 p = (u_int16_t *)mac; 305 306 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 307 (idx * SF_RXFILT_PERFECT_SKIP), htons(p[2])); 308 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 309 (idx * SF_RXFILT_PERFECT_SKIP) + 4, htons(p[1])); 310 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 311 (idx * SF_RXFILT_PERFECT_SKIP) + 8, htons(p[0])); 312 313 return(0); 314} 315 316/* 317 * Set the bit in the 512-bit hash table that corresponds to the 318 * specified mac address 'mac.' If 'prio' is nonzero, update the 319 * priority hash table instead of the filter hash table. 320 */ 321static int sf_sethash(sc, mac, prio) 322 struct sf_softc *sc; 323 caddr_t mac; 324 int prio; 325{ 326 u_int32_t h = 0; 327 328 if (mac == NULL) 329 return(EINVAL); 330 331 h = sf_calchash(mac); 332 333 if (prio) { 334 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_PRIOOFF + 335 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); 336 } else { 337 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_ADDROFF + 338 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); 339 } 340 341 return(0); 342} 343 344#ifdef notdef 345/* 346 * Set a VLAN tag in the receive filter. 347 */ 348static int sf_setvlan(sc, idx, vlan) 349 struct sf_softc *sc; 350 int idx; 351 u_int32_t vlan; 352{ 353 if (idx < 0 || idx >> SF_RXFILT_HASH_CNT) 354 return(EINVAL); 355 356 csr_write_4(sc, SF_RXFILT_HASH_BASE + 357 (idx * SF_RXFILT_HASH_SKIP) + SF_RXFILT_HASH_VLANOFF, vlan); 358 359 return(0); 360} 361#endif 362 363static int sf_miibus_readreg(dev, phy, reg) 364 device_t dev; 365 int phy, reg; 366{ 367 struct sf_softc *sc; 368 int i; 369 u_int32_t val = 0; 370 371 sc = device_get_softc(dev); 372 373 for (i = 0; i < SF_TIMEOUT; i++) { 374 val = csr_read_4(sc, SF_PHY_REG(phy, reg)); 375 if (val & SF_MII_DATAVALID) 376 break; 377 } 378 379 if (i == SF_TIMEOUT) 380 return(0); 381 382 if ((val & 0x0000FFFF) == 0xFFFF) 383 return(0); 384 385 return(val & 0x0000FFFF); 386} 387 388static int sf_miibus_writereg(dev, phy, reg, val) 389 device_t dev; 390 int phy, reg, val; 391{ 392 struct sf_softc *sc; 393 int i; 394 int busy; 395 396 sc = device_get_softc(dev); 397 398 csr_write_4(sc, SF_PHY_REG(phy, reg), val); 399 400 for (i = 0; i < SF_TIMEOUT; i++) { 401 busy = csr_read_4(sc, SF_PHY_REG(phy, reg)); 402 if (!(busy & SF_MII_BUSY)) 403 break; 404 } 405 406 return(0); 407} 408 409static void sf_miibus_statchg(dev) 410 device_t dev; 411{ 412 struct sf_softc *sc; 413 struct mii_data *mii; 414 415 sc = device_get_softc(dev); 416 mii = device_get_softc(sc->sf_miibus); 417 418 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 419 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 420 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_FDX); 421 } else { 422 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 423 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_HDX); 424 } 425 426 return; 427} 428 429static void sf_setmulti(sc) 430 struct sf_softc *sc; 431{ 432 struct ifnet *ifp; 433 int i; 434 struct ifmultiaddr *ifma; 435 u_int8_t dummy[] = { 0, 0, 0, 0, 0, 0 }; 436 437 ifp = &sc->arpcom.ac_if; 438 439 /* First zot all the existing filters. */ 440 for (i = 1; i < SF_RXFILT_PERFECT_CNT; i++) 441 sf_setperf(sc, i, (char *)&dummy); 442 for (i = SF_RXFILT_HASH_BASE; 443 i < (SF_RXFILT_HASH_MAX + 1); i += 4) 444 csr_write_4(sc, i, 0); 445 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI); 446 447 /* Now program new ones. */ 448 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 449 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI); 450 } else { 451 i = 1; 452 /* First find the tail of the list. */ 453 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 454 ifma = ifma->ifma_link.le_next) { 455 if (ifma->ifma_link.le_next == NULL) 456 break; 457 } 458 /* Now traverse the list backwards. */ 459 for (; ifma != NULL && ifma != (void *)&ifp->if_multiaddrs; 460 ifma = (struct ifmultiaddr *)ifma->ifma_link.le_prev) { 461 if (ifma->ifma_addr->sa_family != AF_LINK) 462 continue; 463 /* 464 * Program the first 15 multicast groups 465 * into the perfect filter. For all others, 466 * use the hash table. 467 */ 468 if (i < SF_RXFILT_PERFECT_CNT) { 469 sf_setperf(sc, i, 470 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 471 i++; 472 continue; 473 } 474 475 sf_sethash(sc, 476 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 0); 477 } 478 } 479 480 return; 481} 482 483/* 484 * Set media options. 485 */ 486static int sf_ifmedia_upd(ifp) 487 struct ifnet *ifp; 488{ 489 struct sf_softc *sc; 490 struct mii_data *mii; 491 492 sc = ifp->if_softc; 493 mii = device_get_softc(sc->sf_miibus); 494 sc->sf_link = 0; 495 if (mii->mii_instance) { 496 struct mii_softc *miisc; 497 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 498 miisc = LIST_NEXT(miisc, mii_list)) 499 mii_phy_reset(miisc); 500 } 501 mii_mediachg(mii); 502 503 return(0); 504} 505 506/* 507 * Report current media status. 508 */ 509static void sf_ifmedia_sts(ifp, ifmr) 510 struct ifnet *ifp; 511 struct ifmediareq *ifmr; 512{ 513 struct sf_softc *sc; 514 struct mii_data *mii; 515 516 sc = ifp->if_softc; 517 mii = device_get_softc(sc->sf_miibus); 518 519 mii_pollstat(mii); 520 ifmr->ifm_active = mii->mii_media_active; 521 ifmr->ifm_status = mii->mii_media_status; 522 523 return; 524} 525 526static int sf_ioctl(ifp, command, data) 527 struct ifnet *ifp; 528 u_long command; 529 caddr_t data; 530{ 531 struct sf_softc *sc = ifp->if_softc; 532 struct ifreq *ifr = (struct ifreq *) data; 533 struct mii_data *mii; 534 int s, error = 0; 535 536 s = splimp(); 537 538 switch(command) { 539 case SIOCSIFADDR: 540 case SIOCGIFADDR: 541 case SIOCSIFMTU: 542 error = ether_ioctl(ifp, command, data); 543 break; 544 case SIOCSIFFLAGS: 545 if (ifp->if_flags & IFF_UP) { 546 if (ifp->if_flags & IFF_RUNNING && 547 ifp->if_flags & IFF_PROMISC && 548 !(sc->sf_if_flags & IFF_PROMISC)) { 549 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 550 } else if (ifp->if_flags & IFF_RUNNING && 551 !(ifp->if_flags & IFF_PROMISC) && 552 sc->sf_if_flags & IFF_PROMISC) { 553 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 554 } else if (!(ifp->if_flags & IFF_RUNNING)) 555 sf_init(sc); 556 } else { 557 if (ifp->if_flags & IFF_RUNNING) 558 sf_stop(sc); 559 } 560 sc->sf_if_flags = ifp->if_flags; 561 error = 0; 562 break; 563 case SIOCADDMULTI: 564 case SIOCDELMULTI: 565 sf_setmulti(sc); 566 error = 0; 567 break; 568 case SIOCGIFMEDIA: 569 case SIOCSIFMEDIA: 570 mii = device_get_softc(sc->sf_miibus); 571 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 572 break; 573 default: 574 error = EINVAL; 575 break; 576 } 577 578 (void)splx(s); 579 580 return(error); 581} 582 583static void sf_reset(sc) 584 struct sf_softc *sc; 585{ 586 register int i; 587 588 csr_write_4(sc, SF_GEN_ETH_CTL, 0); 589 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 590 DELAY(1000); 591 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 592 593 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_RESET); 594 595 for (i = 0; i < SF_TIMEOUT; i++) { 596 DELAY(10); 597 if (!(csr_read_4(sc, SF_PCI_DEVCFG) & SF_PCIDEVCFG_RESET)) 598 break; 599 } 600 601 if (i == SF_TIMEOUT) 602 printf("sf%d: reset never completed!\n", sc->sf_unit); 603 604 /* Wait a little while for the chip to get its brains in order. */ 605 DELAY(1000); 606 return; 607} 608 609/* 610 * Probe for an Adaptec AIC-6915 chip. Check the PCI vendor and device 611 * IDs against our list and return a device name if we find a match. 612 * We also check the subsystem ID so that we can identify exactly which 613 * NIC has been found, if possible. 614 */ 615static int sf_probe(dev) 616 device_t dev; 617{ 618 struct sf_type *t; 619 620 t = sf_devs; 621 622 while(t->sf_name != NULL) { 623 if ((pci_get_vendor(dev) == t->sf_vid) && 624 (pci_get_device(dev) == t->sf_did)) { 625 switch((pci_read_config(dev, 626 SF_PCI_SUBVEN_ID, 4) >> 16) & 0xFFFF) { 627 case AD_SUBSYSID_62011_REV0: 628 case AD_SUBSYSID_62011_REV1: 629 device_set_desc(dev, 630 "Adaptec ANA-62011 10/100BaseTX"); 631 return(0); 632 break; 633 case AD_SUBSYSID_62022: 634 device_set_desc(dev, 635 "Adaptec ANA-62022 10/100BaseTX"); 636 return(0); 637 break; 638 case AD_SUBSYSID_62044_REV0: 639 case AD_SUBSYSID_62044_REV1: 640 device_set_desc(dev, 641 "Adaptec ANA-62044 10/100BaseTX"); 642 return(0); 643 break; 644 case AD_SUBSYSID_62020: 645 device_set_desc(dev, 646 "Adaptec ANA-62020 10/100BaseFX"); 647 return(0); 648 break; 649 case AD_SUBSYSID_69011: 650 device_set_desc(dev, 651 "Adaptec ANA-69011 10/100BaseTX"); 652 return(0); 653 break; 654 default: 655 device_set_desc(dev, t->sf_name); 656 return(0); 657 break; 658 } 659 } 660 t++; 661 } 662 663 return(ENXIO); 664} 665 666/* 667 * Attach the interface. Allocate softc structures, do ifmedia 668 * setup and ethernet/BPF attach. 669 */ 670static int sf_attach(dev) 671 device_t dev; 672{ 673 int s, i; 674 u_int32_t command; 675 struct sf_softc *sc; 676 struct ifnet *ifp; 677 int unit, rid, error = 0; 678 679 s = splimp(); 680 681 sc = device_get_softc(dev); 682 unit = device_get_unit(dev); 683 bzero(sc, sizeof(struct sf_softc)); 684 685 /* 686 * Handle power management nonsense. 687 */ 688 command = pci_read_config(dev, SF_PCI_CAPID, 4) & 0x000000FF; 689 if (command == 0x01) { 690 691 command = pci_read_config(dev, SF_PCI_PWRMGMTCTRL, 4); 692 if (command & SF_PSTATE_MASK) { 693 u_int32_t iobase, membase, irq; 694 695 /* Save important PCI config data. */ 696 iobase = pci_read_config(dev, SF_PCI_LOIO, 4); 697 membase = pci_read_config(dev, SF_PCI_LOMEM, 4); 698 irq = pci_read_config(dev, SF_PCI_INTLINE, 4); 699 700 /* Reset the power state. */ 701 printf("sf%d: chip is in D%d power mode " 702 "-- setting to D0\n", unit, command & SF_PSTATE_MASK); 703 command &= 0xFFFFFFFC; 704 pci_write_config(dev, SF_PCI_PWRMGMTCTRL, command, 4); 705 706 /* Restore PCI config data. */ 707 pci_write_config(dev, SF_PCI_LOIO, iobase, 4); 708 pci_write_config(dev, SF_PCI_LOMEM, membase, 4); 709 pci_write_config(dev, SF_PCI_INTLINE, irq, 4); 710 } 711 } 712 713 /* 714 * Map control/status registers. 715 */ 716 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 717 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 718 pci_write_config(dev, PCI_COMMAND_STATUS_REG, command, 4); 719 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 720 721#ifdef SF_USEIOSPACE 722 if (!(command & PCIM_CMD_PORTEN)) { 723 printf("sf%d: failed to enable I/O ports!\n", unit); 724 error = ENXIO; 725 goto fail; 726 } 727#else 728 if (!(command & PCIM_CMD_MEMEN)) { 729 printf("sf%d: failed to enable memory mapping!\n", unit); 730 error = ENXIO; 731 goto fail; 732 } 733#endif 734 735 rid = SF_RID; 736 sc->sf_res = bus_alloc_resource(dev, SF_RES, &rid, 737 0, ~0, 1, RF_ACTIVE); 738 739 if (sc->sf_res == NULL) { 740 printf ("sf%d: couldn't map ports\n", unit); 741 error = ENXIO; 742 goto fail; 743 } 744 745 sc->sf_btag = rman_get_bustag(sc->sf_res); 746 sc->sf_bhandle = rman_get_bushandle(sc->sf_res); 747 748 /* Allocate interrupt */ 749 rid = 0; 750 sc->sf_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 751 RF_SHAREABLE | RF_ACTIVE); 752 753 if (sc->sf_irq == NULL) { 754 printf("sf%d: couldn't map interrupt\n", unit); 755 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 756 error = ENXIO; 757 goto fail; 758 } 759 760 error = bus_setup_intr(dev, sc->sf_irq, INTR_TYPE_NET, 761 sf_intr, sc, &sc->sf_intrhand); 762 763 if (error) { 764 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_res); 765 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 766 printf("sf%d: couldn't set up irq\n", unit); 767 goto fail; 768 } 769 770 callout_handle_init(&sc->sf_stat_ch); 771 772 /* Reset the adapter. */ 773 sf_reset(sc); 774 775 /* 776 * Get station address from the EEPROM. 777 */ 778 for (i = 0; i < ETHER_ADDR_LEN; i++) 779 sc->arpcom.ac_enaddr[i] = 780 sf_read_eeprom(sc, SF_EE_NODEADDR + ETHER_ADDR_LEN - i); 781 782 /* 783 * An Adaptec chip was detected. Inform the world. 784 */ 785 printf("sf%d: Ethernet address: %6D\n", unit, 786 sc->arpcom.ac_enaddr, ":"); 787 788 sc->sf_unit = unit; 789 790 /* Allocate the descriptor queues. */ 791 sc->sf_ldata = contigmalloc(sizeof(struct sf_list_data), M_DEVBUF, 792 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 793 794 if (sc->sf_ldata == NULL) { 795 printf("sf%d: no memory for list buffers!\n", unit); 796 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand); 797 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq); 798 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 799 error = ENXIO; 800 goto fail; 801 } 802 803 bzero(sc->sf_ldata, sizeof(struct sf_list_data)); 804 805 /* Do MII setup. */ 806 if (mii_phy_probe(dev, &sc->sf_miibus, 807 sf_ifmedia_upd, sf_ifmedia_sts)) { 808 printf("sf%d: MII without any phy!\n", sc->sf_unit); 809 contigfree(sc->sf_ldata,sizeof(struct sf_list_data),M_DEVBUF); 810 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand); 811 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq); 812 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 813 error = ENXIO; 814 goto fail; 815 } 816 817 ifp = &sc->arpcom.ac_if; 818 ifp->if_softc = sc; 819 ifp->if_unit = unit; 820 ifp->if_name = "sf"; 821 ifp->if_mtu = ETHERMTU; 822 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 823 ifp->if_ioctl = sf_ioctl; 824 ifp->if_output = ether_output; 825 ifp->if_start = sf_start; 826 ifp->if_watchdog = sf_watchdog; 827 ifp->if_init = sf_init; 828 ifp->if_baudrate = 10000000; 829 ifp->if_snd.ifq_maxlen = SF_TX_DLIST_CNT - 1; 830 831 /* 832 * Call MI attach routines. 833 */ 834 if_attach(ifp); 835 ether_ifattach(ifp); 836 837 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header)); 838 839fail: 840 splx(s); 841 return(error); 842} 843 844static int sf_detach(dev) 845 device_t dev; 846{ 847 struct sf_softc *sc; 848 struct ifnet *ifp; 849 int s; 850 851 s = splimp(); 852 853 sc = device_get_softc(dev); 854 ifp = &sc->arpcom.ac_if; 855 856 if_detach(ifp); 857 sf_stop(sc); 858 859 bus_generic_detach(dev); 860 device_delete_child(dev, sc->sf_miibus); 861 862 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand); 863 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq); 864 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 865 866 contigfree(sc->sf_ldata, sizeof(struct sf_list_data), M_DEVBUF); 867 868 splx(s); 869 870 return(0); 871} 872 873static int sf_init_rx_ring(sc) 874 struct sf_softc *sc; 875{ 876 struct sf_list_data *ld; 877 int i; 878 879 ld = sc->sf_ldata; 880 881 bzero((char *)ld->sf_rx_dlist_big, 882 sizeof(struct sf_rx_bufdesc_type0) * SF_RX_DLIST_CNT); 883 bzero((char *)ld->sf_rx_clist, 884 sizeof(struct sf_rx_cmpdesc_type3) * SF_RX_CLIST_CNT); 885 886 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 887 if (sf_newbuf(sc, &ld->sf_rx_dlist_big[i], NULL) == ENOBUFS) 888 return(ENOBUFS); 889 } 890 891 return(0); 892} 893 894static void sf_init_tx_ring(sc) 895 struct sf_softc *sc; 896{ 897 struct sf_list_data *ld; 898 int i; 899 900 ld = sc->sf_ldata; 901 902 bzero((char *)ld->sf_tx_dlist, 903 sizeof(struct sf_tx_bufdesc_type0) * SF_TX_DLIST_CNT); 904 bzero((char *)ld->sf_tx_clist, 905 sizeof(struct sf_tx_cmpdesc_type0) * SF_TX_CLIST_CNT); 906 907 for (i = 0; i < SF_TX_DLIST_CNT; i++) 908 ld->sf_tx_dlist[i].sf_id = SF_TX_BUFDESC_ID; 909 for (i = 0; i < SF_TX_CLIST_CNT; i++) 910 ld->sf_tx_clist[i].sf_type = SF_TXCMPTYPE_TX; 911 912 ld->sf_tx_dlist[SF_TX_DLIST_CNT - 1].sf_end = 1; 913 sc->sf_tx_cnt = 0; 914 915 return; 916} 917 918static int sf_newbuf(sc, c, m) 919 struct sf_softc *sc; 920 struct sf_rx_bufdesc_type0 *c; 921 struct mbuf *m; 922{ 923 struct mbuf *m_new = NULL; 924 925 if (m == NULL) { 926 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 927 if (m_new == NULL) { 928 printf("sf%d: no memory for rx list -- " 929 "packet dropped!\n", sc->sf_unit); 930 return(ENOBUFS); 931 } 932 933 MCLGET(m_new, M_DONTWAIT); 934 if (!(m_new->m_flags & M_EXT)) { 935 printf("sf%d: no memory for rx list -- " 936 "packet dropped!\n", sc->sf_unit); 937 m_freem(m_new); 938 return(ENOBUFS); 939 } 940 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 941 } else { 942 m_new = m; 943 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 944 m_new->m_data = m_new->m_ext.ext_buf; 945 } 946 947 m_adj(m_new, sizeof(u_int64_t)); 948 949 c->sf_mbuf = m_new; 950 c->sf_addrlo = SF_RX_HOSTADDR(vtophys(mtod(m_new, caddr_t))); 951 c->sf_valid = 1; 952 953 return(0); 954} 955 956/* 957 * The starfire is programmed to use 'normal' mode for packet reception, 958 * which means we use the consumer/producer model for both the buffer 959 * descriptor queue and the completion descriptor queue. The only problem 960 * with this is that it involves a lot of register accesses: we have to 961 * read the RX completion consumer and producer indexes and the RX buffer 962 * producer index, plus the RX completion consumer and RX buffer producer 963 * indexes have to be updated. It would have been easier if Adaptec had 964 * put each index in a separate register, especially given that the damn 965 * NIC has a 512K register space. 966 * 967 * In spite of all the lovely features that Adaptec crammed into the 6915, 968 * it is marred by one truly stupid design flaw, which is that receive 969 * buffer addresses must be aligned on a longword boundary. This forces 970 * the packet payload to be unaligned, which is suboptimal on the x86 and 971 * completely unuseable on the Alpha. Our only recourse is to copy received 972 * packets into properly aligned buffers before handing them off. 973 */ 974 975static void sf_rxeof(sc) 976 struct sf_softc *sc; 977{ 978 struct ether_header *eh; 979 struct mbuf *m; 980 struct ifnet *ifp; 981 struct sf_rx_bufdesc_type0 *desc; 982 struct sf_rx_cmpdesc_type3 *cur_rx; 983 u_int32_t rxcons, rxprod; 984 int cmpprodidx, cmpconsidx, bufprodidx; 985 986 ifp = &sc->arpcom.ac_if; 987 988 rxcons = csr_read_4(sc, SF_CQ_CONSIDX); 989 rxprod = csr_read_4(sc, SF_RXDQ_PTR_Q1); 990 cmpprodidx = SF_IDX_LO(csr_read_4(sc, SF_CQ_PRODIDX)); 991 cmpconsidx = SF_IDX_LO(rxcons); 992 bufprodidx = SF_IDX_LO(rxprod); 993 994 while (cmpconsidx != cmpprodidx) { 995 struct mbuf *m0; 996 997 cur_rx = &sc->sf_ldata->sf_rx_clist[cmpconsidx]; 998 desc = &sc->sf_ldata->sf_rx_dlist_big[cur_rx->sf_endidx]; 999 m = desc->sf_mbuf; 1000 SF_INC(cmpconsidx, SF_RX_CLIST_CNT); 1001 SF_INC(bufprodidx, SF_RX_DLIST_CNT); 1002 1003 if (!(cur_rx->sf_status1 & SF_RXSTAT1_OK)) { 1004 ifp->if_ierrors++; 1005 sf_newbuf(sc, desc, m); 1006 continue; 1007 } 1008 1009 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1010 cur_rx->sf_len + ETHER_ALIGN, 0, ifp, NULL); 1011 sf_newbuf(sc, desc, m); 1012 if (m0 == NULL) { 1013 ifp->if_ierrors++; 1014 continue; 1015 } 1016 m_adj(m0, ETHER_ALIGN); 1017 m = m0; 1018 1019 eh = mtod(m, struct ether_header *); 1020 ifp->if_ipackets++; 1021 1022 /* Remove header from mbuf and pass it on. */ 1023 m_adj(m, sizeof(struct ether_header)); 1024 ether_input(ifp, eh, m); 1025 } 1026 1027 csr_write_4(sc, SF_CQ_CONSIDX, 1028 (rxcons & ~SF_CQ_CONSIDX_RXQ1) | cmpconsidx); 1029 csr_write_4(sc, SF_RXDQ_PTR_Q1, 1030 (rxprod & ~SF_RXDQ_PRODIDX) | bufprodidx); 1031 1032 return; 1033} 1034 1035/* 1036 * Read the transmit status from the completion queue and release 1037 * mbufs. Note that the buffer descriptor index in the completion 1038 * descriptor is an offset from the start of the transmit buffer 1039 * descriptor list in bytes. This is important because the manual 1040 * gives the impression that it should match the producer/consumer 1041 * index, which is the offset in 8 byte blocks. 1042 */ 1043static void sf_txeof(sc) 1044 struct sf_softc *sc; 1045{ 1046 int txcons, cmpprodidx, cmpconsidx; 1047 struct sf_tx_cmpdesc_type1 *cur_cmp; 1048 struct sf_tx_bufdesc_type0 *cur_tx; 1049 struct ifnet *ifp; 1050 1051 ifp = &sc->arpcom.ac_if; 1052 1053 txcons = csr_read_4(sc, SF_CQ_CONSIDX); 1054 cmpprodidx = SF_IDX_HI(csr_read_4(sc, SF_CQ_PRODIDX)); 1055 cmpconsidx = SF_IDX_HI(txcons); 1056 1057 while (cmpconsidx != cmpprodidx) { 1058 cur_cmp = &sc->sf_ldata->sf_tx_clist[cmpconsidx]; 1059 cur_tx = &sc->sf_ldata->sf_tx_dlist[cur_cmp->sf_index >> 7]; 1060 SF_INC(cmpconsidx, SF_TX_CLIST_CNT); 1061 1062 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_OK) 1063 ifp->if_opackets++; 1064 else 1065 ifp->if_oerrors++; 1066 1067 sc->sf_tx_cnt--; 1068 if (cur_tx->sf_mbuf != NULL) { 1069 m_freem(cur_tx->sf_mbuf); 1070 cur_tx->sf_mbuf = NULL; 1071 } 1072 } 1073 1074 ifp->if_timer = 0; 1075 ifp->if_flags &= ~IFF_OACTIVE; 1076 1077 csr_write_4(sc, SF_CQ_CONSIDX, 1078 (txcons & ~SF_CQ_CONSIDX_TXQ) | 1079 ((cmpconsidx << 16) & 0xFFFF0000)); 1080 1081 return; 1082} 1083 1084static void sf_intr(arg) 1085 void *arg; 1086{ 1087 struct sf_softc *sc; 1088 struct ifnet *ifp; 1089 u_int32_t status; 1090 1091 sc = arg; 1092 ifp = &sc->arpcom.ac_if; 1093 1094 if (!(csr_read_4(sc, SF_ISR_SHADOW) & SF_ISR_PCIINT_ASSERTED)) 1095 return; 1096 1097 /* Disable interrupts. */ 1098 csr_write_4(sc, SF_IMR, 0x00000000); 1099 1100 for (;;) { 1101 status = csr_read_4(sc, SF_ISR); 1102 if (status) 1103 csr_write_4(sc, SF_ISR, status); 1104 1105 if (!(status & SF_INTRS)) 1106 break; 1107 1108 if (status & SF_ISR_RXDQ1_DMADONE) 1109 sf_rxeof(sc); 1110 1111 if (status & SF_ISR_TX_TXDONE) 1112 sf_txeof(sc); 1113 1114 if (status & SF_ISR_ABNORMALINTR) { 1115 if (status & SF_ISR_STATSOFLOW) { 1116 untimeout(sf_stats_update, sc, 1117 sc->sf_stat_ch); 1118 sf_stats_update(sc); 1119 } else 1120 sf_init(sc); 1121 } 1122 } 1123 1124 /* Re-enable interrupts. */ 1125 csr_write_4(sc, SF_IMR, SF_INTRS); 1126 1127 if (ifp->if_snd.ifq_head != NULL) 1128 sf_start(ifp); 1129 1130 return; 1131} 1132 1133static void sf_init(xsc) 1134 void *xsc; 1135{ 1136 struct sf_softc *sc; 1137 struct ifnet *ifp; 1138 struct mii_data *mii; 1139 int i, s; 1140 1141 s = splimp(); 1142 1143 sc = xsc; 1144 ifp = &sc->arpcom.ac_if; 1145 mii = device_get_softc(sc->sf_miibus); 1146 1147 sf_stop(sc); 1148 sf_reset(sc); 1149 1150 /* Init all the receive filter registers */ 1151 for (i = SF_RXFILT_PERFECT_BASE; 1152 i < (SF_RXFILT_HASH_MAX + 1); i += 4) 1153 csr_write_4(sc, i, 0); 1154 1155 /* Empty stats counter registers. */ 1156 for (i = 0; i < sizeof(struct sf_stats)/sizeof(u_int32_t); i++) 1157 csr_write_4(sc, SF_STATS_BASE + 1158 (i + sizeof(u_int32_t)), 0); 1159 1160 /* Init our MAC address */ 1161 csr_write_4(sc, SF_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1162 csr_write_4(sc, SF_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1163 sf_setperf(sc, 0, (caddr_t)&sc->arpcom.ac_enaddr); 1164 1165 if (sf_init_rx_ring(sc) == ENOBUFS) { 1166 printf("sf%d: initialization failed: no " 1167 "memory for rx buffers\n", sc->sf_unit); 1168 (void)splx(s); 1169 return; 1170 } 1171 1172 sf_init_tx_ring(sc); 1173 1174 csr_write_4(sc, SF_RXFILT, SF_PERFMODE_NORMAL|SF_HASHMODE_WITHVLAN); 1175 1176 /* If we want promiscuous mode, set the allframes bit. */ 1177 if (ifp->if_flags & IFF_PROMISC) { 1178 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 1179 } else { 1180 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 1181 } 1182 1183 if (ifp->if_flags & IFF_BROADCAST) { 1184 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_BROAD); 1185 } else { 1186 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_BROAD); 1187 } 1188 1189 /* Init the completion queue indexes */ 1190 csr_write_4(sc, SF_CQ_CONSIDX, 0); 1191 csr_write_4(sc, SF_CQ_PRODIDX, 0); 1192 1193 /* Init the RX completion queue */ 1194 csr_write_4(sc, SF_RXCQ_CTL_1, 1195 vtophys(sc->sf_ldata->sf_rx_clist) & SF_RXCQ_ADDR); 1196 SF_SETBIT(sc, SF_RXCQ_CTL_1, SF_RXCQTYPE_3); 1197 1198 /* Init RX DMA control. */ 1199 SF_SETBIT(sc, SF_RXDMA_CTL, SF_RXDMA_REPORTBADPKTS); 1200 1201 /* Init the RX buffer descriptor queue. */ 1202 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 1203 vtophys(sc->sf_ldata->sf_rx_dlist_big)); 1204 csr_write_4(sc, SF_RXDQ_CTL_1, (MCLBYTES << 16) | SF_DESCSPACE_16BYTES); 1205 csr_write_4(sc, SF_RXDQ_PTR_Q1, SF_RX_DLIST_CNT - 1); 1206 1207 /* Init the TX completion queue */ 1208 csr_write_4(sc, SF_TXCQ_CTL, 1209 vtophys(sc->sf_ldata->sf_tx_clist) & SF_RXCQ_ADDR); 1210 1211 /* Init the TX buffer descriptor queue. */ 1212 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 1213 vtophys(sc->sf_ldata->sf_tx_dlist)); 1214 SF_SETBIT(sc, SF_TX_FRAMCTL, SF_TXFRMCTL_CPLAFTERTX); 1215 csr_write_4(sc, SF_TXDQ_CTL, 1216 SF_TXBUFDESC_TYPE0|SF_TXMINSPACE_128BYTES|SF_TXSKIPLEN_8BYTES); 1217 SF_SETBIT(sc, SF_TXDQ_CTL, SF_TXDQCTL_NODMACMP); 1218 1219 /* Enable autopadding of short TX frames. */ 1220 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_AUTOPAD); 1221 1222 /* Enable interrupts. */ 1223 csr_write_4(sc, SF_IMR, SF_INTRS); 1224 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_INTR_ENB); 1225 1226 /* Enable the RX and TX engines. */ 1227 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_RX_ENB|SF_ETHCTL_RXDMA_ENB); 1228 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_TX_ENB|SF_ETHCTL_TXDMA_ENB); 1229 1230 /*mii_mediachg(mii);*/ 1231 sf_ifmedia_upd(ifp); 1232 1233 ifp->if_flags |= IFF_RUNNING; 1234 ifp->if_flags &= ~IFF_OACTIVE; 1235 1236 sc->sf_stat_ch = timeout(sf_stats_update, sc, hz); 1237 1238 splx(s); 1239 1240 return; 1241} 1242 1243static int sf_encap(sc, c, m_head) 1244 struct sf_softc *sc; 1245 struct sf_tx_bufdesc_type0 *c; 1246 struct mbuf *m_head; 1247{ 1248 int frag = 0; 1249 struct sf_frag *f = NULL; 1250 struct mbuf *m; 1251 1252 m = m_head; 1253 1254 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1255 if (m->m_len != 0) { 1256 if (frag == SF_MAXFRAGS) 1257 break; 1258 f = &c->sf_frags[frag]; 1259 if (frag == 0) 1260 f->sf_pktlen = m_head->m_pkthdr.len; 1261 f->sf_fraglen = m->m_len; 1262 f->sf_addr = vtophys(mtod(m, vm_offset_t)); 1263 frag++; 1264 } 1265 } 1266 1267 if (m != NULL) { 1268 struct mbuf *m_new = NULL; 1269 1270 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1271 if (m_new == NULL) { 1272 printf("sf%d: no memory for tx list", sc->sf_unit); 1273 return(1); 1274 } 1275 1276 if (m_head->m_pkthdr.len > MHLEN) { 1277 MCLGET(m_new, M_DONTWAIT); 1278 if (!(m_new->m_flags & M_EXT)) { 1279 m_freem(m_new); 1280 printf("sf%d: no memory for tx list", 1281 sc->sf_unit); 1282 return(1); 1283 } 1284 } 1285 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1286 mtod(m_new, caddr_t)); 1287 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1288 m_freem(m_head); 1289 m_head = m_new; 1290 f = &c->sf_frags[0]; 1291 f->sf_fraglen = f->sf_pktlen = m_head->m_pkthdr.len; 1292 f->sf_addr = vtophys(mtod(m_head, caddr_t)); 1293 frag = 1; 1294 } 1295 1296 c->sf_mbuf = m_head; 1297 c->sf_id = SF_TX_BUFDESC_ID; 1298 c->sf_fragcnt = frag; 1299 c->sf_intr = 1; 1300 c->sf_caltcp = 0; 1301 c->sf_crcen = 1; 1302 1303 return(0); 1304} 1305 1306static void sf_start(ifp) 1307 struct ifnet *ifp; 1308{ 1309 struct sf_softc *sc; 1310 struct sf_tx_bufdesc_type0 *cur_tx = NULL; 1311 struct mbuf *m_head = NULL; 1312 int i, txprod; 1313 1314 sc = ifp->if_softc; 1315 1316 if (!sc->sf_link) 1317 return; 1318 1319 if (ifp->if_flags & IFF_OACTIVE) 1320 return; 1321 1322 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX); 1323 i = SF_IDX_HI(txprod) >> 4; 1324 1325 while(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf == NULL) { 1326 IF_DEQUEUE(&ifp->if_snd, m_head); 1327 if (m_head == NULL) 1328 break; 1329 1330 cur_tx = &sc->sf_ldata->sf_tx_dlist[i]; 1331 sf_encap(sc, cur_tx, m_head); 1332 1333 /* 1334 * If there's a BPF listener, bounce a copy of this frame 1335 * to him. 1336 */ 1337 if (ifp->if_bpf) 1338 bpf_mtap(ifp, m_head); 1339 1340 SF_INC(i, SF_TX_DLIST_CNT); 1341 sc->sf_tx_cnt++; 1342 if (sc->sf_tx_cnt == (SF_TX_DLIST_CNT - 2)) 1343 break; 1344 } 1345 1346 if (cur_tx == NULL) 1347 return; 1348 1349 /* Transmit */ 1350 csr_write_4(sc, SF_TXDQ_PRODIDX, 1351 (txprod & ~SF_TXDQ_PRODIDX_HIPRIO) | 1352 ((i << 20) & 0xFFFF0000)); 1353 1354 ifp->if_timer = 5; 1355 1356 return; 1357} 1358 1359static void sf_stop(sc) 1360 struct sf_softc *sc; 1361{ 1362 int i; 1363 struct ifnet *ifp; 1364 1365 ifp = &sc->arpcom.ac_if; 1366 1367 untimeout(sf_stats_update, sc, sc->sf_stat_ch); 1368 1369 csr_write_4(sc, SF_GEN_ETH_CTL, 0); 1370 csr_write_4(sc, SF_CQ_CONSIDX, 0); 1371 csr_write_4(sc, SF_CQ_PRODIDX, 0); 1372 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 0); 1373 csr_write_4(sc, SF_RXDQ_CTL_1, 0); 1374 csr_write_4(sc, SF_RXDQ_PTR_Q1, 0); 1375 csr_write_4(sc, SF_TXCQ_CTL, 0); 1376 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 0); 1377 csr_write_4(sc, SF_TXDQ_CTL, 0); 1378 sf_reset(sc); 1379 1380 sc->sf_link = 0; 1381 1382 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 1383 if (sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf != NULL) { 1384 m_freem(sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf); 1385 sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf = NULL; 1386 } 1387 } 1388 1389 for (i = 0; i < SF_TX_DLIST_CNT; i++) { 1390 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) { 1391 m_freem(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf); 1392 sc->sf_ldata->sf_tx_dlist[i].sf_mbuf = NULL; 1393 } 1394 } 1395 1396 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 1397 1398 return; 1399} 1400 1401/* 1402 * Note: it is important that this function not be interrupted. We 1403 * use a two-stage register access scheme: if we are interrupted in 1404 * between setting the indirect address register and reading from the 1405 * indirect data register, the contents of the address register could 1406 * be changed out from under us. 1407 */ 1408static void sf_stats_update(xsc) 1409 void *xsc; 1410{ 1411 struct sf_softc *sc; 1412 struct ifnet *ifp; 1413 struct mii_data *mii; 1414 struct sf_stats stats; 1415 u_int32_t *ptr; 1416 int i, s; 1417 1418 s = splimp(); 1419 1420 sc = xsc; 1421 ifp = &sc->arpcom.ac_if; 1422 mii = device_get_softc(sc->sf_miibus); 1423 1424 ptr = (u_int32_t *)&stats; 1425 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++) 1426 ptr[i] = csr_read_4(sc, SF_STATS_BASE + 1427 (i + sizeof(u_int32_t))); 1428 1429 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++) 1430 csr_write_4(sc, SF_STATS_BASE + 1431 (i + sizeof(u_int32_t)), 0); 1432 1433 ifp->if_collisions += stats.sf_tx_single_colls + 1434 stats.sf_tx_multi_colls + stats.sf_tx_excess_colls; 1435 1436 mii_tick(mii); 1437 if (!sc->sf_link) { 1438 mii_pollstat(mii); 1439 if (mii->mii_media_status & IFM_ACTIVE && 1440 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1441 sc->sf_link++; 1442 if (ifp->if_snd.ifq_head != NULL) 1443 sf_start(ifp); 1444 } 1445 1446 sc->sf_stat_ch = timeout(sf_stats_update, sc, hz); 1447 1448 splx(s); 1449 1450 return; 1451} 1452 1453static void sf_watchdog(ifp) 1454 struct ifnet *ifp; 1455{ 1456 struct sf_softc *sc; 1457 1458 sc = ifp->if_softc; 1459 1460 ifp->if_oerrors++; 1461 printf("sf%d: watchdog timeout\n", sc->sf_unit); 1462 1463 sf_stop(sc); 1464 sf_reset(sc); 1465 sf_init(sc); 1466 1467 if (ifp->if_snd.ifq_head != NULL) 1468 sf_start(ifp); 1469 1470 return; 1471} 1472 1473static void sf_shutdown(dev) 1474 device_t dev; 1475{ 1476 struct sf_softc *sc; 1477 1478 sc = device_get_softc(dev); 1479 1480 sf_stop(sc); 1481 1482 return; 1483} 1484