if_sf.c revision 54161
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/dev/sf/if_sf.c 54161 1999-12-05 20:02:45Z wpaul $ 33 */ 34 35/* 36 * Adaptec AIC-6915 "Starfire" PCI fast ethernet driver for FreeBSD. 37 * Programming manual is available from: 38 * ftp.adaptec.com:/pub/BBS/userguides/aic6915_pg.pdf. 39 * 40 * Written by Bill Paul <wpaul@ctr.columbia.edu> 41 * Department of Electical Engineering 42 * Columbia University, New York City 43 */ 44 45/* 46 * The Adaptec AIC-6915 "Starfire" is a 64-bit 10/100 PCI ethernet 47 * controller designed with flexibility and reducing CPU load in mind. 48 * The Starfire offers high and low priority buffer queues, a 49 * producer/consumer index mechanism and several different buffer 50 * queue and completion queue descriptor types. Any one of a number 51 * of different driver designs can be used, depending on system and 52 * OS requirements. This driver makes use of type0 transmit frame 53 * descriptors (since BSD fragments packets across an mbuf chain) 54 * and two RX buffer queues prioritized on size (one queue for small 55 * frames that will fit into a single mbuf, another with full size 56 * mbuf clusters for everything else). The producer/consumer indexes 57 * and completion queues are also used. 58 * 59 * One downside to the Starfire has to do with alignment: buffer 60 * queues must be aligned on 256-byte boundaries, and receive buffers 61 * must be aligned on longword boundaries. The receive buffer alignment 62 * causes problems on the Alpha platform, where the packet payload 63 * should be longword aligned. There is no simple way around this. 64 * 65 * For receive filtering, the Starfire offers 16 perfect filter slots 66 * and a 512-bit hash table. 67 * 68 * The Starfire has no internal transceiver, relying instead on an 69 * external MII-based transceiver. Accessing registers on external 70 * PHYs is done through a special register map rather than with the 71 * usual bitbang MDIO method. 72 * 73 * Acesssing the registers on the Starfire is a little tricky. The 74 * Starfire has a 512K internal register space. When programmed for 75 * PCI memory mapped mode, the entire register space can be accessed 76 * directly. However in I/O space mode, only 256 bytes are directly 77 * mapped into PCI I/O space. The other registers can be accessed 78 * indirectly using the SF_INDIRECTIO_ADDR and SF_INDIRECTIO_DATA 79 * registers inside the 256-byte I/O window. 80 */ 81 82#include <sys/param.h> 83#include <sys/systm.h> 84#include <sys/sockio.h> 85#include <sys/mbuf.h> 86#include <sys/malloc.h> 87#include <sys/kernel.h> 88#include <sys/socket.h> 89 90#include <net/if.h> 91#include <net/if_arp.h> 92#include <net/ethernet.h> 93#include <net/if_dl.h> 94#include <net/if_media.h> 95 96#include <net/bpf.h> 97 98#include <vm/vm.h> /* for vtophys */ 99#include <vm/pmap.h> /* for vtophys */ 100#include <machine/clock.h> /* for DELAY */ 101#include <machine/bus_pio.h> 102#include <machine/bus_memio.h> 103#include <machine/bus.h> 104#include <machine/resource.h> 105#include <sys/bus.h> 106#include <sys/rman.h> 107 108#include <dev/mii/mii.h> 109#include <dev/mii/miivar.h> 110 111/* "controller miibus0" required. See GENERIC if you get errors here. */ 112#include "miibus_if.h" 113 114#include <pci/pcireg.h> 115#include <pci/pcivar.h> 116 117#define SF_USEIOSPACE 118 119#include <pci/if_sfreg.h> 120 121#ifndef lint 122static const char rcsid[] = 123 "$FreeBSD: head/sys/dev/sf/if_sf.c 54161 1999-12-05 20:02:45Z wpaul $"; 124#endif 125 126static struct sf_type sf_devs[] = { 127 { AD_VENDORID, AD_DEVICEID_STARFIRE, 128 "Adaptec AIC-6915 10/100BaseTX" }, 129 { 0, 0, NULL } 130}; 131 132static int sf_probe __P((device_t)); 133static int sf_attach __P((device_t)); 134static int sf_detach __P((device_t)); 135static void sf_intr __P((void *)); 136static void sf_stats_update __P((void *)); 137static void sf_rxeof __P((struct sf_softc *)); 138static void sf_txeof __P((struct sf_softc *)); 139static int sf_encap __P((struct sf_softc *, 140 struct sf_tx_bufdesc_type0 *, 141 struct mbuf *)); 142static void sf_start __P((struct ifnet *)); 143static int sf_ioctl __P((struct ifnet *, u_long, caddr_t)); 144static void sf_init __P((void *)); 145static void sf_stop __P((struct sf_softc *)); 146static void sf_watchdog __P((struct ifnet *)); 147static void sf_shutdown __P((device_t)); 148static int sf_ifmedia_upd __P((struct ifnet *)); 149static void sf_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 150static void sf_reset __P((struct sf_softc *)); 151static int sf_init_rx_ring __P((struct sf_softc *)); 152static void sf_init_tx_ring __P((struct sf_softc *)); 153static int sf_newbuf __P((struct sf_softc *, 154 struct sf_rx_bufdesc_type0 *, 155 struct mbuf *)); 156static void sf_setmulti __P((struct sf_softc *)); 157static int sf_setperf __P((struct sf_softc *, int, caddr_t)); 158static int sf_sethash __P((struct sf_softc *, caddr_t, int)); 159#ifdef notdef 160static int sf_setvlan __P((struct sf_softc *, int, u_int32_t)); 161#endif 162 163static u_int8_t sf_read_eeprom __P((struct sf_softc *, int)); 164static u_int32_t sf_calchash __P((caddr_t)); 165 166static int sf_miibus_readreg __P((device_t, int, int)); 167static int sf_miibus_writereg __P((device_t, int, int, int)); 168static void sf_miibus_statchg __P((device_t)); 169 170static u_int32_t csr_read_4 __P((struct sf_softc *, int)); 171static void csr_write_4 __P((struct sf_softc *, int, u_int32_t)); 172 173#ifdef SF_USEIOSPACE 174#define SF_RES SYS_RES_IOPORT 175#define SF_RID SF_PCI_LOIO 176#else 177#define SF_RES SYS_RES_MEMORY 178#define SF_RID SF_PCI_LOMEM 179#endif 180 181static device_method_t sf_methods[] = { 182 /* Device interface */ 183 DEVMETHOD(device_probe, sf_probe), 184 DEVMETHOD(device_attach, sf_attach), 185 DEVMETHOD(device_detach, sf_detach), 186 DEVMETHOD(device_shutdown, sf_shutdown), 187 188 /* bus interface */ 189 DEVMETHOD(bus_print_child, bus_generic_print_child), 190 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 191 192 /* MII interface */ 193 DEVMETHOD(miibus_readreg, sf_miibus_readreg), 194 DEVMETHOD(miibus_writereg, sf_miibus_writereg), 195 DEVMETHOD(miibus_statchg, sf_miibus_statchg), 196 197 { 0, 0 } 198}; 199 200static driver_t sf_driver = { 201 "sf", 202 sf_methods, 203 sizeof(struct sf_softc), 204}; 205 206static devclass_t sf_devclass; 207 208DRIVER_MODULE(if_sf, pci, sf_driver, sf_devclass, 0, 0); 209DRIVER_MODULE(miibus, sf, miibus_driver, miibus_devclass, 0, 0); 210 211#define SF_SETBIT(sc, reg, x) \ 212 csr_write_4(sc, reg, csr_read_4(sc, reg) | x) 213 214#define SF_CLRBIT(sc, reg, x) \ 215 csr_write_4(sc, reg, csr_read_4(sc, reg) & ~x) 216 217static u_int32_t csr_read_4(sc, reg) 218 struct sf_softc *sc; 219 int reg; 220{ 221 u_int32_t val; 222 223#ifdef SF_USEIOSPACE 224 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); 225 val = CSR_READ_4(sc, SF_INDIRECTIO_DATA); 226#else 227 val = CSR_READ_4(sc, (reg + SF_RMAP_INTREG_BASE)); 228#endif 229 230 return(val); 231} 232 233static u_int8_t sf_read_eeprom(sc, reg) 234 struct sf_softc *sc; 235 int reg; 236{ 237 u_int8_t val; 238 239 val = (csr_read_4(sc, SF_EEADDR_BASE + 240 (reg & 0xFFFFFFFC)) >> (8 * (reg & 3))) & 0xFF; 241 242 return(val); 243} 244 245static void csr_write_4(sc, reg, val) 246 struct sf_softc *sc; 247 int reg; 248 u_int32_t val; 249{ 250#ifdef SF_USEIOSPACE 251 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); 252 CSR_WRITE_4(sc, SF_INDIRECTIO_DATA, val); 253#else 254 CSR_WRITE_4(sc, (reg + SF_RMAP_INTREG_BASE), val); 255#endif 256 return; 257} 258 259static u_int32_t sf_calchash(addr) 260 caddr_t addr; 261{ 262 u_int32_t crc, carry; 263 int i, j; 264 u_int8_t c; 265 266 /* Compute CRC for the address value. */ 267 crc = 0xFFFFFFFF; /* initial value */ 268 269 for (i = 0; i < 6; i++) { 270 c = *(addr + i); 271 for (j = 0; j < 8; j++) { 272 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 273 crc <<= 1; 274 c >>= 1; 275 if (carry) 276 crc = (crc ^ 0x04c11db6) | carry; 277 } 278 } 279 280 /* return the filter bit position */ 281 return(crc >> 23 & 0x1FF); 282} 283 284/* 285 * Copy the address 'mac' into the perfect RX filter entry at 286 * offset 'idx.' The perfect filter only has 16 entries so do 287 * some sanity tests. 288 */ 289static int sf_setperf(sc, idx, mac) 290 struct sf_softc *sc; 291 int idx; 292 caddr_t mac; 293{ 294 u_int16_t *p; 295 296 if (idx < 0 || idx > SF_RXFILT_PERFECT_CNT) 297 return(EINVAL); 298 299 if (mac == NULL) 300 return(EINVAL); 301 302 p = (u_int16_t *)mac; 303 304 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 305 (idx * SF_RXFILT_PERFECT_SKIP), htons(p[2])); 306 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 307 (idx * SF_RXFILT_PERFECT_SKIP) + 4, htons(p[1])); 308 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 309 (idx * SF_RXFILT_PERFECT_SKIP) + 8, htons(p[0])); 310 311 return(0); 312} 313 314/* 315 * Set the bit in the 512-bit hash table that corresponds to the 316 * specified mac address 'mac.' If 'prio' is nonzero, update the 317 * priority hash table instead of the filter hash table. 318 */ 319static int sf_sethash(sc, mac, prio) 320 struct sf_softc *sc; 321 caddr_t mac; 322 int prio; 323{ 324 u_int32_t h = 0; 325 326 if (mac == NULL) 327 return(EINVAL); 328 329 h = sf_calchash(mac); 330 331 if (prio) { 332 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_PRIOOFF + 333 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); 334 } else { 335 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_ADDROFF + 336 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); 337 } 338 339 return(0); 340} 341 342#ifdef notdef 343/* 344 * Set a VLAN tag in the receive filter. 345 */ 346static int sf_setvlan(sc, idx, vlan) 347 struct sf_softc *sc; 348 int idx; 349 u_int32_t vlan; 350{ 351 if (idx < 0 || idx >> SF_RXFILT_HASH_CNT) 352 return(EINVAL); 353 354 csr_write_4(sc, SF_RXFILT_HASH_BASE + 355 (idx * SF_RXFILT_HASH_SKIP) + SF_RXFILT_HASH_VLANOFF, vlan); 356 357 return(0); 358} 359#endif 360 361static int sf_miibus_readreg(dev, phy, reg) 362 device_t dev; 363 int phy, reg; 364{ 365 struct sf_softc *sc; 366 int i; 367 u_int32_t val = 0; 368 369 sc = device_get_softc(dev); 370 371 for (i = 0; i < SF_TIMEOUT; i++) { 372 val = csr_read_4(sc, SF_PHY_REG(phy, reg)); 373 if (val & SF_MII_DATAVALID) 374 break; 375 } 376 377 if (i == SF_TIMEOUT) 378 return(0); 379 380 if ((val & 0x0000FFFF) == 0xFFFF) 381 return(0); 382 383 return(val & 0x0000FFFF); 384} 385 386static int sf_miibus_writereg(dev, phy, reg, val) 387 device_t dev; 388 int phy, reg, val; 389{ 390 struct sf_softc *sc; 391 int i; 392 int busy; 393 394 sc = device_get_softc(dev); 395 396 csr_write_4(sc, SF_PHY_REG(phy, reg), val); 397 398 for (i = 0; i < SF_TIMEOUT; i++) { 399 busy = csr_read_4(sc, SF_PHY_REG(phy, reg)); 400 if (!(busy & SF_MII_BUSY)) 401 break; 402 } 403 404 return(0); 405} 406 407static void sf_miibus_statchg(dev) 408 device_t dev; 409{ 410 struct sf_softc *sc; 411 struct mii_data *mii; 412 413 sc = device_get_softc(dev); 414 mii = device_get_softc(sc->sf_miibus); 415 416 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 417 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 418 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_FDX); 419 } else { 420 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 421 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_HDX); 422 } 423 424 return; 425} 426 427static void sf_setmulti(sc) 428 struct sf_softc *sc; 429{ 430 struct ifnet *ifp; 431 int i; 432 struct ifmultiaddr *ifma; 433 u_int8_t dummy[] = { 0, 0, 0, 0, 0, 0 }; 434 435 ifp = &sc->arpcom.ac_if; 436 437 /* First zot all the existing filters. */ 438 for (i = 1; i < SF_RXFILT_PERFECT_CNT; i++) 439 sf_setperf(sc, i, (char *)&dummy); 440 for (i = SF_RXFILT_HASH_BASE; 441 i < (SF_RXFILT_HASH_MAX + 1); i += 4) 442 csr_write_4(sc, i, 0); 443 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI); 444 445 /* Now program new ones. */ 446 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 447 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI); 448 } else { 449 i = 1; 450 /* First find the tail of the list. */ 451 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 452 ifma = ifma->ifma_link.le_next) { 453 if (ifma->ifma_link.le_next == NULL) 454 break; 455 } 456 /* Now traverse the list backwards. */ 457 for (; ifma != NULL && ifma != (void *)&ifp->if_multiaddrs; 458 ifma = (struct ifmultiaddr *)ifma->ifma_link.le_prev) { 459 if (ifma->ifma_addr->sa_family != AF_LINK) 460 continue; 461 /* 462 * Program the first 15 multicast groups 463 * into the perfect filter. For all others, 464 * use the hash table. 465 */ 466 if (i < SF_RXFILT_PERFECT_CNT) { 467 sf_setperf(sc, i, 468 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 469 i++; 470 continue; 471 } 472 473 sf_sethash(sc, 474 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 0); 475 } 476 } 477 478 return; 479} 480 481/* 482 * Set media options. 483 */ 484static int sf_ifmedia_upd(ifp) 485 struct ifnet *ifp; 486{ 487 struct sf_softc *sc; 488 struct mii_data *mii; 489 490 sc = ifp->if_softc; 491 mii = device_get_softc(sc->sf_miibus); 492 sc->sf_link = 0; 493 if (mii->mii_instance) { 494 struct mii_softc *miisc; 495 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 496 miisc = LIST_NEXT(miisc, mii_list)) 497 mii_phy_reset(miisc); 498 } 499 mii_mediachg(mii); 500 501 return(0); 502} 503 504/* 505 * Report current media status. 506 */ 507static void sf_ifmedia_sts(ifp, ifmr) 508 struct ifnet *ifp; 509 struct ifmediareq *ifmr; 510{ 511 struct sf_softc *sc; 512 struct mii_data *mii; 513 514 sc = ifp->if_softc; 515 mii = device_get_softc(sc->sf_miibus); 516 517 mii_pollstat(mii); 518 ifmr->ifm_active = mii->mii_media_active; 519 ifmr->ifm_status = mii->mii_media_status; 520 521 return; 522} 523 524static int sf_ioctl(ifp, command, data) 525 struct ifnet *ifp; 526 u_long command; 527 caddr_t data; 528{ 529 struct sf_softc *sc = ifp->if_softc; 530 struct ifreq *ifr = (struct ifreq *) data; 531 struct mii_data *mii; 532 int s, error = 0; 533 534 s = splimp(); 535 536 switch(command) { 537 case SIOCSIFADDR: 538 case SIOCGIFADDR: 539 case SIOCSIFMTU: 540 error = ether_ioctl(ifp, command, data); 541 break; 542 case SIOCSIFFLAGS: 543 if (ifp->if_flags & IFF_UP) { 544 if (ifp->if_flags & IFF_RUNNING && 545 ifp->if_flags & IFF_PROMISC && 546 !(sc->sf_if_flags & IFF_PROMISC)) { 547 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 548 } else if (ifp->if_flags & IFF_RUNNING && 549 !(ifp->if_flags & IFF_PROMISC) && 550 sc->sf_if_flags & IFF_PROMISC) { 551 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 552 } else if (!(ifp->if_flags & IFF_RUNNING)) 553 sf_init(sc); 554 } else { 555 if (ifp->if_flags & IFF_RUNNING) 556 sf_stop(sc); 557 } 558 sc->sf_if_flags = ifp->if_flags; 559 error = 0; 560 break; 561 case SIOCADDMULTI: 562 case SIOCDELMULTI: 563 sf_setmulti(sc); 564 error = 0; 565 break; 566 case SIOCGIFMEDIA: 567 case SIOCSIFMEDIA: 568 mii = device_get_softc(sc->sf_miibus); 569 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 570 break; 571 default: 572 error = EINVAL; 573 break; 574 } 575 576 (void)splx(s); 577 578 return(error); 579} 580 581static void sf_reset(sc) 582 struct sf_softc *sc; 583{ 584 register int i; 585 586 csr_write_4(sc, SF_GEN_ETH_CTL, 0); 587 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 588 DELAY(1000); 589 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 590 591 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_RESET); 592 593 for (i = 0; i < SF_TIMEOUT; i++) { 594 DELAY(10); 595 if (!(csr_read_4(sc, SF_PCI_DEVCFG) & SF_PCIDEVCFG_RESET)) 596 break; 597 } 598 599 if (i == SF_TIMEOUT) 600 printf("sf%d: reset never completed!\n", sc->sf_unit); 601 602 /* Wait a little while for the chip to get its brains in order. */ 603 DELAY(1000); 604 return; 605} 606 607/* 608 * Probe for an Adaptec AIC-6915 chip. Check the PCI vendor and device 609 * IDs against our list and return a device name if we find a match. 610 * We also check the subsystem ID so that we can identify exactly which 611 * NIC has been found, if possible. 612 */ 613static int sf_probe(dev) 614 device_t dev; 615{ 616 struct sf_type *t; 617 618 t = sf_devs; 619 620 while(t->sf_name != NULL) { 621 if ((pci_get_vendor(dev) == t->sf_vid) && 622 (pci_get_device(dev) == t->sf_did)) { 623 switch((pci_read_config(dev, 624 SF_PCI_SUBVEN_ID, 4) >> 16) & 0xFFFF) { 625 case AD_SUBSYSID_62011_REV0: 626 case AD_SUBSYSID_62011_REV1: 627 device_set_desc(dev, 628 "Adaptec ANA-62011 10/100BaseTX"); 629 return(0); 630 break; 631 case AD_SUBSYSID_62022: 632 device_set_desc(dev, 633 "Adaptec ANA-62022 10/100BaseTX"); 634 return(0); 635 break; 636 case AD_SUBSYSID_62044_REV0: 637 case AD_SUBSYSID_62044_REV1: 638 device_set_desc(dev, 639 "Adaptec ANA-62044 10/100BaseTX"); 640 return(0); 641 break; 642 case AD_SUBSYSID_62020: 643 device_set_desc(dev, 644 "Adaptec ANA-62020 10/100BaseFX"); 645 return(0); 646 break; 647 case AD_SUBSYSID_69011: 648 device_set_desc(dev, 649 "Adaptec ANA-69011 10/100BaseTX"); 650 return(0); 651 break; 652 default: 653 device_set_desc(dev, t->sf_name); 654 return(0); 655 break; 656 } 657 } 658 t++; 659 } 660 661 return(ENXIO); 662} 663 664/* 665 * Attach the interface. Allocate softc structures, do ifmedia 666 * setup and ethernet/BPF attach. 667 */ 668static int sf_attach(dev) 669 device_t dev; 670{ 671 int s, i; 672 u_int32_t command; 673 struct sf_softc *sc; 674 struct ifnet *ifp; 675 int unit, rid, error = 0; 676 677 s = splimp(); 678 679 sc = device_get_softc(dev); 680 unit = device_get_unit(dev); 681 bzero(sc, sizeof(struct sf_softc)); 682 683 /* 684 * Handle power management nonsense. 685 */ 686 command = pci_read_config(dev, SF_PCI_CAPID, 4) & 0x000000FF; 687 if (command == 0x01) { 688 689 command = pci_read_config(dev, SF_PCI_PWRMGMTCTRL, 4); 690 if (command & SF_PSTATE_MASK) { 691 u_int32_t iobase, membase, irq; 692 693 /* Save important PCI config data. */ 694 iobase = pci_read_config(dev, SF_PCI_LOIO, 4); 695 membase = pci_read_config(dev, SF_PCI_LOMEM, 4); 696 irq = pci_read_config(dev, SF_PCI_INTLINE, 4); 697 698 /* Reset the power state. */ 699 printf("sf%d: chip is in D%d power mode " 700 "-- setting to D0\n", unit, command & SF_PSTATE_MASK); 701 command &= 0xFFFFFFFC; 702 pci_write_config(dev, SF_PCI_PWRMGMTCTRL, command, 4); 703 704 /* Restore PCI config data. */ 705 pci_write_config(dev, SF_PCI_LOIO, iobase, 4); 706 pci_write_config(dev, SF_PCI_LOMEM, membase, 4); 707 pci_write_config(dev, SF_PCI_INTLINE, irq, 4); 708 } 709 } 710 711 /* 712 * Map control/status registers. 713 */ 714 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 715 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 716 pci_write_config(dev, PCI_COMMAND_STATUS_REG, command, 4); 717 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 718 719#ifdef SF_USEIOSPACE 720 if (!(command & PCIM_CMD_PORTEN)) { 721 printf("sf%d: failed to enable I/O ports!\n", unit); 722 error = ENXIO; 723 goto fail; 724 } 725#else 726 if (!(command & PCIM_CMD_MEMEN)) { 727 printf("sf%d: failed to enable memory mapping!\n", unit); 728 error = ENXIO; 729 goto fail; 730 } 731#endif 732 733 rid = SF_RID; 734 sc->sf_res = bus_alloc_resource(dev, SF_RES, &rid, 735 0, ~0, 1, RF_ACTIVE); 736 737 if (sc->sf_res == NULL) { 738 printf ("sf%d: couldn't map ports\n", unit); 739 error = ENXIO; 740 goto fail; 741 } 742 743 sc->sf_btag = rman_get_bustag(sc->sf_res); 744 sc->sf_bhandle = rman_get_bushandle(sc->sf_res); 745 746 /* Allocate interrupt */ 747 rid = 0; 748 sc->sf_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 749 RF_SHAREABLE | RF_ACTIVE); 750 751 if (sc->sf_irq == NULL) { 752 printf("sf%d: couldn't map interrupt\n", unit); 753 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 754 error = ENXIO; 755 goto fail; 756 } 757 758 error = bus_setup_intr(dev, sc->sf_irq, INTR_TYPE_NET, 759 sf_intr, sc, &sc->sf_intrhand); 760 761 if (error) { 762 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_res); 763 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 764 printf("sf%d: couldn't set up irq\n", unit); 765 goto fail; 766 } 767 768 callout_handle_init(&sc->sf_stat_ch); 769 770 /* Reset the adapter. */ 771 sf_reset(sc); 772 773 /* 774 * Get station address from the EEPROM. 775 */ 776 for (i = 0; i < ETHER_ADDR_LEN; i++) 777 sc->arpcom.ac_enaddr[i] = 778 sf_read_eeprom(sc, SF_EE_NODEADDR + ETHER_ADDR_LEN - i); 779 780 /* 781 * An Adaptec chip was detected. Inform the world. 782 */ 783 printf("sf%d: Ethernet address: %6D\n", unit, 784 sc->arpcom.ac_enaddr, ":"); 785 786 sc->sf_unit = unit; 787 788 /* Allocate the descriptor queues. */ 789 sc->sf_ldata = contigmalloc(sizeof(struct sf_list_data), M_DEVBUF, 790 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 791 792 if (sc->sf_ldata == NULL) { 793 printf("sf%d: no memory for list buffers!\n", unit); 794 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand); 795 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq); 796 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 797 error = ENXIO; 798 goto fail; 799 } 800 801 bzero(sc->sf_ldata, sizeof(struct sf_list_data)); 802 803 /* Do MII setup. */ 804 if (mii_phy_probe(dev, &sc->sf_miibus, 805 sf_ifmedia_upd, sf_ifmedia_sts)) { 806 printf("sf%d: MII without any phy!\n", sc->sf_unit); 807 contigfree(sc->sf_ldata,sizeof(struct sf_list_data),M_DEVBUF); 808 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand); 809 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq); 810 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 811 error = ENXIO; 812 goto fail; 813 } 814 815 ifp = &sc->arpcom.ac_if; 816 ifp->if_softc = sc; 817 ifp->if_unit = unit; 818 ifp->if_name = "sf"; 819 ifp->if_mtu = ETHERMTU; 820 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 821 ifp->if_ioctl = sf_ioctl; 822 ifp->if_output = ether_output; 823 ifp->if_start = sf_start; 824 ifp->if_watchdog = sf_watchdog; 825 ifp->if_init = sf_init; 826 ifp->if_baudrate = 10000000; 827 ifp->if_snd.ifq_maxlen = SF_TX_DLIST_CNT - 1; 828 829 /* 830 * Call MI attach routines. 831 */ 832 if_attach(ifp); 833 ether_ifattach(ifp); 834 835 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header)); 836 837fail: 838 splx(s); 839 return(error); 840} 841 842static int sf_detach(dev) 843 device_t dev; 844{ 845 struct sf_softc *sc; 846 struct ifnet *ifp; 847 int s; 848 849 s = splimp(); 850 851 sc = device_get_softc(dev); 852 ifp = &sc->arpcom.ac_if; 853 854 if_detach(ifp); 855 sf_stop(sc); 856 857 bus_generic_detach(dev); 858 device_delete_child(dev, sc->sf_miibus); 859 860 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand); 861 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq); 862 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 863 864 contigfree(sc->sf_ldata, sizeof(struct sf_list_data), M_DEVBUF); 865 866 splx(s); 867 868 return(0); 869} 870 871static int sf_init_rx_ring(sc) 872 struct sf_softc *sc; 873{ 874 struct sf_list_data *ld; 875 int i; 876 877 ld = sc->sf_ldata; 878 879 bzero((char *)ld->sf_rx_dlist_big, 880 sizeof(struct sf_rx_bufdesc_type0) * SF_RX_DLIST_CNT); 881 bzero((char *)ld->sf_rx_clist, 882 sizeof(struct sf_rx_cmpdesc_type3) * SF_RX_CLIST_CNT); 883 884 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 885 if (sf_newbuf(sc, &ld->sf_rx_dlist_big[i], NULL) == ENOBUFS) 886 return(ENOBUFS); 887 } 888 889 return(0); 890} 891 892static void sf_init_tx_ring(sc) 893 struct sf_softc *sc; 894{ 895 struct sf_list_data *ld; 896 int i; 897 898 ld = sc->sf_ldata; 899 900 bzero((char *)ld->sf_tx_dlist, 901 sizeof(struct sf_tx_bufdesc_type0) * SF_TX_DLIST_CNT); 902 bzero((char *)ld->sf_tx_clist, 903 sizeof(struct sf_tx_cmpdesc_type0) * SF_TX_CLIST_CNT); 904 905 for (i = 0; i < SF_TX_DLIST_CNT; i++) 906 ld->sf_tx_dlist[i].sf_id = SF_TX_BUFDESC_ID; 907 for (i = 0; i < SF_TX_CLIST_CNT; i++) 908 ld->sf_tx_clist[i].sf_type = SF_TXCMPTYPE_TX; 909 910 ld->sf_tx_dlist[SF_TX_DLIST_CNT - 1].sf_end = 1; 911 sc->sf_tx_cnt = 0; 912 913 return; 914} 915 916static int sf_newbuf(sc, c, m) 917 struct sf_softc *sc; 918 struct sf_rx_bufdesc_type0 *c; 919 struct mbuf *m; 920{ 921 struct mbuf *m_new = NULL; 922 923 if (m == NULL) { 924 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 925 if (m_new == NULL) { 926 printf("sf%d: no memory for rx list -- " 927 "packet dropped!\n", sc->sf_unit); 928 return(ENOBUFS); 929 } 930 931 MCLGET(m_new, M_DONTWAIT); 932 if (!(m_new->m_flags & M_EXT)) { 933 printf("sf%d: no memory for rx list -- " 934 "packet dropped!\n", sc->sf_unit); 935 m_freem(m_new); 936 return(ENOBUFS); 937 } 938 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 939 } else { 940 m_new = m; 941 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 942 m_new->m_data = m_new->m_ext.ext_buf; 943 } 944 945 m_adj(m_new, sizeof(u_int64_t)); 946 947 c->sf_mbuf = m_new; 948 c->sf_addrlo = SF_RX_HOSTADDR(vtophys(mtod(m_new, caddr_t))); 949 c->sf_valid = 1; 950 951 return(0); 952} 953 954/* 955 * The starfire is programmed to use 'normal' mode for packet reception, 956 * which means we use the consumer/producer model for both the buffer 957 * descriptor queue and the completion descriptor queue. The only problem 958 * with this is that it involves a lot of register accesses: we have to 959 * read the RX completion consumer and producer indexes and the RX buffer 960 * producer index, plus the RX completion consumer and RX buffer producer 961 * indexes have to be updated. It would have been easier if Adaptec had 962 * put each index in a separate register, especially given that the damn 963 * NIC has a 512K register space. 964 * 965 * In spite of all the lovely features that Adaptec crammed into the 6915, 966 * it is marred by one truly stupid design flaw, which is that receive 967 * buffer addresses must be aligned on a longword boundary. This forces 968 * the packet payload to be unaligned, which is suboptimal on the x86 and 969 * completely unuseable on the Alpha. Our only recourse is to copy received 970 * packets into properly aligned buffers before handing them off. 971 */ 972 973static void sf_rxeof(sc) 974 struct sf_softc *sc; 975{ 976 struct ether_header *eh; 977 struct mbuf *m; 978 struct ifnet *ifp; 979 struct sf_rx_bufdesc_type0 *desc; 980 struct sf_rx_cmpdesc_type3 *cur_rx; 981 u_int32_t rxcons, rxprod; 982 int cmpprodidx, cmpconsidx, bufprodidx; 983 984 ifp = &sc->arpcom.ac_if; 985 986 rxcons = csr_read_4(sc, SF_CQ_CONSIDX); 987 rxprod = csr_read_4(sc, SF_RXDQ_PTR_Q1); 988 cmpprodidx = SF_IDX_LO(csr_read_4(sc, SF_CQ_PRODIDX)); 989 cmpconsidx = SF_IDX_LO(rxcons); 990 bufprodidx = SF_IDX_LO(rxprod); 991 992 while (cmpconsidx != cmpprodidx) { 993 struct mbuf *m0; 994 995 cur_rx = &sc->sf_ldata->sf_rx_clist[cmpconsidx]; 996 desc = &sc->sf_ldata->sf_rx_dlist_big[cur_rx->sf_endidx]; 997 m = desc->sf_mbuf; 998 SF_INC(cmpconsidx, SF_RX_CLIST_CNT); 999 SF_INC(bufprodidx, SF_RX_DLIST_CNT); 1000 1001 if (!(cur_rx->sf_status1 & SF_RXSTAT1_OK)) { 1002 ifp->if_ierrors++; 1003 sf_newbuf(sc, desc, m); 1004 continue; 1005 } 1006 1007 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1008 cur_rx->sf_len + ETHER_ALIGN, 0, ifp, NULL); 1009 sf_newbuf(sc, desc, m); 1010 if (m0 == NULL) { 1011 ifp->if_ierrors++; 1012 continue; 1013 } 1014 m_adj(m0, ETHER_ALIGN); 1015 m = m0; 1016 1017 eh = mtod(m, struct ether_header *); 1018 ifp->if_ipackets++; 1019 1020 if (ifp->if_bpf) { 1021 bpf_mtap(ifp, m); 1022 if (ifp->if_flags & IFF_PROMISC && 1023 (bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr, 1024 ETHER_ADDR_LEN) && !(eh->ether_dhost[0] & 1))) { 1025 m_freem(m); 1026 continue; 1027 } 1028 } 1029 1030 /* Remove header from mbuf and pass it on. */ 1031 m_adj(m, sizeof(struct ether_header)); 1032 ether_input(ifp, eh, m); 1033 1034 } 1035 1036 csr_write_4(sc, SF_CQ_CONSIDX, 1037 (rxcons & ~SF_CQ_CONSIDX_RXQ1) | cmpconsidx); 1038 csr_write_4(sc, SF_RXDQ_PTR_Q1, 1039 (rxprod & ~SF_RXDQ_PRODIDX) | bufprodidx); 1040 1041 return; 1042} 1043 1044/* 1045 * Read the transmit status from the completion queue and release 1046 * mbufs. Note that the buffer descriptor index in the completion 1047 * descriptor is an offset from the start of the transmit buffer 1048 * descriptor list in bytes. This is important because the manual 1049 * gives the impression that it should match the producer/consumer 1050 * index, which is the offset in 8 byte blocks. 1051 */ 1052static void sf_txeof(sc) 1053 struct sf_softc *sc; 1054{ 1055 int txcons, cmpprodidx, cmpconsidx; 1056 struct sf_tx_cmpdesc_type1 *cur_cmp; 1057 struct sf_tx_bufdesc_type0 *cur_tx; 1058 struct ifnet *ifp; 1059 1060 ifp = &sc->arpcom.ac_if; 1061 1062 txcons = csr_read_4(sc, SF_CQ_CONSIDX); 1063 cmpprodidx = SF_IDX_HI(csr_read_4(sc, SF_CQ_PRODIDX)); 1064 cmpconsidx = SF_IDX_HI(txcons); 1065 1066 while (cmpconsidx != cmpprodidx) { 1067 cur_cmp = &sc->sf_ldata->sf_tx_clist[cmpconsidx]; 1068 cur_tx = &sc->sf_ldata->sf_tx_dlist[cur_cmp->sf_index >> 7]; 1069 SF_INC(cmpconsidx, SF_TX_CLIST_CNT); 1070 1071 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_OK) 1072 ifp->if_opackets++; 1073 else 1074 ifp->if_oerrors++; 1075 1076 sc->sf_tx_cnt--; 1077 if (cur_tx->sf_mbuf != NULL) { 1078 m_freem(cur_tx->sf_mbuf); 1079 cur_tx->sf_mbuf = NULL; 1080 } 1081 } 1082 1083 ifp->if_timer = 0; 1084 ifp->if_flags &= ~IFF_OACTIVE; 1085 1086 csr_write_4(sc, SF_CQ_CONSIDX, 1087 (txcons & ~SF_CQ_CONSIDX_TXQ) | 1088 ((cmpconsidx << 16) & 0xFFFF0000)); 1089 1090 return; 1091} 1092 1093static void sf_intr(arg) 1094 void *arg; 1095{ 1096 struct sf_softc *sc; 1097 struct ifnet *ifp; 1098 u_int32_t status; 1099 1100 sc = arg; 1101 ifp = &sc->arpcom.ac_if; 1102 1103 if (!(csr_read_4(sc, SF_ISR_SHADOW) & SF_ISR_PCIINT_ASSERTED)) 1104 return; 1105 1106 /* Disable interrupts. */ 1107 csr_write_4(sc, SF_IMR, 0x00000000); 1108 1109 for (;;) { 1110 status = csr_read_4(sc, SF_ISR); 1111 if (status) 1112 csr_write_4(sc, SF_ISR, status); 1113 1114 if (!(status & SF_INTRS)) 1115 break; 1116 1117 if (status & SF_ISR_RXDQ1_DMADONE) 1118 sf_rxeof(sc); 1119 1120 if (status & SF_ISR_TX_TXDONE) 1121 sf_txeof(sc); 1122 1123 if (status & SF_ISR_ABNORMALINTR) { 1124 if (status & SF_ISR_STATSOFLOW) { 1125 untimeout(sf_stats_update, sc, 1126 sc->sf_stat_ch); 1127 sf_stats_update(sc); 1128 } else 1129 sf_init(sc); 1130 } 1131 } 1132 1133 /* Re-enable interrupts. */ 1134 csr_write_4(sc, SF_IMR, SF_INTRS); 1135 1136 if (ifp->if_snd.ifq_head != NULL) 1137 sf_start(ifp); 1138 1139 return; 1140} 1141 1142static void sf_init(xsc) 1143 void *xsc; 1144{ 1145 struct sf_softc *sc; 1146 struct ifnet *ifp; 1147 struct mii_data *mii; 1148 int i, s; 1149 1150 s = splimp(); 1151 1152 sc = xsc; 1153 ifp = &sc->arpcom.ac_if; 1154 mii = device_get_softc(sc->sf_miibus); 1155 1156 sf_stop(sc); 1157 sf_reset(sc); 1158 1159 /* Init all the receive filter registers */ 1160 for (i = SF_RXFILT_PERFECT_BASE; 1161 i < (SF_RXFILT_HASH_MAX + 1); i += 4) 1162 csr_write_4(sc, i, 0); 1163 1164 /* Empty stats counter registers. */ 1165 for (i = 0; i < sizeof(struct sf_stats)/sizeof(u_int32_t); i++) 1166 csr_write_4(sc, SF_STATS_BASE + 1167 (i + sizeof(u_int32_t)), 0); 1168 1169 /* Init our MAC address */ 1170 csr_write_4(sc, SF_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1171 csr_write_4(sc, SF_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1172 sf_setperf(sc, 0, (caddr_t)&sc->arpcom.ac_enaddr); 1173 1174 if (sf_init_rx_ring(sc) == ENOBUFS) { 1175 printf("sf%d: initialization failed: no " 1176 "memory for rx buffers\n", sc->sf_unit); 1177 (void)splx(s); 1178 return; 1179 } 1180 1181 sf_init_tx_ring(sc); 1182 1183 csr_write_4(sc, SF_RXFILT, SF_PERFMODE_NORMAL|SF_HASHMODE_WITHVLAN); 1184 1185 /* If we want promiscuous mode, set the allframes bit. */ 1186 if (ifp->if_flags & IFF_PROMISC) { 1187 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 1188 } else { 1189 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 1190 } 1191 1192 if (ifp->if_flags & IFF_BROADCAST) { 1193 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_BROAD); 1194 } else { 1195 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_BROAD); 1196 } 1197 1198 /* Init the completion queue indexes */ 1199 csr_write_4(sc, SF_CQ_CONSIDX, 0); 1200 csr_write_4(sc, SF_CQ_PRODIDX, 0); 1201 1202 /* Init the RX completion queue */ 1203 csr_write_4(sc, SF_RXCQ_CTL_1, 1204 vtophys(sc->sf_ldata->sf_rx_clist) & SF_RXCQ_ADDR); 1205 SF_SETBIT(sc, SF_RXCQ_CTL_1, SF_RXCQTYPE_3); 1206 1207 /* Init RX DMA control. */ 1208 SF_SETBIT(sc, SF_RXDMA_CTL, SF_RXDMA_REPORTBADPKTS); 1209 1210 /* Init the RX buffer descriptor queue. */ 1211 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 1212 vtophys(sc->sf_ldata->sf_rx_dlist_big)); 1213 csr_write_4(sc, SF_RXDQ_CTL_1, (MCLBYTES << 16) | SF_DESCSPACE_16BYTES); 1214 csr_write_4(sc, SF_RXDQ_PTR_Q1, SF_RX_DLIST_CNT - 1); 1215 1216 /* Init the TX completion queue */ 1217 csr_write_4(sc, SF_TXCQ_CTL, 1218 vtophys(sc->sf_ldata->sf_tx_clist) & SF_RXCQ_ADDR); 1219 1220 /* Init the TX buffer descriptor queue. */ 1221 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 1222 vtophys(sc->sf_ldata->sf_tx_dlist)); 1223 SF_SETBIT(sc, SF_TX_FRAMCTL, SF_TXFRMCTL_CPLAFTERTX); 1224 csr_write_4(sc, SF_TXDQ_CTL, 1225 SF_TXBUFDESC_TYPE0|SF_TXMINSPACE_128BYTES|SF_TXSKIPLEN_8BYTES); 1226 SF_SETBIT(sc, SF_TXDQ_CTL, SF_TXDQCTL_NODMACMP); 1227 1228 /* Enable autopadding of short TX frames. */ 1229 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_AUTOPAD); 1230 1231 /* Enable interrupts. */ 1232 csr_write_4(sc, SF_IMR, SF_INTRS); 1233 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_INTR_ENB); 1234 1235 /* Enable the RX and TX engines. */ 1236 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_RX_ENB|SF_ETHCTL_RXDMA_ENB); 1237 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_TX_ENB|SF_ETHCTL_TXDMA_ENB); 1238 1239 /*mii_mediachg(mii);*/ 1240 sf_ifmedia_upd(ifp); 1241 1242 ifp->if_flags |= IFF_RUNNING; 1243 ifp->if_flags &= ~IFF_OACTIVE; 1244 1245 sc->sf_stat_ch = timeout(sf_stats_update, sc, hz); 1246 1247 splx(s); 1248 1249 return; 1250} 1251 1252static int sf_encap(sc, c, m_head) 1253 struct sf_softc *sc; 1254 struct sf_tx_bufdesc_type0 *c; 1255 struct mbuf *m_head; 1256{ 1257 int frag = 0; 1258 struct sf_frag *f = NULL; 1259 struct mbuf *m; 1260 1261 m = m_head; 1262 1263 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1264 if (m->m_len != 0) { 1265 if (frag == SF_MAXFRAGS) 1266 break; 1267 f = &c->sf_frags[frag]; 1268 if (frag == 0) 1269 f->sf_pktlen = m_head->m_pkthdr.len; 1270 f->sf_fraglen = m->m_len; 1271 f->sf_addr = vtophys(mtod(m, vm_offset_t)); 1272 frag++; 1273 } 1274 } 1275 1276 if (m != NULL) { 1277 struct mbuf *m_new = NULL; 1278 1279 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1280 if (m_new == NULL) { 1281 printf("sf%d: no memory for tx list", sc->sf_unit); 1282 return(1); 1283 } 1284 1285 if (m_head->m_pkthdr.len > MHLEN) { 1286 MCLGET(m_new, M_DONTWAIT); 1287 if (!(m_new->m_flags & M_EXT)) { 1288 m_freem(m_new); 1289 printf("sf%d: no memory for tx list", 1290 sc->sf_unit); 1291 return(1); 1292 } 1293 } 1294 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1295 mtod(m_new, caddr_t)); 1296 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1297 m_freem(m_head); 1298 m_head = m_new; 1299 f = &c->sf_frags[0]; 1300 f->sf_fraglen = f->sf_pktlen = m_head->m_pkthdr.len; 1301 f->sf_addr = vtophys(mtod(m_head, caddr_t)); 1302 frag = 1; 1303 } 1304 1305 c->sf_mbuf = m_head; 1306 c->sf_id = SF_TX_BUFDESC_ID; 1307 c->sf_fragcnt = frag; 1308 c->sf_intr = 1; 1309 c->sf_caltcp = 0; 1310 c->sf_crcen = 1; 1311 1312 return(0); 1313} 1314 1315static void sf_start(ifp) 1316 struct ifnet *ifp; 1317{ 1318 struct sf_softc *sc; 1319 struct sf_tx_bufdesc_type0 *cur_tx = NULL; 1320 struct mbuf *m_head = NULL; 1321 int i, txprod; 1322 1323 sc = ifp->if_softc; 1324 1325 if (!sc->sf_link) 1326 return; 1327 1328 if (ifp->if_flags & IFF_OACTIVE) 1329 return; 1330 1331 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX); 1332 i = SF_IDX_HI(txprod) >> 4; 1333 1334 while(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf == NULL) { 1335 IF_DEQUEUE(&ifp->if_snd, m_head); 1336 if (m_head == NULL) 1337 break; 1338 1339 cur_tx = &sc->sf_ldata->sf_tx_dlist[i]; 1340 sf_encap(sc, cur_tx, m_head); 1341 1342 /* 1343 * If there's a BPF listener, bounce a copy of this frame 1344 * to him. 1345 */ 1346 if (ifp->if_bpf) 1347 bpf_mtap(ifp, m_head); 1348 1349 SF_INC(i, SF_TX_DLIST_CNT); 1350 sc->sf_tx_cnt++; 1351 if (sc->sf_tx_cnt == (SF_TX_DLIST_CNT - 2)) 1352 break; 1353 } 1354 1355 if (cur_tx == NULL) 1356 return; 1357 1358 /* Transmit */ 1359 csr_write_4(sc, SF_TXDQ_PRODIDX, 1360 (txprod & ~SF_TXDQ_PRODIDX_HIPRIO) | 1361 ((i << 20) & 0xFFFF0000)); 1362 1363 ifp->if_timer = 5; 1364 1365 return; 1366} 1367 1368static void sf_stop(sc) 1369 struct sf_softc *sc; 1370{ 1371 int i; 1372 struct ifnet *ifp; 1373 1374 ifp = &sc->arpcom.ac_if; 1375 1376 untimeout(sf_stats_update, sc, sc->sf_stat_ch); 1377 1378 csr_write_4(sc, SF_GEN_ETH_CTL, 0); 1379 csr_write_4(sc, SF_CQ_CONSIDX, 0); 1380 csr_write_4(sc, SF_CQ_PRODIDX, 0); 1381 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 0); 1382 csr_write_4(sc, SF_RXDQ_CTL_1, 0); 1383 csr_write_4(sc, SF_RXDQ_PTR_Q1, 0); 1384 csr_write_4(sc, SF_TXCQ_CTL, 0); 1385 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 0); 1386 csr_write_4(sc, SF_TXDQ_CTL, 0); 1387 sf_reset(sc); 1388 1389 sc->sf_link = 0; 1390 1391 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 1392 if (sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf != NULL) { 1393 m_freem(sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf); 1394 sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf = NULL; 1395 } 1396 } 1397 1398 for (i = 0; i < SF_TX_DLIST_CNT; i++) { 1399 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) { 1400 m_freem(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf); 1401 sc->sf_ldata->sf_tx_dlist[i].sf_mbuf = NULL; 1402 } 1403 } 1404 1405 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 1406 1407 return; 1408} 1409 1410/* 1411 * Note: it is important that this function not be interrupted. We 1412 * use a two-stage register access scheme: if we are interrupted in 1413 * between setting the indirect address register and reading from the 1414 * indirect data register, the contents of the address register could 1415 * be changed out from under us. 1416 */ 1417static void sf_stats_update(xsc) 1418 void *xsc; 1419{ 1420 struct sf_softc *sc; 1421 struct ifnet *ifp; 1422 struct mii_data *mii; 1423 struct sf_stats stats; 1424 u_int32_t *ptr; 1425 int i, s; 1426 1427 s = splimp(); 1428 1429 sc = xsc; 1430 ifp = &sc->arpcom.ac_if; 1431 mii = device_get_softc(sc->sf_miibus); 1432 1433 ptr = (u_int32_t *)&stats; 1434 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++) 1435 ptr[i] = csr_read_4(sc, SF_STATS_BASE + 1436 (i + sizeof(u_int32_t))); 1437 1438 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++) 1439 csr_write_4(sc, SF_STATS_BASE + 1440 (i + sizeof(u_int32_t)), 0); 1441 1442 ifp->if_collisions += stats.sf_tx_single_colls + 1443 stats.sf_tx_multi_colls + stats.sf_tx_excess_colls; 1444 1445 mii_tick(mii); 1446 if (!sc->sf_link) { 1447 mii_pollstat(mii); 1448 if (mii->mii_media_status & IFM_ACTIVE && 1449 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1450 sc->sf_link++; 1451 if (ifp->if_snd.ifq_head != NULL) 1452 sf_start(ifp); 1453 } 1454 1455 sc->sf_stat_ch = timeout(sf_stats_update, sc, hz); 1456 1457 splx(s); 1458 1459 return; 1460} 1461 1462static void sf_watchdog(ifp) 1463 struct ifnet *ifp; 1464{ 1465 struct sf_softc *sc; 1466 1467 sc = ifp->if_softc; 1468 1469 ifp->if_oerrors++; 1470 printf("sf%d: watchdog timeout\n", sc->sf_unit); 1471 1472 sf_stop(sc); 1473 sf_reset(sc); 1474 sf_init(sc); 1475 1476 if (ifp->if_snd.ifq_head != NULL) 1477 sf_start(ifp); 1478 1479 return; 1480} 1481 1482static void sf_shutdown(dev) 1483 device_t dev; 1484{ 1485 struct sf_softc *sc; 1486 1487 sc = device_get_softc(dev); 1488 1489 sf_stop(sc); 1490 1491 return; 1492} 1493