if_sf.c revision 53468
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/dev/sf/if_sf.c 53468 1999-11-20 18:29:44Z wpaul $ 33 */ 34 35/* 36 * Adaptec AIC-6915 "Starfire" PCI fast ethernet driver for FreeBSD. 37 * Programming manual is available from: 38 * ftp.adaptec.com:/pub/BBS/userguides/aic6915_pg.pdf. 39 * 40 * Written by Bill Paul <wpaul@ctr.columbia.edu> 41 * Department of Electical Engineering 42 * Columbia University, New York City 43 */ 44 45/* 46 * The Adaptec AIC-6915 "Starfire" is a 64-bit 10/100 PCI ethernet 47 * controller designed with flexibility and reducing CPU load in mind. 48 * The Starfire offers high and low priority buffer queues, a 49 * producer/consumer index mechanism and several different buffer 50 * queue and completion queue descriptor types. Any one of a number 51 * of different driver designs can be used, depending on system and 52 * OS requirements. This driver makes use of type0 transmit frame 53 * descriptors (since BSD fragments packets across an mbuf chain) 54 * and two RX buffer queues prioritized on size (one queue for small 55 * frames that will fit into a single mbuf, another with full size 56 * mbuf clusters for everything else). The producer/consumer indexes 57 * and completion queues are also used. 58 * 59 * One downside to the Starfire has to do with alignment: buffer 60 * queues must be aligned on 256-byte boundaries, and receive buffers 61 * must be aligned on longword boundaries. The receive buffer alignment 62 * causes problems on the Alpha platform, where the packet payload 63 * should be longword aligned. There is no simple way around this. 64 * 65 * For receive filtering, the Starfire offers 16 perfect filter slots 66 * and a 512-bit hash table. 67 * 68 * The Starfire has no internal transceiver, relying instead on an 69 * external MII-based transceiver. Accessing registers on external 70 * PHYs is done through a special register map rather than with the 71 * usual bitbang MDIO method. 72 * 73 * Acesssing the registers on the Starfire is a little tricky. The 74 * Starfire has a 512K internal register space. When programmed for 75 * PCI memory mapped mode, the entire register space can be accessed 76 * directly. However in I/O space mode, only 256 bytes are directly 77 * mapped into PCI I/O space. The other registers can be accessed 78 * indirectly using the SF_INDIRECTIO_ADDR and SF_INDIRECTIO_DATA 79 * registers inside the 256-byte I/O window. 80 */ 81 82#include <sys/param.h> 83#include <sys/systm.h> 84#include <sys/sockio.h> 85#include <sys/mbuf.h> 86#include <sys/malloc.h> 87#include <sys/kernel.h> 88#include <sys/socket.h> 89 90#include <net/if.h> 91#include <net/if_arp.h> 92#include <net/ethernet.h> 93#include <net/if_dl.h> 94#include <net/if_media.h> 95 96#include <net/bpf.h> 97 98#include <vm/vm.h> /* for vtophys */ 99#include <vm/pmap.h> /* for vtophys */ 100#include <machine/clock.h> /* for DELAY */ 101#include <machine/bus_pio.h> 102#include <machine/bus_memio.h> 103#include <machine/bus.h> 104#include <machine/resource.h> 105#include <sys/bus.h> 106#include <sys/rman.h> 107 108#include <dev/mii/mii.h> 109#include <dev/mii/miivar.h> 110 111/* "controller miibus0" required. See GENERIC if you get errors here. */ 112#include "miibus_if.h" 113 114#include <pci/pcireg.h> 115#include <pci/pcivar.h> 116 117#define SF_USEIOSPACE 118 119#include <pci/if_sfreg.h> 120 121#ifndef lint 122static const char rcsid[] = 123 "$FreeBSD: head/sys/dev/sf/if_sf.c 53468 1999-11-20 18:29:44Z wpaul $"; 124#endif 125 126static struct sf_type sf_devs[] = { 127 { AD_VENDORID, AD_DEVICEID_STARFIRE, 128 "Adaptec AIC-6915 10/100BaseTX" }, 129 { 0, 0, NULL } 130}; 131 132static int sf_probe __P((device_t)); 133static int sf_attach __P((device_t)); 134static int sf_detach __P((device_t)); 135static void sf_intr __P((void *)); 136static void sf_stats_update __P((void *)); 137static void sf_rxeof __P((struct sf_softc *)); 138static void sf_txeof __P((struct sf_softc *)); 139static int sf_encap __P((struct sf_softc *, 140 struct sf_tx_bufdesc_type0 *, 141 struct mbuf *)); 142static void sf_start __P((struct ifnet *)); 143static int sf_ioctl __P((struct ifnet *, u_long, caddr_t)); 144static void sf_init __P((void *)); 145static void sf_stop __P((struct sf_softc *)); 146static void sf_watchdog __P((struct ifnet *)); 147static void sf_shutdown __P((device_t)); 148static int sf_ifmedia_upd __P((struct ifnet *)); 149static void sf_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 150static void sf_reset __P((struct sf_softc *)); 151static int sf_init_rx_ring __P((struct sf_softc *)); 152static void sf_init_tx_ring __P((struct sf_softc *)); 153static int sf_newbuf __P((struct sf_softc *, 154 struct sf_rx_bufdesc_type0 *, 155 struct mbuf *)); 156static void sf_setmulti __P((struct sf_softc *)); 157static int sf_setperf __P((struct sf_softc *, int, caddr_t)); 158static int sf_sethash __P((struct sf_softc *, caddr_t, int)); 159#ifdef notdef 160static int sf_setvlan __P((struct sf_softc *, int, u_int32_t)); 161#endif 162 163static u_int8_t sf_read_eeprom __P((struct sf_softc *, int)); 164static u_int32_t sf_calchash __P((caddr_t)); 165 166static int sf_miibus_readreg __P((device_t, int, int)); 167static int sf_miibus_writereg __P((device_t, int, int, int)); 168static void sf_miibus_statchg __P((device_t)); 169 170static u_int32_t csr_read_4 __P((struct sf_softc *, int)); 171static void csr_write_4 __P((struct sf_softc *, int, u_int32_t)); 172 173#ifdef SF_USEIOSPACE 174#define SF_RES SYS_RES_IOPORT 175#define SF_RID SF_PCI_LOIO 176#else 177#define SF_RES SYS_RES_MEMORY 178#define SF_RID SF_PCI_LOMEM 179#endif 180 181static device_method_t sf_methods[] = { 182 /* Device interface */ 183 DEVMETHOD(device_probe, sf_probe), 184 DEVMETHOD(device_attach, sf_attach), 185 DEVMETHOD(device_detach, sf_detach), 186 DEVMETHOD(device_shutdown, sf_shutdown), 187 188 /* bus interface */ 189 DEVMETHOD(bus_print_child, bus_generic_print_child), 190 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 191 192 /* MII interface */ 193 DEVMETHOD(miibus_readreg, sf_miibus_readreg), 194 DEVMETHOD(miibus_writereg, sf_miibus_writereg), 195 DEVMETHOD(miibus_statchg, sf_miibus_statchg), 196 197 { 0, 0 } 198}; 199 200static driver_t sf_driver = { 201 "sf", 202 sf_methods, 203 sizeof(struct sf_softc), 204}; 205 206static devclass_t sf_devclass; 207 208DRIVER_MODULE(if_sf, pci, sf_driver, sf_devclass, 0, 0); 209DRIVER_MODULE(miibus, sf, miibus_driver, miibus_devclass, 0, 0); 210 211#define SF_SETBIT(sc, reg, x) \ 212 csr_write_4(sc, reg, csr_read_4(sc, reg) | x) 213 214#define SF_CLRBIT(sc, reg, x) \ 215 csr_write_4(sc, reg, csr_read_4(sc, reg) & ~x) 216 217static u_int32_t csr_read_4(sc, reg) 218 struct sf_softc *sc; 219 int reg; 220{ 221 u_int32_t val; 222 223#ifdef SF_USEIOSPACE 224 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); 225 val = CSR_READ_4(sc, SF_INDIRECTIO_DATA); 226#else 227 val = CSR_READ_4(sc, (reg + SF_RMAP_INTREG_BASE)); 228#endif 229 230 return(val); 231} 232 233static u_int8_t sf_read_eeprom(sc, reg) 234 struct sf_softc *sc; 235 int reg; 236{ 237 u_int8_t val; 238 239 val = (csr_read_4(sc, SF_EEADDR_BASE + 240 (reg & 0xFFFFFFFC)) >> (8 * (reg & 3))) & 0xFF; 241 242 return(val); 243} 244 245static void csr_write_4(sc, reg, val) 246 struct sf_softc *sc; 247 int reg; 248 u_int32_t val; 249{ 250#ifdef SF_USEIOSPACE 251 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); 252 CSR_WRITE_4(sc, SF_INDIRECTIO_DATA, val); 253#else 254 CSR_WRITE_4(sc, (reg + SF_RMAP_INTREG_BASE), val); 255#endif 256 return; 257} 258 259static u_int32_t sf_calchash(addr) 260 caddr_t addr; 261{ 262 u_int32_t crc, carry; 263 int i, j; 264 u_int8_t c; 265 266 /* Compute CRC for the address value. */ 267 crc = 0xFFFFFFFF; /* initial value */ 268 269 for (i = 0; i < 6; i++) { 270 c = *(addr + i); 271 for (j = 0; j < 8; j++) { 272 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 273 crc <<= 1; 274 c >>= 1; 275 if (carry) 276 crc = (crc ^ 0x04c11db6) | carry; 277 } 278 } 279 280 /* return the filter bit position */ 281 return(crc >> 23 & 0x1FF); 282} 283 284/* 285 * Copy the address 'mac' into the perfect RX filter entry at 286 * offset 'idx.' The perfect filter only has 16 entries so do 287 * some sanity tests. 288 */ 289static int sf_setperf(sc, idx, mac) 290 struct sf_softc *sc; 291 int idx; 292 caddr_t mac; 293{ 294 u_int16_t *p; 295 296 if (idx < 0 || idx > SF_RXFILT_PERFECT_CNT) 297 return(EINVAL); 298 299 if (mac == NULL) 300 return(EINVAL); 301 302 p = (u_int16_t *)mac; 303 304 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 305 (idx * SF_RXFILT_PERFECT_SKIP), htons(p[2])); 306 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 307 (idx * SF_RXFILT_PERFECT_SKIP) + 4, htons(p[1])); 308 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 309 (idx * SF_RXFILT_PERFECT_SKIP) + 8, htons(p[0])); 310 311 return(0); 312} 313 314/* 315 * Set the bit in the 512-bit hash table that corresponds to the 316 * specified mac address 'mac.' If 'prio' is nonzero, update the 317 * priority hash table instead of the filter hash table. 318 */ 319static int sf_sethash(sc, mac, prio) 320 struct sf_softc *sc; 321 caddr_t mac; 322 int prio; 323{ 324 u_int32_t h = 0; 325 326 if (mac == NULL) 327 return(EINVAL); 328 329 h = sf_calchash(mac); 330 331 if (prio) { 332 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_PRIOOFF + 333 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); 334 } else { 335 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_ADDROFF + 336 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); 337 } 338 339 return(0); 340} 341 342#ifdef notdef 343/* 344 * Set a VLAN tag in the receive filter. 345 */ 346static int sf_setvlan(sc, idx, vlan) 347 struct sf_softc *sc; 348 int idx; 349 u_int32_t vlan; 350{ 351 if (idx < 0 || idx >> SF_RXFILT_HASH_CNT) 352 return(EINVAL); 353 354 csr_write_4(sc, SF_RXFILT_HASH_BASE + 355 (idx * SF_RXFILT_HASH_SKIP) + SF_RXFILT_HASH_VLANOFF, vlan); 356 357 return(0); 358} 359#endif 360 361static int sf_miibus_readreg(dev, phy, reg) 362 device_t dev; 363 int phy, reg; 364{ 365 struct sf_softc *sc; 366 int i; 367 u_int32_t val = 0; 368 369 sc = device_get_softc(dev); 370 371 for (i = 0; i < SF_TIMEOUT; i++) { 372 val = csr_read_4(sc, SF_PHY_REG(phy, reg)); 373 if (val & SF_MII_DATAVALID) 374 break; 375 } 376 377 if (i == SF_TIMEOUT) 378 return(0); 379 380 if ((val & 0x0000FFFF) == 0xFFFF) 381 return(0); 382 383 return(val & 0x0000FFFF); 384} 385 386static int sf_miibus_writereg(dev, phy, reg, val) 387 device_t dev; 388 int phy, reg, val; 389{ 390 struct sf_softc *sc; 391 int i; 392 int busy; 393 394 sc = device_get_softc(dev); 395 396 csr_write_4(sc, SF_PHY_REG(phy, reg), val); 397 398 for (i = 0; i < SF_TIMEOUT; i++) { 399 busy = csr_read_4(sc, SF_PHY_REG(phy, reg)); 400 if (!(busy & SF_MII_BUSY)) 401 break; 402 } 403 404 return(0); 405} 406 407static void sf_miibus_statchg(dev) 408 device_t dev; 409{ 410 struct sf_softc *sc; 411 struct mii_data *mii; 412 413 sc = device_get_softc(dev); 414 mii = device_get_softc(sc->sf_miibus); 415 416 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 417 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 418 } else { 419 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 420 } 421 422 return; 423} 424 425static void sf_setmulti(sc) 426 struct sf_softc *sc; 427{ 428 struct ifnet *ifp; 429 int i; 430 struct ifmultiaddr *ifma; 431 u_int8_t dummy[] = { 0, 0, 0, 0, 0, 0 }; 432 433 ifp = &sc->arpcom.ac_if; 434 435 /* First zot all the existing filters. */ 436 for (i = 1; i < SF_RXFILT_PERFECT_CNT; i++) 437 sf_setperf(sc, i, (char *)&dummy); 438 for (i = SF_RXFILT_HASH_BASE; 439 i < (SF_RXFILT_HASH_MAX + 1); i += 4) 440 csr_write_4(sc, i, 0); 441 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI); 442 443 /* Now program new ones. */ 444 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 445 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI); 446 } else { 447 i = 1; 448 /* First find the tail of the list. */ 449 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 450 ifma = ifma->ifma_link.le_next) { 451 if (ifma->ifma_link.le_next == NULL) 452 break; 453 } 454 /* Now traverse the list backwards. */ 455 for (; ifma != NULL && ifma != (void *)&ifp->if_multiaddrs; 456 ifma = (struct ifmultiaddr *)ifma->ifma_link.le_prev) { 457 if (ifma->ifma_addr->sa_family != AF_LINK) 458 continue; 459 /* 460 * Program the first 15 multicast groups 461 * into the perfect filter. For all others, 462 * use the hash table. 463 */ 464 if (i < SF_RXFILT_PERFECT_CNT) { 465 sf_setperf(sc, i, 466 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 467 i++; 468 continue; 469 } 470 471 sf_sethash(sc, 472 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 0); 473 } 474 } 475 476 return; 477} 478 479/* 480 * Set media options. 481 */ 482static int sf_ifmedia_upd(ifp) 483 struct ifnet *ifp; 484{ 485 struct sf_softc *sc; 486 struct mii_data *mii; 487 488 sc = ifp->if_softc; 489 mii = device_get_softc(sc->sf_miibus); 490 mii_mediachg(mii); 491 492 return(0); 493} 494 495/* 496 * Report current media status. 497 */ 498static void sf_ifmedia_sts(ifp, ifmr) 499 struct ifnet *ifp; 500 struct ifmediareq *ifmr; 501{ 502 struct sf_softc *sc; 503 struct mii_data *mii; 504 505 sc = ifp->if_softc; 506 mii = device_get_softc(sc->sf_miibus); 507 508 mii_pollstat(mii); 509 ifmr->ifm_active = mii->mii_media_active; 510 ifmr->ifm_status = mii->mii_media_status; 511 512 return; 513} 514 515static int sf_ioctl(ifp, command, data) 516 struct ifnet *ifp; 517 u_long command; 518 caddr_t data; 519{ 520 struct sf_softc *sc = ifp->if_softc; 521 struct ifreq *ifr = (struct ifreq *) data; 522 struct mii_data *mii; 523 int s, error = 0; 524 525 s = splimp(); 526 527 switch(command) { 528 case SIOCSIFADDR: 529 case SIOCGIFADDR: 530 case SIOCSIFMTU: 531 error = ether_ioctl(ifp, command, data); 532 break; 533 case SIOCSIFFLAGS: 534 if (ifp->if_flags & IFF_UP) { 535 sf_init(sc); 536 } else { 537 if (ifp->if_flags & IFF_RUNNING) 538 sf_stop(sc); 539 } 540 error = 0; 541 break; 542 case SIOCADDMULTI: 543 case SIOCDELMULTI: 544 sf_setmulti(sc); 545 error = 0; 546 break; 547 case SIOCGIFMEDIA: 548 case SIOCSIFMEDIA: 549 mii = device_get_softc(sc->sf_miibus); 550 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 551 break; 552 default: 553 error = EINVAL; 554 break; 555 } 556 557 (void)splx(s); 558 559 return(error); 560} 561 562static void sf_reset(sc) 563 struct sf_softc *sc; 564{ 565 register int i; 566 567 csr_write_4(sc, SF_GEN_ETH_CTL, 0); 568 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 569 DELAY(1000); 570 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 571 572 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_RESET); 573 574 for (i = 0; i < SF_TIMEOUT; i++) { 575 DELAY(10); 576 if (!(csr_read_4(sc, SF_PCI_DEVCFG) & SF_PCIDEVCFG_RESET)) 577 break; 578 } 579 580 if (i == SF_TIMEOUT) 581 printf("sf%d: reset never completed!\n", sc->sf_unit); 582 583 /* Wait a little while for the chip to get its brains in order. */ 584 DELAY(1000); 585 return; 586} 587 588/* 589 * Probe for an Adaptec AIC-6915 chip. Check the PCI vendor and device 590 * IDs against our list and return a device name if we find a match. 591 * We also check the subsystem ID so that we can identify exactly which 592 * NIC has been found, if possible. 593 */ 594static int sf_probe(dev) 595 device_t dev; 596{ 597 struct sf_type *t; 598 599 t = sf_devs; 600 601 while(t->sf_name != NULL) { 602 if ((pci_get_vendor(dev) == t->sf_vid) && 603 (pci_get_device(dev) == t->sf_did)) { 604 switch((pci_read_config(dev, 605 SF_PCI_SUBVEN_ID, 4) >> 16) & 0xFFFF) { 606 case AD_SUBSYSID_62011_REV0: 607 case AD_SUBSYSID_62011_REV1: 608 device_set_desc(dev, 609 "Adaptec ANA-62011 10/100BaseTX"); 610 return(0); 611 break; 612 case AD_SUBSYSID_62022: 613 device_set_desc(dev, 614 "Adaptec ANA-62022 10/100BaseTX"); 615 return(0); 616 break; 617 case AD_SUBSYSID_62044_REV0: 618 case AD_SUBSYSID_62044_REV1: 619 device_set_desc(dev, 620 "Adaptec ANA-62044 10/100BaseTX"); 621 return(0); 622 break; 623 case AD_SUBSYSID_62020: 624 device_set_desc(dev, 625 "Adaptec ANA-62020 10/100BaseFX"); 626 return(0); 627 break; 628 case AD_SUBSYSID_69011: 629 device_set_desc(dev, 630 "Adaptec ANA-69011 10/100BaseTX"); 631 return(0); 632 break; 633 default: 634 device_set_desc(dev, t->sf_name); 635 return(0); 636 break; 637 } 638 } 639 t++; 640 } 641 642 return(ENXIO); 643} 644 645/* 646 * Attach the interface. Allocate softc structures, do ifmedia 647 * setup and ethernet/BPF attach. 648 */ 649static int sf_attach(dev) 650 device_t dev; 651{ 652 int s, i; 653 u_int32_t command; 654 struct sf_softc *sc; 655 struct ifnet *ifp; 656 int unit, rid, error = 0; 657 658 s = splimp(); 659 660 sc = device_get_softc(dev); 661 unit = device_get_unit(dev); 662 bzero(sc, sizeof(struct sf_softc)); 663 664 /* 665 * Handle power management nonsense. 666 */ 667 command = pci_read_config(dev, SF_PCI_CAPID, 4) & 0x000000FF; 668 if (command == 0x01) { 669 670 command = pci_read_config(dev, SF_PCI_PWRMGMTCTRL, 4); 671 if (command & SF_PSTATE_MASK) { 672 u_int32_t iobase, membase, irq; 673 674 /* Save important PCI config data. */ 675 iobase = pci_read_config(dev, SF_PCI_LOIO, 4); 676 membase = pci_read_config(dev, SF_PCI_LOMEM, 4); 677 irq = pci_read_config(dev, SF_PCI_INTLINE, 4); 678 679 /* Reset the power state. */ 680 printf("sf%d: chip is in D%d power mode " 681 "-- setting to D0\n", unit, command & SF_PSTATE_MASK); 682 command &= 0xFFFFFFFC; 683 pci_write_config(dev, SF_PCI_PWRMGMTCTRL, command, 4); 684 685 /* Restore PCI config data. */ 686 pci_write_config(dev, SF_PCI_LOIO, iobase, 4); 687 pci_write_config(dev, SF_PCI_LOMEM, membase, 4); 688 pci_write_config(dev, SF_PCI_INTLINE, irq, 4); 689 } 690 } 691 692 /* 693 * Map control/status registers. 694 */ 695 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 696 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 697 pci_write_config(dev, PCI_COMMAND_STATUS_REG, command, 4); 698 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 699 700#ifdef SF_USEIOSPACE 701 if (!(command & PCIM_CMD_PORTEN)) { 702 printf("sf%d: failed to enable I/O ports!\n", unit); 703 error = ENXIO; 704 goto fail; 705 } 706#else 707 if (!(command & PCIM_CMD_MEMEN)) { 708 printf("sf%d: failed to enable memory mapping!\n", unit); 709 error = ENXIO; 710 goto fail; 711 } 712#endif 713 714 rid = SF_RID; 715 sc->sf_res = bus_alloc_resource(dev, SF_RES, &rid, 716 0, ~0, 1, RF_ACTIVE); 717 718 if (sc->sf_res == NULL) { 719 printf ("sf%d: couldn't map ports\n", unit); 720 error = ENXIO; 721 goto fail; 722 } 723 724 sc->sf_btag = rman_get_bustag(sc->sf_res); 725 sc->sf_bhandle = rman_get_bushandle(sc->sf_res); 726 727 /* Allocate interrupt */ 728 rid = 0; 729 sc->sf_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 730 RF_SHAREABLE | RF_ACTIVE); 731 732 if (sc->sf_irq == NULL) { 733 printf("sf%d: couldn't map interrupt\n", unit); 734 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 735 error = ENXIO; 736 goto fail; 737 } 738 739 error = bus_setup_intr(dev, sc->sf_irq, INTR_TYPE_NET, 740 sf_intr, sc, &sc->sf_intrhand); 741 742 if (error) { 743 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_res); 744 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 745 printf("sf%d: couldn't set up irq\n", unit); 746 goto fail; 747 } 748 749 callout_handle_init(&sc->sf_stat_ch); 750 751 /* Reset the adapter. */ 752 sf_reset(sc); 753 754 /* 755 * Get station address from the EEPROM. 756 */ 757 for (i = 0; i < ETHER_ADDR_LEN; i++) 758 sc->arpcom.ac_enaddr[i] = 759 sf_read_eeprom(sc, SF_EE_NODEADDR + ETHER_ADDR_LEN - i); 760 761 /* 762 * An Adaptec chip was detected. Inform the world. 763 */ 764 printf("sf%d: Ethernet address: %6D\n", unit, 765 sc->arpcom.ac_enaddr, ":"); 766 767 sc->sf_unit = unit; 768 769 /* Allocate the descriptor queues. */ 770 sc->sf_ldata = contigmalloc(sizeof(struct sf_list_data), M_DEVBUF, 771 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 772 773 if (sc->sf_ldata == NULL) { 774 printf("sf%d: no memory for list buffers!\n", unit); 775 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand); 776 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq); 777 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 778 error = ENXIO; 779 goto fail; 780 } 781 782 bzero(sc->sf_ldata, sizeof(struct sf_list_data)); 783 784 /* Do MII setup. */ 785 if (mii_phy_probe(dev, &sc->sf_miibus, 786 sf_ifmedia_upd, sf_ifmedia_sts)) { 787 printf("sf%d: MII without any phy!\n", sc->sf_unit); 788 free(sc->sf_ldata, M_DEVBUF); 789 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand); 790 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq); 791 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 792 error = ENXIO; 793 goto fail; 794 } 795 796 ifp = &sc->arpcom.ac_if; 797 ifp->if_softc = sc; 798 ifp->if_unit = unit; 799 ifp->if_name = "sf"; 800 ifp->if_mtu = ETHERMTU; 801 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 802 ifp->if_ioctl = sf_ioctl; 803 ifp->if_output = ether_output; 804 ifp->if_start = sf_start; 805 ifp->if_watchdog = sf_watchdog; 806 ifp->if_init = sf_init; 807 ifp->if_baudrate = 10000000; 808 ifp->if_snd.ifq_maxlen = SF_TX_DLIST_CNT - 1; 809 810 /* 811 * Call MI attach routines. 812 */ 813 if_attach(ifp); 814 ether_ifattach(ifp); 815 816 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header)); 817 818fail: 819 splx(s); 820 return(error); 821} 822 823static int sf_detach(dev) 824 device_t dev; 825{ 826 struct sf_softc *sc; 827 struct ifnet *ifp; 828 int s; 829 830 s = splimp(); 831 832 sc = device_get_softc(dev); 833 ifp = &sc->arpcom.ac_if; 834 835 if_detach(ifp); 836 sf_stop(sc); 837 838 bus_generic_detach(dev); 839 device_delete_child(dev, sc->sf_miibus); 840 841 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand); 842 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq); 843 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 844 845 free(sc->sf_ldata, M_DEVBUF); 846 847 splx(s); 848 849 return(0); 850} 851 852static int sf_init_rx_ring(sc) 853 struct sf_softc *sc; 854{ 855 struct sf_list_data *ld; 856 int i; 857 858 ld = sc->sf_ldata; 859 860 bzero((char *)ld->sf_rx_dlist_big, 861 sizeof(struct sf_rx_bufdesc_type0) * SF_RX_DLIST_CNT); 862 bzero((char *)ld->sf_rx_clist, 863 sizeof(struct sf_rx_cmpdesc_type3) * SF_RX_CLIST_CNT); 864 865 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 866 if (sf_newbuf(sc, &ld->sf_rx_dlist_big[i], NULL) == ENOBUFS) 867 return(ENOBUFS); 868 } 869 870 return(0); 871} 872 873static void sf_init_tx_ring(sc) 874 struct sf_softc *sc; 875{ 876 struct sf_list_data *ld; 877 int i; 878 879 ld = sc->sf_ldata; 880 881 bzero((char *)ld->sf_tx_dlist, 882 sizeof(struct sf_tx_bufdesc_type0) * SF_TX_DLIST_CNT); 883 bzero((char *)ld->sf_tx_clist, 884 sizeof(struct sf_tx_cmpdesc_type0) * SF_TX_CLIST_CNT); 885 886 for (i = 0; i < SF_TX_DLIST_CNT; i++) 887 ld->sf_tx_dlist[i].sf_id = SF_TX_BUFDESC_ID; 888 for (i = 0; i < SF_TX_CLIST_CNT; i++) 889 ld->sf_tx_clist[i].sf_type = SF_TXCMPTYPE_TX; 890 891 ld->sf_tx_dlist[SF_TX_DLIST_CNT - 1].sf_end = 1; 892 sc->sf_tx_cnt = 0; 893 894 return; 895} 896 897static int sf_newbuf(sc, c, m) 898 struct sf_softc *sc; 899 struct sf_rx_bufdesc_type0 *c; 900 struct mbuf *m; 901{ 902 struct mbuf *m_new = NULL; 903 904 if (m == NULL) { 905 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 906 if (m_new == NULL) { 907 printf("sf%d: no memory for rx list -- " 908 "packet dropped!\n", sc->sf_unit); 909 return(ENOBUFS); 910 } 911 912 MCLGET(m_new, M_DONTWAIT); 913 if (!(m_new->m_flags & M_EXT)) { 914 printf("sf%d: no memory for rx list -- " 915 "packet dropped!\n", sc->sf_unit); 916 m_freem(m_new); 917 return(ENOBUFS); 918 } 919 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 920 } else { 921 m_new = m; 922 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 923 m_new->m_data = m_new->m_ext.ext_buf; 924 } 925 926 m_adj(m_new, sizeof(u_int64_t)); 927 928 c->sf_mbuf = m_new; 929 c->sf_addrlo = SF_RX_HOSTADDR(vtophys(mtod(m_new, caddr_t))); 930 c->sf_valid = 1; 931 932 return(0); 933} 934 935/* 936 * The starfire is programmed to use 'normal' mode for packet reception, 937 * which means we use the consumer/producer model for both the buffer 938 * descriptor queue and the completion descriptor queue. The only problem 939 * with this is that it involves a lot of register accesses: we have to 940 * read the RX completion consumer and producer indexes and the RX buffer 941 * producer index, plus the RX completion consumer and RX buffer producer 942 * indexes have to be updated. It would have been easier if Adaptec had 943 * put each index in a separate register, especially given that the damn 944 * NIC has a 512K register space. 945 * 946 * In spite of all the lovely features that Adaptec crammed into the 6915, 947 * it is marred by one truly stupid design flaw, which is that receive 948 * buffer addresses must be aligned on a longword boundary. This forces 949 * the packet payload to be unaligned, which is suboptimal on the x86 and 950 * completely unuseable on the Alpha. Our only recourse is to copy received 951 * packets into properly aligned buffers before handing them off. 952 */ 953 954static void sf_rxeof(sc) 955 struct sf_softc *sc; 956{ 957 struct ether_header *eh; 958 struct mbuf *m; 959 struct ifnet *ifp; 960 struct sf_rx_bufdesc_type0 *desc; 961 struct sf_rx_cmpdesc_type3 *cur_rx; 962 u_int32_t rxcons, rxprod; 963 int cmpprodidx, cmpconsidx, bufprodidx; 964 965 ifp = &sc->arpcom.ac_if; 966 967 rxcons = csr_read_4(sc, SF_CQ_CONSIDX); 968 rxprod = csr_read_4(sc, SF_RXDQ_PTR_Q1); 969 cmpprodidx = SF_IDX_LO(csr_read_4(sc, SF_CQ_PRODIDX)); 970 cmpconsidx = SF_IDX_LO(rxcons); 971 bufprodidx = SF_IDX_LO(rxprod); 972 973 while (cmpconsidx != cmpprodidx) { 974 struct mbuf *m0; 975 976 cur_rx = &sc->sf_ldata->sf_rx_clist[cmpconsidx]; 977 desc = &sc->sf_ldata->sf_rx_dlist_big[cur_rx->sf_endidx]; 978 m = desc->sf_mbuf; 979 SF_INC(cmpconsidx, SF_RX_CLIST_CNT); 980 SF_INC(bufprodidx, SF_RX_DLIST_CNT); 981 982 if (!(cur_rx->sf_status1 & SF_RXSTAT1_OK)) { 983 ifp->if_ierrors++; 984 sf_newbuf(sc, desc, m); 985 continue; 986 } 987 988 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 989 cur_rx->sf_len + ETHER_ALIGN, 0, ifp, NULL); 990 sf_newbuf(sc, desc, m); 991 if (m0 == NULL) { 992 ifp->if_ierrors++; 993 continue; 994 } 995 m_adj(m0, ETHER_ALIGN); 996 m = m0; 997 998 eh = mtod(m, struct ether_header *); 999 ifp->if_ipackets++; 1000 1001 if (ifp->if_bpf) { 1002 bpf_mtap(ifp, m); 1003 if (ifp->if_flags & IFF_PROMISC && 1004 (bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr, 1005 ETHER_ADDR_LEN) && !(eh->ether_dhost[0] & 1))) { 1006 m_freem(m); 1007 continue; 1008 } 1009 } 1010 1011 /* Remove header from mbuf and pass it on. */ 1012 m_adj(m, sizeof(struct ether_header)); 1013 ether_input(ifp, eh, m); 1014 1015 } 1016 1017 csr_write_4(sc, SF_CQ_CONSIDX, 1018 (rxcons & ~SF_CQ_CONSIDX_RXQ1) | cmpconsidx); 1019 csr_write_4(sc, SF_RXDQ_PTR_Q1, 1020 (rxprod & ~SF_RXDQ_PRODIDX) | bufprodidx); 1021 1022 return; 1023} 1024 1025/* 1026 * Read the transmit status from the completion queue and release 1027 * mbufs. Note that the buffer descriptor index in the completion 1028 * descriptor is an offset from the start of the transmit buffer 1029 * descriptor list in bytes. This is important because the manual 1030 * gives the impression that it should match the producer/consumer 1031 * index, which is the offset in 8 byte blocks. 1032 */ 1033static void sf_txeof(sc) 1034 struct sf_softc *sc; 1035{ 1036 int txcons, cmpprodidx, cmpconsidx; 1037 struct sf_tx_cmpdesc_type1 *cur_cmp; 1038 struct sf_tx_bufdesc_type0 *cur_tx; 1039 struct ifnet *ifp; 1040 1041 ifp = &sc->arpcom.ac_if; 1042 1043 txcons = csr_read_4(sc, SF_CQ_CONSIDX); 1044 cmpprodidx = SF_IDX_HI(csr_read_4(sc, SF_CQ_PRODIDX)); 1045 cmpconsidx = SF_IDX_HI(txcons); 1046 1047 while (cmpconsidx != cmpprodidx) { 1048 cur_cmp = &sc->sf_ldata->sf_tx_clist[cmpconsidx]; 1049 cur_tx = &sc->sf_ldata->sf_tx_dlist[cur_cmp->sf_index >> 7]; 1050 SF_INC(cmpconsidx, SF_TX_CLIST_CNT); 1051 1052 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_OK) 1053 ifp->if_opackets++; 1054 else 1055 ifp->if_oerrors++; 1056 1057 sc->sf_tx_cnt--; 1058 if (cur_tx->sf_mbuf != NULL) { 1059 m_freem(cur_tx->sf_mbuf); 1060 cur_tx->sf_mbuf = NULL; 1061 } 1062 } 1063 1064 ifp->if_timer = 0; 1065 ifp->if_flags &= ~IFF_OACTIVE; 1066 1067 csr_write_4(sc, SF_CQ_CONSIDX, 1068 (txcons & ~SF_CQ_CONSIDX_TXQ) | 1069 ((cmpconsidx << 16) & 0xFFFF0000)); 1070 1071 return; 1072} 1073 1074static void sf_intr(arg) 1075 void *arg; 1076{ 1077 struct sf_softc *sc; 1078 struct ifnet *ifp; 1079 u_int32_t status; 1080 1081 sc = arg; 1082 ifp = &sc->arpcom.ac_if; 1083 1084 if (!(csr_read_4(sc, SF_ISR_SHADOW) & SF_ISR_PCIINT_ASSERTED)) 1085 return; 1086 1087 /* Disable interrupts. */ 1088 csr_write_4(sc, SF_IMR, 0x00000000); 1089 1090 for (;;) { 1091 status = csr_read_4(sc, SF_ISR); 1092 if (status) 1093 csr_write_4(sc, SF_ISR, status); 1094 1095 if (!(status & SF_INTRS)) 1096 break; 1097 1098 if (status & SF_ISR_RXDQ1_DMADONE) 1099 sf_rxeof(sc); 1100 1101 if (status & SF_ISR_TX_TXDONE) 1102 sf_txeof(sc); 1103 1104 if (status & SF_ISR_ABNORMALINTR) { 1105 if (status & SF_ISR_STATSOFLOW) { 1106 untimeout(sf_stats_update, sc, 1107 sc->sf_stat_ch); 1108 sf_stats_update(sc); 1109 } else 1110 sf_init(sc); 1111 } 1112 } 1113 1114 /* Re-enable interrupts. */ 1115 csr_write_4(sc, SF_IMR, SF_INTRS); 1116 1117 if (ifp->if_snd.ifq_head != NULL) 1118 sf_start(ifp); 1119 1120 return; 1121} 1122 1123static void sf_init(xsc) 1124 void *xsc; 1125{ 1126 struct sf_softc *sc; 1127 struct ifnet *ifp; 1128 struct mii_data *mii; 1129 int i, s; 1130 1131 s = splimp(); 1132 1133 sc = xsc; 1134 ifp = &sc->arpcom.ac_if; 1135 mii = device_get_softc(sc->sf_miibus); 1136 1137 sf_stop(sc); 1138 sf_reset(sc); 1139 1140 /* Init all the receive filter registers */ 1141 for (i = SF_RXFILT_PERFECT_BASE; 1142 i < (SF_RXFILT_HASH_MAX + 1); i += 4) 1143 csr_write_4(sc, i, 0); 1144 1145 /* Empty stats counter registers. */ 1146 for (i = 0; i < sizeof(struct sf_stats)/sizeof(u_int32_t); i++) 1147 csr_write_4(sc, SF_STATS_BASE + 1148 (i + sizeof(u_int32_t)), 0); 1149 1150 /* Init our MAC address */ 1151 csr_write_4(sc, SF_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1152 csr_write_4(sc, SF_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1153 sf_setperf(sc, 0, (caddr_t)&sc->arpcom.ac_enaddr); 1154 1155 if (sf_init_rx_ring(sc) == ENOBUFS) { 1156 printf("sf%d: initialization failed: no " 1157 "memory for rx buffers\n", sc->sf_unit); 1158 (void)splx(s); 1159 return; 1160 } 1161 1162 sf_init_tx_ring(sc); 1163 1164 csr_write_4(sc, SF_RXFILT, SF_PERFMODE_NORMAL|SF_HASHMODE_WITHVLAN); 1165 1166 /* If we want promiscuous mode, set the allframes bit. */ 1167 if (ifp->if_flags & IFF_PROMISC) { 1168 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 1169 } else { 1170 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 1171 } 1172 1173 if (ifp->if_flags & IFF_BROADCAST) { 1174 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_BROAD); 1175 } else { 1176 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_BROAD); 1177 } 1178 1179 /* Init the completion queue indexes */ 1180 csr_write_4(sc, SF_CQ_CONSIDX, 0); 1181 csr_write_4(sc, SF_CQ_PRODIDX, 0); 1182 1183 /* Init the RX completion queue */ 1184 csr_write_4(sc, SF_RXCQ_CTL_1, 1185 vtophys(sc->sf_ldata->sf_rx_clist) & SF_RXCQ_ADDR); 1186 SF_SETBIT(sc, SF_RXCQ_CTL_1, SF_RXCQTYPE_3); 1187 1188 /* Init RX DMA control. */ 1189 SF_SETBIT(sc, SF_RXDMA_CTL, SF_RXDMA_REPORTBADPKTS); 1190 1191 /* Init the RX buffer descriptor queue. */ 1192 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 1193 vtophys(sc->sf_ldata->sf_rx_dlist_big)); 1194 csr_write_4(sc, SF_RXDQ_CTL_1, (MCLBYTES << 16) | SF_DESCSPACE_16BYTES); 1195 csr_write_4(sc, SF_RXDQ_PTR_Q1, SF_RX_DLIST_CNT - 1); 1196 1197 /* Init the TX completion queue */ 1198 csr_write_4(sc, SF_TXCQ_CTL, 1199 vtophys(sc->sf_ldata->sf_tx_clist) & SF_RXCQ_ADDR); 1200 1201 /* Init the TX buffer descriptor queue. */ 1202 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 1203 vtophys(sc->sf_ldata->sf_tx_dlist)); 1204 SF_SETBIT(sc, SF_TX_FRAMCTL, SF_TXFRMCTL_CPLAFTERTX); 1205 csr_write_4(sc, SF_TXDQ_CTL, 1206 SF_TXBUFDESC_TYPE0|SF_TXMINSPACE_128BYTES|SF_TXSKIPLEN_8BYTES); 1207 SF_SETBIT(sc, SF_TXDQ_CTL, SF_TXDQCTL_NODMACMP); 1208 1209 /* Enable autopadding of short TX frames. */ 1210 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_AUTOPAD); 1211 1212 /* Make sure the duplex mode is set correctly. */ 1213 if ((mii->mii_media.ifm_media & IFM_GMASK) == IFM_FDX) { 1214 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 1215 } else { 1216 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 1217 } 1218 1219 /* Enable interrupts. */ 1220 csr_write_4(sc, SF_IMR, SF_INTRS); 1221 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_INTR_ENB); 1222 1223 /* Enable the RX and TX engines. */ 1224 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_RX_ENB|SF_ETHCTL_RXDMA_ENB); 1225 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_TX_ENB|SF_ETHCTL_TXDMA_ENB); 1226 1227 mii_mediachg(mii); 1228 1229 ifp->if_flags |= IFF_RUNNING; 1230 ifp->if_flags &= ~IFF_OACTIVE; 1231 1232 sc->sf_stat_ch = timeout(sf_stats_update, sc, hz); 1233 1234 splx(s); 1235 1236 return; 1237} 1238 1239static int sf_encap(sc, c, m_head) 1240 struct sf_softc *sc; 1241 struct sf_tx_bufdesc_type0 *c; 1242 struct mbuf *m_head; 1243{ 1244 int frag = 0; 1245 struct sf_frag *f = NULL; 1246 struct mbuf *m; 1247 1248 m = m_head; 1249 1250 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1251 if (m->m_len != 0) { 1252 if (frag == SF_MAXFRAGS) 1253 break; 1254 f = &c->sf_frags[frag]; 1255 if (frag == 0) 1256 f->sf_pktlen = m_head->m_pkthdr.len; 1257 f->sf_fraglen = m->m_len; 1258 f->sf_addr = vtophys(mtod(m, vm_offset_t)); 1259 frag++; 1260 } 1261 } 1262 1263 if (m != NULL) { 1264 struct mbuf *m_new = NULL; 1265 1266 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1267 if (m_new == NULL) { 1268 printf("sf%d: no memory for tx list", sc->sf_unit); 1269 return(1); 1270 } 1271 1272 if (m_head->m_pkthdr.len > MHLEN) { 1273 MCLGET(m_new, M_DONTWAIT); 1274 if (!(m_new->m_flags & M_EXT)) { 1275 m_freem(m_new); 1276 printf("sf%d: no memory for tx list", 1277 sc->sf_unit); 1278 return(1); 1279 } 1280 } 1281 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1282 mtod(m_new, caddr_t)); 1283 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1284 m_freem(m_head); 1285 m_head = m_new; 1286 f = &c->sf_frags[0]; 1287 f->sf_fraglen = f->sf_pktlen = m_head->m_pkthdr.len; 1288 f->sf_addr = vtophys(mtod(m_head, caddr_t)); 1289 frag = 1; 1290 } 1291 1292 c->sf_mbuf = m_head; 1293 c->sf_id = SF_TX_BUFDESC_ID; 1294 c->sf_fragcnt = frag; 1295 c->sf_intr = 1; 1296 c->sf_caltcp = 0; 1297 c->sf_crcen = 1; 1298 1299 return(0); 1300} 1301 1302static void sf_start(ifp) 1303 struct ifnet *ifp; 1304{ 1305 struct sf_softc *sc; 1306 struct sf_tx_bufdesc_type0 *cur_tx = NULL; 1307 struct mbuf *m_head = NULL; 1308 int i, txprod; 1309 1310 sc = ifp->if_softc; 1311 1312 if (ifp->if_flags & IFF_OACTIVE) 1313 return; 1314 1315 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX); 1316 i = SF_IDX_HI(txprod) >> 4; 1317 1318 while(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf == NULL) { 1319 IF_DEQUEUE(&ifp->if_snd, m_head); 1320 if (m_head == NULL) 1321 break; 1322 1323 cur_tx = &sc->sf_ldata->sf_tx_dlist[i]; 1324 sf_encap(sc, cur_tx, m_head); 1325 1326 /* 1327 * If there's a BPF listener, bounce a copy of this frame 1328 * to him. 1329 */ 1330 if (ifp->if_bpf) 1331 bpf_mtap(ifp, m_head); 1332 1333 SF_INC(i, SF_TX_DLIST_CNT); 1334 sc->sf_tx_cnt++; 1335 if (sc->sf_tx_cnt == (SF_TX_DLIST_CNT - 2)) 1336 break; 1337 } 1338 1339 if (cur_tx == NULL) 1340 return; 1341 1342 /* Transmit */ 1343 csr_write_4(sc, SF_TXDQ_PRODIDX, 1344 (txprod & ~SF_TXDQ_PRODIDX_HIPRIO) | 1345 ((i << 20) & 0xFFFF0000)); 1346 1347 ifp->if_timer = 5; 1348 1349 return; 1350} 1351 1352static void sf_stop(sc) 1353 struct sf_softc *sc; 1354{ 1355 int i; 1356 struct ifnet *ifp; 1357 1358 ifp = &sc->arpcom.ac_if; 1359 1360 untimeout(sf_stats_update, sc, sc->sf_stat_ch); 1361 1362 csr_write_4(sc, SF_GEN_ETH_CTL, 0); 1363 csr_write_4(sc, SF_CQ_CONSIDX, 0); 1364 csr_write_4(sc, SF_CQ_PRODIDX, 0); 1365 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 0); 1366 csr_write_4(sc, SF_RXDQ_CTL_1, 0); 1367 csr_write_4(sc, SF_RXDQ_PTR_Q1, 0); 1368 csr_write_4(sc, SF_TXCQ_CTL, 0); 1369 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 0); 1370 csr_write_4(sc, SF_TXDQ_CTL, 0); 1371 sf_reset(sc); 1372 1373 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 1374 if (sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf != NULL) { 1375 m_freem(sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf); 1376 sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf = NULL; 1377 } 1378 } 1379 1380 for (i = 0; i < SF_TX_DLIST_CNT; i++) { 1381 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) { 1382 m_freem(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf); 1383 sc->sf_ldata->sf_tx_dlist[i].sf_mbuf = NULL; 1384 } 1385 } 1386 1387 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 1388 1389 return; 1390} 1391 1392/* 1393 * Note: it is important that this function not be interrupted. We 1394 * use a two-stage register access scheme: if we are interrupted in 1395 * between setting the indirect address register and reading from the 1396 * indirect data register, the contents of the address register could 1397 * be changed out from under us. 1398 */ 1399static void sf_stats_update(xsc) 1400 void *xsc; 1401{ 1402 struct sf_softc *sc; 1403 struct ifnet *ifp; 1404 struct mii_data *mii; 1405 struct sf_stats stats; 1406 u_int32_t *ptr; 1407 int i, s; 1408 1409 s = splimp(); 1410 1411 sc = xsc; 1412 ifp = &sc->arpcom.ac_if; 1413 mii = device_get_softc(sc->sf_miibus); 1414 1415 ptr = (u_int32_t *)&stats; 1416 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++) 1417 ptr[i] = csr_read_4(sc, SF_STATS_BASE + 1418 (i + sizeof(u_int32_t))); 1419 1420 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++) 1421 csr_write_4(sc, SF_STATS_BASE + 1422 (i + sizeof(u_int32_t)), 0); 1423 1424 ifp->if_collisions += stats.sf_tx_single_colls + 1425 stats.sf_tx_multi_colls + stats.sf_tx_excess_colls; 1426 1427 mii_tick(mii); 1428 1429 sc->sf_stat_ch = timeout(sf_stats_update, sc, hz); 1430 1431 splx(s); 1432 1433 return; 1434} 1435 1436static void sf_watchdog(ifp) 1437 struct ifnet *ifp; 1438{ 1439 struct sf_softc *sc; 1440 1441 sc = ifp->if_softc; 1442 1443 ifp->if_oerrors++; 1444 printf("sf%d: watchdog timeout\n", sc->sf_unit); 1445 1446 sf_stop(sc); 1447 sf_reset(sc); 1448 sf_init(sc); 1449 1450 if (ifp->if_snd.ifq_head != NULL) 1451 sf_start(ifp); 1452 1453 return; 1454} 1455 1456static void sf_shutdown(dev) 1457 device_t dev; 1458{ 1459 struct sf_softc *sc; 1460 1461 sc = device_get_softc(dev); 1462 1463 sf_stop(sc); 1464 1465 return; 1466} 1467