if_sf.c revision 51682
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/dev/sf/if_sf.c 51682 1999-09-26 18:35:30Z wpaul $ 33 */ 34 35/* 36 * Adaptec AIC-6915 "Starfire" PCI fast ethernet driver for FreeBSD. 37 * Programming manual is available from: 38 * ftp.adaptec.com:/pub/BBS/userguides/aic6915_pg.pdf. 39 * 40 * Written by Bill Paul <wpaul@ctr.columbia.edu> 41 * Department of Electical Engineering 42 * Columbia University, New York City 43 */ 44 45/* 46 * The Adaptec AIC-6915 "Starfire" is a 64-bit 10/100 PCI ethernet 47 * controller designed with flexibility and reducing CPU load in mind. 48 * The Starfire offers high and low priority buffer queues, a 49 * producer/consumer index mechanism and several different buffer 50 * queue and completion queue descriptor types. Any one of a number 51 * of different driver designs can be used, depending on system and 52 * OS requirements. This driver makes use of type0 transmit frame 53 * descriptors (since BSD fragments packets across an mbuf chain) 54 * and two RX buffer queues prioritized on size (one queue for small 55 * frames that will fit into a single mbuf, another with full size 56 * mbuf clusters for everything else). The producer/consumer indexes 57 * and completion queues are also used. 58 * 59 * One downside to the Starfire has to do with alignment: buffer 60 * queues must be aligned on 256-byte boundaries, and receive buffers 61 * must be aligned on longword boundaries. The receive buffer alignment 62 * causes problems on the Alpha platform, where the packet payload 63 * should be longword aligned. There is no simple way around this. 64 * 65 * For receive filtering, the Starfire offers 16 perfect filter slots 66 * and a 512-bit hash table. 67 * 68 * The Starfire has no internal transceiver, relying instead on an 69 * external MII-based transceiver. Accessing registers on external 70 * PHYs is done through a special register map rather than with the 71 * usual bitbang MDIO method. 72 * 73 * Acesssing the registers on the Starfire is a little tricky. The 74 * Starfire has a 512K internal register space. When programmed for 75 * PCI memory mapped mode, the entire register space can be accessed 76 * directly. However in I/O space mode, only 256 bytes are directly 77 * mapped into PCI I/O space. The other registers can be accessed 78 * indirectly using the SF_INDIRECTIO_ADDR and SF_INDIRECTIO_DATA 79 * registers inside the 256-byte I/O window. 80 */ 81 82#include <sys/param.h> 83#include <sys/systm.h> 84#include <sys/sockio.h> 85#include <sys/mbuf.h> 86#include <sys/malloc.h> 87#include <sys/kernel.h> 88#include <sys/socket.h> 89 90#include <net/if.h> 91#include <net/if_arp.h> 92#include <net/ethernet.h> 93#include <net/if_dl.h> 94#include <net/if_media.h> 95 96#include <net/bpf.h> 97 98#include <vm/vm.h> /* for vtophys */ 99#include <vm/pmap.h> /* for vtophys */ 100#include <machine/clock.h> /* for DELAY */ 101#include <machine/bus_pio.h> 102#include <machine/bus_memio.h> 103#include <machine/bus.h> 104#include <machine/resource.h> 105#include <sys/bus.h> 106#include <sys/rman.h> 107 108#include <dev/mii/mii.h> 109#include <dev/mii/miivar.h> 110 111/* "controller miibus0" required. See GENERIC if you get errors here. */ 112#include "miibus_if.h" 113 114#include <pci/pcireg.h> 115#include <pci/pcivar.h> 116 117#define SF_USEIOSPACE 118 119#include <pci/if_sfreg.h> 120 121#ifndef lint 122static const char rcsid[] = 123 "$FreeBSD: head/sys/dev/sf/if_sf.c 51682 1999-09-26 18:35:30Z wpaul $"; 124#endif 125 126static struct sf_type sf_devs[] = { 127 { AD_VENDORID, AD_DEVICEID_STARFIRE, 128 "Adaptec AIC-6915 10/100BaseTX" }, 129 { 0, 0, NULL } 130}; 131 132static int sf_probe __P((device_t)); 133static int sf_attach __P((device_t)); 134static int sf_detach __P((device_t)); 135static void sf_intr __P((void *)); 136static void sf_stats_update __P((void *)); 137static void sf_rxeof __P((struct sf_softc *)); 138static void sf_txeof __P((struct sf_softc *)); 139static int sf_encap __P((struct sf_softc *, 140 struct sf_tx_bufdesc_type0 *, 141 struct mbuf *)); 142static void sf_start __P((struct ifnet *)); 143static int sf_ioctl __P((struct ifnet *, u_long, caddr_t)); 144static void sf_init __P((void *)); 145static void sf_stop __P((struct sf_softc *)); 146static void sf_watchdog __P((struct ifnet *)); 147static void sf_shutdown __P((device_t)); 148static int sf_ifmedia_upd __P((struct ifnet *)); 149static void sf_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 150static void sf_reset __P((struct sf_softc *)); 151static int sf_init_rx_ring __P((struct sf_softc *)); 152static void sf_init_tx_ring __P((struct sf_softc *)); 153static int sf_newbuf __P((struct sf_softc *, 154 struct sf_rx_bufdesc_type0 *, 155 struct mbuf *)); 156static void sf_setmulti __P((struct sf_softc *)); 157static int sf_setperf __P((struct sf_softc *, int, caddr_t)); 158static int sf_sethash __P((struct sf_softc *, caddr_t, int)); 159#ifdef notdef 160static int sf_setvlan __P((struct sf_softc *, int, u_int32_t)); 161#endif 162 163static u_int8_t sf_read_eeprom __P((struct sf_softc *, int)); 164static u_int32_t sf_calchash __P((caddr_t)); 165 166static int sf_miibus_readreg __P((device_t, int, int)); 167static int sf_miibus_writereg __P((device_t, int, int, int)); 168static void sf_miibus_statchg __P((device_t)); 169 170static u_int32_t csr_read_4 __P((struct sf_softc *, int)); 171static void csr_write_4 __P((struct sf_softc *, int, u_int32_t)); 172 173#ifdef SF_USEIOSPACE 174#define SF_RES SYS_RES_IOPORT 175#define SF_RID SF_PCI_LOIO 176#else 177#define SF_RES SYS_RES_MEMORY 178#define SF_RID SF_PCI_LOMEM 179#endif 180 181static device_method_t sf_methods[] = { 182 /* Device interface */ 183 DEVMETHOD(device_probe, sf_probe), 184 DEVMETHOD(device_attach, sf_attach), 185 DEVMETHOD(device_detach, sf_detach), 186 DEVMETHOD(device_shutdown, sf_shutdown), 187 188 /* bus interface */ 189 DEVMETHOD(bus_print_child, bus_generic_print_child), 190 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 191 192 /* MII interface */ 193 DEVMETHOD(miibus_readreg, sf_miibus_readreg), 194 DEVMETHOD(miibus_writereg, sf_miibus_writereg), 195 DEVMETHOD(miibus_statchg, sf_miibus_statchg), 196 197 { 0, 0 } 198}; 199 200static driver_t sf_driver = { 201 "sf", 202 sf_methods, 203 sizeof(struct sf_softc), 204}; 205 206static devclass_t sf_devclass; 207 208DRIVER_MODULE(if_sf, pci, sf_driver, sf_devclass, 0, 0); 209DRIVER_MODULE(miibus, sf, miibus_driver, miibus_devclass, 0, 0); 210 211#define SF_SETBIT(sc, reg, x) \ 212 csr_write_4(sc, reg, csr_read_4(sc, reg) | x) 213 214#define SF_CLRBIT(sc, reg, x) \ 215 csr_write_4(sc, reg, csr_read_4(sc, reg) & ~x) 216 217static u_int32_t csr_read_4(sc, reg) 218 struct sf_softc *sc; 219 int reg; 220{ 221 u_int32_t val; 222 223#ifdef SF_USEIOSPACE 224 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); 225 val = CSR_READ_4(sc, SF_INDIRECTIO_DATA); 226#else 227 val = CSR_READ_4(sc, (reg + SF_RMAP_INTREG_BASE)); 228#endif 229 230 return(val); 231} 232 233static u_int8_t sf_read_eeprom(sc, reg) 234 struct sf_softc *sc; 235 int reg; 236{ 237 u_int8_t val; 238 239 val = (csr_read_4(sc, SF_EEADDR_BASE + 240 (reg & 0xFFFFFFFC)) >> (8 * (reg & 3))) & 0xFF; 241 242 return(val); 243} 244 245static void csr_write_4(sc, reg, val) 246 struct sf_softc *sc; 247 int reg; 248 u_int32_t val; 249{ 250#ifdef SF_USEIOSPACE 251 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); 252 CSR_WRITE_4(sc, SF_INDIRECTIO_DATA, val); 253#else 254 CSR_WRITE_4(sc, (reg + SF_RMAP_INTREG_BASE), val); 255#endif 256 return; 257} 258 259static u_int32_t sf_calchash(addr) 260 caddr_t addr; 261{ 262 u_int32_t crc, carry; 263 int i, j; 264 u_int8_t c; 265 266 /* Compute CRC for the address value. */ 267 crc = 0xFFFFFFFF; /* initial value */ 268 269 for (i = 0; i < 6; i++) { 270 c = *(addr + i); 271 for (j = 0; j < 8; j++) { 272 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 273 crc <<= 1; 274 c >>= 1; 275 if (carry) 276 crc = (crc ^ 0x04c11db6) | carry; 277 } 278 } 279 280 /* return the filter bit position */ 281 return(crc >> 23 & 0x1FF); 282} 283 284/* 285 * Copy the address 'mac' into the perfect RX filter entry at 286 * offset 'idx.' The perfect filter only has 16 entries so do 287 * some sanity tests. 288 */ 289static int sf_setperf(sc, idx, mac) 290 struct sf_softc *sc; 291 int idx; 292 caddr_t mac; 293{ 294 u_int16_t *p; 295 296 if (idx < 0 || idx > SF_RXFILT_PERFECT_CNT) 297 return(EINVAL); 298 299 if (mac == NULL) 300 return(EINVAL); 301 302 p = (u_int16_t *)mac; 303 304 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 305 (idx * SF_RXFILT_PERFECT_SKIP), htons(p[2])); 306 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 307 (idx * SF_RXFILT_PERFECT_SKIP) + 4, htons(p[1])); 308 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 309 (idx * SF_RXFILT_PERFECT_SKIP) + 8, htons(p[0])); 310 311 return(0); 312} 313 314/* 315 * Set the bit in the 512-bit hash table that corresponds to the 316 * specified mac address 'mac.' If 'prio' is nonzero, update the 317 * priority hash table instead of the filter hash table. 318 */ 319static int sf_sethash(sc, mac, prio) 320 struct sf_softc *sc; 321 caddr_t mac; 322 int prio; 323{ 324 u_int32_t h = 0; 325 326 if (mac == NULL) 327 return(EINVAL); 328 329 h = sf_calchash(mac); 330 331 if (prio) { 332 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_PRIOOFF + 333 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); 334 } else { 335 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_ADDROFF + 336 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); 337 } 338 339 return(0); 340} 341 342#ifdef notdef 343/* 344 * Set a VLAN tag in the receive filter. 345 */ 346static int sf_setvlan(sc, idx, vlan) 347 struct sf_softc *sc; 348 int idx; 349 u_int32_t vlan; 350{ 351 if (idx < 0 || idx >> SF_RXFILT_HASH_CNT) 352 return(EINVAL); 353 354 csr_write_4(sc, SF_RXFILT_HASH_BASE + 355 (idx * SF_RXFILT_HASH_SKIP) + SF_RXFILT_HASH_VLANOFF, vlan); 356 357 return(0); 358} 359#endif 360 361static int sf_miibus_readreg(dev, phy, reg) 362 device_t dev; 363 int phy, reg; 364{ 365 struct sf_softc *sc; 366 int i; 367 u_int32_t val = 0; 368 369 sc = device_get_softc(dev); 370 371 for (i = 0; i < SF_TIMEOUT; i++) { 372 val = csr_read_4(sc, SF_PHY_REG(phy, reg)); 373 if (val & SF_MII_DATAVALID) 374 break; 375 } 376 377 if (i == SF_TIMEOUT) 378 return(0); 379 380 if ((val & 0x0000FFFF) == 0xFFFF) 381 return(0); 382 383 return(val & 0x0000FFFF); 384} 385 386static int sf_miibus_writereg(dev, phy, reg, val) 387 device_t dev; 388 int phy, reg, val; 389{ 390 struct sf_softc *sc; 391 int i; 392 int busy; 393 394 sc = device_get_softc(dev); 395 396 csr_write_4(sc, SF_PHY_REG(phy, reg), val); 397 398 for (i = 0; i < SF_TIMEOUT; i++) { 399 busy = csr_read_4(sc, SF_PHY_REG(phy, reg)); 400 if (!(busy & SF_MII_BUSY)) 401 break; 402 } 403 404 return(0); 405} 406 407static void sf_miibus_statchg(dev) 408 device_t dev; 409{ 410 struct sf_softc *sc; 411 struct mii_data *mii; 412 413 sc = device_get_softc(dev); 414 mii = device_get_softc(sc->sf_miibus); 415 416 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 417 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 418 } else { 419 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 420 } 421 422 return; 423} 424 425static void sf_setmulti(sc) 426 struct sf_softc *sc; 427{ 428 struct ifnet *ifp; 429 int i; 430 struct ifmultiaddr *ifma; 431 u_int8_t dummy[] = { 0, 0, 0, 0, 0, 0 }; 432 433 ifp = &sc->arpcom.ac_if; 434 435 /* First zot all the existing filters. */ 436 for (i = 1; i < SF_RXFILT_PERFECT_CNT; i++) 437 sf_setperf(sc, i, (char *)&dummy); 438 for (i = SF_RXFILT_HASH_BASE; 439 i < (SF_RXFILT_HASH_MAX + 1); i += 4) 440 csr_write_4(sc, i, 0); 441 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI); 442 443 /* Now program new ones. */ 444 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 445 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI); 446 } else { 447 i = 1; 448 /* First find the tail of the list. */ 449 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 450 ifma = ifma->ifma_link.le_next) { 451 if (ifma->ifma_link.le_next == NULL) 452 break; 453 } 454 /* Now traverse the list backwards. */ 455 for (; ifma != NULL && ifma != (void *)&ifp->if_multiaddrs; 456 ifma = (struct ifmultiaddr *)ifma->ifma_link.le_prev) { 457 if (ifma->ifma_addr->sa_family != AF_LINK) 458 continue; 459 /* 460 * Program the first 15 multicast groups 461 * into the perfect filter. For all others, 462 * use the hash table. 463 */ 464 if (i < SF_RXFILT_PERFECT_CNT) { 465 sf_setperf(sc, i, 466 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 467 i++; 468 continue; 469 } 470 471 sf_sethash(sc, 472 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 0); 473 } 474 } 475 476 return; 477} 478 479/* 480 * Set media options. 481 */ 482static int sf_ifmedia_upd(ifp) 483 struct ifnet *ifp; 484{ 485 struct sf_softc *sc; 486 struct mii_data *mii; 487 488 sc = ifp->if_softc; 489 mii = device_get_softc(sc->sf_miibus); 490 mii_mediachg(mii); 491 492 return(0); 493} 494 495/* 496 * Report current media status. 497 */ 498static void sf_ifmedia_sts(ifp, ifmr) 499 struct ifnet *ifp; 500 struct ifmediareq *ifmr; 501{ 502 struct sf_softc *sc; 503 struct mii_data *mii; 504 505 sc = ifp->if_softc; 506 mii = device_get_softc(sc->sf_miibus); 507 508 mii_pollstat(mii); 509 ifmr->ifm_active = mii->mii_media_active; 510 ifmr->ifm_status = mii->mii_media_status; 511 512 return; 513} 514 515static int sf_ioctl(ifp, command, data) 516 struct ifnet *ifp; 517 u_long command; 518 caddr_t data; 519{ 520 struct sf_softc *sc = ifp->if_softc; 521 struct ifreq *ifr = (struct ifreq *) data; 522 struct mii_data *mii; 523 int s, error = 0; 524 525 s = splimp(); 526 527 switch(command) { 528 case SIOCSIFADDR: 529 case SIOCGIFADDR: 530 case SIOCSIFMTU: 531 error = ether_ioctl(ifp, command, data); 532 break; 533 case SIOCSIFFLAGS: 534 if (ifp->if_flags & IFF_UP) { 535 sf_init(sc); 536 } else { 537 if (ifp->if_flags & IFF_RUNNING) 538 sf_stop(sc); 539 } 540 error = 0; 541 break; 542 case SIOCADDMULTI: 543 case SIOCDELMULTI: 544 sf_setmulti(sc); 545 error = 0; 546 break; 547 case SIOCGIFMEDIA: 548 case SIOCSIFMEDIA: 549 mii = device_get_softc(sc->sf_miibus); 550 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 551 break; 552 default: 553 error = EINVAL; 554 break; 555 } 556 557 (void)splx(s); 558 559 return(error); 560} 561 562static void sf_reset(sc) 563 struct sf_softc *sc; 564{ 565 register int i; 566 567 csr_write_4(sc, SF_GEN_ETH_CTL, 0); 568 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 569 DELAY(1000); 570 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 571 572 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_RESET); 573 574 for (i = 0; i < SF_TIMEOUT; i++) { 575 DELAY(10); 576 if (!(csr_read_4(sc, SF_PCI_DEVCFG) & SF_PCIDEVCFG_RESET)) 577 break; 578 } 579 580 if (i == SF_TIMEOUT) 581 printf("sf%d: reset never completed!\n", sc->sf_unit); 582 583 /* Wait a little while for the chip to get its brains in order. */ 584 DELAY(1000); 585 return; 586} 587 588/* 589 * Probe for an Adaptec AIC-6915 chip. Check the PCI vendor and device 590 * IDs against our list and return a device name if we find a match. 591 * We also check the subsystem ID so that we can identify exactly which 592 * NIC has been found, if possible. 593 */ 594static int sf_probe(dev) 595 device_t dev; 596{ 597 struct sf_type *t; 598 599 t = sf_devs; 600 601 while(t->sf_name != NULL) { 602 if ((pci_get_vendor(dev) == t->sf_vid) && 603 (pci_get_device(dev) == t->sf_did)) { 604 switch((pci_read_config(dev, 605 SF_PCI_SUBVEN_ID, 4) >> 16) & 0xFFFF) { 606 case AD_SUBSYSID_62011_REV0: 607 case AD_SUBSYSID_62011_REV1: 608 device_set_desc(dev, 609 "Adaptec ANA-62011 10/100BaseTX"); 610 return(0); 611 break; 612 case AD_SUBSYSID_62022: 613 device_set_desc(dev, 614 "Adaptec ANA-62022 10/100BaseTX"); 615 return(0); 616 break; 617 case AD_SUBSYSID_62044: 618 device_set_desc(dev, 619 "Adaptec ANA-62044 10/100BaseTX"); 620 return(0); 621 break; 622 case AD_SUBSYSID_62020: 623 device_set_desc(dev, 624 "Adaptec ANA-62020 10/100BaseFX"); 625 return(0); 626 break; 627 case AD_SUBSYSID_69011: 628 device_set_desc(dev, 629 "Adaptec ANA-69011 10/100BaseTX"); 630 return(0); 631 break; 632 default: 633 device_set_desc(dev, t->sf_name); 634 return(0); 635 break; 636 } 637 } 638 t++; 639 } 640 641 return(ENXIO); 642} 643 644/* 645 * Attach the interface. Allocate softc structures, do ifmedia 646 * setup and ethernet/BPF attach. 647 */ 648static int sf_attach(dev) 649 device_t dev; 650{ 651 int s, i; 652 u_int32_t command; 653 struct sf_softc *sc; 654 struct ifnet *ifp; 655 int unit, rid, error = 0; 656 657 s = splimp(); 658 659 sc = device_get_softc(dev); 660 unit = device_get_unit(dev); 661 bzero(sc, sizeof(struct sf_softc)); 662 663 /* 664 * Handle power management nonsense. 665 */ 666 command = pci_read_config(dev, SF_PCI_CAPID, 4) & 0x000000FF; 667 if (command == 0x01) { 668 669 command = pci_read_config(dev, SF_PCI_PWRMGMTCTRL, 4); 670 if (command & SF_PSTATE_MASK) { 671 u_int32_t iobase, membase, irq; 672 673 /* Save important PCI config data. */ 674 iobase = pci_read_config(dev, SF_PCI_LOIO, 4); 675 membase = pci_read_config(dev, SF_PCI_LOMEM, 4); 676 irq = pci_read_config(dev, SF_PCI_INTLINE, 4); 677 678 /* Reset the power state. */ 679 printf("sf%d: chip is in D%d power mode " 680 "-- setting to D0\n", unit, command & SF_PSTATE_MASK); 681 command &= 0xFFFFFFFC; 682 pci_write_config(dev, SF_PCI_PWRMGMTCTRL, command, 4); 683 684 /* Restore PCI config data. */ 685 pci_write_config(dev, SF_PCI_LOIO, iobase, 4); 686 pci_write_config(dev, SF_PCI_LOMEM, membase, 4); 687 pci_write_config(dev, SF_PCI_INTLINE, irq, 4); 688 } 689 } 690 691 /* 692 * Map control/status registers. 693 */ 694 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 695 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 696 pci_write_config(dev, PCI_COMMAND_STATUS_REG, command, 4); 697 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 698 699#ifdef SF_USEIOSPACE 700 if (!(command & PCIM_CMD_PORTEN)) { 701 printf("sf%d: failed to enable I/O ports!\n", unit); 702 error = ENXIO; 703 goto fail; 704 } 705#else 706 if (!(command & PCIM_CMD_MEMEN)) { 707 printf("sf%d: failed to enable memory mapping!\n", unit); 708 error = ENXIO; 709 goto fail; 710 } 711#endif 712 713 rid = SF_RID; 714 sc->sf_res = bus_alloc_resource(dev, SF_RES, &rid, 715 0, ~0, 1, RF_ACTIVE); 716 717 if (sc->sf_res == NULL) { 718 printf ("sf%d: couldn't map ports\n", unit); 719 error = ENXIO; 720 goto fail; 721 } 722 723 sc->sf_btag = rman_get_bustag(sc->sf_res); 724 sc->sf_bhandle = rman_get_bushandle(sc->sf_res); 725 726 /* Allocate interrupt */ 727 rid = 0; 728 sc->sf_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 729 RF_SHAREABLE | RF_ACTIVE); 730 731 if (sc->sf_irq == NULL) { 732 printf("sf%d: couldn't map interrupt\n", unit); 733 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 734 error = ENXIO; 735 goto fail; 736 } 737 738 error = bus_setup_intr(dev, sc->sf_irq, INTR_TYPE_NET, 739 sf_intr, sc, &sc->sf_intrhand); 740 741 if (error) { 742 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_res); 743 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 744 printf("sf%d: couldn't set up irq\n", unit); 745 goto fail; 746 } 747 748 callout_handle_init(&sc->sf_stat_ch); 749 750 /* Reset the adapter. */ 751 sf_reset(sc); 752 753 /* 754 * Get station address from the EEPROM. 755 */ 756 for (i = 0; i < ETHER_ADDR_LEN; i++) 757 sc->arpcom.ac_enaddr[i] = 758 sf_read_eeprom(sc, SF_EE_NODEADDR + ETHER_ADDR_LEN - i); 759 760 /* 761 * An Adaptec chip was detected. Inform the world. 762 */ 763 printf("sf%d: Ethernet address: %6D\n", unit, 764 sc->arpcom.ac_enaddr, ":"); 765 766 sc->sf_unit = unit; 767 768 /* Allocate the descriptor queues. */ 769 sc->sf_ldata = contigmalloc(sizeof(struct sf_list_data), M_DEVBUF, 770 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 771 772 if (sc->sf_ldata == NULL) { 773 printf("sf%d: no memory for list buffers!\n", unit); 774 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand); 775 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq); 776 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 777 error = ENXIO; 778 goto fail; 779 } 780 781 bzero(sc->sf_ldata, sizeof(struct sf_list_data)); 782 783 /* Do MII setup. */ 784 if (mii_phy_probe(dev, &sc->sf_miibus, 785 sf_ifmedia_upd, sf_ifmedia_sts)) { 786 printf("sf%d: MII without any phy!\n", sc->sf_unit); 787 free(sc->sf_ldata, M_DEVBUF); 788 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand); 789 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq); 790 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 791 error = ENXIO; 792 goto fail; 793 } 794 795 ifp = &sc->arpcom.ac_if; 796 ifp->if_softc = sc; 797 ifp->if_unit = unit; 798 ifp->if_name = "sf"; 799 ifp->if_mtu = ETHERMTU; 800 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 801 ifp->if_ioctl = sf_ioctl; 802 ifp->if_output = ether_output; 803 ifp->if_start = sf_start; 804 ifp->if_watchdog = sf_watchdog; 805 ifp->if_init = sf_init; 806 ifp->if_baudrate = 10000000; 807 ifp->if_snd.ifq_maxlen = SF_TX_DLIST_CNT - 1; 808 809 /* 810 * Call MI attach routines. 811 */ 812 if_attach(ifp); 813 ether_ifattach(ifp); 814 815 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header)); 816 817fail: 818 splx(s); 819 return(error); 820} 821 822static int sf_detach(dev) 823 device_t dev; 824{ 825 struct sf_softc *sc; 826 struct ifnet *ifp; 827 int s; 828 829 s = splimp(); 830 831 sc = device_get_softc(dev); 832 ifp = &sc->arpcom.ac_if; 833 834 if_detach(ifp); 835 sf_stop(sc); 836 837 bus_generic_detach(dev); 838 device_delete_child(dev, sc->sf_miibus); 839 840 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand); 841 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq); 842 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 843 844 free(sc->sf_ldata, M_DEVBUF); 845 846 splx(s); 847 848 return(0); 849} 850 851static int sf_init_rx_ring(sc) 852 struct sf_softc *sc; 853{ 854 struct sf_list_data *ld; 855 int i; 856 857 ld = sc->sf_ldata; 858 859 bzero((char *)ld->sf_rx_dlist_big, 860 sizeof(struct sf_rx_bufdesc_type0) * SF_RX_DLIST_CNT); 861 bzero((char *)ld->sf_rx_clist, 862 sizeof(struct sf_rx_cmpdesc_type3) * SF_RX_CLIST_CNT); 863 864 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 865 if (sf_newbuf(sc, &ld->sf_rx_dlist_big[i], NULL) == ENOBUFS) 866 return(ENOBUFS); 867 } 868 869 return(0); 870} 871 872static void sf_init_tx_ring(sc) 873 struct sf_softc *sc; 874{ 875 struct sf_list_data *ld; 876 int i; 877 878 ld = sc->sf_ldata; 879 880 bzero((char *)ld->sf_tx_dlist, 881 sizeof(struct sf_tx_bufdesc_type0) * SF_TX_DLIST_CNT); 882 bzero((char *)ld->sf_tx_clist, 883 sizeof(struct sf_tx_cmpdesc_type0) * SF_TX_CLIST_CNT); 884 885 for (i = 0; i < SF_TX_DLIST_CNT; i++) 886 ld->sf_tx_dlist[i].sf_id = SF_TX_BUFDESC_ID; 887 for (i = 0; i < SF_TX_CLIST_CNT; i++) 888 ld->sf_tx_clist[i].sf_type = SF_TXCMPTYPE_TX; 889 890 ld->sf_tx_dlist[SF_TX_DLIST_CNT - 1].sf_end = 1; 891 sc->sf_tx_cnt = 0; 892 893 return; 894} 895 896static int sf_newbuf(sc, c, m) 897 struct sf_softc *sc; 898 struct sf_rx_bufdesc_type0 *c; 899 struct mbuf *m; 900{ 901 struct mbuf *m_new = NULL; 902 903 if (m == NULL) { 904 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 905 if (m_new == NULL) { 906 printf("sf%d: no memory for rx list -- " 907 "packet dropped!\n", sc->sf_unit); 908 return(ENOBUFS); 909 } 910 911 MCLGET(m_new, M_DONTWAIT); 912 if (!(m_new->m_flags & M_EXT)) { 913 printf("sf%d: no memory for rx list -- " 914 "packet dropped!\n", sc->sf_unit); 915 m_freem(m_new); 916 return(ENOBUFS); 917 } 918 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 919 } else { 920 m_new = m; 921 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 922 m_new->m_data = m_new->m_ext.ext_buf; 923 } 924 925 m_adj(m_new, sizeof(u_int64_t)); 926 927 c->sf_mbuf = m_new; 928 c->sf_addrlo = SF_RX_HOSTADDR(vtophys(mtod(m_new, caddr_t))); 929 c->sf_valid = 1; 930 931 return(0); 932} 933 934/* 935 * The starfire is programmed to use 'normal' mode for packet reception, 936 * which means we use the consumer/producer model for both the buffer 937 * descriptor queue and the completion descriptor queue. The only problem 938 * with this is that it involves a lot of register accesses: we have to 939 * read the RX completion consumer and producer indexes and the RX buffer 940 * producer index, plus the RX completion consumer and RX buffer producer 941 * indexes have to be updated. It would have been easier if Adaptec had 942 * put each index in a separate register, especially given that the damn 943 * NIC has a 512K register space. 944 * 945 * In spite of all the lovely features that Adaptec crammed into the 6915, 946 * it is marred by one truly stupid design flaw, which is that receive 947 * buffer addresses must be aligned on a longword boundary. This forces 948 * the packet payload to be unaligned, which is suboptimal on the x86 and 949 * completely unuseable on the Alpha. Our only recourse is to copy received 950 * packets into properly aligned buffers before handing them off. 951 */ 952 953static void sf_rxeof(sc) 954 struct sf_softc *sc; 955{ 956 struct ether_header *eh; 957 struct mbuf *m; 958 struct ifnet *ifp; 959 struct sf_rx_bufdesc_type0 *desc; 960 struct sf_rx_cmpdesc_type3 *cur_rx; 961 u_int32_t rxcons, rxprod; 962 int cmpprodidx, cmpconsidx, bufprodidx; 963 964 ifp = &sc->arpcom.ac_if; 965 966 rxcons = csr_read_4(sc, SF_CQ_CONSIDX); 967 rxprod = csr_read_4(sc, SF_RXDQ_PTR_Q1); 968 cmpprodidx = SF_IDX_LO(csr_read_4(sc, SF_CQ_PRODIDX)); 969 cmpconsidx = SF_IDX_LO(rxcons); 970 bufprodidx = SF_IDX_LO(rxprod); 971 972 while (cmpconsidx != cmpprodidx) { 973 struct mbuf *m0; 974 975 cur_rx = &sc->sf_ldata->sf_rx_clist[cmpconsidx]; 976 desc = &sc->sf_ldata->sf_rx_dlist_big[cur_rx->sf_endidx]; 977 m = desc->sf_mbuf; 978 SF_INC(cmpconsidx, SF_RX_CLIST_CNT); 979 SF_INC(bufprodidx, SF_RX_DLIST_CNT); 980 981 if (!(cur_rx->sf_status1 & SF_RXSTAT1_OK)) { 982 ifp->if_ierrors++; 983 sf_newbuf(sc, desc, m); 984 continue; 985 } 986 987 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 988 cur_rx->sf_len + ETHER_ALIGN, 0, ifp, NULL); 989 sf_newbuf(sc, desc, m); 990 if (m0 == NULL) { 991 ifp->if_ierrors++; 992 continue; 993 } 994 m_adj(m0, ETHER_ALIGN); 995 m = m0; 996 997 eh = mtod(m, struct ether_header *); 998 ifp->if_ipackets++; 999 1000 if (ifp->if_bpf) { 1001 bpf_mtap(ifp, m); 1002 if (ifp->if_flags & IFF_PROMISC && 1003 (bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr, 1004 ETHER_ADDR_LEN) && !(eh->ether_dhost[0] & 1))) { 1005 m_freem(m); 1006 continue; 1007 } 1008 } 1009 1010 /* Remove header from mbuf and pass it on. */ 1011 m_adj(m, sizeof(struct ether_header)); 1012 ether_input(ifp, eh, m); 1013 1014 } 1015 1016 csr_write_4(sc, SF_CQ_CONSIDX, 1017 (rxcons & ~SF_CQ_CONSIDX_RXQ1) | cmpconsidx); 1018 csr_write_4(sc, SF_RXDQ_PTR_Q1, 1019 (rxprod & ~SF_RXDQ_PRODIDX) | bufprodidx); 1020 1021 return; 1022} 1023 1024/* 1025 * Read the transmit status from the completion queue and release 1026 * mbufs. Note that the buffer descriptor index in the completion 1027 * descriptor is an offset from the start of the transmit buffer 1028 * descriptor list in bytes. This is important because the manual 1029 * gives the impression that it should match the producer/consumer 1030 * index, which is the offset in 8 byte blocks. 1031 */ 1032static void sf_txeof(sc) 1033 struct sf_softc *sc; 1034{ 1035 int txcons, cmpprodidx, cmpconsidx; 1036 struct sf_tx_cmpdesc_type1 *cur_cmp; 1037 struct sf_tx_bufdesc_type0 *cur_tx; 1038 struct ifnet *ifp; 1039 1040 ifp = &sc->arpcom.ac_if; 1041 1042 txcons = csr_read_4(sc, SF_CQ_CONSIDX); 1043 cmpprodidx = SF_IDX_HI(csr_read_4(sc, SF_CQ_PRODIDX)); 1044 cmpconsidx = SF_IDX_HI(txcons); 1045 1046 while (cmpconsidx != cmpprodidx) { 1047 cur_cmp = &sc->sf_ldata->sf_tx_clist[cmpconsidx]; 1048 cur_tx = &sc->sf_ldata->sf_tx_dlist[cur_cmp->sf_index >> 7]; 1049 SF_INC(cmpconsidx, SF_TX_CLIST_CNT); 1050 1051 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_OK) 1052 ifp->if_opackets++; 1053 else 1054 ifp->if_oerrors++; 1055 1056 sc->sf_tx_cnt--; 1057 if (cur_tx->sf_mbuf != NULL) { 1058 m_freem(cur_tx->sf_mbuf); 1059 cur_tx->sf_mbuf = NULL; 1060 } 1061 } 1062 1063 ifp->if_timer = 0; 1064 ifp->if_flags &= ~IFF_OACTIVE; 1065 1066 csr_write_4(sc, SF_CQ_CONSIDX, 1067 (txcons & ~SF_CQ_CONSIDX_TXQ) | 1068 ((cmpconsidx << 16) & 0xFFFF0000)); 1069 1070 return; 1071} 1072 1073static void sf_intr(arg) 1074 void *arg; 1075{ 1076 struct sf_softc *sc; 1077 struct ifnet *ifp; 1078 u_int32_t status; 1079 1080 sc = arg; 1081 ifp = &sc->arpcom.ac_if; 1082 1083 if (!(csr_read_4(sc, SF_ISR_SHADOW) & SF_ISR_PCIINT_ASSERTED)) 1084 return; 1085 1086 /* Disable interrupts. */ 1087 csr_write_4(sc, SF_IMR, 0x00000000); 1088 1089 for (;;) { 1090 status = csr_read_4(sc, SF_ISR); 1091 if (status) 1092 csr_write_4(sc, SF_ISR, status); 1093 1094 if (!(status & SF_INTRS)) 1095 break; 1096 1097 if (status & SF_ISR_RXDQ1_DMADONE) 1098 sf_rxeof(sc); 1099 1100 if (status & SF_ISR_TX_TXDONE) 1101 sf_txeof(sc); 1102 1103 if (status & SF_ISR_ABNORMALINTR) { 1104 if (status & SF_ISR_STATSOFLOW) { 1105 untimeout(sf_stats_update, sc, 1106 sc->sf_stat_ch); 1107 sf_stats_update(sc); 1108 } else 1109 sf_init(sc); 1110 } 1111 } 1112 1113 /* Re-enable interrupts. */ 1114 csr_write_4(sc, SF_IMR, SF_INTRS); 1115 1116 if (ifp->if_snd.ifq_head != NULL) 1117 sf_start(ifp); 1118 1119 return; 1120} 1121 1122static void sf_init(xsc) 1123 void *xsc; 1124{ 1125 struct sf_softc *sc; 1126 struct ifnet *ifp; 1127 struct mii_data *mii; 1128 int i, s; 1129 1130 s = splimp(); 1131 1132 sc = xsc; 1133 ifp = &sc->arpcom.ac_if; 1134 mii = device_get_softc(sc->sf_miibus); 1135 1136 sf_stop(sc); 1137 sf_reset(sc); 1138 1139 /* Init all the receive filter registers */ 1140 for (i = SF_RXFILT_PERFECT_BASE; 1141 i < (SF_RXFILT_HASH_MAX + 1); i += 4) 1142 csr_write_4(sc, i, 0); 1143 1144 /* Empty stats counter registers. */ 1145 for (i = 0; i < sizeof(struct sf_stats)/sizeof(u_int32_t); i++) 1146 csr_write_4(sc, SF_STATS_BASE + 1147 (i + sizeof(u_int32_t)), 0); 1148 1149 /* Init our MAC address */ 1150 csr_write_4(sc, SF_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1151 csr_write_4(sc, SF_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1152 sf_setperf(sc, 0, (caddr_t)&sc->arpcom.ac_enaddr); 1153 1154 if (sf_init_rx_ring(sc) == ENOBUFS) { 1155 printf("sf%d: initialization failed: no " 1156 "memory for rx buffers\n", sc->sf_unit); 1157 (void)splx(s); 1158 return; 1159 } 1160 1161 sf_init_tx_ring(sc); 1162 1163 csr_write_4(sc, SF_RXFILT, SF_PERFMODE_NORMAL|SF_HASHMODE_WITHVLAN); 1164 1165 /* If we want promiscuous mode, set the allframes bit. */ 1166 if (ifp->if_flags & IFF_PROMISC) { 1167 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 1168 } else { 1169 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 1170 } 1171 1172 if (ifp->if_flags & IFF_BROADCAST) { 1173 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_BROAD); 1174 } else { 1175 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_BROAD); 1176 } 1177 1178 /* Init the completion queue indexes */ 1179 csr_write_4(sc, SF_CQ_CONSIDX, 0); 1180 csr_write_4(sc, SF_CQ_PRODIDX, 0); 1181 1182 /* Init the RX completion queue */ 1183 csr_write_4(sc, SF_RXCQ_CTL_1, 1184 vtophys(sc->sf_ldata->sf_rx_clist) & SF_RXCQ_ADDR); 1185 SF_SETBIT(sc, SF_RXCQ_CTL_1, SF_RXCQTYPE_3); 1186 1187 /* Init RX DMA control. */ 1188 SF_SETBIT(sc, SF_RXDMA_CTL, SF_RXDMA_REPORTBADPKTS); 1189 1190 /* Init the RX buffer descriptor queue. */ 1191 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 1192 vtophys(sc->sf_ldata->sf_rx_dlist_big)); 1193 csr_write_4(sc, SF_RXDQ_CTL_1, (MCLBYTES << 16) | SF_DESCSPACE_16BYTES); 1194 csr_write_4(sc, SF_RXDQ_PTR_Q1, SF_RX_DLIST_CNT - 1); 1195 1196 /* Init the TX completion queue */ 1197 csr_write_4(sc, SF_TXCQ_CTL, 1198 vtophys(sc->sf_ldata->sf_tx_clist) & SF_RXCQ_ADDR); 1199 1200 /* Init the TX buffer descriptor queue. */ 1201 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 1202 vtophys(sc->sf_ldata->sf_tx_dlist)); 1203 SF_SETBIT(sc, SF_TX_FRAMCTL, SF_TXFRMCTL_CPLAFTERTX); 1204 csr_write_4(sc, SF_TXDQ_CTL, 1205 SF_TXBUFDESC_TYPE0|SF_TXMINSPACE_128BYTES|SF_TXSKIPLEN_8BYTES); 1206 SF_SETBIT(sc, SF_TXDQ_CTL, SF_TXDQCTL_NODMACMP); 1207 1208 /* Enable autopadding of short TX frames. */ 1209 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_AUTOPAD); 1210 1211 /* Make sure the duplex mode is set correctly. */ 1212 if ((mii->mii_media.ifm_media & IFM_GMASK) == IFM_FDX) { 1213 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 1214 } else { 1215 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 1216 } 1217 1218 /* Enable interrupts. */ 1219 csr_write_4(sc, SF_IMR, SF_INTRS); 1220 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_INTR_ENB); 1221 1222 /* Enable the RX and TX engines. */ 1223 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_RX_ENB|SF_ETHCTL_RXDMA_ENB); 1224 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_TX_ENB|SF_ETHCTL_TXDMA_ENB); 1225 1226 mii_mediachg(mii); 1227 1228 ifp->if_flags |= IFF_RUNNING; 1229 ifp->if_flags &= ~IFF_OACTIVE; 1230 1231 sc->sf_stat_ch = timeout(sf_stats_update, sc, hz); 1232 1233 splx(s); 1234 1235 return; 1236} 1237 1238static int sf_encap(sc, c, m_head) 1239 struct sf_softc *sc; 1240 struct sf_tx_bufdesc_type0 *c; 1241 struct mbuf *m_head; 1242{ 1243 int frag = 0; 1244 struct sf_frag *f = NULL; 1245 struct mbuf *m; 1246 1247 m = m_head; 1248 1249 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1250 if (m->m_len != 0) { 1251 if (frag == SF_MAXFRAGS) 1252 break; 1253 f = &c->sf_frags[frag]; 1254 if (frag == 0) 1255 f->sf_pktlen = m_head->m_pkthdr.len; 1256 f->sf_fraglen = m->m_len; 1257 f->sf_addr = vtophys(mtod(m, vm_offset_t)); 1258 frag++; 1259 } 1260 } 1261 1262 if (m != NULL) { 1263 struct mbuf *m_new = NULL; 1264 1265 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1266 if (m_new == NULL) { 1267 printf("sf%d: no memory for tx list", sc->sf_unit); 1268 return(1); 1269 } 1270 1271 if (m_head->m_pkthdr.len > MHLEN) { 1272 MCLGET(m_new, M_DONTWAIT); 1273 if (!(m_new->m_flags & M_EXT)) { 1274 m_freem(m_new); 1275 printf("sf%d: no memory for tx list", 1276 sc->sf_unit); 1277 return(1); 1278 } 1279 } 1280 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1281 mtod(m_new, caddr_t)); 1282 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1283 m_freem(m_head); 1284 m_head = m_new; 1285 f = &c->sf_frags[0]; 1286 f->sf_fraglen = f->sf_pktlen = m_head->m_pkthdr.len; 1287 f->sf_addr = vtophys(mtod(m_head, caddr_t)); 1288 frag = 1; 1289 } 1290 1291 c->sf_mbuf = m_head; 1292 c->sf_id = SF_TX_BUFDESC_ID; 1293 c->sf_fragcnt = frag; 1294 c->sf_intr = 1; 1295 c->sf_caltcp = 0; 1296 c->sf_crcen = 1; 1297 1298 return(0); 1299} 1300 1301static void sf_start(ifp) 1302 struct ifnet *ifp; 1303{ 1304 struct sf_softc *sc; 1305 struct sf_tx_bufdesc_type0 *cur_tx = NULL; 1306 struct mbuf *m_head = NULL; 1307 int i, txprod; 1308 1309 sc = ifp->if_softc; 1310 1311 if (ifp->if_flags & IFF_OACTIVE) 1312 return; 1313 1314 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX); 1315 i = SF_IDX_HI(txprod) >> 4; 1316 1317 while(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf == NULL) { 1318 IF_DEQUEUE(&ifp->if_snd, m_head); 1319 if (m_head == NULL) 1320 break; 1321 1322 cur_tx = &sc->sf_ldata->sf_tx_dlist[i]; 1323 sf_encap(sc, cur_tx, m_head); 1324 1325 /* 1326 * If there's a BPF listener, bounce a copy of this frame 1327 * to him. 1328 */ 1329 if (ifp->if_bpf) 1330 bpf_mtap(ifp, m_head); 1331 1332 SF_INC(i, SF_TX_DLIST_CNT); 1333 sc->sf_tx_cnt++; 1334 if (sc->sf_tx_cnt == (SF_TX_DLIST_CNT - 2)) 1335 break; 1336 } 1337 1338 if (cur_tx == NULL) 1339 return; 1340 1341 /* Transmit */ 1342 csr_write_4(sc, SF_TXDQ_PRODIDX, 1343 (txprod & ~SF_TXDQ_PRODIDX_HIPRIO) | 1344 ((i << 20) & 0xFFFF0000)); 1345 1346 ifp->if_timer = 5; 1347 1348 return; 1349} 1350 1351static void sf_stop(sc) 1352 struct sf_softc *sc; 1353{ 1354 int i; 1355 struct ifnet *ifp; 1356 1357 ifp = &sc->arpcom.ac_if; 1358 1359 untimeout(sf_stats_update, sc, sc->sf_stat_ch); 1360 1361 csr_write_4(sc, SF_GEN_ETH_CTL, 0); 1362 csr_write_4(sc, SF_CQ_CONSIDX, 0); 1363 csr_write_4(sc, SF_CQ_PRODIDX, 0); 1364 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 0); 1365 csr_write_4(sc, SF_RXDQ_CTL_1, 0); 1366 csr_write_4(sc, SF_RXDQ_PTR_Q1, 0); 1367 csr_write_4(sc, SF_TXCQ_CTL, 0); 1368 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 0); 1369 csr_write_4(sc, SF_TXDQ_CTL, 0); 1370 sf_reset(sc); 1371 1372 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 1373 if (sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf != NULL) { 1374 m_freem(sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf); 1375 sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf = NULL; 1376 } 1377 } 1378 1379 for (i = 0; i < SF_TX_DLIST_CNT; i++) { 1380 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) { 1381 m_freem(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf); 1382 sc->sf_ldata->sf_tx_dlist[i].sf_mbuf = NULL; 1383 } 1384 } 1385 1386 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 1387 1388 return; 1389} 1390 1391/* 1392 * Note: it is important that this function not be interrupted. We 1393 * use a two-stage register access scheme: if we are interrupted in 1394 * between setting the indirect address register and reading from the 1395 * indirect data register, the contents of the address register could 1396 * be changed out from under us. 1397 */ 1398static void sf_stats_update(xsc) 1399 void *xsc; 1400{ 1401 struct sf_softc *sc; 1402 struct ifnet *ifp; 1403 struct mii_data *mii; 1404 struct sf_stats stats; 1405 u_int32_t *ptr; 1406 int i, s; 1407 1408 s = splimp(); 1409 1410 sc = xsc; 1411 ifp = &sc->arpcom.ac_if; 1412 mii = device_get_softc(sc->sf_miibus); 1413 1414 ptr = (u_int32_t *)&stats; 1415 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++) 1416 ptr[i] = csr_read_4(sc, SF_STATS_BASE + 1417 (i + sizeof(u_int32_t))); 1418 1419 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++) 1420 csr_write_4(sc, SF_STATS_BASE + 1421 (i + sizeof(u_int32_t)), 0); 1422 1423 ifp->if_collisions += stats.sf_tx_single_colls + 1424 stats.sf_tx_multi_colls + stats.sf_tx_excess_colls; 1425 1426 mii_tick(mii); 1427 1428 sc->sf_stat_ch = timeout(sf_stats_update, sc, hz); 1429 1430 splx(s); 1431 1432 return; 1433} 1434 1435static void sf_watchdog(ifp) 1436 struct ifnet *ifp; 1437{ 1438 struct sf_softc *sc; 1439 1440 sc = ifp->if_softc; 1441 1442 ifp->if_oerrors++; 1443 printf("sf%d: watchdog timeout\n", sc->sf_unit); 1444 1445 sf_stop(sc); 1446 sf_reset(sc); 1447 sf_init(sc); 1448 1449 if (ifp->if_snd.ifq_head != NULL) 1450 sf_start(ifp); 1451 1452 return; 1453} 1454 1455static void sf_shutdown(dev) 1456 device_t dev; 1457{ 1458 struct sf_softc *sc; 1459 1460 sc = device_get_softc(dev); 1461 1462 sf_stop(sc); 1463 1464 return; 1465} 1466