if_sf.c revision 51583
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/dev/sf/if_sf.c 51583 1999-09-23 03:32:57Z wpaul $ 33 */ 34 35/* 36 * Adaptec AIC-6915 "Starfire" PCI fast ethernet driver for FreeBSD. 37 * Programming manual is available from www.adaptec.com. 38 * 39 * Written by Bill Paul <wpaul@ctr.columbia.edu> 40 * Department of Electical Engineering 41 * Columbia University, New York City 42 */ 43 44/* 45 * The Adaptec AIC-6915 "Starfire" is a 64-bit 10/100 PCI ethernet 46 * controller designed with flexibility and reducing CPU load in mind. 47 * The Starfire offers high and low priority buffer queues, a 48 * producer/consumer index mechanism and several different buffer 49 * queue and completion queue descriptor types. Any one of a number 50 * of different driver designs can be used, depending on system and 51 * OS requirements. This driver makes use of type0 transmit frame 52 * descriptors (since BSD fragments packets across an mbuf chain) 53 * and two RX buffer queues prioritized on size (one queue for small 54 * frames that will fit into a single mbuf, another with full size 55 * mbuf clusters for everything else). The producer/consumer indexes 56 * and completion queues are also used. 57 * 58 * One downside to the Starfire has to do with alignment: buffer 59 * queues must be aligned on 256-byte boundaries, and receive buffers 60 * must be aligned on longword boundaries. The receive buffer alignment 61 * causes problems on the Alpha platform, where the packet payload 62 * should be longword aligned. There is no simple way around this. 63 * 64 * For receive filtering, the Starfire offers 16 perfect filter slots 65 * and a 512-bit hash table. 66 * 67 * The Starfire has no internal transceiver, relying instead on an 68 * external MII-based transceiver. Accessing registers on external 69 * PHYs is done through a special register map rather than with the 70 * usual bitbang MDIO method. 71 * 72 * Acesssing the registers on the Starfire is a little tricky. The 73 * Starfire has a 512K internal register space. When programmed for 74 * PCI memory mapped mode, the entire register space can be accessed 75 * directly. However in I/O space mode, only 256 bytes are directly 76 * mapped into PCI I/O space. The other registers can be accessed 77 * indirectly using the SF_INDIRECTIO_ADDR and SF_INDIRECTIO_DATA 78 * registers inside the 256-byte I/O window. 79 */ 80 81#include <sys/param.h> 82#include <sys/systm.h> 83#include <sys/sockio.h> 84#include <sys/mbuf.h> 85#include <sys/malloc.h> 86#include <sys/kernel.h> 87#include <sys/socket.h> 88 89#include <net/if.h> 90#include <net/if_arp.h> 91#include <net/ethernet.h> 92#include <net/if_dl.h> 93#include <net/if_media.h> 94 95#include <net/bpf.h> 96 97#include <vm/vm.h> /* for vtophys */ 98#include <vm/pmap.h> /* for vtophys */ 99#include <machine/clock.h> /* for DELAY */ 100#include <machine/bus_pio.h> 101#include <machine/bus_memio.h> 102#include <machine/bus.h> 103#include <machine/resource.h> 104#include <sys/bus.h> 105#include <sys/rman.h> 106 107#include <dev/mii/mii.h> 108#include <dev/mii/miivar.h> 109 110/* "controller miibus0" required. See GENERIC if you get errors here. */ 111#include "miibus_if.h" 112 113#include <pci/pcireg.h> 114#include <pci/pcivar.h> 115 116#define SF_USEIOSPACE 117 118#include <pci/if_sfreg.h> 119 120#ifndef lint 121static const char rcsid[] = 122 "$FreeBSD: head/sys/dev/sf/if_sf.c 51583 1999-09-23 03:32:57Z wpaul $"; 123#endif 124 125static struct sf_type sf_devs[] = { 126 { AD_VENDORID, AD_DEVICEID_STARFIRE, 127 "Adaptec AIC-6915 10/100BaseTX" }, 128 { 0, 0, NULL } 129}; 130 131static int sf_probe __P((device_t)); 132static int sf_attach __P((device_t)); 133static int sf_detach __P((device_t)); 134static void sf_intr __P((void *)); 135static void sf_stats_update __P((void *)); 136static void sf_rxeof __P((struct sf_softc *)); 137static void sf_txeof __P((struct sf_softc *)); 138static int sf_encap __P((struct sf_softc *, 139 struct sf_tx_bufdesc_type0 *, 140 struct mbuf *)); 141static void sf_start __P((struct ifnet *)); 142static int sf_ioctl __P((struct ifnet *, u_long, caddr_t)); 143static void sf_init __P((void *)); 144static void sf_stop __P((struct sf_softc *)); 145static void sf_watchdog __P((struct ifnet *)); 146static void sf_shutdown __P((device_t)); 147static int sf_ifmedia_upd __P((struct ifnet *)); 148static void sf_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 149static void sf_reset __P((struct sf_softc *)); 150static int sf_init_rx_ring __P((struct sf_softc *)); 151static void sf_init_tx_ring __P((struct sf_softc *)); 152static int sf_newbuf __P((struct sf_softc *, 153 struct sf_rx_bufdesc_type0 *, 154 struct mbuf *)); 155static void sf_setmulti __P((struct sf_softc *)); 156static int sf_setperf __P((struct sf_softc *, int, caddr_t)); 157static int sf_sethash __P((struct sf_softc *, caddr_t, int)); 158#ifdef notdef 159static int sf_setvlan __P((struct sf_softc *, int, u_int32_t)); 160#endif 161 162static u_int8_t sf_read_eeprom __P((struct sf_softc *, int)); 163static u_int32_t sf_calchash __P((caddr_t)); 164 165static int sf_miibus_readreg __P((device_t, int, int)); 166static int sf_miibus_writereg __P((device_t, int, int, int)); 167static void sf_miibus_statchg __P((device_t)); 168 169static u_int32_t csr_read_4 __P((struct sf_softc *, int)); 170static void csr_write_4 __P((struct sf_softc *, int, u_int32_t)); 171 172#ifdef SF_USEIOSPACE 173#define SF_RES SYS_RES_IOPORT 174#define SF_RID SF_PCI_LOIO 175#else 176#define SF_RES SYS_RES_MEMORY 177#define SF_RID SF_PCI_LOMEM 178#endif 179 180static device_method_t sf_methods[] = { 181 /* Device interface */ 182 DEVMETHOD(device_probe, sf_probe), 183 DEVMETHOD(device_attach, sf_attach), 184 DEVMETHOD(device_detach, sf_detach), 185 DEVMETHOD(device_shutdown, sf_shutdown), 186 187 /* bus interface */ 188 DEVMETHOD(bus_print_child, bus_generic_print_child), 189 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 190 191 /* MII interface */ 192 DEVMETHOD(miibus_readreg, sf_miibus_readreg), 193 DEVMETHOD(miibus_writereg, sf_miibus_writereg), 194 DEVMETHOD(miibus_statchg, sf_miibus_statchg), 195 196 { 0, 0 } 197}; 198 199static driver_t sf_driver = { 200 "sf", 201 sf_methods, 202 sizeof(struct sf_softc), 203}; 204 205static devclass_t sf_devclass; 206 207DRIVER_MODULE(if_sf, pci, sf_driver, sf_devclass, 0, 0); 208DRIVER_MODULE(miibus, sf, miibus_driver, miibus_devclass, 0, 0); 209 210#define SF_SETBIT(sc, reg, x) \ 211 csr_write_4(sc, reg, csr_read_4(sc, reg) | x) 212 213#define SF_CLRBIT(sc, reg, x) \ 214 csr_write_4(sc, reg, csr_read_4(sc, reg) & ~x) 215 216static u_int32_t csr_read_4(sc, reg) 217 struct sf_softc *sc; 218 int reg; 219{ 220 u_int32_t val; 221 222#ifdef SF_USEIOSPACE 223 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); 224 val = CSR_READ_4(sc, SF_INDIRECTIO_DATA); 225#else 226 val = CSR_READ_4(sc, (reg + SF_RMAP_INTREG_BASE)); 227#endif 228 229 return(val); 230} 231 232static u_int8_t sf_read_eeprom(sc, reg) 233 struct sf_softc *sc; 234 int reg; 235{ 236 u_int8_t val; 237 238 val = (csr_read_4(sc, SF_EEADDR_BASE + 239 (reg & 0xFFFFFFFC)) >> (8 * (reg & 3))) & 0xFF; 240 241 return(val); 242} 243 244static void csr_write_4(sc, reg, val) 245 struct sf_softc *sc; 246 int reg; 247 u_int32_t val; 248{ 249#ifdef SF_USEIOSPACE 250 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); 251 CSR_WRITE_4(sc, SF_INDIRECTIO_DATA, val); 252#else 253 CSR_WRITE_4(sc, (reg + SF_RMAP_INTREG_BASE), val); 254#endif 255 return; 256} 257 258static u_int32_t sf_calchash(addr) 259 caddr_t addr; 260{ 261 u_int32_t crc, carry; 262 int i, j; 263 u_int8_t c; 264 265 /* Compute CRC for the address value. */ 266 crc = 0xFFFFFFFF; /* initial value */ 267 268 for (i = 0; i < 6; i++) { 269 c = *(addr + i); 270 for (j = 0; j < 8; j++) { 271 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 272 crc <<= 1; 273 c >>= 1; 274 if (carry) 275 crc = (crc ^ 0x04c11db6) | carry; 276 } 277 } 278 279 /* return the filter bit position */ 280 return(crc >> 23 & 0x1FF); 281} 282 283/* 284 * Copy the address 'mac' into the perfect RX filter entry at 285 * offset 'idx.' The perfect filter only has 16 entries so do 286 * some sanity tests. 287 */ 288static int sf_setperf(sc, idx, mac) 289 struct sf_softc *sc; 290 int idx; 291 caddr_t mac; 292{ 293 u_int16_t *p; 294 295 if (idx < 0 || idx > SF_RXFILT_PERFECT_CNT) 296 return(EINVAL); 297 298 if (mac == NULL) 299 return(EINVAL); 300 301 p = (u_int16_t *)mac; 302 303 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 304 (idx * SF_RXFILT_PERFECT_SKIP), htons(p[2])); 305 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 306 (idx * SF_RXFILT_PERFECT_SKIP) + 4, htons(p[1])); 307 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 308 (idx * SF_RXFILT_PERFECT_SKIP) + 8, htons(p[0])); 309 310 return(0); 311} 312 313/* 314 * Set the bit in the 512-bit hash table that corresponds to the 315 * specified mac address 'mac.' If 'prio' is nonzero, update the 316 * priority hash table instead of the filter hash table. 317 */ 318static int sf_sethash(sc, mac, prio) 319 struct sf_softc *sc; 320 caddr_t mac; 321 int prio; 322{ 323 u_int32_t h = 0; 324 325 if (mac == NULL) 326 return(EINVAL); 327 328 h = sf_calchash(mac); 329 330 if (prio) { 331 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_PRIOOFF + 332 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); 333 } else { 334 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_ADDROFF + 335 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); 336 } 337 338 return(0); 339} 340 341#ifdef notdef 342/* 343 * Set a VLAN tag in the receive filter. 344 */ 345static int sf_setvlan(sc, idx, vlan) 346 struct sf_softc *sc; 347 int idx; 348 u_int32_t vlan; 349{ 350 if (idx < 0 || idx >> SF_RXFILT_HASH_CNT) 351 return(EINVAL); 352 353 csr_write_4(sc, SF_RXFILT_HASH_BASE + 354 (idx * SF_RXFILT_HASH_SKIP) + SF_RXFILT_HASH_VLANOFF, vlan); 355 356 return(0); 357} 358#endif 359 360static int sf_miibus_readreg(dev, phy, reg) 361 device_t dev; 362 int phy, reg; 363{ 364 struct sf_softc *sc; 365 int i; 366 u_int32_t val = 0; 367 368 sc = device_get_softc(dev); 369 370 for (i = 0; i < SF_TIMEOUT; i++) { 371 val = csr_read_4(sc, SF_PHY_REG(phy, reg)); 372 if (val & SF_MII_DATAVALID) 373 break; 374 } 375 376 if (i == SF_TIMEOUT) 377 return(0); 378 379 if ((val & 0x0000FFFF) == 0xFFFF) 380 return(0); 381 382 return(val & 0x0000FFFF); 383} 384 385static int sf_miibus_writereg(dev, phy, reg, val) 386 device_t dev; 387 int phy, reg, val; 388{ 389 struct sf_softc *sc; 390 int i; 391 int busy; 392 393 sc = device_get_softc(dev); 394 395 csr_write_4(sc, SF_PHY_REG(phy, reg), val); 396 397 for (i = 0; i < SF_TIMEOUT; i++) { 398 busy = csr_read_4(sc, SF_PHY_REG(phy, reg)); 399 if (!(busy & SF_MII_BUSY)) 400 break; 401 } 402 403 return(0); 404} 405 406static void sf_miibus_statchg(dev) 407 device_t dev; 408{ 409 struct sf_softc *sc; 410 struct mii_data *mii; 411 412 sc = device_get_softc(dev); 413 mii = device_get_softc(sc->sf_miibus); 414 415 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 416 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 417 } else { 418 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 419 } 420 421 return; 422} 423 424static void sf_setmulti(sc) 425 struct sf_softc *sc; 426{ 427 struct ifnet *ifp; 428 int i; 429 struct ifmultiaddr *ifma; 430 u_int8_t dummy[] = { 0, 0, 0, 0, 0, 0 }; 431 432 ifp = &sc->arpcom.ac_if; 433 434 /* First zot all the existing filters. */ 435 for (i = 1; i < SF_RXFILT_PERFECT_CNT; i++) 436 sf_setperf(sc, i, (char *)&dummy); 437 for (i = SF_RXFILT_HASH_BASE; 438 i < (SF_RXFILT_HASH_MAX + 1); i += 4) 439 csr_write_4(sc, i, 0); 440 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI); 441 442 /* Now program new ones. */ 443 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 444 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI); 445 } else { 446 i = 1; 447 /* First find the tail of the list. */ 448 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 449 ifma = ifma->ifma_link.le_next) { 450 if (ifma->ifma_link.le_next == NULL) 451 break; 452 } 453 /* Now traverse the list backwards. */ 454 for (; ifma != NULL && ifma != (void *)&ifp->if_multiaddrs; 455 ifma = (struct ifmultiaddr *)ifma->ifma_link.le_prev) { 456 if (ifma->ifma_addr->sa_family != AF_LINK) 457 continue; 458 /* 459 * Program the first 15 multicast groups 460 * into the perfect filter. For all others, 461 * use the hash table. 462 */ 463 if (i < SF_RXFILT_PERFECT_CNT) { 464 sf_setperf(sc, i, 465 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 466 i++; 467 continue; 468 } 469 470 sf_sethash(sc, 471 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 0); 472 } 473 } 474 475 return; 476} 477 478/* 479 * Set media options. 480 */ 481static int sf_ifmedia_upd(ifp) 482 struct ifnet *ifp; 483{ 484 struct sf_softc *sc; 485 struct mii_data *mii; 486 487 sc = ifp->if_softc; 488 mii = device_get_softc(sc->sf_miibus); 489 mii_mediachg(mii); 490 491 return(0); 492} 493 494/* 495 * Report current media status. 496 */ 497static void sf_ifmedia_sts(ifp, ifmr) 498 struct ifnet *ifp; 499 struct ifmediareq *ifmr; 500{ 501 struct sf_softc *sc; 502 struct mii_data *mii; 503 504 sc = ifp->if_softc; 505 mii = device_get_softc(sc->sf_miibus); 506 507 mii_pollstat(mii); 508 ifmr->ifm_active = mii->mii_media_active; 509 ifmr->ifm_status = mii->mii_media_status; 510 511 return; 512} 513 514static int sf_ioctl(ifp, command, data) 515 struct ifnet *ifp; 516 u_long command; 517 caddr_t data; 518{ 519 struct sf_softc *sc = ifp->if_softc; 520 struct ifreq *ifr = (struct ifreq *) data; 521 struct mii_data *mii; 522 int s, error = 0; 523 524 s = splimp(); 525 526 switch(command) { 527 case SIOCSIFADDR: 528 case SIOCGIFADDR: 529 case SIOCSIFMTU: 530 error = ether_ioctl(ifp, command, data); 531 break; 532 case SIOCSIFFLAGS: 533 if (ifp->if_flags & IFF_UP) { 534 sf_init(sc); 535 } else { 536 if (ifp->if_flags & IFF_RUNNING) 537 sf_stop(sc); 538 } 539 error = 0; 540 break; 541 case SIOCADDMULTI: 542 case SIOCDELMULTI: 543 sf_setmulti(sc); 544 error = 0; 545 break; 546 case SIOCGIFMEDIA: 547 case SIOCSIFMEDIA: 548 mii = device_get_softc(sc->sf_miibus); 549 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 550 break; 551 default: 552 error = EINVAL; 553 break; 554 } 555 556 (void)splx(s); 557 558 return(error); 559} 560 561static void sf_reset(sc) 562 struct sf_softc *sc; 563{ 564 register int i; 565 566 csr_write_4(sc, SF_GEN_ETH_CTL, 0); 567 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 568 DELAY(1000); 569 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 570 571 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_RESET); 572 573 for (i = 0; i < SF_TIMEOUT; i++) { 574 DELAY(10); 575 if (!(csr_read_4(sc, SF_PCI_DEVCFG) & SF_PCIDEVCFG_RESET)) 576 break; 577 } 578 579 if (i == SF_TIMEOUT) 580 printf("sf%d: reset never completed!\n", sc->sf_unit); 581 582 /* Wait a little while for the chip to get its brains in order. */ 583 DELAY(1000); 584 return; 585} 586 587/* 588 * Probe for an Adaptec AIC-6915 chip. Check the PCI vendor and device 589 * IDs against our list and return a device name if we find a match. 590 * We also check the subsystem ID so that we can identify exactly which 591 * NIC has been found, if possible. 592 */ 593static int sf_probe(dev) 594 device_t dev; 595{ 596 struct sf_type *t; 597 598 t = sf_devs; 599 600 while(t->sf_name != NULL) { 601 if ((pci_get_vendor(dev) == t->sf_vid) && 602 (pci_get_device(dev) == t->sf_did)) { 603 switch((pci_read_config(dev, 604 SF_PCI_SUBVEN_ID, 4) >> 16) & 0xFFFF) { 605 case AD_SUBSYSID_62011_REV0: 606 case AD_SUBSYSID_62011_REV1: 607 device_set_desc(dev, 608 "Adaptec ANA-62011 10/100BaseTX"); 609 return(0); 610 break; 611 case AD_SUBSYSID_62022: 612 device_set_desc(dev, 613 "Adaptec ANA-62022 10/100BaseTX"); 614 return(0); 615 break; 616 case AD_SUBSYSID_62044: 617 device_set_desc(dev, 618 "Adaptec ANA-62044 10/100BaseTX"); 619 return(0); 620 break; 621 case AD_SUBSYSID_62020: 622 device_set_desc(dev, 623 "Adaptec ANA-62020 10/100BaseFX"); 624 return(0); 625 break; 626 case AD_SUBSYSID_69011: 627 device_set_desc(dev, 628 "Adaptec ANA-69011 10/100BaseTX"); 629 return(0); 630 break; 631 default: 632 device_set_desc(dev, t->sf_name); 633 return(0); 634 break; 635 } 636 } 637 t++; 638 } 639 640 return(ENXIO); 641} 642 643/* 644 * Attach the interface. Allocate softc structures, do ifmedia 645 * setup and ethernet/BPF attach. 646 */ 647static int sf_attach(dev) 648 device_t dev; 649{ 650 int s, i; 651 u_int32_t command; 652 struct sf_softc *sc; 653 struct ifnet *ifp; 654 int unit, rid, error = 0; 655 656 s = splimp(); 657 658 sc = device_get_softc(dev); 659 unit = device_get_unit(dev); 660 bzero(sc, sizeof(struct sf_softc)); 661 662 /* 663 * Handle power management nonsense. 664 */ 665 command = pci_read_config(dev, SF_PCI_CAPID, 4) & 0x000000FF; 666 if (command == 0x01) { 667 668 command = pci_read_config(dev, SF_PCI_PWRMGMTCTRL, 4); 669 if (command & SF_PSTATE_MASK) { 670 u_int32_t iobase, membase, irq; 671 672 /* Save important PCI config data. */ 673 iobase = pci_read_config(dev, SF_PCI_LOIO, 4); 674 membase = pci_read_config(dev, SF_PCI_LOMEM, 4); 675 irq = pci_read_config(dev, SF_PCI_INTLINE, 4); 676 677 /* Reset the power state. */ 678 printf("sf%d: chip is in D%d power mode " 679 "-- setting to D0\n", unit, command & SF_PSTATE_MASK); 680 command &= 0xFFFFFFFC; 681 pci_write_config(dev, SF_PCI_PWRMGMTCTRL, command, 4); 682 683 /* Restore PCI config data. */ 684 pci_write_config(dev, SF_PCI_LOIO, iobase, 4); 685 pci_write_config(dev, SF_PCI_LOMEM, membase, 4); 686 pci_write_config(dev, SF_PCI_INTLINE, irq, 4); 687 } 688 } 689 690 /* 691 * Map control/status registers. 692 */ 693 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 694 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 695 pci_write_config(dev, PCI_COMMAND_STATUS_REG, command, 4); 696 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 697 698#ifdef SF_USEIOSPACE 699 if (!(command & PCIM_CMD_PORTEN)) { 700 printf("sf%d: failed to enable I/O ports!\n", unit); 701 error = ENXIO; 702 goto fail; 703 } 704#else 705 if (!(command & PCIM_CMD_MEMEN)) { 706 printf("sf%d: failed to enable memory mapping!\n", unit); 707 error = ENXIO; 708 goto fail; 709 } 710#endif 711 712 rid = SF_RID; 713 sc->sf_res = bus_alloc_resource(dev, SF_RES, &rid, 714 0, ~0, 1, RF_ACTIVE); 715 716 if (sc->sf_res == NULL) { 717 printf ("sf%d: couldn't map ports\n", unit); 718 error = ENXIO; 719 goto fail; 720 } 721 722 sc->sf_btag = rman_get_bustag(sc->sf_res); 723 sc->sf_bhandle = rman_get_bushandle(sc->sf_res); 724 725 /* Allocate interrupt */ 726 rid = 0; 727 sc->sf_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 728 RF_SHAREABLE | RF_ACTIVE); 729 730 if (sc->sf_irq == NULL) { 731 printf("sf%d: couldn't map interrupt\n", unit); 732 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 733 error = ENXIO; 734 goto fail; 735 } 736 737 error = bus_setup_intr(dev, sc->sf_irq, INTR_TYPE_NET, 738 sf_intr, sc, &sc->sf_intrhand); 739 740 if (error) { 741 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_res); 742 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 743 printf("sf%d: couldn't set up irq\n", unit); 744 goto fail; 745 } 746 747 callout_handle_init(&sc->sf_stat_ch); 748 749 /* Reset the adapter. */ 750 sf_reset(sc); 751 752 /* 753 * Get station address from the EEPROM. 754 */ 755 for (i = 0; i < ETHER_ADDR_LEN; i++) 756 sc->arpcom.ac_enaddr[i] = 757 sf_read_eeprom(sc, SF_EE_NODEADDR + ETHER_ADDR_LEN - i); 758 759 /* 760 * An Adaptec chip was detected. Inform the world. 761 */ 762 printf("sf%d: Ethernet address: %6D\n", unit, 763 sc->arpcom.ac_enaddr, ":"); 764 765 sc->sf_unit = unit; 766 767 /* Allocate the descriptor queues. */ 768 sc->sf_ldata = contigmalloc(sizeof(struct sf_list_data), M_DEVBUF, 769 M_NOWAIT, 0x100000, 0xffffffff, PAGE_SIZE, 0); 770 771 if (sc->sf_ldata == NULL) { 772 printf("sf%d: no memory for list buffers!\n", unit); 773 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand); 774 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq); 775 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 776 error = ENXIO; 777 goto fail; 778 } 779 780 bzero(sc->sf_ldata, sizeof(struct sf_list_data)); 781 782 /* Do MII setup. */ 783 if (mii_phy_probe(dev, &sc->sf_miibus, 784 sf_ifmedia_upd, sf_ifmedia_sts)) { 785 printf("sf%d: MII without any phy!\n", sc->sf_unit); 786 free(sc->sf_ldata, M_DEVBUF); 787 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand); 788 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq); 789 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 790 error = ENXIO; 791 goto fail; 792 } 793 794 ifp = &sc->arpcom.ac_if; 795 ifp->if_softc = sc; 796 ifp->if_unit = unit; 797 ifp->if_name = "sf"; 798 ifp->if_mtu = ETHERMTU; 799 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 800 ifp->if_ioctl = sf_ioctl; 801 ifp->if_output = ether_output; 802 ifp->if_start = sf_start; 803 ifp->if_watchdog = sf_watchdog; 804 ifp->if_init = sf_init; 805 ifp->if_baudrate = 10000000; 806 ifp->if_snd.ifq_maxlen = SF_TX_DLIST_CNT - 1; 807 808 /* 809 * Call MI attach routines. 810 */ 811 if_attach(ifp); 812 ether_ifattach(ifp); 813 814 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header)); 815 816fail: 817 splx(s); 818 return(error); 819} 820 821static int sf_detach(dev) 822 device_t dev; 823{ 824 struct sf_softc *sc; 825 struct ifnet *ifp; 826 int s; 827 828 s = splimp(); 829 830 sc = device_get_softc(dev); 831 ifp = &sc->arpcom.ac_if; 832 833 if_detach(ifp); 834 sf_stop(sc); 835 836 bus_generic_detach(dev); 837 device_delete_child(dev, sc->sf_miibus); 838 839 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand); 840 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq); 841 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 842 843 free(sc->sf_ldata, M_DEVBUF); 844 845 splx(s); 846 847 return(0); 848} 849 850static int sf_init_rx_ring(sc) 851 struct sf_softc *sc; 852{ 853 struct sf_list_data *ld; 854 int i; 855 856 ld = sc->sf_ldata; 857 858 bzero((char *)ld->sf_rx_dlist_big, 859 sizeof(struct sf_rx_bufdesc_type0) * SF_RX_DLIST_CNT); 860 bzero((char *)ld->sf_rx_clist, 861 sizeof(struct sf_rx_cmpdesc_type3) * SF_RX_CLIST_CNT); 862 863 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 864 if (sf_newbuf(sc, &ld->sf_rx_dlist_big[i], NULL) == ENOBUFS) 865 return(ENOBUFS); 866 } 867 868 return(0); 869} 870 871static void sf_init_tx_ring(sc) 872 struct sf_softc *sc; 873{ 874 struct sf_list_data *ld; 875 int i; 876 877 ld = sc->sf_ldata; 878 879 bzero((char *)ld->sf_tx_dlist, 880 sizeof(struct sf_tx_bufdesc_type0) * SF_TX_DLIST_CNT); 881 bzero((char *)ld->sf_tx_clist, 882 sizeof(struct sf_tx_cmpdesc_type0) * SF_TX_CLIST_CNT); 883 884 for (i = 0; i < SF_TX_DLIST_CNT; i++) 885 ld->sf_tx_dlist[i].sf_id = SF_TX_BUFDESC_ID; 886 for (i = 0; i < SF_TX_CLIST_CNT; i++) 887 ld->sf_tx_clist[i].sf_type = SF_TXCMPTYPE_TX; 888 889 ld->sf_tx_dlist[SF_TX_DLIST_CNT - 1].sf_end = 1; 890 sc->sf_tx_cnt = 0; 891 892 return; 893} 894 895static int sf_newbuf(sc, c, m) 896 struct sf_softc *sc; 897 struct sf_rx_bufdesc_type0 *c; 898 struct mbuf *m; 899{ 900 struct mbuf *m_new = NULL; 901 902 if (m == NULL) { 903 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 904 if (m_new == NULL) { 905 printf("sf%d: no memory for rx list -- " 906 "packet dropped!\n", sc->sf_unit); 907 return(ENOBUFS); 908 } 909 910 MCLGET(m_new, M_DONTWAIT); 911 if (!(m_new->m_flags & M_EXT)) { 912 printf("sf%d: no memory for rx list -- " 913 "packet dropped!\n", sc->sf_unit); 914 m_freem(m_new); 915 return(ENOBUFS); 916 } 917 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 918 } else { 919 m_new = m; 920 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 921 m_new->m_data = m_new->m_ext.ext_buf; 922 } 923 924 m_adj(m_new, sizeof(u_int64_t)); 925 926 c->sf_mbuf = m_new; 927 c->sf_addrlo = SF_RX_HOSTADDR(vtophys(mtod(m_new, caddr_t))); 928 c->sf_valid = 1; 929 930 return(0); 931} 932 933/* 934 * The starfire is programmed to use 'normal' mode for packet reception, 935 * which means we use the consumer/producer model for both the buffer 936 * descriptor queue and the completion descriptor queue. The only problem 937 * with this is that it involves a lot of register accesses: we have to 938 * read the RX completion consumer and producer indexes and the RX buffer 939 * producer index, plus the RX completion consumer and RX buffer producer 940 * indexes have to be updated. It would have been easier if Adaptec had 941 * put each index in a separate register, especially given that the damn 942 * NIC has a 512K register space. 943 * 944 * In spite of all the lovely features that Adaptec crammed into the 6915, 945 * it is marred by one truly stupid design flaw, which is that receive 946 * buffer addresses must be aligned on a longword boundary. This forces 947 * the packet payload to be unaligned, which is suboptimal on the x86 and 948 * completely unuseable on the Alpha. Our only recourse is to copy received 949 * packets into properly aligned buffers before handing them off. 950 */ 951 952static void sf_rxeof(sc) 953 struct sf_softc *sc; 954{ 955 struct ether_header *eh; 956 struct mbuf *m; 957 struct ifnet *ifp; 958 struct sf_rx_bufdesc_type0 *desc; 959 struct sf_rx_cmpdesc_type3 *cur_rx; 960 u_int32_t rxcons, rxprod; 961 int cmpprodidx, cmpconsidx, bufprodidx; 962 963 ifp = &sc->arpcom.ac_if; 964 965 rxcons = csr_read_4(sc, SF_CQ_CONSIDX); 966 rxprod = csr_read_4(sc, SF_RXDQ_PTR_Q1); 967 cmpprodidx = SF_IDX_LO(csr_read_4(sc, SF_CQ_PRODIDX)); 968 cmpconsidx = SF_IDX_LO(rxcons); 969 bufprodidx = SF_IDX_LO(rxprod); 970 971 while (cmpconsidx != cmpprodidx) { 972 struct mbuf *m0; 973 974 cur_rx = &sc->sf_ldata->sf_rx_clist[cmpconsidx]; 975 desc = &sc->sf_ldata->sf_rx_dlist_big[cur_rx->sf_endidx]; 976 m = desc->sf_mbuf; 977 SF_INC(cmpconsidx, SF_RX_CLIST_CNT); 978 SF_INC(bufprodidx, SF_RX_DLIST_CNT); 979 980 if (!(cur_rx->sf_status1 & SF_RXSTAT1_OK)) { 981 ifp->if_ierrors++; 982 sf_newbuf(sc, desc, m); 983 continue; 984 } 985 986 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 987 cur_rx->sf_len + ETHER_ALIGN, 0, ifp, NULL); 988 sf_newbuf(sc, desc, m); 989 if (m0 == NULL) { 990 ifp->if_ierrors++; 991 continue; 992 } 993 m_adj(m0, ETHER_ALIGN); 994 m = m0; 995 996 eh = mtod(m, struct ether_header *); 997 ifp->if_ipackets++; 998 999 if (ifp->if_bpf) { 1000 bpf_mtap(ifp, m); 1001 if (ifp->if_flags & IFF_PROMISC && 1002 (bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr, 1003 ETHER_ADDR_LEN) && !(eh->ether_dhost[0] & 1))) { 1004 m_freem(m); 1005 continue; 1006 } 1007 } 1008 1009 /* Remove header from mbuf and pass it on. */ 1010 m_adj(m, sizeof(struct ether_header)); 1011 ether_input(ifp, eh, m); 1012 1013 } 1014 1015 csr_write_4(sc, SF_CQ_CONSIDX, 1016 (rxcons & ~SF_CQ_CONSIDX_RXQ1) | cmpconsidx); 1017 csr_write_4(sc, SF_RXDQ_PTR_Q1, 1018 (rxprod & ~SF_RXDQ_PRODIDX) | bufprodidx); 1019 1020 return; 1021} 1022 1023/* 1024 * Read the transmit status from the completion queue and release 1025 * mbufs. Note that the buffer descriptor index in the completion 1026 * descriptor is an offset from the start of the transmit buffer 1027 * descriptor list in bytes. This is important because the manual 1028 * gives the impression that it should match the producer/consumer 1029 * index, which is the offset in 8 byte blocks. 1030 */ 1031static void sf_txeof(sc) 1032 struct sf_softc *sc; 1033{ 1034 int txcons, cmpprodidx, cmpconsidx; 1035 struct sf_tx_cmpdesc_type1 *cur_cmp; 1036 struct sf_tx_bufdesc_type0 *cur_tx; 1037 struct ifnet *ifp; 1038 1039 ifp = &sc->arpcom.ac_if; 1040 1041 txcons = csr_read_4(sc, SF_CQ_CONSIDX); 1042 cmpprodidx = SF_IDX_HI(csr_read_4(sc, SF_CQ_PRODIDX)); 1043 cmpconsidx = SF_IDX_HI(txcons); 1044 1045 while (cmpconsidx != cmpprodidx) { 1046 cur_cmp = &sc->sf_ldata->sf_tx_clist[cmpconsidx]; 1047 cur_tx = &sc->sf_ldata->sf_tx_dlist[cur_cmp->sf_index >> 7]; 1048 SF_INC(cmpconsidx, SF_TX_CLIST_CNT); 1049 1050 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_OK) 1051 ifp->if_opackets++; 1052 else 1053 ifp->if_oerrors++; 1054 1055 sc->sf_tx_cnt--; 1056 if (cur_tx->sf_mbuf != NULL) { 1057 m_freem(cur_tx->sf_mbuf); 1058 cur_tx->sf_mbuf = NULL; 1059 } 1060 } 1061 1062 ifp->if_timer = 0; 1063 ifp->if_flags &= ~IFF_OACTIVE; 1064 1065 csr_write_4(sc, SF_CQ_CONSIDX, 1066 (txcons & ~SF_CQ_CONSIDX_TXQ) | 1067 ((cmpconsidx << 16) & 0xFFFF0000)); 1068 1069 return; 1070} 1071 1072static void sf_intr(arg) 1073 void *arg; 1074{ 1075 struct sf_softc *sc; 1076 struct ifnet *ifp; 1077 u_int32_t status; 1078 1079 sc = arg; 1080 ifp = &sc->arpcom.ac_if; 1081 1082 if (!(csr_read_4(sc, SF_ISR_SHADOW) & SF_ISR_PCIINT_ASSERTED)) 1083 return; 1084 1085 /* Disable interrupts. */ 1086 csr_write_4(sc, SF_IMR, 0x00000000); 1087 1088 for (;;) { 1089 status = csr_read_4(sc, SF_ISR); 1090 if (status) 1091 csr_write_4(sc, SF_ISR, status); 1092 1093 if (!(status & SF_INTRS)) 1094 break; 1095 1096 if (status & SF_ISR_RXDQ1_DMADONE) 1097 sf_rxeof(sc); 1098 1099 if (status & SF_ISR_TX_TXDONE) 1100 sf_txeof(sc); 1101 1102 if (status & SF_ISR_ABNORMALINTR) { 1103 if (status & SF_ISR_STATSOFLOW) { 1104 untimeout(sf_stats_update, sc, 1105 sc->sf_stat_ch); 1106 sf_stats_update(sc); 1107 } else 1108 sf_init(sc); 1109 } 1110 } 1111 1112 /* Re-enable interrupts. */ 1113 csr_write_4(sc, SF_IMR, SF_INTRS); 1114 1115 if (ifp->if_snd.ifq_head != NULL) 1116 sf_start(ifp); 1117 1118 return; 1119} 1120 1121static void sf_init(xsc) 1122 void *xsc; 1123{ 1124 struct sf_softc *sc; 1125 struct ifnet *ifp; 1126 struct mii_data *mii; 1127 int i, s; 1128 1129 s = splimp(); 1130 1131 sc = xsc; 1132 ifp = &sc->arpcom.ac_if; 1133 mii = device_get_softc(sc->sf_miibus); 1134 1135 sf_stop(sc); 1136 sf_reset(sc); 1137 1138 /* Init all the receive filter registers */ 1139 for (i = SF_RXFILT_PERFECT_BASE; 1140 i < (SF_RXFILT_HASH_MAX + 1); i += 4) 1141 csr_write_4(sc, i, 0); 1142 1143 /* Empty stats counter registers. */ 1144 for (i = 0; i < sizeof(struct sf_stats)/sizeof(u_int32_t); i++) 1145 csr_write_4(sc, SF_STATS_BASE + 1146 (i + sizeof(u_int32_t)), 0); 1147 1148 /* Init our MAC address */ 1149 csr_write_4(sc, SF_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1150 csr_write_4(sc, SF_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1151 sf_setperf(sc, 0, (caddr_t)&sc->arpcom.ac_enaddr); 1152 1153 if (sf_init_rx_ring(sc) == ENOBUFS) { 1154 printf("sf%d: initialization failed: no " 1155 "memory for rx buffers\n", sc->sf_unit); 1156 (void)splx(s); 1157 return; 1158 } 1159 1160 sf_init_tx_ring(sc); 1161 1162 csr_write_4(sc, SF_RXFILT, SF_PERFMODE_NORMAL|SF_HASHMODE_WITHVLAN); 1163 1164 /* If we want promiscuous mode, set the allframes bit. */ 1165 if (ifp->if_flags & IFF_PROMISC) { 1166 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 1167 } else { 1168 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 1169 } 1170 1171 if (ifp->if_flags & IFF_BROADCAST) { 1172 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_BROAD); 1173 } else { 1174 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_BROAD); 1175 } 1176 1177 /* Init the completion queue indexes */ 1178 csr_write_4(sc, SF_CQ_CONSIDX, 0); 1179 csr_write_4(sc, SF_CQ_PRODIDX, 0); 1180 1181 /* Init the RX completion queue */ 1182 csr_write_4(sc, SF_RXCQ_CTL_1, 1183 vtophys(sc->sf_ldata->sf_rx_clist) & SF_RXCQ_ADDR); 1184 SF_SETBIT(sc, SF_RXCQ_CTL_1, SF_RXCQTYPE_3); 1185 1186 /* Init RX DMA control. */ 1187 SF_SETBIT(sc, SF_RXDMA_CTL, SF_RXDMA_REPORTBADPKTS); 1188 1189 /* Init the RX buffer descriptor queue. */ 1190 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 1191 vtophys(sc->sf_ldata->sf_rx_dlist_big)); 1192 csr_write_4(sc, SF_RXDQ_CTL_1, (MCLBYTES << 16) | SF_DESCSPACE_16BYTES); 1193 csr_write_4(sc, SF_RXDQ_PTR_Q1, SF_RX_DLIST_CNT - 1); 1194 1195 /* Init the TX completion queue */ 1196 csr_write_4(sc, SF_TXCQ_CTL, 1197 vtophys(sc->sf_ldata->sf_tx_clist) & SF_RXCQ_ADDR); 1198 1199 /* Init the TX buffer descriptor queue. */ 1200 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 1201 vtophys(sc->sf_ldata->sf_tx_dlist)); 1202 SF_SETBIT(sc, SF_TX_FRAMCTL, SF_TXFRMCTL_CPLAFTERTX); 1203 csr_write_4(sc, SF_TXDQ_CTL, 1204 SF_TXBUFDESC_TYPE0|SF_TXMINSPACE_128BYTES|SF_TXSKIPLEN_8BYTES); 1205 SF_SETBIT(sc, SF_TXDQ_CTL, SF_TXDQCTL_NODMACMP); 1206 1207 /* Enable autopadding of short TX frames. */ 1208 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_AUTOPAD); 1209 1210 /* Make sure the duplex mode is set correctly. */ 1211 if ((mii->mii_media.ifm_media & IFM_GMASK) == IFM_FDX) { 1212 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 1213 } else { 1214 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 1215 } 1216 1217 /* Enable interrupts. */ 1218 csr_write_4(sc, SF_IMR, SF_INTRS); 1219 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_INTR_ENB); 1220 1221 /* Enable the RX and TX engines. */ 1222 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_RX_ENB|SF_ETHCTL_RXDMA_ENB); 1223 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_TX_ENB|SF_ETHCTL_TXDMA_ENB); 1224 1225 mii_mediachg(mii); 1226 1227 ifp->if_flags |= IFF_RUNNING; 1228 ifp->if_flags &= ~IFF_OACTIVE; 1229 1230 sc->sf_stat_ch = timeout(sf_stats_update, sc, hz); 1231 1232 splx(s); 1233 1234 return; 1235} 1236 1237static int sf_encap(sc, c, m_head) 1238 struct sf_softc *sc; 1239 struct sf_tx_bufdesc_type0 *c; 1240 struct mbuf *m_head; 1241{ 1242 int frag = 0; 1243 struct sf_frag *f = NULL; 1244 struct mbuf *m; 1245 1246 m = m_head; 1247 1248 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1249 if (m->m_len != 0) { 1250 if (frag == SF_MAXFRAGS) 1251 break; 1252 f = &c->sf_frags[frag]; 1253 if (frag == 0) 1254 f->sf_pktlen = m_head->m_pkthdr.len; 1255 f->sf_fraglen = m->m_len; 1256 f->sf_addr = vtophys(mtod(m, vm_offset_t)); 1257 frag++; 1258 } 1259 } 1260 1261 if (m != NULL) { 1262 struct mbuf *m_new = NULL; 1263 1264 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1265 if (m_new == NULL) { 1266 printf("sf%d: no memory for tx list", sc->sf_unit); 1267 return(1); 1268 } 1269 1270 if (m_head->m_pkthdr.len > MHLEN) { 1271 MCLGET(m_new, M_DONTWAIT); 1272 if (!(m_new->m_flags & M_EXT)) { 1273 m_freem(m_new); 1274 printf("sf%d: no memory for tx list", 1275 sc->sf_unit); 1276 return(1); 1277 } 1278 } 1279 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1280 mtod(m_new, caddr_t)); 1281 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1282 m_freem(m_head); 1283 m_head = m_new; 1284 f = &c->sf_frags[0]; 1285 f->sf_fraglen = f->sf_pktlen = m_head->m_pkthdr.len; 1286 f->sf_addr = vtophys(mtod(m_head, caddr_t)); 1287 frag = 1; 1288 } 1289 1290 c->sf_mbuf = m_head; 1291 c->sf_id = SF_TX_BUFDESC_ID; 1292 c->sf_fragcnt = frag; 1293 c->sf_intr = 1; 1294 c->sf_caltcp = 0; 1295 c->sf_crcen = 1; 1296 1297 return(0); 1298} 1299 1300static void sf_start(ifp) 1301 struct ifnet *ifp; 1302{ 1303 struct sf_softc *sc; 1304 struct sf_tx_bufdesc_type0 *cur_tx = NULL; 1305 struct mbuf *m_head = NULL; 1306 int i, txprod; 1307 1308 sc = ifp->if_softc; 1309 1310 if (ifp->if_flags & IFF_OACTIVE) 1311 return; 1312 1313 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX); 1314 i = SF_IDX_HI(txprod) >> 4; 1315 1316 while(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf == NULL) { 1317 IF_DEQUEUE(&ifp->if_snd, m_head); 1318 if (m_head == NULL) 1319 break; 1320 1321 cur_tx = &sc->sf_ldata->sf_tx_dlist[i]; 1322 sf_encap(sc, cur_tx, m_head); 1323 1324 /* 1325 * If there's a BPF listener, bounce a copy of this frame 1326 * to him. 1327 */ 1328 if (ifp->if_bpf) 1329 bpf_mtap(ifp, m_head); 1330 1331 SF_INC(i, SF_TX_DLIST_CNT); 1332 sc->sf_tx_cnt++; 1333 if (sc->sf_tx_cnt == (SF_TX_DLIST_CNT - 2)) 1334 break; 1335 } 1336 1337 if (cur_tx == NULL) 1338 return; 1339 1340 /* Transmit */ 1341 csr_write_4(sc, SF_TXDQ_PRODIDX, 1342 (txprod & ~SF_TXDQ_PRODIDX_HIPRIO) | 1343 ((i << 20) & 0xFFFF0000)); 1344 1345 ifp->if_timer = 5; 1346 1347 return; 1348} 1349 1350static void sf_stop(sc) 1351 struct sf_softc *sc; 1352{ 1353 int i; 1354 struct ifnet *ifp; 1355 1356 ifp = &sc->arpcom.ac_if; 1357 1358 untimeout(sf_stats_update, sc, sc->sf_stat_ch); 1359 1360 csr_write_4(sc, SF_GEN_ETH_CTL, 0); 1361 csr_write_4(sc, SF_CQ_CONSIDX, 0); 1362 csr_write_4(sc, SF_CQ_PRODIDX, 0); 1363 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 0); 1364 csr_write_4(sc, SF_RXDQ_CTL_1, 0); 1365 csr_write_4(sc, SF_RXDQ_PTR_Q1, 0); 1366 csr_write_4(sc, SF_TXCQ_CTL, 0); 1367 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 0); 1368 csr_write_4(sc, SF_TXDQ_CTL, 0); 1369 sf_reset(sc); 1370 1371 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 1372 if (sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf != NULL) { 1373 m_freem(sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf); 1374 sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf = NULL; 1375 } 1376 } 1377 1378 for (i = 0; i < SF_TX_DLIST_CNT; i++) { 1379 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) { 1380 m_freem(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf); 1381 sc->sf_ldata->sf_tx_dlist[i].sf_mbuf = NULL; 1382 } 1383 } 1384 1385 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 1386 1387 return; 1388} 1389 1390/* 1391 * Note: it is important that this function not be interrupted. We 1392 * use a two-stage register access scheme: if we are interrupted in 1393 * between setting the indirect address register and reading from the 1394 * indirect data register, the contents of the address register could 1395 * be changed out from under us. 1396 */ 1397static void sf_stats_update(xsc) 1398 void *xsc; 1399{ 1400 struct sf_softc *sc; 1401 struct ifnet *ifp; 1402 struct mii_data *mii; 1403 struct sf_stats stats; 1404 u_int32_t *ptr; 1405 int i, s; 1406 1407 s = splimp(); 1408 1409 sc = xsc; 1410 ifp = &sc->arpcom.ac_if; 1411 mii = device_get_softc(sc->sf_miibus); 1412 1413 ptr = (u_int32_t *)&stats; 1414 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++) 1415 ptr[i] = csr_read_4(sc, SF_STATS_BASE + 1416 (i + sizeof(u_int32_t))); 1417 1418 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++) 1419 csr_write_4(sc, SF_STATS_BASE + 1420 (i + sizeof(u_int32_t)), 0); 1421 1422 ifp->if_collisions += stats.sf_tx_single_colls + 1423 stats.sf_tx_multi_colls + stats.sf_tx_excess_colls; 1424 1425 mii_tick(mii); 1426 1427 sc->sf_stat_ch = timeout(sf_stats_update, sc, hz); 1428 1429 splx(s); 1430 1431 return; 1432} 1433 1434static void sf_watchdog(ifp) 1435 struct ifnet *ifp; 1436{ 1437 struct sf_softc *sc; 1438 1439 sc = ifp->if_softc; 1440 1441 ifp->if_oerrors++; 1442 printf("sf%d: watchdog timeout\n", sc->sf_unit); 1443 1444 sf_stop(sc); 1445 sf_reset(sc); 1446 sf_init(sc); 1447 1448 if (ifp->if_snd.ifq_head != NULL) 1449 sf_start(ifp); 1450 1451 return; 1452} 1453 1454static void sf_shutdown(dev) 1455 device_t dev; 1456{ 1457 struct sf_softc *sc; 1458 1459 sc = device_get_softc(dev); 1460 1461 sf_stop(sc); 1462 1463 return; 1464} 1465