if_sf.c revision 51533
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/dev/sf/if_sf.c 51533 1999-09-22 06:08:11Z wpaul $ 33 */ 34 35/* 36 * Adaptec AIC-6915 "Starfire" PCI fast ethernet driver for FreeBSD. 37 * Programming manual is available from www.adaptec.com. 38 * 39 * Written by Bill Paul <wpaul@ctr.columbia.edu> 40 * Department of Electical Engineering 41 * Columbia University, New York City 42 */ 43 44/* 45 * The Adaptec AIC-6915 "Starfire" is a 64-bit 10/100 PCI ethernet 46 * controller designed with flexibility and reducing CPU load in mind. 47 * The Starfire offers high and low priority buffer queues, a 48 * producer/consumer index mechanism and several different buffer 49 * queue and completion queue descriptor types. Any one of a number 50 * of different driver designs can be used, depending on system and 51 * OS requirements. This driver makes use of type0 transmit frame 52 * descriptors (since BSD fragments packets across an mbuf chain) 53 * and two RX buffer queues prioritized on size (one queue for small 54 * frames that will fit into a single mbuf, another with full size 55 * mbuf clusters for everything else). The producer/consumer indexes 56 * and completion queues are also used. 57 * 58 * One downside to the Starfire has to do with alignment: buffer 59 * queues must be aligned on 256-byte boundaries, and receive buffers 60 * must be aligned on longword boundaries. The receive buffer alignment 61 * causes problems on the Alpha platform, where the packet payload 62 * should be longword aligned. There is no simple way around this. 63 * 64 * For receive filtering, the Starfire offers 16 perfect filter slots 65 * and a 512-bit hash table. 66 * 67 * The Starfire has no internal transceiver, relying instead on an 68 * external MII-based transceiver. Accessing registers on external 69 * PHYs is done through a special register map rather than with the 70 * usual bitbang MDIO method. 71 * 72 * Acesssing the registers on the Starfire is a little tricky. The 73 * Starfire has a 512K internal register space. When programmed for 74 * PCI memory mapped mode, the entire register space can be accessed 75 * directly. However in I/O space mode, only 256 bytes are directly 76 * mapped into PCI I/O space. The other registers can be accessed 77 * indirectly using the SF_INDIRECTIO_ADDR and SF_INDIRECTIO_DATA 78 * registers inside the 256-byte I/O window. 79 */ 80 81#include "bpf.h" 82 83#include <sys/param.h> 84#include <sys/systm.h> 85#include <sys/sockio.h> 86#include <sys/mbuf.h> 87#include <sys/malloc.h> 88#include <sys/kernel.h> 89#include <sys/socket.h> 90 91#include <net/if.h> 92#include <net/if_arp.h> 93#include <net/ethernet.h> 94#include <net/if_dl.h> 95#include <net/if_media.h> 96 97#if NBPF > 0 98#include <net/bpf.h> 99#endif 100 101#include <vm/vm.h> /* for vtophys */ 102#include <vm/pmap.h> /* for vtophys */ 103#include <machine/clock.h> /* for DELAY */ 104#include <machine/bus_pio.h> 105#include <machine/bus_memio.h> 106#include <machine/bus.h> 107#include <machine/resource.h> 108#include <sys/bus.h> 109#include <sys/rman.h> 110 111#include <dev/mii/mii.h> 112#include <dev/mii/miivar.h> 113 114/* "controller miibus0" required. See GENERIC if you get errors here. */ 115#include "miibus_if.h" 116 117#include <pci/pcireg.h> 118#include <pci/pcivar.h> 119 120#define SF_USEIOSPACE 121 122#include <pci/if_sfreg.h> 123 124#ifndef lint 125static const char rcsid[] = 126 "$FreeBSD: head/sys/dev/sf/if_sf.c 51533 1999-09-22 06:08:11Z wpaul $"; 127#endif 128 129static struct sf_type sf_devs[] = { 130 { AD_VENDORID, AD_DEVICEID_STARFIRE, 131 "Adaptec AIC-6915 10/100BaseTX" }, 132 { 0, 0, NULL } 133}; 134 135static int sf_probe __P((device_t)); 136static int sf_attach __P((device_t)); 137static int sf_detach __P((device_t)); 138static void sf_intr __P((void *)); 139static void sf_stats_update __P((void *)); 140static void sf_rxeof __P((struct sf_softc *)); 141static void sf_txeof __P((struct sf_softc *)); 142static int sf_encap __P((struct sf_softc *, 143 struct sf_tx_bufdesc_type0 *, 144 struct mbuf *)); 145static void sf_start __P((struct ifnet *)); 146static int sf_ioctl __P((struct ifnet *, u_long, caddr_t)); 147static void sf_init __P((void *)); 148static void sf_stop __P((struct sf_softc *)); 149static void sf_watchdog __P((struct ifnet *)); 150static void sf_shutdown __P((device_t)); 151static int sf_ifmedia_upd __P((struct ifnet *)); 152static void sf_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 153static void sf_reset __P((struct sf_softc *)); 154static int sf_init_rx_ring __P((struct sf_softc *)); 155static void sf_init_tx_ring __P((struct sf_softc *)); 156static int sf_newbuf __P((struct sf_softc *, 157 struct sf_rx_bufdesc_type0 *, 158 struct mbuf *)); 159static void sf_setmulti __P((struct sf_softc *)); 160static int sf_setperf __P((struct sf_softc *, int, caddr_t)); 161static int sf_sethash __P((struct sf_softc *, caddr_t, int)); 162#ifdef notdef 163static int sf_setvlan __P((struct sf_softc *, int, u_int32_t)); 164#endif 165 166static u_int8_t sf_read_eeprom __P((struct sf_softc *, int)); 167static u_int32_t sf_calchash __P((caddr_t)); 168 169static int sf_miibus_readreg __P((device_t, int, int)); 170static int sf_miibus_writereg __P((device_t, int, int, int)); 171static void sf_miibus_statchg __P((device_t)); 172 173static u_int32_t csr_read_4 __P((struct sf_softc *, int)); 174static void csr_write_4 __P((struct sf_softc *, int, u_int32_t)); 175 176#ifdef SF_USEIOSPACE 177#define SF_RES SYS_RES_IOPORT 178#define SF_RID SF_PCI_LOIO 179#else 180#define SF_RES SYS_RES_MEMORY 181#define SF_RID SF_PCI_LOMEM 182#endif 183 184static device_method_t sf_methods[] = { 185 /* Device interface */ 186 DEVMETHOD(device_probe, sf_probe), 187 DEVMETHOD(device_attach, sf_attach), 188 DEVMETHOD(device_detach, sf_detach), 189 DEVMETHOD(device_shutdown, sf_shutdown), 190 191 /* bus interface */ 192 DEVMETHOD(bus_print_child, bus_generic_print_child), 193 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 194 195 /* MII interface */ 196 DEVMETHOD(miibus_readreg, sf_miibus_readreg), 197 DEVMETHOD(miibus_writereg, sf_miibus_writereg), 198 DEVMETHOD(miibus_statchg, sf_miibus_statchg), 199 200 { 0, 0 } 201}; 202 203static driver_t sf_driver = { 204 "sf", 205 sf_methods, 206 sizeof(struct sf_softc), 207}; 208 209static devclass_t sf_devclass; 210 211DRIVER_MODULE(if_sf, pci, sf_driver, sf_devclass, 0, 0); 212DRIVER_MODULE(miibus, sf, miibus_driver, miibus_devclass, 0, 0); 213 214#define SF_SETBIT(sc, reg, x) \ 215 csr_write_4(sc, reg, csr_read_4(sc, reg) | x) 216 217#define SF_CLRBIT(sc, reg, x) \ 218 csr_write_4(sc, reg, csr_read_4(sc, reg) & ~x) 219 220static u_int32_t csr_read_4(sc, reg) 221 struct sf_softc *sc; 222 int reg; 223{ 224 u_int32_t val; 225 226#ifdef SF_USEIOSPACE 227 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); 228 val = CSR_READ_4(sc, SF_INDIRECTIO_DATA); 229#else 230 val = CSR_READ_4(sc, (reg + SF_RMAP_INTREG_BASE)); 231#endif 232 233 return(val); 234} 235 236static u_int8_t sf_read_eeprom(sc, reg) 237 struct sf_softc *sc; 238 int reg; 239{ 240 u_int8_t val; 241 242 val = (csr_read_4(sc, SF_EEADDR_BASE + 243 (reg & 0xFFFFFFFC)) >> (8 * (reg & 3))) & 0xFF; 244 245 return(val); 246} 247 248static void csr_write_4(sc, reg, val) 249 struct sf_softc *sc; 250 int reg; 251 u_int32_t val; 252{ 253#ifdef SF_USEIOSPACE 254 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); 255 CSR_WRITE_4(sc, SF_INDIRECTIO_DATA, val); 256#else 257 CSR_WRITE_4(sc, (reg + SF_RMAP_INTREG_BASE), val); 258#endif 259 return; 260} 261 262static u_int32_t sf_calchash(addr) 263 caddr_t addr; 264{ 265 u_int32_t crc, carry; 266 int i, j; 267 u_int8_t c; 268 269 /* Compute CRC for the address value. */ 270 crc = 0xFFFFFFFF; /* initial value */ 271 272 for (i = 0; i < 6; i++) { 273 c = *(addr + i); 274 for (j = 0; j < 8; j++) { 275 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 276 crc <<= 1; 277 c >>= 1; 278 if (carry) 279 crc = (crc ^ 0x04c11db6) | carry; 280 } 281 } 282 283 /* return the filter bit position */ 284 return(crc >> 23 & 0x1FF); 285} 286 287/* 288 * Copy the address 'mac' into the perfect RX filter entry at 289 * offset 'idx.' The perfect filter only has 16 entries so do 290 * some sanity tests. 291 */ 292static int sf_setperf(sc, idx, mac) 293 struct sf_softc *sc; 294 int idx; 295 caddr_t mac; 296{ 297 u_int16_t *p; 298 299 if (idx < 0 || idx > SF_RXFILT_PERFECT_CNT) 300 return(EINVAL); 301 302 if (mac == NULL) 303 return(EINVAL); 304 305 p = (u_int16_t *)mac; 306 307 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 308 (idx * SF_RXFILT_PERFECT_SKIP), htons(p[2])); 309 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 310 (idx * SF_RXFILT_PERFECT_SKIP) + 4, htons(p[1])); 311 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 312 (idx * SF_RXFILT_PERFECT_SKIP) + 8, htons(p[0])); 313 314 return(0); 315} 316 317/* 318 * Set the bit in the 512-bit hash table that corresponds to the 319 * specified mac address 'mac.' If 'prio' is nonzero, update the 320 * priority hash table instead of the filter hash table. 321 */ 322static int sf_sethash(sc, mac, prio) 323 struct sf_softc *sc; 324 caddr_t mac; 325 int prio; 326{ 327 u_int32_t h = 0; 328 329 if (mac == NULL) 330 return(EINVAL); 331 332 h = sf_calchash(mac); 333 334 if (prio) { 335 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_PRIOOFF + 336 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); 337 } else { 338 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_ADDROFF + 339 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); 340 } 341 342 return(0); 343} 344 345#ifdef notdef 346/* 347 * Set a VLAN tag in the receive filter. 348 */ 349static int sf_setvlan(sc, idx, vlan) 350 struct sf_softc *sc; 351 int idx; 352 u_int32_t vlan; 353{ 354 if (idx < 0 || idx >> SF_RXFILT_HASH_CNT) 355 return(EINVAL); 356 357 csr_write_4(sc, SF_RXFILT_HASH_BASE + 358 (idx * SF_RXFILT_HASH_SKIP) + SF_RXFILT_HASH_VLANOFF, vlan); 359 360 return(0); 361} 362#endif 363 364static int sf_miibus_readreg(dev, phy, reg) 365 device_t dev; 366 int phy, reg; 367{ 368 struct sf_softc *sc; 369 int i; 370 u_int32_t val = 0; 371 372 sc = device_get_softc(dev); 373 374 for (i = 0; i < SF_TIMEOUT; i++) { 375 val = csr_read_4(sc, SF_PHY_REG(phy, reg)); 376 if (val & SF_MII_DATAVALID) 377 break; 378 } 379 380 if (i == SF_TIMEOUT) 381 return(0); 382 383 if ((val & 0x0000FFFF) == 0xFFFF) 384 return(0); 385 386 return(val & 0x0000FFFF); 387} 388 389static int sf_miibus_writereg(dev, phy, reg, val) 390 device_t dev; 391 int phy, reg, val; 392{ 393 struct sf_softc *sc; 394 int i; 395 int busy; 396 397 sc = device_get_softc(dev); 398 399 csr_write_4(sc, SF_PHY_REG(phy, reg), val); 400 401 for (i = 0; i < SF_TIMEOUT; i++) { 402 busy = csr_read_4(sc, SF_PHY_REG(phy, reg)); 403 if (!(busy & SF_MII_BUSY)) 404 break; 405 } 406 407 return(0); 408} 409 410static void sf_miibus_statchg(dev) 411 device_t dev; 412{ 413 struct sf_softc *sc; 414 struct mii_data *mii; 415 416 sc = device_get_softc(dev); 417 mii = device_get_softc(sc->sf_miibus); 418 419 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 420 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 421 } else { 422 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 423 } 424 425 return; 426} 427 428static void sf_setmulti(sc) 429 struct sf_softc *sc; 430{ 431 struct ifnet *ifp; 432 int i; 433 struct ifmultiaddr *ifma; 434 u_int8_t dummy[] = { 0, 0, 0, 0, 0, 0 }; 435 436 ifp = &sc->arpcom.ac_if; 437 438 /* First zot all the existing filters. */ 439 for (i = 1; i < SF_RXFILT_PERFECT_CNT; i++) 440 sf_setperf(sc, i, (char *)&dummy); 441 for (i = SF_RXFILT_HASH_BASE; 442 i < (SF_RXFILT_HASH_MAX + 1); i += 4) 443 csr_write_4(sc, i, 0); 444 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI); 445 446 /* Now program new ones. */ 447 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 448 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI); 449 } else { 450 i = 1; 451 /* First find the tail of the list. */ 452 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 453 ifma = ifma->ifma_link.le_next) { 454 if (ifma->ifma_link.le_next == NULL) 455 break; 456 } 457 /* Now traverse the list backwards. */ 458 for (; ifma != NULL && ifma != (void *)&ifp->if_multiaddrs; 459 ifma = (struct ifmultiaddr *)ifma->ifma_link.le_prev) { 460 if (ifma->ifma_addr->sa_family != AF_LINK) 461 continue; 462 /* 463 * Program the first 15 multicast groups 464 * into the perfect filter. For all others, 465 * use the hash table. 466 */ 467 if (i < SF_RXFILT_PERFECT_CNT) { 468 sf_setperf(sc, i, 469 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 470 i++; 471 continue; 472 } 473 474 sf_sethash(sc, 475 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 0); 476 } 477 } 478 479 return; 480} 481 482/* 483 * Set media options. 484 */ 485static int sf_ifmedia_upd(ifp) 486 struct ifnet *ifp; 487{ 488 struct sf_softc *sc; 489 struct mii_data *mii; 490 491 sc = ifp->if_softc; 492 mii = device_get_softc(sc->sf_miibus); 493 mii_mediachg(mii); 494 495 return(0); 496} 497 498/* 499 * Report current media status. 500 */ 501static void sf_ifmedia_sts(ifp, ifmr) 502 struct ifnet *ifp; 503 struct ifmediareq *ifmr; 504{ 505 struct sf_softc *sc; 506 struct mii_data *mii; 507 508 sc = ifp->if_softc; 509 mii = device_get_softc(sc->sf_miibus); 510 511 mii_pollstat(mii); 512 ifmr->ifm_active = mii->mii_media_active; 513 ifmr->ifm_status = mii->mii_media_status; 514 515 return; 516} 517 518static int sf_ioctl(ifp, command, data) 519 struct ifnet *ifp; 520 u_long command; 521 caddr_t data; 522{ 523 struct sf_softc *sc = ifp->if_softc; 524 struct ifreq *ifr = (struct ifreq *) data; 525 struct mii_data *mii; 526 int s, error = 0; 527 528 s = splimp(); 529 530 switch(command) { 531 case SIOCSIFADDR: 532 case SIOCGIFADDR: 533 case SIOCSIFMTU: 534 error = ether_ioctl(ifp, command, data); 535 break; 536 case SIOCSIFFLAGS: 537 if (ifp->if_flags & IFF_UP) { 538 sf_init(sc); 539 } else { 540 if (ifp->if_flags & IFF_RUNNING) 541 sf_stop(sc); 542 } 543 error = 0; 544 break; 545 case SIOCADDMULTI: 546 case SIOCDELMULTI: 547 sf_setmulti(sc); 548 error = 0; 549 break; 550 case SIOCGIFMEDIA: 551 case SIOCSIFMEDIA: 552 mii = device_get_softc(sc->sf_miibus); 553 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 554 break; 555 default: 556 error = EINVAL; 557 break; 558 } 559 560 (void)splx(s); 561 562 return(error); 563} 564 565static void sf_reset(sc) 566 struct sf_softc *sc; 567{ 568 register int i; 569 570 csr_write_4(sc, SF_GEN_ETH_CTL, 0); 571 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 572 DELAY(1000); 573 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 574 575 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_RESET); 576 577 for (i = 0; i < SF_TIMEOUT; i++) { 578 DELAY(10); 579 if (!(csr_read_4(sc, SF_PCI_DEVCFG) & SF_PCIDEVCFG_RESET)) 580 break; 581 } 582 583 if (i == SF_TIMEOUT) 584 printf("sf%d: reset never completed!\n", sc->sf_unit); 585 586 /* Wait a little while for the chip to get its brains in order. */ 587 DELAY(1000); 588 return; 589} 590 591/* 592 * Probe for an Adaptec AIC-6915 chip. Check the PCI vendor and device 593 * IDs against our list and return a device name if we find a match. 594 * We also check the subsystem ID so that we can identify exactly which 595 * NIC has been found, if possible. 596 */ 597static int sf_probe(dev) 598 device_t dev; 599{ 600 struct sf_type *t; 601 602 t = sf_devs; 603 604 while(t->sf_name != NULL) { 605 if ((pci_get_vendor(dev) == t->sf_vid) && 606 (pci_get_device(dev) == t->sf_did)) { 607 switch((pci_read_config(dev, 608 SF_PCI_SUBVEN_ID, 4) >> 16) & 0xFFFF) { 609 case AD_SUBSYSID_62011_REV0: 610 case AD_SUBSYSID_62011_REV1: 611 device_set_desc(dev, 612 "Adaptec ANA-62011 10/100BaseTX"); 613 return(0); 614 break; 615 case AD_SUBSYSID_62022: 616 device_set_desc(dev, 617 "Adaptec ANA-62022 10/100BaseTX"); 618 return(0); 619 break; 620 case AD_SUBSYSID_62044: 621 device_set_desc(dev, 622 "Adaptec ANA-62044 10/100BaseTX"); 623 return(0); 624 break; 625 case AD_SUBSYSID_62020: 626 device_set_desc(dev, 627 "Adaptec ANA-62020 10/100BaseFX"); 628 return(0); 629 break; 630 case AD_SUBSYSID_69011: 631 device_set_desc(dev, 632 "Adaptec ANA-69011 10/100BaseTX"); 633 return(0); 634 break; 635 default: 636 device_set_desc(dev, t->sf_name); 637 return(0); 638 break; 639 } 640 } 641 t++; 642 } 643 644 return(ENXIO); 645} 646 647/* 648 * Attach the interface. Allocate softc structures, do ifmedia 649 * setup and ethernet/BPF attach. 650 */ 651static int sf_attach(dev) 652 device_t dev; 653{ 654 int s, i; 655 u_int32_t command; 656 struct sf_softc *sc; 657 struct ifnet *ifp; 658 int unit, rid, error = 0; 659 660 s = splimp(); 661 662 sc = device_get_softc(dev); 663 unit = device_get_unit(dev); 664 bzero(sc, sizeof(struct sf_softc)); 665 666 /* 667 * Handle power management nonsense. 668 */ 669 command = pci_read_config(dev, SF_PCI_CAPID, 4) & 0x000000FF; 670 if (command == 0x01) { 671 672 command = pci_read_config(dev, SF_PCI_PWRMGMTCTRL, 4); 673 if (command & SF_PSTATE_MASK) { 674 u_int32_t iobase, membase, irq; 675 676 /* Save important PCI config data. */ 677 iobase = pci_read_config(dev, SF_PCI_LOIO, 4); 678 membase = pci_read_config(dev, SF_PCI_LOMEM, 4); 679 irq = pci_read_config(dev, SF_PCI_INTLINE, 4); 680 681 /* Reset the power state. */ 682 printf("sf%d: chip is in D%d power mode " 683 "-- setting to D0\n", unit, command & SF_PSTATE_MASK); 684 command &= 0xFFFFFFFC; 685 pci_write_config(dev, SF_PCI_PWRMGMTCTRL, command, 4); 686 687 /* Restore PCI config data. */ 688 pci_write_config(dev, SF_PCI_LOIO, iobase, 4); 689 pci_write_config(dev, SF_PCI_LOMEM, membase, 4); 690 pci_write_config(dev, SF_PCI_INTLINE, irq, 4); 691 } 692 } 693 694 /* 695 * Map control/status registers. 696 */ 697 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 698 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 699 pci_write_config(dev, PCI_COMMAND_STATUS_REG, command, 4); 700 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 701 702#ifdef SF_USEIOSPACE 703 if (!(command & PCIM_CMD_PORTEN)) { 704 printf("sf%d: failed to enable I/O ports!\n", unit); 705 error = ENXIO; 706 goto fail; 707 } 708#else 709 if (!(command & PCIM_CMD_MEMEN)) { 710 printf("sf%d: failed to enable memory mapping!\n", unit); 711 error = ENXIO; 712 goto fail; 713 } 714#endif 715 716 rid = SF_RID; 717 sc->sf_res = bus_alloc_resource(dev, SF_RES, &rid, 718 0, ~0, 1, RF_ACTIVE); 719 720 if (sc->sf_res == NULL) { 721 printf ("sf%d: couldn't map ports\n", unit); 722 error = ENXIO; 723 goto fail; 724 } 725 726 sc->sf_btag = rman_get_bustag(sc->sf_res); 727 sc->sf_bhandle = rman_get_bushandle(sc->sf_res); 728 729 /* Allocate interrupt */ 730 rid = 0; 731 sc->sf_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 732 RF_SHAREABLE | RF_ACTIVE); 733 734 if (sc->sf_irq == NULL) { 735 printf("sf%d: couldn't map interrupt\n", unit); 736 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 737 error = ENXIO; 738 goto fail; 739 } 740 741 error = bus_setup_intr(dev, sc->sf_irq, INTR_TYPE_NET, 742 sf_intr, sc, &sc->sf_intrhand); 743 744 if (error) { 745 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_res); 746 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 747 printf("sf%d: couldn't set up irq\n", unit); 748 goto fail; 749 } 750 751 callout_handle_init(&sc->sf_stat_ch); 752 753 /* Reset the adapter. */ 754 sf_reset(sc); 755 756 /* 757 * Get station address from the EEPROM. 758 */ 759 for (i = 0; i < ETHER_ADDR_LEN; i++) 760 sc->arpcom.ac_enaddr[i] = 761 sf_read_eeprom(sc, SF_EE_NODEADDR + ETHER_ADDR_LEN - i); 762 763 /* 764 * An Adaptec chip was detected. Inform the world. 765 */ 766 printf("sf%d: Ethernet address: %6D\n", unit, 767 sc->arpcom.ac_enaddr, ":"); 768 769 sc->sf_unit = unit; 770 771 /* Allocate the descriptor queues. */ 772 sc->sf_ldata = contigmalloc(sizeof(struct sf_list_data), M_DEVBUF, 773 M_NOWAIT, 0x100000, 0xffffffff, PAGE_SIZE, 0); 774 775 if (sc->sf_ldata == NULL) { 776 printf("sf%d: no memory for list buffers!\n", unit); 777 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand); 778 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq); 779 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 780 error = ENXIO; 781 goto fail; 782 } 783 784 bzero(sc->sf_ldata, sizeof(struct sf_list_data)); 785 786 /* Do MII setup. */ 787 if (mii_phy_probe(dev, &sc->sf_miibus, 788 sf_ifmedia_upd, sf_ifmedia_sts)) { 789 printf("sf%d: MII without any phy!\n", sc->sf_unit); 790 free(sc->sf_ldata, M_DEVBUF); 791 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand); 792 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq); 793 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 794 error = ENXIO; 795 goto fail; 796 } 797 798 ifp = &sc->arpcom.ac_if; 799 ifp->if_softc = sc; 800 ifp->if_unit = unit; 801 ifp->if_name = "sf"; 802 ifp->if_mtu = ETHERMTU; 803 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 804 ifp->if_ioctl = sf_ioctl; 805 ifp->if_output = ether_output; 806 ifp->if_start = sf_start; 807 ifp->if_watchdog = sf_watchdog; 808 ifp->if_init = sf_init; 809 ifp->if_baudrate = 10000000; 810 ifp->if_snd.ifq_maxlen = SF_TX_DLIST_CNT - 1; 811 812 /* 813 * Call MI attach routines. 814 */ 815 if_attach(ifp); 816 ether_ifattach(ifp); 817 818#if NBPF > 0 819 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header)); 820#endif 821 822fail: 823 splx(s); 824 return(error); 825} 826 827static int sf_detach(dev) 828 device_t dev; 829{ 830 struct sf_softc *sc; 831 struct ifnet *ifp; 832 int s; 833 834 s = splimp(); 835 836 sc = device_get_softc(dev); 837 ifp = &sc->arpcom.ac_if; 838 839 if_detach(ifp); 840 sf_stop(sc); 841 842 bus_generic_detach(dev); 843 device_delete_child(dev, sc->sf_miibus); 844 845 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand); 846 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq); 847 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 848 849 free(sc->sf_ldata, M_DEVBUF); 850 851 splx(s); 852 853 return(0); 854} 855 856static int sf_init_rx_ring(sc) 857 struct sf_softc *sc; 858{ 859 struct sf_list_data *ld; 860 int i; 861 862 ld = sc->sf_ldata; 863 864 bzero((char *)ld->sf_rx_dlist_big, 865 sizeof(struct sf_rx_bufdesc_type0) * SF_RX_DLIST_CNT); 866 bzero((char *)ld->sf_rx_clist, 867 sizeof(struct sf_rx_cmpdesc_type3) * SF_RX_CLIST_CNT); 868 869 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 870 if (sf_newbuf(sc, &ld->sf_rx_dlist_big[i], NULL) == ENOBUFS) 871 return(ENOBUFS); 872 } 873 874 return(0); 875} 876 877static void sf_init_tx_ring(sc) 878 struct sf_softc *sc; 879{ 880 struct sf_list_data *ld; 881 int i; 882 883 ld = sc->sf_ldata; 884 885 bzero((char *)ld->sf_tx_dlist, 886 sizeof(struct sf_tx_bufdesc_type0) * SF_TX_DLIST_CNT); 887 bzero((char *)ld->sf_tx_clist, 888 sizeof(struct sf_tx_cmpdesc_type0) * SF_TX_CLIST_CNT); 889 890 for (i = 0; i < SF_TX_DLIST_CNT; i++) 891 ld->sf_tx_dlist[i].sf_id = SF_TX_BUFDESC_ID; 892 for (i = 0; i < SF_TX_CLIST_CNT; i++) 893 ld->sf_tx_clist[i].sf_type = SF_TXCMPTYPE_TX; 894 895 ld->sf_tx_dlist[SF_TX_DLIST_CNT - 1].sf_end = 1; 896 sc->sf_tx_cnt = 0; 897 898 return; 899} 900 901static int sf_newbuf(sc, c, m) 902 struct sf_softc *sc; 903 struct sf_rx_bufdesc_type0 *c; 904 struct mbuf *m; 905{ 906 struct mbuf *m_new = NULL; 907 908 if (m == NULL) { 909 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 910 if (m_new == NULL) { 911 printf("sf%d: no memory for rx list -- " 912 "packet dropped!\n", sc->sf_unit); 913 return(ENOBUFS); 914 } 915 916 MCLGET(m_new, M_DONTWAIT); 917 if (!(m_new->m_flags & M_EXT)) { 918 printf("sf%d: no memory for rx list -- " 919 "packet dropped!\n", sc->sf_unit); 920 m_freem(m_new); 921 return(ENOBUFS); 922 } 923 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 924 } else { 925 m_new = m; 926 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 927 m_new->m_data = m_new->m_ext.ext_buf; 928 } 929 930 m_adj(m_new, sizeof(u_int64_t)); 931 932 c->sf_mbuf = m_new; 933 c->sf_addrlo = SF_RX_HOSTADDR(vtophys(mtod(m_new, caddr_t))); 934 c->sf_valid = 1; 935 936 return(0); 937} 938 939/* 940 * The starfire is programmed to use 'normal' mode for packet reception, 941 * which means we use the consumer/producer model for both the buffer 942 * descriptor queue and the completion descriptor queue. The only problem 943 * with this is that it involves a lot of register accesses: we have to 944 * read the RX completion consumer and producer indexes and the RX buffer 945 * producer index, plus the RX completion consumer and RX buffer producer 946 * indexes have to be updated. It would have been easier if Adaptec had 947 * put each index in a separate register, especially given that the damn 948 * NIC has a 512K register space. 949 * 950 * In spite of all the lovely features that Adaptec crammed into the 6915, 951 * it is marred by one truly stupid design flaw, which is that receive 952 * buffer addresses must be aligned on a longword boundary. This forces 953 * the packet payload to be unaligned, which is suboptimal on the x86 and 954 * completely unuseable on the Alpha. Our only recourse is to copy received 955 * packets into properly aligned buffers before handing them off. 956 */ 957 958static void sf_rxeof(sc) 959 struct sf_softc *sc; 960{ 961 struct ether_header *eh; 962 struct mbuf *m; 963 struct ifnet *ifp; 964 struct sf_rx_bufdesc_type0 *desc; 965 struct sf_rx_cmpdesc_type3 *cur_rx; 966 u_int32_t rxcons, rxprod; 967 int cmpprodidx, cmpconsidx, bufprodidx; 968 969 ifp = &sc->arpcom.ac_if; 970 971 rxcons = csr_read_4(sc, SF_CQ_CONSIDX); 972 rxprod = csr_read_4(sc, SF_RXDQ_PTR_Q1); 973 cmpprodidx = SF_IDX_LO(csr_read_4(sc, SF_CQ_PRODIDX)); 974 cmpconsidx = SF_IDX_LO(rxcons); 975 bufprodidx = SF_IDX_LO(rxprod); 976 977 while (cmpconsidx != cmpprodidx) { 978 struct mbuf *m0; 979 980 cur_rx = &sc->sf_ldata->sf_rx_clist[cmpconsidx]; 981 desc = &sc->sf_ldata->sf_rx_dlist_big[cur_rx->sf_endidx]; 982 m = desc->sf_mbuf; 983 SF_INC(cmpconsidx, SF_RX_CLIST_CNT); 984 SF_INC(bufprodidx, SF_RX_DLIST_CNT); 985 986 if (!(cur_rx->sf_status1 & SF_RXSTAT1_OK)) { 987 ifp->if_ierrors++; 988 sf_newbuf(sc, desc, m); 989 continue; 990 } 991 992 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 993 cur_rx->sf_len + ETHER_ALIGN, 0, ifp, NULL); 994 sf_newbuf(sc, desc, m); 995 if (m0 == NULL) { 996 ifp->if_ierrors++; 997 continue; 998 } 999 m_adj(m0, ETHER_ALIGN); 1000 m = m0; 1001 1002 eh = mtod(m, struct ether_header *); 1003 ifp->if_ipackets++; 1004 1005#if NBPF > 0 1006 if (ifp->if_bpf) { 1007 bpf_mtap(ifp, m); 1008 if (ifp->if_flags & IFF_PROMISC && 1009 (bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr, 1010 ETHER_ADDR_LEN) && !(eh->ether_dhost[0] & 1))) { 1011 m_freem(m); 1012 continue; 1013 } 1014 } 1015#endif 1016 1017 /* Remove header from mbuf and pass it on. */ 1018 m_adj(m, sizeof(struct ether_header)); 1019 ether_input(ifp, eh, m); 1020 1021 } 1022 1023 csr_write_4(sc, SF_CQ_CONSIDX, 1024 (rxcons & ~SF_CQ_CONSIDX_RXQ1) | cmpconsidx); 1025 csr_write_4(sc, SF_RXDQ_PTR_Q1, 1026 (rxprod & ~SF_RXDQ_PRODIDX) | bufprodidx); 1027 1028 return; 1029} 1030 1031/* 1032 * Read the transmit status from the completion queue and release 1033 * mbufs. Note that the buffer descriptor index in the completion 1034 * descriptor is an offset from the start of the transmit buffer 1035 * descriptor list in bytes. This is important because the manual 1036 * gives the impression that it should match the producer/consumer 1037 * index, which is the offset in 8 byte blocks. 1038 */ 1039static void sf_txeof(sc) 1040 struct sf_softc *sc; 1041{ 1042 int txcons, cmpprodidx, cmpconsidx; 1043 struct sf_tx_cmpdesc_type1 *cur_cmp; 1044 struct sf_tx_bufdesc_type0 *cur_tx; 1045 struct ifnet *ifp; 1046 1047 ifp = &sc->arpcom.ac_if; 1048 1049 txcons = csr_read_4(sc, SF_CQ_CONSIDX); 1050 cmpprodidx = SF_IDX_HI(csr_read_4(sc, SF_CQ_PRODIDX)); 1051 cmpconsidx = SF_IDX_HI(txcons); 1052 1053 while (cmpconsidx != cmpprodidx) { 1054 cur_cmp = &sc->sf_ldata->sf_tx_clist[cmpconsidx]; 1055 cur_tx = &sc->sf_ldata->sf_tx_dlist[cur_cmp->sf_index >> 7]; 1056 SF_INC(cmpconsidx, SF_TX_CLIST_CNT); 1057 1058 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_OK) 1059 ifp->if_opackets++; 1060 else 1061 ifp->if_oerrors++; 1062 1063 sc->sf_tx_cnt--; 1064 if (cur_tx->sf_mbuf != NULL) { 1065 m_freem(cur_tx->sf_mbuf); 1066 cur_tx->sf_mbuf = NULL; 1067 } 1068 } 1069 1070 ifp->if_timer = 0; 1071 ifp->if_flags &= ~IFF_OACTIVE; 1072 1073 csr_write_4(sc, SF_CQ_CONSIDX, 1074 (txcons & ~SF_CQ_CONSIDX_TXQ) | 1075 ((cmpconsidx << 16) & 0xFFFF0000)); 1076 1077 return; 1078} 1079 1080static void sf_intr(arg) 1081 void *arg; 1082{ 1083 struct sf_softc *sc; 1084 struct ifnet *ifp; 1085 u_int32_t status; 1086 1087 sc = arg; 1088 ifp = &sc->arpcom.ac_if; 1089 1090 if (!(csr_read_4(sc, SF_ISR_SHADOW) & SF_ISR_PCIINT_ASSERTED)) 1091 return; 1092 1093 /* Disable interrupts. */ 1094 csr_write_4(sc, SF_IMR, 0x00000000); 1095 1096 for (;;) { 1097 status = csr_read_4(sc, SF_ISR); 1098 if (status) 1099 csr_write_4(sc, SF_ISR, status); 1100 1101 if (!(status & SF_INTRS)) 1102 break; 1103 1104 if (status & SF_ISR_RXDQ1_DMADONE) 1105 sf_rxeof(sc); 1106 1107 if (status & SF_ISR_TX_TXDONE) 1108 sf_txeof(sc); 1109 1110 if (status & SF_ISR_ABNORMALINTR) { 1111 if (status & SF_ISR_STATSOFLOW) { 1112 untimeout(sf_stats_update, sc, 1113 sc->sf_stat_ch); 1114 sf_stats_update(sc); 1115 } else 1116 sf_init(sc); 1117 } 1118 } 1119 1120 /* Re-enable interrupts. */ 1121 csr_write_4(sc, SF_IMR, SF_INTRS); 1122 1123 if (ifp->if_snd.ifq_head != NULL) 1124 sf_start(ifp); 1125 1126 return; 1127} 1128 1129static void sf_init(xsc) 1130 void *xsc; 1131{ 1132 struct sf_softc *sc; 1133 struct ifnet *ifp; 1134 struct mii_data *mii; 1135 int i, s; 1136 1137 s = splimp(); 1138 1139 sc = xsc; 1140 ifp = &sc->arpcom.ac_if; 1141 mii = device_get_softc(sc->sf_miibus); 1142 1143 sf_stop(sc); 1144 sf_reset(sc); 1145 1146 /* Init all the receive filter registers */ 1147 for (i = SF_RXFILT_PERFECT_BASE; 1148 i < (SF_RXFILT_HASH_MAX + 1); i += 4) 1149 csr_write_4(sc, i, 0); 1150 1151 /* Empty stats counter registers. */ 1152 for (i = 0; i < sizeof(struct sf_stats)/sizeof(u_int32_t); i++) 1153 csr_write_4(sc, SF_STATS_BASE + 1154 (i + sizeof(u_int32_t)), 0); 1155 1156 /* Init our MAC address */ 1157 csr_write_4(sc, SF_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1158 csr_write_4(sc, SF_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1159 sf_setperf(sc, 0, (caddr_t)&sc->arpcom.ac_enaddr); 1160 1161 if (sf_init_rx_ring(sc) == ENOBUFS) { 1162 printf("sf%d: initialization failed: no " 1163 "memory for rx buffers\n", sc->sf_unit); 1164 (void)splx(s); 1165 return; 1166 } 1167 1168 sf_init_tx_ring(sc); 1169 1170 csr_write_4(sc, SF_RXFILT, SF_PERFMODE_NORMAL|SF_HASHMODE_WITHVLAN); 1171 1172 /* If we want promiscuous mode, set the allframes bit. */ 1173 if (ifp->if_flags & IFF_PROMISC) { 1174 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 1175 } else { 1176 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 1177 } 1178 1179 if (ifp->if_flags & IFF_BROADCAST) { 1180 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_BROAD); 1181 } else { 1182 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_BROAD); 1183 } 1184 1185 /* Init the completion queue indexes */ 1186 csr_write_4(sc, SF_CQ_CONSIDX, 0); 1187 csr_write_4(sc, SF_CQ_PRODIDX, 0); 1188 1189 /* Init the RX completion queue */ 1190 csr_write_4(sc, SF_RXCQ_CTL_1, 1191 vtophys(sc->sf_ldata->sf_rx_clist) & SF_RXCQ_ADDR); 1192 SF_SETBIT(sc, SF_RXCQ_CTL_1, SF_RXCQTYPE_3); 1193 1194 /* Init RX DMA control. */ 1195 SF_SETBIT(sc, SF_RXDMA_CTL, SF_RXDMA_REPORTBADPKTS); 1196 1197 /* Init the RX buffer descriptor queue. */ 1198 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 1199 vtophys(sc->sf_ldata->sf_rx_dlist_big)); 1200 csr_write_4(sc, SF_RXDQ_CTL_1, (MCLBYTES << 16) | SF_DESCSPACE_16BYTES); 1201 csr_write_4(sc, SF_RXDQ_PTR_Q1, SF_RX_DLIST_CNT - 1); 1202 1203 /* Init the TX completion queue */ 1204 csr_write_4(sc, SF_TXCQ_CTL, 1205 vtophys(sc->sf_ldata->sf_tx_clist) & SF_RXCQ_ADDR); 1206 1207 /* Init the TX buffer descriptor queue. */ 1208 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 1209 vtophys(sc->sf_ldata->sf_tx_dlist)); 1210 SF_SETBIT(sc, SF_TX_FRAMCTL, SF_TXFRMCTL_CPLAFTERTX); 1211 csr_write_4(sc, SF_TXDQ_CTL, 1212 SF_TXBUFDESC_TYPE0|SF_TXMINSPACE_128BYTES|SF_TXSKIPLEN_8BYTES); 1213 SF_SETBIT(sc, SF_TXDQ_CTL, SF_TXDQCTL_NODMACMP); 1214 1215 /* Enable autopadding of short TX frames. */ 1216 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_AUTOPAD); 1217 1218 /* Make sure the duplex mode is set correctly. */ 1219 if ((mii->mii_media.ifm_media & IFM_GMASK) == IFM_FDX) { 1220 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 1221 } else { 1222 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 1223 } 1224 1225 /* Enable interrupts. */ 1226 csr_write_4(sc, SF_IMR, SF_INTRS); 1227 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_INTR_ENB); 1228 1229 /* Enable the RX and TX engines. */ 1230 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_RX_ENB|SF_ETHCTL_RXDMA_ENB); 1231 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_TX_ENB|SF_ETHCTL_TXDMA_ENB); 1232 1233 mii_mediachg(mii); 1234 1235 ifp->if_flags |= IFF_RUNNING; 1236 ifp->if_flags &= ~IFF_OACTIVE; 1237 1238 sc->sf_stat_ch = timeout(sf_stats_update, sc, hz); 1239 1240 splx(s); 1241 1242 return; 1243} 1244 1245static int sf_encap(sc, c, m_head) 1246 struct sf_softc *sc; 1247 struct sf_tx_bufdesc_type0 *c; 1248 struct mbuf *m_head; 1249{ 1250 int frag = 0; 1251 struct sf_frag *f = NULL; 1252 struct mbuf *m; 1253 1254 m = m_head; 1255 1256 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1257 if (m->m_len != 0) { 1258 if (frag == SF_MAXFRAGS) 1259 break; 1260 f = &c->sf_frags[frag]; 1261 if (frag == 0) 1262 f->sf_pktlen = m_head->m_pkthdr.len; 1263 f->sf_fraglen = m->m_len; 1264 f->sf_addr = vtophys(mtod(m, vm_offset_t)); 1265 frag++; 1266 } 1267 } 1268 1269 if (m != NULL) { 1270 struct mbuf *m_new = NULL; 1271 1272 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1273 if (m_new == NULL) { 1274 printf("sf%d: no memory for tx list", sc->sf_unit); 1275 return(1); 1276 } 1277 1278 if (m_head->m_pkthdr.len > MHLEN) { 1279 MCLGET(m_new, M_DONTWAIT); 1280 if (!(m_new->m_flags & M_EXT)) { 1281 m_freem(m_new); 1282 printf("sf%d: no memory for tx list", 1283 sc->sf_unit); 1284 return(1); 1285 } 1286 } 1287 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1288 mtod(m_new, caddr_t)); 1289 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1290 m_freem(m_head); 1291 m_head = m_new; 1292 f = &c->sf_frags[0]; 1293 f->sf_fraglen = f->sf_pktlen = m_head->m_pkthdr.len; 1294 f->sf_addr = vtophys(mtod(m_head, caddr_t)); 1295 frag = 1; 1296 } 1297 1298 c->sf_mbuf = m_head; 1299 c->sf_id = SF_TX_BUFDESC_ID; 1300 c->sf_fragcnt = frag; 1301 c->sf_intr = 1; 1302 c->sf_caltcp = 0; 1303 c->sf_crcen = 1; 1304 1305 return(0); 1306} 1307 1308static void sf_start(ifp) 1309 struct ifnet *ifp; 1310{ 1311 struct sf_softc *sc; 1312 struct sf_tx_bufdesc_type0 *cur_tx = NULL; 1313 struct mbuf *m_head = NULL; 1314 int i, txprod; 1315 1316 sc = ifp->if_softc; 1317 1318 if (ifp->if_flags & IFF_OACTIVE) 1319 return; 1320 1321 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX); 1322 i = SF_IDX_HI(txprod) >> 4; 1323 1324 while(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf == NULL) { 1325 IF_DEQUEUE(&ifp->if_snd, m_head); 1326 if (m_head == NULL) 1327 break; 1328 1329 cur_tx = &sc->sf_ldata->sf_tx_dlist[i]; 1330 sf_encap(sc, cur_tx, m_head); 1331 1332 /* 1333 * If there's a BPF listener, bounce a copy of this frame 1334 * to him. 1335 */ 1336#if NBPF > 0 1337 if (ifp->if_bpf) 1338 bpf_mtap(ifp, m_head); 1339#endif 1340 SF_INC(i, SF_TX_DLIST_CNT); 1341 sc->sf_tx_cnt++; 1342 if (sc->sf_tx_cnt == (SF_TX_DLIST_CNT - 2)) 1343 break; 1344 } 1345 1346 if (cur_tx == NULL) 1347 return; 1348 1349 /* Transmit */ 1350 csr_write_4(sc, SF_TXDQ_PRODIDX, 1351 (txprod & ~SF_TXDQ_PRODIDX_HIPRIO) | 1352 ((i << 20) & 0xFFFF0000)); 1353 1354 ifp->if_timer = 5; 1355 1356 return; 1357} 1358 1359static void sf_stop(sc) 1360 struct sf_softc *sc; 1361{ 1362 int i; 1363 struct ifnet *ifp; 1364 1365 ifp = &sc->arpcom.ac_if; 1366 1367 untimeout(sf_stats_update, sc, sc->sf_stat_ch); 1368 1369 csr_write_4(sc, SF_GEN_ETH_CTL, 0); 1370 csr_write_4(sc, SF_CQ_CONSIDX, 0); 1371 csr_write_4(sc, SF_CQ_PRODIDX, 0); 1372 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 0); 1373 csr_write_4(sc, SF_RXDQ_CTL_1, 0); 1374 csr_write_4(sc, SF_RXDQ_PTR_Q1, 0); 1375 csr_write_4(sc, SF_TXCQ_CTL, 0); 1376 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 0); 1377 csr_write_4(sc, SF_TXDQ_CTL, 0); 1378 sf_reset(sc); 1379 1380 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 1381 if (sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf != NULL) { 1382 m_freem(sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf); 1383 sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf = NULL; 1384 } 1385 } 1386 1387 for (i = 0; i < SF_TX_DLIST_CNT; i++) { 1388 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) { 1389 m_freem(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf); 1390 sc->sf_ldata->sf_tx_dlist[i].sf_mbuf = NULL; 1391 } 1392 } 1393 1394 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 1395 1396 return; 1397} 1398 1399/* 1400 * Note: it is important that this function not be interrupted. We 1401 * use a two-stage register access scheme: if we are interrupted in 1402 * between setting the indirect address register and reading from the 1403 * indirect data register, the contents of the address register could 1404 * be changed out from under us. 1405 */ 1406static void sf_stats_update(xsc) 1407 void *xsc; 1408{ 1409 struct sf_softc *sc; 1410 struct ifnet *ifp; 1411 struct mii_data *mii; 1412 struct sf_stats stats; 1413 u_int32_t *ptr; 1414 int i, s; 1415 1416 s = splimp(); 1417 1418 sc = xsc; 1419 ifp = &sc->arpcom.ac_if; 1420 mii = device_get_softc(sc->sf_miibus); 1421 1422 ptr = (u_int32_t *)&stats; 1423 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++) 1424 ptr[i] = csr_read_4(sc, SF_STATS_BASE + 1425 (i + sizeof(u_int32_t))); 1426 1427 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++) 1428 csr_write_4(sc, SF_STATS_BASE + 1429 (i + sizeof(u_int32_t)), 0); 1430 1431 ifp->if_collisions += stats.sf_tx_single_colls + 1432 stats.sf_tx_multi_colls + stats.sf_tx_excess_colls; 1433 1434 mii_tick(mii); 1435 1436 sc->sf_stat_ch = timeout(sf_stats_update, sc, hz); 1437 1438 splx(s); 1439 1440 return; 1441} 1442 1443static void sf_watchdog(ifp) 1444 struct ifnet *ifp; 1445{ 1446 struct sf_softc *sc; 1447 1448 sc = ifp->if_softc; 1449 1450 ifp->if_oerrors++; 1451 printf("sf%d: watchdog timeout\n", sc->sf_unit); 1452 1453 sf_stop(sc); 1454 sf_reset(sc); 1455 sf_init(sc); 1456 1457 if (ifp->if_snd.ifq_head != NULL) 1458 sf_start(ifp); 1459 1460 return; 1461} 1462 1463static void sf_shutdown(dev) 1464 device_t dev; 1465{ 1466 struct sf_softc *sc; 1467 1468 sc = device_get_softc(dev); 1469 1470 sf_stop(sc); 1471 1472 return; 1473} 1474