if_sf.c revision 50675
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/dev/sf/if_sf.c 50675 1999-08-30 23:08:32Z wpaul $ 33 */ 34 35/* 36 * Adaptec AIC-6915 "Starfire" PCI fast ethernet driver for FreeBSD. 37 * Programming manual is available from www.adaptec.com. 38 * 39 * Written by Bill Paul <wpaul@ctr.columbia.edu> 40 * Department of Electical Engineering 41 * Columbia University, New York City 42 */ 43 44/* 45 * The Adaptec AIC-6915 "Starfire" is a 64-bit 10/100 PCI ethernet 46 * controller designed with flexibility and reducing CPU load in mind. 47 * The Starfire offers high and low priority buffer queues, a 48 * producer/consumer index mechanism and several different buffer 49 * queue and completion queue descriptor types. Any one of a number 50 * of different driver designs can be used, depending on system and 51 * OS requirements. This driver makes use of type0 transmit frame 52 * descriptors (since BSD fragments packets across an mbuf chain) 53 * and two RX buffer queues prioritized on size (one queue for small 54 * frames that will fit into a single mbuf, another with full size 55 * mbuf clusters for everything else). The producer/consumer indexes 56 * and completion queues are also used. 57 * 58 * One downside to the Starfire has to do with alignment: buffer 59 * queues must be aligned on 256-byte boundaries, and receive buffers 60 * must be aligned on longword boundaries. The receive buffer alignment 61 * causes problems on the Alpha platform, where the packet payload 62 * should be longword aligned. There is no simple way around this. 63 * 64 * For receive filtering, the Starfire offers 16 perfect filter slots 65 * and a 512-bit hash table. 66 * 67 * The Starfire has no internal transceiver, relying instead on an 68 * external MII-based transceiver. Accessing registers on external 69 * PHYs is done through a special register map rather than with the 70 * usual bitbang MDIO method. 71 * 72 * Acesssing the registers on the Starfire is a little tricky. The 73 * Starfire has a 512K internal register space. When programmed for 74 * PCI memory mapped mode, the entire register space can be accessed 75 * directly. However in I/O space mode, only 256 bytes are directly 76 * mapped into PCI I/O space. The other registers can be accessed 77 * indirectly using the SF_INDIRECTIO_ADDR and SF_INDIRECTIO_DATA 78 * registers inside the 256-byte I/O window. 79 */ 80 81#include "bpf.h" 82 83#include <sys/param.h> 84#include <sys/systm.h> 85#include <sys/sockio.h> 86#include <sys/mbuf.h> 87#include <sys/malloc.h> 88#include <sys/kernel.h> 89#include <sys/socket.h> 90 91#include <net/if.h> 92#include <net/if_arp.h> 93#include <net/ethernet.h> 94#include <net/if_dl.h> 95#include <net/if_media.h> 96 97#if NBPF > 0 98#include <net/bpf.h> 99#endif 100 101#include <vm/vm.h> /* for vtophys */ 102#include <vm/pmap.h> /* for vtophys */ 103#include <machine/clock.h> /* for DELAY */ 104#include <machine/bus_pio.h> 105#include <machine/bus_memio.h> 106#include <machine/bus.h> 107#include <machine/resource.h> 108#include <sys/bus.h> 109#include <sys/rman.h> 110 111#include <dev/mii/mii.h> 112#include <dev/mii/miivar.h> 113 114#include "miibus_if.h" 115 116#include <pci/pcireg.h> 117#include <pci/pcivar.h> 118 119#define SF_USEIOSPACE 120 121#include <pci/if_sfreg.h> 122 123#ifndef lint 124static const char rcsid[] = 125 "$FreeBSD: head/sys/dev/sf/if_sf.c 50675 1999-08-30 23:08:32Z wpaul $"; 126#endif 127 128static struct sf_type sf_devs[] = { 129 { AD_VENDORID, AD_DEVICEID_STARFIRE, 130 "Adaptec AIC-6915 10/100BaseTX" }, 131 { 0, 0, NULL } 132}; 133 134static int sf_probe __P((device_t)); 135static int sf_attach __P((device_t)); 136static int sf_detach __P((device_t)); 137static void sf_intr __P((void *)); 138static void sf_stats_update __P((void *)); 139static void sf_rxeof __P((struct sf_softc *)); 140static void sf_txeof __P((struct sf_softc *)); 141static int sf_encap __P((struct sf_softc *, 142 struct sf_tx_bufdesc_type0 *, 143 struct mbuf *)); 144static void sf_start __P((struct ifnet *)); 145static int sf_ioctl __P((struct ifnet *, u_long, caddr_t)); 146static void sf_init __P((void *)); 147static void sf_stop __P((struct sf_softc *)); 148static void sf_watchdog __P((struct ifnet *)); 149static void sf_shutdown __P((device_t)); 150static int sf_ifmedia_upd __P((struct ifnet *)); 151static void sf_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 152static void sf_reset __P((struct sf_softc *)); 153static int sf_init_rx_ring __P((struct sf_softc *)); 154static void sf_init_tx_ring __P((struct sf_softc *)); 155static int sf_newbuf __P((struct sf_softc *, 156 struct sf_rx_bufdesc_type0 *, 157 struct mbuf *)); 158static void sf_setmulti __P((struct sf_softc *)); 159static int sf_setperf __P((struct sf_softc *, int, caddr_t)); 160static int sf_sethash __P((struct sf_softc *, caddr_t, int)); 161#ifdef notdef 162static int sf_setvlan __P((struct sf_softc *, int, u_int32_t)); 163#endif 164 165static u_int8_t sf_read_eeprom __P((struct sf_softc *, int)); 166static u_int32_t sf_calchash __P((caddr_t)); 167 168static int sf_miibus_readreg __P((device_t, int, int)); 169static int sf_miibus_writereg __P((device_t, int, int, int)); 170static void sf_miibus_statchg __P((device_t)); 171 172static u_int32_t csr_read_4 __P((struct sf_softc *, int)); 173static void csr_write_4 __P((struct sf_softc *, int, u_int32_t)); 174 175#ifdef SF_USEIOSPACE 176#define SF_RES SYS_RES_IOPORT 177#define SF_RID SF_PCI_LOIO 178#else 179#define SF_RES SYS_RES_MEMORY 180#define SF_RID SF_PCI_LOMEM 181#endif 182 183static device_method_t sf_methods[] = { 184 /* Device interface */ 185 DEVMETHOD(device_probe, sf_probe), 186 DEVMETHOD(device_attach, sf_attach), 187 DEVMETHOD(device_detach, sf_detach), 188 DEVMETHOD(device_shutdown, sf_shutdown), 189 190 /* bus interface */ 191 DEVMETHOD(bus_print_child, bus_generic_print_child), 192 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 193 194 /* MII interface */ 195 DEVMETHOD(miibus_readreg, sf_miibus_readreg), 196 DEVMETHOD(miibus_writereg, sf_miibus_writereg), 197 DEVMETHOD(miibus_statchg, sf_miibus_statchg), 198 199 { 0, 0 } 200}; 201 202static driver_t sf_driver = { 203 "sf", 204 sf_methods, 205 sizeof(struct sf_softc), 206}; 207 208static devclass_t sf_devclass; 209 210DRIVER_MODULE(sf, pci, sf_driver, sf_devclass, 0, 0); 211DRIVER_MODULE(miibus, sf, miibus_driver, miibus_devclass, 0, 0); 212 213#define SF_SETBIT(sc, reg, x) \ 214 csr_write_4(sc, reg, csr_read_4(sc, reg) | x) 215 216#define SF_CLRBIT(sc, reg, x) \ 217 csr_write_4(sc, reg, csr_read_4(sc, reg) & ~x) 218 219static u_int32_t csr_read_4(sc, reg) 220 struct sf_softc *sc; 221 int reg; 222{ 223 u_int32_t val; 224 225#ifdef SF_USEIOSPACE 226 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); 227 val = CSR_READ_4(sc, SF_INDIRECTIO_DATA); 228#else 229 val = CSR_READ_4(sc, (reg + SF_RMAP_INTREG_BASE)); 230#endif 231 232 return(val); 233} 234 235static u_int8_t sf_read_eeprom(sc, reg) 236 struct sf_softc *sc; 237 int reg; 238{ 239 u_int8_t val; 240 241 val = (csr_read_4(sc, SF_EEADDR_BASE + 242 (reg & 0xFFFFFFFC)) >> (8 * (reg & 3))) & 0xFF; 243 244 return(val); 245} 246 247static void csr_write_4(sc, reg, val) 248 struct sf_softc *sc; 249 int reg; 250 u_int32_t val; 251{ 252#ifdef SF_USEIOSPACE 253 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); 254 CSR_WRITE_4(sc, SF_INDIRECTIO_DATA, val); 255#else 256 CSR_WRITE_4(sc, (reg + SF_RMAP_INTREG_BASE), val); 257#endif 258 return; 259} 260 261static u_int32_t sf_calchash(addr) 262 caddr_t addr; 263{ 264 u_int32_t crc, carry; 265 int i, j; 266 u_int8_t c; 267 268 /* Compute CRC for the address value. */ 269 crc = 0xFFFFFFFF; /* initial value */ 270 271 for (i = 0; i < 6; i++) { 272 c = *(addr + i); 273 for (j = 0; j < 8; j++) { 274 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 275 crc <<= 1; 276 c >>= 1; 277 if (carry) 278 crc = (crc ^ 0x04c11db6) | carry; 279 } 280 } 281 282 /* return the filter bit position */ 283 return(crc >> 23 & 0x1FF); 284} 285 286/* 287 * Copy the address 'mac' into the perfect RX filter entry at 288 * offset 'idx.' The perfect filter only has 16 entries so do 289 * some sanity tests. 290 */ 291static int sf_setperf(sc, idx, mac) 292 struct sf_softc *sc; 293 int idx; 294 caddr_t mac; 295{ 296 u_int16_t *p; 297 298 if (idx < 0 || idx > SF_RXFILT_PERFECT_CNT) 299 return(EINVAL); 300 301 if (mac == NULL) 302 return(EINVAL); 303 304 p = (u_int16_t *)mac; 305 306 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 307 (idx * SF_RXFILT_PERFECT_SKIP), htons(p[2])); 308 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 309 (idx * SF_RXFILT_PERFECT_SKIP) + 4, htons(p[1])); 310 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 311 (idx * SF_RXFILT_PERFECT_SKIP) + 8, htons(p[0])); 312 313 return(0); 314} 315 316/* 317 * Set the bit in the 512-bit hash table that corresponds to the 318 * specified mac address 'mac.' If 'prio' is nonzero, update the 319 * priority hash table instead of the filter hash table. 320 */ 321static int sf_sethash(sc, mac, prio) 322 struct sf_softc *sc; 323 caddr_t mac; 324 int prio; 325{ 326 u_int32_t h = 0; 327 328 if (mac == NULL) 329 return(EINVAL); 330 331 h = sf_calchash(mac); 332 333 if (prio) { 334 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_PRIOOFF + 335 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); 336 } else { 337 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_ADDROFF + 338 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); 339 } 340 341 return(0); 342} 343 344#ifdef notdef 345/* 346 * Set a VLAN tag in the receive filter. 347 */ 348static int sf_setvlan(sc, idx, vlan) 349 struct sf_softc *sc; 350 int idx; 351 u_int32_t vlan; 352{ 353 if (idx < 0 || idx >> SF_RXFILT_HASH_CNT) 354 return(EINVAL); 355 356 csr_write_4(sc, SF_RXFILT_HASH_BASE + 357 (idx * SF_RXFILT_HASH_SKIP) + SF_RXFILT_HASH_VLANOFF, vlan); 358 359 return(0); 360} 361#endif 362 363static int sf_miibus_readreg(dev, phy, reg) 364 device_t dev; 365 int phy, reg; 366{ 367 struct sf_softc *sc; 368 int i; 369 u_int32_t val = 0; 370 371 sc = device_get_softc(dev); 372 373 for (i = 0; i < SF_TIMEOUT; i++) { 374 val = csr_read_4(sc, SF_PHY_REG(phy, reg)); 375 if (val & SF_MII_DATAVALID) 376 break; 377 } 378 379 if (i == SF_TIMEOUT) 380 return(0); 381 382 if ((val & 0x0000FFFF) == 0xFFFF) 383 return(0); 384 385 return(val & 0x0000FFFF); 386} 387 388static int sf_miibus_writereg(dev, phy, reg, val) 389 device_t dev; 390 int phy, reg, val; 391{ 392 struct sf_softc *sc; 393 int i; 394 int busy; 395 396 sc = device_get_softc(dev); 397 398 csr_write_4(sc, SF_PHY_REG(phy, reg), val); 399 400 for (i = 0; i < SF_TIMEOUT; i++) { 401 busy = csr_read_4(sc, SF_PHY_REG(phy, reg)); 402 if (!(busy & SF_MII_BUSY)) 403 break; 404 } 405 406 return(0); 407} 408 409static void sf_miibus_statchg(dev) 410 device_t dev; 411{ 412 struct sf_softc *sc; 413 struct mii_data *mii; 414 415 sc = device_get_softc(dev); 416 mii = device_get_softc(sc->sf_miibus); 417 418 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 419 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 420 } else { 421 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 422 } 423 424 return; 425} 426 427static void sf_setmulti(sc) 428 struct sf_softc *sc; 429{ 430 struct ifnet *ifp; 431 int i; 432 struct ifmultiaddr *ifma; 433 u_int8_t dummy[] = { 0, 0, 0, 0, 0, 0 }; 434 435 ifp = &sc->arpcom.ac_if; 436 437 /* First zot all the existing filters. */ 438 for (i = 1; i < SF_RXFILT_PERFECT_CNT; i++) 439 sf_setperf(sc, i, (char *)&dummy); 440 for (i = SF_RXFILT_HASH_BASE; 441 i < (SF_RXFILT_HASH_MAX + 1); i += 4) 442 csr_write_4(sc, i, 0); 443 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI); 444 445 /* Now program new ones. */ 446 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 447 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI); 448 } else { 449 i = 1; 450 /* First find the tail of the list. */ 451 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 452 ifma = ifma->ifma_link.le_next) { 453 if (ifma->ifma_link.le_next == NULL) 454 break; 455 } 456 /* Now traverse the list backwards. */ 457 for (; ifma != NULL && ifma != (void *)&ifp->if_multiaddrs; 458 ifma = (struct ifmultiaddr *)ifma->ifma_link.le_prev) { 459 if (ifma->ifma_addr->sa_family != AF_LINK) 460 continue; 461 /* 462 * Program the first 15 multicast groups 463 * into the perfect filter. For all others, 464 * use the hash table. 465 */ 466 if (i < SF_RXFILT_PERFECT_CNT) { 467 sf_setperf(sc, i, 468 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 469 i++; 470 continue; 471 } 472 473 sf_sethash(sc, 474 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 0); 475 } 476 } 477 478 return; 479} 480 481/* 482 * Set media options. 483 */ 484static int sf_ifmedia_upd(ifp) 485 struct ifnet *ifp; 486{ 487 struct sf_softc *sc; 488 struct mii_data *mii; 489 490 sc = ifp->if_softc; 491 mii = device_get_softc(sc->sf_miibus); 492 mii_mediachg(mii); 493 494 return(0); 495} 496 497/* 498 * Report current media status. 499 */ 500static void sf_ifmedia_sts(ifp, ifmr) 501 struct ifnet *ifp; 502 struct ifmediareq *ifmr; 503{ 504 struct sf_softc *sc; 505 struct mii_data *mii; 506 507 sc = ifp->if_softc; 508 mii = device_get_softc(sc->sf_miibus); 509 510 mii_pollstat(mii); 511 ifmr->ifm_active = mii->mii_media_active; 512 ifmr->ifm_status = mii->mii_media_status; 513 514 return; 515} 516 517static int sf_ioctl(ifp, command, data) 518 struct ifnet *ifp; 519 u_long command; 520 caddr_t data; 521{ 522 struct sf_softc *sc = ifp->if_softc; 523 struct ifreq *ifr = (struct ifreq *) data; 524 struct mii_data *mii; 525 int s, error = 0; 526 527 s = splimp(); 528 529 switch(command) { 530 case SIOCSIFADDR: 531 case SIOCGIFADDR: 532 case SIOCSIFMTU: 533 error = ether_ioctl(ifp, command, data); 534 break; 535 case SIOCSIFFLAGS: 536 if (ifp->if_flags & IFF_UP) { 537 sf_init(sc); 538 } else { 539 if (ifp->if_flags & IFF_RUNNING) 540 sf_stop(sc); 541 } 542 error = 0; 543 break; 544 case SIOCADDMULTI: 545 case SIOCDELMULTI: 546 sf_setmulti(sc); 547 error = 0; 548 break; 549 case SIOCGIFMEDIA: 550 case SIOCSIFMEDIA: 551 mii = device_get_softc(sc->sf_miibus); 552 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 553 break; 554 default: 555 error = EINVAL; 556 break; 557 } 558 559 (void)splx(s); 560 561 return(error); 562} 563 564static void sf_reset(sc) 565 struct sf_softc *sc; 566{ 567 register int i; 568 569 csr_write_4(sc, SF_GEN_ETH_CTL, 0); 570 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 571 DELAY(1000); 572 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 573 574 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_RESET); 575 576 for (i = 0; i < SF_TIMEOUT; i++) { 577 DELAY(10); 578 if (!(csr_read_4(sc, SF_PCI_DEVCFG) & SF_PCIDEVCFG_RESET)) 579 break; 580 } 581 582 if (i == SF_TIMEOUT) 583 printf("sf%d: reset never completed!\n", sc->sf_unit); 584 585 /* Wait a little while for the chip to get its brains in order. */ 586 DELAY(1000); 587 return; 588} 589 590/* 591 * Probe for an Adaptec AIC-6915 chip. Check the PCI vendor and device 592 * IDs against our list and return a device name if we find a match. 593 * We also check the subsystem ID so that we can identify exactly which 594 * NIC has been found, if possible. 595 */ 596static int sf_probe(dev) 597 device_t dev; 598{ 599 struct sf_type *t; 600 601 t = sf_devs; 602 603 while(t->sf_name != NULL) { 604 if ((pci_get_vendor(dev) == t->sf_vid) && 605 (pci_get_device(dev) == t->sf_did)) { 606 switch(pci_read_config(dev, 607 SF_PCI_SUBVEN_ID >> 16, 4) & 0x8FFF) { 608 case AD_SUBSYSID_62011_REV0: 609 case AD_SUBSYSID_62011_REV1: 610 device_set_desc(dev, 611 "Adaptec ANA-62011 10/100BaseTX"); 612 return(0); 613 break; 614 case AD_SUBSYSID_62022: 615 device_set_desc(dev, 616 "Adaptec ANA-62022 10/100BaseTX"); 617 return(0); 618 break; 619 case AD_SUBSYSID_62044: 620 device_set_desc(dev, 621 "Adaptec ANA-62044 10/100BaseTX"); 622 return(0); 623 break; 624 case AD_SUBSYSID_62020: 625 device_set_desc(dev, 626 "Adaptec ANA-62020 10/100BaseFX"); 627 return(0); 628 break; 629 case AD_SUBSYSID_69011: 630 device_set_desc(dev, 631 "Adaptec ANA-69011 10/100BaseTX"); 632 return(0); 633 break; 634 default: 635 device_set_desc(dev, t->sf_name); 636 return(0); 637 break; 638 } 639 } 640 t++; 641 } 642 643 return(ENXIO); 644} 645 646/* 647 * Attach the interface. Allocate softc structures, do ifmedia 648 * setup and ethernet/BPF attach. 649 */ 650static int sf_attach(dev) 651 device_t dev; 652{ 653 int s, i; 654 u_int32_t command; 655 struct sf_softc *sc; 656 struct ifnet *ifp; 657 int unit, rid, error = 0; 658 659 s = splimp(); 660 661 sc = device_get_softc(dev); 662 unit = device_get_unit(dev); 663 bzero(sc, sizeof(struct sf_softc)); 664 665 /* 666 * Handle power management nonsense. 667 */ 668 command = pci_read_config(dev, SF_PCI_CAPID, 4) & 0x000000FF; 669 if (command == 0x01) { 670 671 command = pci_read_config(dev, SF_PCI_PWRMGMTCTRL, 4); 672 if (command & SF_PSTATE_MASK) { 673 u_int32_t iobase, membase, irq; 674 675 /* Save important PCI config data. */ 676 iobase = pci_read_config(dev, SF_PCI_LOIO, 4); 677 membase = pci_read_config(dev, SF_PCI_LOMEM, 4); 678 irq = pci_read_config(dev, SF_PCI_INTLINE, 4); 679 680 /* Reset the power state. */ 681 printf("sf%d: chip is in D%d power mode " 682 "-- setting to D0\n", unit, command & SF_PSTATE_MASK); 683 command &= 0xFFFFFFFC; 684 pci_write_config(dev, SF_PCI_PWRMGMTCTRL, command, 4); 685 686 /* Restore PCI config data. */ 687 pci_write_config(dev, SF_PCI_LOIO, iobase, 4); 688 pci_write_config(dev, SF_PCI_LOMEM, membase, 4); 689 pci_write_config(dev, SF_PCI_INTLINE, irq, 4); 690 } 691 } 692 693 /* 694 * Map control/status registers. 695 */ 696 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 697 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 698 pci_write_config(dev, PCI_COMMAND_STATUS_REG, command, 4); 699 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 700 701#ifdef SF_USEIOSPACE 702 if (!(command & PCIM_CMD_PORTEN)) { 703 printf("sf%d: failed to enable I/O ports!\n", unit); 704 error = ENXIO; 705 goto fail; 706 } 707#else 708 if (!(command & PCIM_CMD_MEMEN)) { 709 printf("sf%d: failed to enable memory mapping!\n", unit); 710 error = ENXIO; 711 goto fail; 712 } 713#endif 714 715 rid = SF_RID; 716 sc->sf_res = bus_alloc_resource(dev, SF_RES, &rid, 717 0, ~0, 1, RF_ACTIVE); 718 719 if (sc->sf_res == NULL) { 720 printf ("sf%d: couldn't map ports\n", unit); 721 error = ENXIO; 722 goto fail; 723 } 724 725 sc->sf_btag = rman_get_bustag(sc->sf_res); 726 sc->sf_bhandle = rman_get_bushandle(sc->sf_res); 727 728 /* Allocate interrupt */ 729 rid = 0; 730 sc->sf_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 731 RF_SHAREABLE | RF_ACTIVE); 732 733 if (sc->sf_irq == NULL) { 734 printf("sf%d: couldn't map interrupt\n", unit); 735 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 736 error = ENXIO; 737 goto fail; 738 } 739 740 error = bus_setup_intr(dev, sc->sf_irq, INTR_TYPE_NET, 741 sf_intr, sc, &sc->sf_intrhand); 742 743 if (error) { 744 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_res); 745 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 746 printf("sf%d: couldn't set up irq\n", unit); 747 goto fail; 748 } 749 750 callout_handle_init(&sc->sf_stat_ch); 751 752 /* Reset the adapter. */ 753 sf_reset(sc); 754 755 /* 756 * Get station address from the EEPROM. 757 */ 758 for (i = 0; i < ETHER_ADDR_LEN; i++) 759 sc->arpcom.ac_enaddr[i] = 760 sf_read_eeprom(sc, SF_EE_NODEADDR + ETHER_ADDR_LEN - i); 761 762 /* 763 * An Adaptec chip was detected. Inform the world. 764 */ 765 printf("sf%d: Ethernet address: %6D\n", unit, 766 sc->arpcom.ac_enaddr, ":"); 767 768 sc->sf_unit = unit; 769 770 /* Allocate the descriptor queues. */ 771 sc->sf_ldata = contigmalloc(sizeof(struct sf_list_data), M_DEVBUF, 772 M_NOWAIT, 0x100000, 0xffffffff, PAGE_SIZE, 0); 773 774 if (sc->sf_ldata == NULL) { 775 printf("sf%d: no memory for list buffers!\n", unit); 776 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand); 777 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq); 778 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 779 error = ENXIO; 780 goto fail; 781 } 782 783 bzero(sc->sf_ldata, sizeof(struct sf_list_data)); 784 785 /* Do MII setup. */ 786 if (mii_phy_probe(dev, &sc->sf_miibus, 787 sf_ifmedia_upd, sf_ifmedia_sts)) { 788 printf("sf%d: MII without any phy!\n", sc->sf_unit); 789 free(sc->sf_ldata, M_DEVBUF); 790 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand); 791 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq); 792 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 793 error = ENXIO; 794 goto fail; 795 } 796 797 ifp = &sc->arpcom.ac_if; 798 ifp->if_softc = sc; 799 ifp->if_unit = unit; 800 ifp->if_name = "sf"; 801 ifp->if_mtu = ETHERMTU; 802 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 803 ifp->if_ioctl = sf_ioctl; 804 ifp->if_output = ether_output; 805 ifp->if_start = sf_start; 806 ifp->if_watchdog = sf_watchdog; 807 ifp->if_init = sf_init; 808 ifp->if_baudrate = 10000000; 809 ifp->if_snd.ifq_maxlen = SF_TX_DLIST_CNT - 1; 810 811 /* 812 * Call MI attach routines. 813 */ 814 if_attach(ifp); 815 ether_ifattach(ifp); 816 817#if NBPF > 0 818 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header)); 819#endif 820 821fail: 822 splx(s); 823 return(error); 824} 825 826static int sf_detach(dev) 827 device_t dev; 828{ 829 struct sf_softc *sc; 830 struct ifnet *ifp; 831 int s; 832 833 s = splimp(); 834 835 sc = device_get_softc(dev); 836 ifp = &sc->arpcom.ac_if; 837 838 if_detach(ifp); 839 sf_stop(sc); 840 841 bus_generic_detach(dev); 842 device_delete_child(dev, sc->sf_miibus); 843 844 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand); 845 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq); 846 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 847 848 free(sc->sf_ldata, M_DEVBUF); 849 850 splx(s); 851 852 return(0); 853} 854 855static int sf_init_rx_ring(sc) 856 struct sf_softc *sc; 857{ 858 struct sf_list_data *ld; 859 int i; 860 861 ld = sc->sf_ldata; 862 863 bzero((char *)ld->sf_rx_dlist_big, 864 sizeof(struct sf_rx_bufdesc_type0) * SF_RX_DLIST_CNT); 865 bzero((char *)ld->sf_rx_clist, 866 sizeof(struct sf_rx_cmpdesc_type3) * SF_RX_CLIST_CNT); 867 868 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 869 if (sf_newbuf(sc, &ld->sf_rx_dlist_big[i], NULL) == ENOBUFS) 870 return(ENOBUFS); 871 } 872 873 return(0); 874} 875 876static void sf_init_tx_ring(sc) 877 struct sf_softc *sc; 878{ 879 struct sf_list_data *ld; 880 int i; 881 882 ld = sc->sf_ldata; 883 884 bzero((char *)ld->sf_tx_dlist, 885 sizeof(struct sf_tx_bufdesc_type0) * SF_TX_DLIST_CNT); 886 bzero((char *)ld->sf_tx_clist, 887 sizeof(struct sf_tx_cmpdesc_type0) * SF_TX_CLIST_CNT); 888 889 for (i = 0; i < SF_TX_DLIST_CNT; i++) 890 ld->sf_tx_dlist[i].sf_id = SF_TX_BUFDESC_ID; 891 for (i = 0; i < SF_TX_CLIST_CNT; i++) 892 ld->sf_tx_clist[i].sf_type = SF_TXCMPTYPE_TX; 893 894 ld->sf_tx_dlist[SF_TX_DLIST_CNT - 1].sf_end = 1; 895 sc->sf_tx_cnt = 0; 896 897 return; 898} 899 900static int sf_newbuf(sc, c, m) 901 struct sf_softc *sc; 902 struct sf_rx_bufdesc_type0 *c; 903 struct mbuf *m; 904{ 905 struct mbuf *m_new = NULL; 906 907 if (m == NULL) { 908 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 909 if (m_new == NULL) { 910 printf("sf%d: no memory for rx list -- " 911 "packet dropped!\n", sc->sf_unit); 912 return(ENOBUFS); 913 } 914 915 MCLGET(m_new, M_DONTWAIT); 916 if (!(m_new->m_flags & M_EXT)) { 917 printf("sf%d: no memory for rx list -- " 918 "packet dropped!\n", sc->sf_unit); 919 m_freem(m_new); 920 return(ENOBUFS); 921 } 922 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 923 } else { 924 m_new = m; 925 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 926 m_new->m_data = m_new->m_ext.ext_buf; 927 } 928 929 m_adj(m_new, sizeof(u_int64_t)); 930 931 c->sf_mbuf = m_new; 932 c->sf_addrlo = SF_RX_HOSTADDR(vtophys(mtod(m_new, caddr_t))); 933 c->sf_valid = 1; 934 935 return(0); 936} 937 938/* 939 * The starfire is programmed to use 'normal' mode for packet reception, 940 * which means we use the consumer/producer model for both the buffer 941 * descriptor queue and the completion descriptor queue. The only problem 942 * with this is that it involves a lot of register accesses: we have to 943 * read the RX completion consumer and producer indexes and the RX buffer 944 * producer index, plus the RX completion consumer and RX buffer producer 945 * indexes have to be updated. It would have been easier if Adaptec had 946 * put each index in a separate register, especially given that the damn 947 * NIC has a 512K register space. 948 * 949 * In spite of all the lovely features that Adaptec crammed into the 6915, 950 * it is marred by one truly stupid design flaw, which is that receive 951 * buffer addresses must be aligned on a longword boundary. This forces 952 * the packet payload to be unaligned, which is suboptimal on the x86 and 953 * completely unuseable on the Alpha. Our only recourse is to copy received 954 * packets into properly aligned buffers before handing them off. 955 */ 956 957static void sf_rxeof(sc) 958 struct sf_softc *sc; 959{ 960 struct ether_header *eh; 961 struct mbuf *m; 962 struct ifnet *ifp; 963 struct sf_rx_bufdesc_type0 *desc; 964 struct sf_rx_cmpdesc_type3 *cur_rx; 965 u_int32_t rxcons, rxprod; 966 int cmpprodidx, cmpconsidx, bufprodidx; 967 968 ifp = &sc->arpcom.ac_if; 969 970 rxcons = csr_read_4(sc, SF_CQ_CONSIDX); 971 rxprod = csr_read_4(sc, SF_RXDQ_PTR_Q1); 972 cmpprodidx = SF_IDX_LO(csr_read_4(sc, SF_CQ_PRODIDX)); 973 cmpconsidx = SF_IDX_LO(rxcons); 974 bufprodidx = SF_IDX_LO(rxprod); 975 976 while (cmpconsidx != cmpprodidx) { 977 struct mbuf *m0; 978 979 cur_rx = &sc->sf_ldata->sf_rx_clist[cmpconsidx]; 980 desc = &sc->sf_ldata->sf_rx_dlist_big[cur_rx->sf_endidx]; 981 m = desc->sf_mbuf; 982 SF_INC(cmpconsidx, SF_RX_CLIST_CNT); 983 SF_INC(bufprodidx, SF_RX_DLIST_CNT); 984 985 if (!(cur_rx->sf_status1 & SF_RXSTAT1_OK)) { 986 ifp->if_ierrors++; 987 sf_newbuf(sc, desc, m); 988 continue; 989 } 990 991 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 992 cur_rx->sf_len + ETHER_ALIGN, 0, ifp, NULL); 993 sf_newbuf(sc, desc, m); 994 if (m0 == NULL) { 995 ifp->if_ierrors++; 996 continue; 997 } 998 m_adj(m0, ETHER_ALIGN); 999 m = m0; 1000 1001 eh = mtod(m, struct ether_header *); 1002 ifp->if_ipackets++; 1003 1004#if NBPF > 0 1005 if (ifp->if_bpf) { 1006 bpf_mtap(ifp, m); 1007 if (ifp->if_flags & IFF_PROMISC && 1008 (bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr, 1009 ETHER_ADDR_LEN) && !(eh->ether_dhost[0] & 1))) { 1010 m_freem(m); 1011 continue; 1012 } 1013 } 1014#endif 1015 1016 /* Remove header from mbuf and pass it on. */ 1017 m_adj(m, sizeof(struct ether_header)); 1018 ether_input(ifp, eh, m); 1019 1020 } 1021 1022 csr_write_4(sc, SF_CQ_CONSIDX, 1023 (rxcons & ~SF_CQ_CONSIDX_RXQ1) | cmpconsidx); 1024 csr_write_4(sc, SF_RXDQ_PTR_Q1, 1025 (rxprod & ~SF_RXDQ_PRODIDX) | bufprodidx); 1026 1027 return; 1028} 1029 1030/* 1031 * Read the transmit status from the completion queue and release 1032 * mbufs. Note that the buffer descriptor index in the completion 1033 * descriptor is an offset from the start of the transmit buffer 1034 * descriptor list in bytes. This is important because the manual 1035 * gives the impression that it should match the producer/consumer 1036 * index, which is the offset in 8 byte blocks. 1037 */ 1038static void sf_txeof(sc) 1039 struct sf_softc *sc; 1040{ 1041 int txcons, cmpprodidx, cmpconsidx; 1042 struct sf_tx_cmpdesc_type1 *cur_cmp; 1043 struct sf_tx_bufdesc_type0 *cur_tx; 1044 struct ifnet *ifp; 1045 1046 ifp = &sc->arpcom.ac_if; 1047 1048 txcons = csr_read_4(sc, SF_CQ_CONSIDX); 1049 cmpprodidx = SF_IDX_HI(csr_read_4(sc, SF_CQ_PRODIDX)); 1050 cmpconsidx = SF_IDX_HI(txcons); 1051 1052 while (cmpconsidx != cmpprodidx) { 1053 cur_cmp = &sc->sf_ldata->sf_tx_clist[cmpconsidx]; 1054 cur_tx = &sc->sf_ldata->sf_tx_dlist[cur_cmp->sf_index >> 7]; 1055 SF_INC(cmpconsidx, SF_TX_CLIST_CNT); 1056 1057 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_OK) 1058 ifp->if_opackets++; 1059 else 1060 ifp->if_oerrors++; 1061 1062 sc->sf_tx_cnt--; 1063 if (cur_tx->sf_mbuf != NULL) { 1064 m_freem(cur_tx->sf_mbuf); 1065 cur_tx->sf_mbuf = NULL; 1066 } 1067 } 1068 1069 ifp->if_timer = 0; 1070 ifp->if_flags &= ~IFF_OACTIVE; 1071 1072 csr_write_4(sc, SF_CQ_CONSIDX, 1073 (txcons & ~SF_CQ_CONSIDX_TXQ) | 1074 ((cmpconsidx << 16) & 0xFFFF0000)); 1075 1076 return; 1077} 1078 1079static void sf_intr(arg) 1080 void *arg; 1081{ 1082 struct sf_softc *sc; 1083 struct ifnet *ifp; 1084 u_int32_t status; 1085 1086 sc = arg; 1087 ifp = &sc->arpcom.ac_if; 1088 1089 if (!(csr_read_4(sc, SF_ISR_SHADOW) & SF_ISR_PCIINT_ASSERTED)) 1090 return; 1091 1092 /* Disable interrupts. */ 1093 csr_write_4(sc, SF_IMR, 0x00000000); 1094 1095 for (;;) { 1096 status = csr_read_4(sc, SF_ISR); 1097 if (status) 1098 csr_write_4(sc, SF_ISR, status); 1099 1100 if (!(status & SF_INTRS)) 1101 break; 1102 1103 if (status & SF_ISR_RXDQ1_DMADONE) 1104 sf_rxeof(sc); 1105 1106 if (status & SF_ISR_TX_TXDONE) 1107 sf_txeof(sc); 1108 1109 if (status & SF_ISR_ABNORMALINTR) { 1110 if (status & SF_ISR_STATSOFLOW) { 1111 untimeout(sf_stats_update, sc, 1112 sc->sf_stat_ch); 1113 sf_stats_update(sc); 1114 } else 1115 sf_init(sc); 1116 } 1117 } 1118 1119 /* Re-enable interrupts. */ 1120 csr_write_4(sc, SF_IMR, SF_INTRS); 1121 1122 if (ifp->if_snd.ifq_head != NULL) 1123 sf_start(ifp); 1124 1125 return; 1126} 1127 1128static void sf_init(xsc) 1129 void *xsc; 1130{ 1131 struct sf_softc *sc; 1132 struct ifnet *ifp; 1133 struct mii_data *mii; 1134 int i, s; 1135 1136 s = splimp(); 1137 1138 sc = xsc; 1139 ifp = &sc->arpcom.ac_if; 1140 mii = device_get_softc(sc->sf_miibus); 1141 1142 sf_stop(sc); 1143 sf_reset(sc); 1144 1145 /* Init all the receive filter registers */ 1146 for (i = SF_RXFILT_PERFECT_BASE; 1147 i < (SF_RXFILT_HASH_MAX + 1); i += 4) 1148 csr_write_4(sc, i, 0); 1149 1150 /* Empty stats counter registers. */ 1151 for (i = 0; i < sizeof(struct sf_stats)/sizeof(u_int32_t); i++) 1152 csr_write_4(sc, SF_STATS_BASE + 1153 (i + sizeof(u_int32_t)), 0); 1154 1155 /* Init our MAC address */ 1156 csr_write_4(sc, SF_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1157 csr_write_4(sc, SF_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1158 sf_setperf(sc, 0, (caddr_t)&sc->arpcom.ac_enaddr); 1159 1160 if (sf_init_rx_ring(sc) == ENOBUFS) { 1161 printf("sf%d: initialization failed: no " 1162 "memory for rx buffers\n", sc->sf_unit); 1163 (void)splx(s); 1164 return; 1165 } 1166 1167 sf_init_tx_ring(sc); 1168 1169 csr_write_4(sc, SF_RXFILT, SF_PERFMODE_NORMAL|SF_HASHMODE_WITHVLAN); 1170 1171 /* If we want promiscuous mode, set the allframes bit. */ 1172 if (ifp->if_flags & IFF_PROMISC) { 1173 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 1174 } else { 1175 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 1176 } 1177 1178 if (ifp->if_flags & IFF_BROADCAST) { 1179 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_BROAD); 1180 } else { 1181 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_BROAD); 1182 } 1183 1184 /* Init the completion queue indexes */ 1185 csr_write_4(sc, SF_CQ_CONSIDX, 0); 1186 csr_write_4(sc, SF_CQ_PRODIDX, 0); 1187 1188 /* Init the RX completion queue */ 1189 csr_write_4(sc, SF_RXCQ_CTL_1, 1190 vtophys(sc->sf_ldata->sf_rx_clist) & SF_RXCQ_ADDR); 1191 SF_SETBIT(sc, SF_RXCQ_CTL_1, SF_RXCQTYPE_3); 1192 1193 /* Init RX DMA control. */ 1194 SF_SETBIT(sc, SF_RXDMA_CTL, SF_RXDMA_REPORTBADPKTS); 1195 1196 /* Init the RX buffer descriptor queue. */ 1197 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 1198 vtophys(sc->sf_ldata->sf_rx_dlist_big)); 1199 csr_write_4(sc, SF_RXDQ_CTL_1, (MCLBYTES << 16) | SF_DESCSPACE_16BYTES); 1200 csr_write_4(sc, SF_RXDQ_PTR_Q1, SF_RX_DLIST_CNT - 1); 1201 1202 /* Init the TX completion queue */ 1203 csr_write_4(sc, SF_TXCQ_CTL, 1204 vtophys(sc->sf_ldata->sf_tx_clist) & SF_RXCQ_ADDR); 1205 1206 /* Init the TX buffer descriptor queue. */ 1207 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 1208 vtophys(sc->sf_ldata->sf_tx_dlist)); 1209 SF_SETBIT(sc, SF_TX_FRAMCTL, SF_TXFRMCTL_CPLAFTERTX); 1210 csr_write_4(sc, SF_TXDQ_CTL, 1211 SF_TXBUFDESC_TYPE0|SF_TXMINSPACE_128BYTES|SF_TXSKIPLEN_8BYTES); 1212 SF_SETBIT(sc, SF_TXDQ_CTL, SF_TXDQCTL_NODMACMP); 1213 1214 /* Enable autopadding of short TX frames. */ 1215 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_AUTOPAD); 1216 1217 /* Make sure the duplex mode is set correctly. */ 1218 if ((mii->mii_media.ifm_media & IFM_GMASK) == IFM_FDX) { 1219 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 1220 } else { 1221 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 1222 } 1223 1224 /* Enable interrupts. */ 1225 csr_write_4(sc, SF_IMR, SF_INTRS); 1226 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_INTR_ENB); 1227 1228 /* Enable the RX and TX engines. */ 1229 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_RX_ENB|SF_ETHCTL_RXDMA_ENB); 1230 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_TX_ENB|SF_ETHCTL_TXDMA_ENB); 1231 1232 mii_mediachg(mii); 1233 1234 ifp->if_flags |= IFF_RUNNING; 1235 ifp->if_flags &= ~IFF_OACTIVE; 1236 1237 sc->sf_stat_ch = timeout(sf_stats_update, sc, hz); 1238 1239 splx(s); 1240 1241 return; 1242} 1243 1244static int sf_encap(sc, c, m_head) 1245 struct sf_softc *sc; 1246 struct sf_tx_bufdesc_type0 *c; 1247 struct mbuf *m_head; 1248{ 1249 int frag = 0; 1250 struct sf_frag *f = NULL; 1251 struct mbuf *m; 1252 1253 m = m_head; 1254 1255 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1256 if (m->m_len != 0) { 1257 if (frag == SF_MAXFRAGS) 1258 break; 1259 f = &c->sf_frags[frag]; 1260 if (frag == 0) 1261 f->sf_pktlen = m_head->m_pkthdr.len; 1262 f->sf_fraglen = m->m_len; 1263 f->sf_addr = vtophys(mtod(m, vm_offset_t)); 1264 frag++; 1265 } 1266 } 1267 1268 if (m != NULL) { 1269 struct mbuf *m_new = NULL; 1270 1271 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1272 if (m_new == NULL) { 1273 printf("sf%d: no memory for tx list", sc->sf_unit); 1274 return(1); 1275 } 1276 1277 if (m_head->m_pkthdr.len > MHLEN) { 1278 MCLGET(m_new, M_DONTWAIT); 1279 if (!(m_new->m_flags & M_EXT)) { 1280 m_freem(m_new); 1281 printf("sf%d: no memory for tx list", 1282 sc->sf_unit); 1283 return(1); 1284 } 1285 } 1286 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1287 mtod(m_new, caddr_t)); 1288 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1289 m_freem(m_head); 1290 m_head = m_new; 1291 f = &c->sf_frags[0]; 1292 f->sf_fraglen = f->sf_pktlen = m_head->m_pkthdr.len; 1293 f->sf_addr = vtophys(mtod(m_head, caddr_t)); 1294 frag = 1; 1295 } 1296 1297 c->sf_mbuf = m_head; 1298 c->sf_id = SF_TX_BUFDESC_ID; 1299 c->sf_fragcnt = frag; 1300 c->sf_intr = 1; 1301 c->sf_caltcp = 0; 1302 c->sf_crcen = 1; 1303 1304 return(0); 1305} 1306 1307static void sf_start(ifp) 1308 struct ifnet *ifp; 1309{ 1310 struct sf_softc *sc; 1311 struct sf_tx_bufdesc_type0 *cur_tx = NULL; 1312 struct mbuf *m_head = NULL; 1313 int i, txprod; 1314 1315 sc = ifp->if_softc; 1316 1317 if (ifp->if_flags & IFF_OACTIVE) 1318 return; 1319 1320 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX); 1321 i = SF_IDX_HI(txprod) >> 4; 1322 1323 while(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf == NULL) { 1324 IF_DEQUEUE(&ifp->if_snd, m_head); 1325 if (m_head == NULL) 1326 break; 1327 1328 cur_tx = &sc->sf_ldata->sf_tx_dlist[i]; 1329 sf_encap(sc, cur_tx, m_head); 1330 1331 /* 1332 * If there's a BPF listener, bounce a copy of this frame 1333 * to him. 1334 */ 1335#if NBPF > 0 1336 if (ifp->if_bpf) 1337 bpf_mtap(ifp, m_head); 1338#endif 1339 SF_INC(i, SF_TX_DLIST_CNT); 1340 sc->sf_tx_cnt++; 1341 if (sc->sf_tx_cnt == (SF_TX_DLIST_CNT - 2)) 1342 break; 1343 } 1344 1345 if (cur_tx == NULL) 1346 return; 1347 1348 /* Transmit */ 1349 csr_write_4(sc, SF_TXDQ_PRODIDX, 1350 (txprod & ~SF_TXDQ_PRODIDX_HIPRIO) | 1351 ((i << 20) & 0xFFFF0000)); 1352 1353 ifp->if_timer = 5; 1354 1355 return; 1356} 1357 1358static void sf_stop(sc) 1359 struct sf_softc *sc; 1360{ 1361 int i; 1362 struct ifnet *ifp; 1363 1364 ifp = &sc->arpcom.ac_if; 1365 1366 untimeout(sf_stats_update, sc, sc->sf_stat_ch); 1367 1368 csr_write_4(sc, SF_GEN_ETH_CTL, 0); 1369 csr_write_4(sc, SF_CQ_CONSIDX, 0); 1370 csr_write_4(sc, SF_CQ_PRODIDX, 0); 1371 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 0); 1372 csr_write_4(sc, SF_RXDQ_CTL_1, 0); 1373 csr_write_4(sc, SF_RXDQ_PTR_Q1, 0); 1374 csr_write_4(sc, SF_TXCQ_CTL, 0); 1375 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 0); 1376 csr_write_4(sc, SF_TXDQ_CTL, 0); 1377 sf_reset(sc); 1378 1379 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 1380 if (sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf != NULL) { 1381 m_freem(sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf); 1382 sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf = NULL; 1383 } 1384 } 1385 1386 for (i = 0; i < SF_TX_DLIST_CNT; i++) { 1387 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) { 1388 m_freem(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf); 1389 sc->sf_ldata->sf_tx_dlist[i].sf_mbuf = NULL; 1390 } 1391 } 1392 1393 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 1394 1395 return; 1396} 1397 1398/* 1399 * Note: it is important that this function not be interrupted. We 1400 * use a two-stage register access scheme: if we are interrupted in 1401 * between setting the indirect address register and reading from the 1402 * indirect data register, the contents of the address register could 1403 * be changed out from under us. 1404 */ 1405static void sf_stats_update(xsc) 1406 void *xsc; 1407{ 1408 struct sf_softc *sc; 1409 struct ifnet *ifp; 1410 struct mii_data *mii; 1411 struct sf_stats stats; 1412 u_int32_t *ptr; 1413 int i, s; 1414 1415 s = splimp(); 1416 1417 sc = xsc; 1418 ifp = &sc->arpcom.ac_if; 1419 mii = device_get_softc(sc->sf_miibus); 1420 1421 ptr = (u_int32_t *)&stats; 1422 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++) 1423 ptr[i] = csr_read_4(sc, SF_STATS_BASE + 1424 (i + sizeof(u_int32_t))); 1425 1426 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++) 1427 csr_write_4(sc, SF_STATS_BASE + 1428 (i + sizeof(u_int32_t)), 0); 1429 1430 ifp->if_collisions += stats.sf_tx_single_colls + 1431 stats.sf_tx_multi_colls + stats.sf_tx_excess_colls; 1432 1433 mii_tick(mii); 1434 1435 sc->sf_stat_ch = timeout(sf_stats_update, sc, hz); 1436 1437 splx(s); 1438 1439 return; 1440} 1441 1442static void sf_watchdog(ifp) 1443 struct ifnet *ifp; 1444{ 1445 struct sf_softc *sc; 1446 1447 sc = ifp->if_softc; 1448 1449 ifp->if_oerrors++; 1450 printf("sf%d: watchdog timeout\n", sc->sf_unit); 1451 1452 sf_stop(sc); 1453 sf_reset(sc); 1454 sf_init(sc); 1455 1456 if (ifp->if_snd.ifq_head != NULL) 1457 sf_start(ifp); 1458 1459 return; 1460} 1461 1462static void sf_shutdown(dev) 1463 device_t dev; 1464{ 1465 struct sf_softc *sc; 1466 1467 sc = device_get_softc(dev); 1468 1469 sf_stop(sc); 1470 1471 return; 1472} 1473