if_sf.c revision 49076
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $Id: if_sf.c,v 1.11 1999/07/24 21:13:38 wpaul Exp $ 33 */ 34 35/* 36 * Adaptec AIC-6915 "Starfire" PCI fast ethernet driver for FreeBSD. 37 * Programming manual is available from www.adaptec.com. 38 * 39 * Written by Bill Paul <wpaul@ctr.columbia.edu> 40 * Department of Electical Engineering 41 * Columbia University, New York City 42 */ 43 44/* 45 * The Adaptec AIC-6915 "Starfire" is a 64-bit 10/100 PCI ethernet 46 * controller designed with flexibility and reducing CPU load in mind. 47 * The Starfire offers high and low priority buffer queues, a 48 * producer/consumer index mechanism and several different buffer 49 * queue and completion queue descriptor types. Any one of a number 50 * of different driver designs can be used, depending on system and 51 * OS requirements. This driver makes use of type0 transmit frame 52 * descriptors (since BSD fragments packets across an mbuf chain) 53 * and two RX buffer queues prioritized on size (one queue for small 54 * frames that will fit into a single mbuf, another with full size 55 * mbuf clusters for everything else). The producer/consumer indexes 56 * and completion queues are also used. 57 * 58 * One downside to the Starfire has to do with alignment: buffer 59 * queues must be aligned on 256-byte boundaries, and receive buffers 60 * must be aligned on longword boundaries. The receive buffer alignment 61 * causes problems on the Alpha platform, where the packet payload 62 * should be longword aligned. There is no simple way around this. 63 * 64 * For receive filtering, the Starfire offers 16 perfect filter slots 65 * and a 512-bit hash table. 66 * 67 * The Starfire has no internal transceiver, relying instead on an 68 * external MII-based transceiver. Accessing registers on external 69 * PHYs is done through a special register map rather than with the 70 * usual bitbang MDIO method. 71 * 72 * Acesssing the registers on the Starfire is a little tricky. The 73 * Starfire has a 512K internal register space. When programmed for 74 * PCI memory mapped mode, the entire register space can be accessed 75 * directly. However in I/O space mode, only 256 bytes are directly 76 * mapped into PCI I/O space. The other registers can be accessed 77 * indirectly using the SF_INDIRECTIO_ADDR and SF_INDIRECTIO_DATA 78 * registers inside the 256-byte I/O window. 79 */ 80 81#include "bpf.h" 82 83#include <sys/param.h> 84#include <sys/systm.h> 85#include <sys/sockio.h> 86#include <sys/mbuf.h> 87#include <sys/malloc.h> 88#include <sys/kernel.h> 89#include <sys/socket.h> 90 91#include <net/if.h> 92#include <net/if_arp.h> 93#include <net/ethernet.h> 94#include <net/if_dl.h> 95#include <net/if_media.h> 96 97#if NBPF > 0 98#include <net/bpf.h> 99#endif 100 101#include <vm/vm.h> /* for vtophys */ 102#include <vm/pmap.h> /* for vtophys */ 103#include <machine/clock.h> /* for DELAY */ 104#include <machine/bus_pio.h> 105#include <machine/bus_memio.h> 106#include <machine/bus.h> 107#include <machine/resource.h> 108#include <sys/bus.h> 109#include <sys/rman.h> 110 111#include <pci/pcireg.h> 112#include <pci/pcivar.h> 113 114#define SF_USEIOSPACE 115 116/* #define SF_BACKGROUND_AUTONEG */ 117 118#include <pci/if_sfreg.h> 119 120#ifndef lint 121static const char rcsid[] = 122 "$Id: if_sf.c,v 1.11 1999/07/24 21:13:38 wpaul Exp $"; 123#endif 124 125static struct sf_type sf_devs[] = { 126 { AD_VENDORID, AD_DEVICEID_STARFIRE, 127 "Adaptec AIC-6915 10/100BaseTX" }, 128 { 0, 0, NULL } 129}; 130 131static struct sf_type sf_phys[] = { 132 { 0, 0, "<MII-compliant physical interface>" } 133}; 134 135static int sf_probe __P((device_t)); 136static int sf_attach __P((device_t)); 137static int sf_detach __P((device_t)); 138static void sf_intr __P((void *)); 139static void sf_stats_update __P((void *)); 140static void sf_rxeof __P((struct sf_softc *)); 141static void sf_txeof __P((struct sf_softc *)); 142static int sf_encap __P((struct sf_softc *, 143 struct sf_tx_bufdesc_type0 *, 144 struct mbuf *)); 145static void sf_start __P((struct ifnet *)); 146static int sf_ioctl __P((struct ifnet *, u_long, caddr_t)); 147static void sf_init __P((void *)); 148static void sf_stop __P((struct sf_softc *)); 149static void sf_watchdog __P((struct ifnet *)); 150static void sf_shutdown __P((device_t)); 151static int sf_ifmedia_upd __P((struct ifnet *)); 152static void sf_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 153static void sf_reset __P((struct sf_softc *)); 154static int sf_init_rx_ring __P((struct sf_softc *)); 155static void sf_init_tx_ring __P((struct sf_softc *)); 156static int sf_newbuf __P((struct sf_softc *, 157 struct sf_rx_bufdesc_type0 *, 158 struct mbuf *)); 159static void sf_setmulti __P((struct sf_softc *)); 160static int sf_setperf __P((struct sf_softc *, int, caddr_t)); 161static int sf_sethash __P((struct sf_softc *, caddr_t, int)); 162#ifdef notdef 163static int sf_setvlan __P((struct sf_softc *, int, u_int32_t)); 164#endif 165 166static u_int8_t sf_read_eeprom __P((struct sf_softc *, int)); 167static u_int32_t sf_calchash __P((caddr_t)); 168 169static int sf_phy_readreg __P((struct sf_softc *, int)); 170static void sf_phy_writereg __P((struct sf_softc *, int, int)); 171static void sf_autoneg_xmit __P((struct sf_softc *)); 172static void sf_autoneg_mii __P((struct sf_softc *, int, int)); 173static void sf_getmode_mii __P((struct sf_softc *)); 174static void sf_setmode_mii __P((struct sf_softc *, int)); 175 176static u_int32_t csr_read_4 __P((struct sf_softc *, int)); 177static void csr_write_4 __P((struct sf_softc *, int, u_int32_t)); 178 179#ifdef SF_USEIOSPACE 180#define SF_RES SYS_RES_IOPORT 181#define SF_RID SF_PCI_LOIO 182#else 183#define SF_RES SYS_RES_MEMORY 184#define SF_RID SF_PCI_LOMEM 185#endif 186 187static device_method_t sf_methods[] = { 188 /* Device interface */ 189 DEVMETHOD(device_probe, sf_probe), 190 DEVMETHOD(device_attach, sf_attach), 191 DEVMETHOD(device_detach, sf_detach), 192 DEVMETHOD(device_shutdown, sf_shutdown), 193 { 0, 0 } 194}; 195 196static driver_t sf_driver = { 197 "sf", 198 sf_methods, 199 sizeof(struct sf_softc), 200}; 201 202static devclass_t sf_devclass; 203 204DRIVER_MODULE(sf, pci, sf_driver, sf_devclass, 0, 0); 205 206#define SF_SETBIT(sc, reg, x) \ 207 csr_write_4(sc, reg, csr_read_4(sc, reg) | x) 208 209#define SF_CLRBIT(sc, reg, x) \ 210 csr_write_4(sc, reg, csr_read_4(sc, reg) & ~x) 211 212static u_int32_t csr_read_4(sc, reg) 213 struct sf_softc *sc; 214 int reg; 215{ 216 u_int32_t val; 217 218#ifdef SF_USEIOSPACE 219 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); 220 val = CSR_READ_4(sc, SF_INDIRECTIO_DATA); 221#else 222 val = CSR_READ_4(sc, (reg + SF_RMAP_INTREG_BASE)); 223#endif 224 225 return(val); 226} 227 228static u_int8_t sf_read_eeprom(sc, reg) 229 struct sf_softc *sc; 230 int reg; 231{ 232 u_int8_t val; 233 234 val = (csr_read_4(sc, SF_EEADDR_BASE + 235 (reg & 0xFFFFFFFC)) >> (8 * (reg & 3))) & 0xFF; 236 237 return(val); 238} 239 240static void csr_write_4(sc, reg, val) 241 struct sf_softc *sc; 242 int reg; 243 u_int32_t val; 244{ 245#ifdef SF_USEIOSPACE 246 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); 247 CSR_WRITE_4(sc, SF_INDIRECTIO_DATA, val); 248#else 249 CSR_WRITE_4(sc, (reg + SF_RMAP_INTREG_BASE), val); 250#endif 251 return; 252} 253 254static u_int32_t sf_calchash(addr) 255 caddr_t addr; 256{ 257 u_int32_t crc, carry; 258 int i, j; 259 u_int8_t c; 260 261 /* Compute CRC for the address value. */ 262 crc = 0xFFFFFFFF; /* initial value */ 263 264 for (i = 0; i < 6; i++) { 265 c = *(addr + i); 266 for (j = 0; j < 8; j++) { 267 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 268 crc <<= 1; 269 c >>= 1; 270 if (carry) 271 crc = (crc ^ 0x04c11db6) | carry; 272 } 273 } 274 275 /* return the filter bit position */ 276 return(crc >> 23 & 0x1FF); 277} 278 279/* 280 * Copy the address 'mac' into the perfect RX filter entry at 281 * offset 'idx.' The perfect filter only has 16 entries so do 282 * some sanity tests. 283 */ 284static int sf_setperf(sc, idx, mac) 285 struct sf_softc *sc; 286 int idx; 287 caddr_t mac; 288{ 289 u_int16_t *p; 290 291 if (idx < 0 || idx > SF_RXFILT_PERFECT_CNT) 292 return(EINVAL); 293 294 if (mac == NULL) 295 return(EINVAL); 296 297 p = (u_int16_t *)mac; 298 299 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 300 (idx * SF_RXFILT_PERFECT_SKIP), htons(p[2])); 301 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 302 (idx * SF_RXFILT_PERFECT_SKIP) + 4, htons(p[1])); 303 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 304 (idx * SF_RXFILT_PERFECT_SKIP) + 8, htons(p[0])); 305 306 return(0); 307} 308 309/* 310 * Set the bit in the 512-bit hash table that corresponds to the 311 * specified mac address 'mac.' If 'prio' is nonzero, update the 312 * priority hash table instead of the filter hash table. 313 */ 314static int sf_sethash(sc, mac, prio) 315 struct sf_softc *sc; 316 caddr_t mac; 317 int prio; 318{ 319 u_int32_t h = 0; 320 321 if (mac == NULL) 322 return(EINVAL); 323 324 h = sf_calchash(mac); 325 326 if (prio) { 327 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_PRIOOFF + 328 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); 329 } else { 330 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_ADDROFF + 331 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); 332 } 333 334 return(0); 335} 336 337#ifdef notdef 338/* 339 * Set a VLAN tag in the receive filter. 340 */ 341static int sf_setvlan(sc, idx, vlan) 342 struct sf_softc *sc; 343 int idx; 344 u_int32_t vlan; 345{ 346 if (idx < 0 || idx >> SF_RXFILT_HASH_CNT) 347 return(EINVAL); 348 349 csr_write_4(sc, SF_RXFILT_HASH_BASE + 350 (idx * SF_RXFILT_HASH_SKIP) + SF_RXFILT_HASH_VLANOFF, vlan); 351 352 return(0); 353} 354#endif 355 356static int sf_phy_readreg(sc, reg) 357 struct sf_softc *sc; 358 int reg; 359{ 360 int i; 361 u_int32_t val = 0; 362 363 for (i = 0; i < SF_TIMEOUT; i++) { 364 val = csr_read_4(sc, SF_PHY_REG(sc->sf_phy_addr, reg)); 365 if (val & SF_MII_DATAVALID) 366 break; 367 } 368 369 if (i == SF_TIMEOUT) 370 return(0); 371 372 if ((val & 0x0000FFFF) == 0xFFFF) 373 return(0); 374 375 return(val & 0x0000FFFF); 376} 377 378static void sf_phy_writereg(sc, reg, val) 379 struct sf_softc *sc; 380 int reg, val; 381{ 382 int i; 383 int busy; 384 385 csr_write_4(sc, SF_PHY_REG(sc->sf_phy_addr, reg), val); 386 387 for (i = 0; i < SF_TIMEOUT; i++) { 388 busy = csr_read_4(sc, SF_PHY_REG(sc->sf_phy_addr, reg)); 389 if (!(busy & SF_MII_BUSY)) 390 break; 391 } 392 393 return; 394} 395 396static void sf_setmulti(sc) 397 struct sf_softc *sc; 398{ 399 struct ifnet *ifp; 400 int i; 401 struct ifmultiaddr *ifma; 402 u_int8_t dummy[] = { 0, 0, 0, 0, 0, 0 }; 403 404 ifp = &sc->arpcom.ac_if; 405 406 /* First zot all the existing filters. */ 407 for (i = 1; i < SF_RXFILT_PERFECT_CNT; i++) 408 sf_setperf(sc, i, (char *)&dummy); 409 for (i = SF_RXFILT_HASH_BASE; 410 i < (SF_RXFILT_HASH_MAX + 1); i += 4) 411 csr_write_4(sc, i, 0); 412 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI); 413 414 /* Now program new ones. */ 415 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 416 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI); 417 } else { 418 i = 1; 419 /* First find the tail of the list. */ 420 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 421 ifma = ifma->ifma_link.le_next) { 422 if (ifma->ifma_link.le_next == NULL) 423 break; 424 } 425 /* Now traverse the list backwards. */ 426 for (; ifma != NULL && ifma != (void *)&ifp->if_multiaddrs; 427 ifma = (struct ifmultiaddr *)ifma->ifma_link.le_prev) { 428 if (ifma->ifma_addr->sa_family != AF_LINK) 429 continue; 430 /* 431 * Program the first 15 multicast groups 432 * into the perfect filter. For all others, 433 * use the hash table. 434 */ 435 if (i < SF_RXFILT_PERFECT_CNT) { 436 sf_setperf(sc, i, 437 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 438 i++; 439 continue; 440 } 441 442 sf_sethash(sc, 443 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 0); 444 } 445 } 446 447 return; 448} 449 450/* 451 * Initiate an autonegotiation session. 452 */ 453static void sf_autoneg_xmit(sc) 454 struct sf_softc *sc; 455{ 456 u_int16_t phy_sts; 457 458 sf_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET); 459 DELAY(500); 460 while(sf_phy_readreg(sc, PHY_BMCR) 461 & PHY_BMCR_RESET); 462 463 phy_sts = sf_phy_readreg(sc, PHY_BMCR); 464 phy_sts |= PHY_BMCR_AUTONEGENBL|PHY_BMCR_AUTONEGRSTR; 465 sf_phy_writereg(sc, PHY_BMCR, phy_sts); 466 467 return; 468} 469 470/* 471 * Invoke autonegotiation on a PHY. 472 */ 473static void sf_autoneg_mii(sc, flag, verbose) 474 struct sf_softc *sc; 475 int flag; 476 int verbose; 477{ 478 u_int16_t phy_sts = 0, media, advert, ability; 479 struct ifnet *ifp; 480 struct ifmedia *ifm; 481 482 ifm = &sc->ifmedia; 483 ifp = &sc->arpcom.ac_if; 484 485 ifm->ifm_media = IFM_ETHER | IFM_AUTO; 486 487#ifndef FORCE_AUTONEG_TFOUR 488 /* 489 * First, see if autoneg is supported. If not, there's 490 * no point in continuing. 491 */ 492 phy_sts = sf_phy_readreg(sc, PHY_BMSR); 493 if (!(phy_sts & PHY_BMSR_CANAUTONEG)) { 494 if (verbose) 495 printf("sf%d: autonegotiation not supported\n", 496 sc->sf_unit); 497 ifm->ifm_media = IFM_ETHER|IFM_10_T|IFM_HDX; 498 return; 499 } 500#endif 501 502 switch (flag) { 503 case SF_FLAG_FORCEDELAY: 504 /* 505 * XXX Never use this option anywhere but in the probe 506 * routine: making the kernel stop dead in its tracks 507 * for three whole seconds after we've gone multi-user 508 * is really bad manners. 509 */ 510 sf_autoneg_xmit(sc); 511 DELAY(5000000); 512 break; 513 case SF_FLAG_SCHEDDELAY: 514 /* 515 * Wait for the transmitter to go idle before starting 516 * an autoneg session, otherwise sf_start() may clobber 517 * our timeout, and we don't want to allow transmission 518 * during an autoneg session since that can screw it up. 519 */ 520 if (sc->sf_tx_cnt) { 521 sc->sf_want_auto = 1; 522 return; 523 } 524 sf_autoneg_xmit(sc); 525 ifp->if_timer = 5; 526 sc->sf_autoneg = 1; 527 sc->sf_want_auto = 0; 528 return; 529 break; 530 case SF_FLAG_DELAYTIMEO: 531 ifp->if_timer = 0; 532 sc->sf_autoneg = 0; 533 break; 534 default: 535 printf("sf%d: invalid autoneg flag: %d\n", sc->sf_unit, flag); 536 return; 537 } 538 539 if (sf_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_AUTONEGCOMP) { 540 if (verbose) 541 printf("sf%d: autoneg complete, ", sc->sf_unit); 542 phy_sts = sf_phy_readreg(sc, PHY_BMSR); 543 } else { 544 if (verbose) 545 printf("sf%d: autoneg not complete, ", sc->sf_unit); 546 } 547 548 media = sf_phy_readreg(sc, PHY_BMCR); 549 550 /* Link is good. Report modes and set duplex mode. */ 551 if (sf_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT) { 552 if (verbose) 553 printf("link status good "); 554 advert = sf_phy_readreg(sc, PHY_ANAR); 555 ability = sf_phy_readreg(sc, PHY_LPAR); 556 557 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) { 558 ifm->ifm_media = IFM_ETHER|IFM_100_T4; 559 media |= PHY_BMCR_SPEEDSEL; 560 media &= ~PHY_BMCR_DUPLEX; 561 printf("(100baseT4)\n"); 562 } else if (advert & PHY_ANAR_100BTXFULL && 563 ability & PHY_ANAR_100BTXFULL) { 564 ifm->ifm_media = IFM_ETHER|IFM_100_TX|IFM_FDX; 565 media |= PHY_BMCR_SPEEDSEL; 566 media |= PHY_BMCR_DUPLEX; 567 printf("(full-duplex, 100Mbps)\n"); 568 } else if (advert & PHY_ANAR_100BTXHALF && 569 ability & PHY_ANAR_100BTXHALF) { 570 ifm->ifm_media = IFM_ETHER|IFM_100_TX|IFM_HDX; 571 media |= PHY_BMCR_SPEEDSEL; 572 media &= ~PHY_BMCR_DUPLEX; 573 printf("(half-duplex, 100Mbps)\n"); 574 } else if (advert & PHY_ANAR_10BTFULL && 575 ability & PHY_ANAR_10BTFULL) { 576 ifm->ifm_media = IFM_ETHER|IFM_10_T|IFM_FDX; 577 media &= ~PHY_BMCR_SPEEDSEL; 578 media |= PHY_BMCR_DUPLEX; 579 printf("(full-duplex, 10Mbps)\n"); 580 } else if (advert & PHY_ANAR_10BTHALF && 581 ability & PHY_ANAR_10BTHALF) { 582 ifm->ifm_media = IFM_ETHER|IFM_10_T|IFM_HDX; 583 media &= ~PHY_BMCR_SPEEDSEL; 584 media &= ~PHY_BMCR_DUPLEX; 585 printf("(half-duplex, 10Mbps)\n"); 586 } 587 588 media &= ~PHY_BMCR_AUTONEGENBL; 589 590 /* Set ASIC's duplex mode to match the PHY. */ 591 sf_phy_writereg(sc, PHY_BMCR, media); 592 if ((media & IFM_GMASK) == IFM_FDX) { 593 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 594 } else { 595 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 596 } 597 } else { 598 if (verbose) 599 printf("no carrier\n"); 600 } 601 602 sf_init(sc); 603 604 if (sc->sf_tx_pend) { 605 sc->sf_autoneg = 0; 606 sc->sf_tx_pend = 0; 607 sf_start(ifp); 608 } 609 610 return; 611} 612 613static void sf_getmode_mii(sc) 614 struct sf_softc *sc; 615{ 616 u_int16_t bmsr; 617 struct ifnet *ifp; 618 619 ifp = &sc->arpcom.ac_if; 620 621 bmsr = sf_phy_readreg(sc, PHY_BMSR); 622 if (bootverbose) 623 printf("sf%d: PHY status word: %x\n", sc->sf_unit, bmsr); 624 625 /* fallback */ 626 sc->ifmedia.ifm_media = IFM_ETHER|IFM_10_T|IFM_HDX; 627 628 if (bmsr & PHY_BMSR_10BTHALF) { 629 if (bootverbose) 630 printf("sf%d: 10Mbps half-duplex mode supported\n", 631 sc->sf_unit); 632 ifmedia_add(&sc->ifmedia, 633 IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); 634 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 635 } 636 637 if (bmsr & PHY_BMSR_10BTFULL) { 638 if (bootverbose) 639 printf("sf%d: 10Mbps full-duplex mode supported\n", 640 sc->sf_unit); 641 ifmedia_add(&sc->ifmedia, 642 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 643 sc->ifmedia.ifm_media = IFM_ETHER|IFM_10_T|IFM_FDX; 644 } 645 646 if (bmsr & PHY_BMSR_100BTXHALF) { 647 if (bootverbose) 648 printf("sf%d: 100Mbps half-duplex mode supported\n", 649 sc->sf_unit); 650 ifp->if_baudrate = 100000000; 651 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 652 ifmedia_add(&sc->ifmedia, 653 IFM_ETHER|IFM_100_TX|IFM_HDX, 0, NULL); 654 sc->ifmedia.ifm_media = IFM_ETHER|IFM_100_TX|IFM_HDX; 655 } 656 657 if (bmsr & PHY_BMSR_100BTXFULL) { 658 if (bootverbose) 659 printf("sf%d: 100Mbps full-duplex mode supported\n", 660 sc->sf_unit); 661 ifp->if_baudrate = 100000000; 662 ifmedia_add(&sc->ifmedia, 663 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 664 sc->ifmedia.ifm_media = IFM_ETHER|IFM_100_TX|IFM_FDX; 665 } 666 667 /* Some also support 100BaseT4. */ 668 if (bmsr & PHY_BMSR_100BT4) { 669 if (bootverbose) 670 printf("sf%d: 100baseT4 mode supported\n", sc->sf_unit); 671 ifp->if_baudrate = 100000000; 672 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_T4, 0, NULL); 673 sc->ifmedia.ifm_media = IFM_ETHER|IFM_100_T4; 674#ifdef FORCE_AUTONEG_TFOUR 675 if (bootverbose) 676 printf("sf%d: forcing on autoneg support for BT4\n", 677 sc->sf_unit); 678 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0 NULL): 679 sc->ifmedia.ifm_media = IFM_ETHER|IFM_AUTO; 680#endif 681 } 682 683 if (bmsr & PHY_BMSR_CANAUTONEG) { 684 if (bootverbose) 685 printf("sf%d: autoneg supported\n", sc->sf_unit); 686 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 687 sc->ifmedia.ifm_media = IFM_ETHER|IFM_AUTO; 688 } 689 690 return; 691} 692 693/* 694 * Set speed and duplex mode. 695 */ 696static void sf_setmode_mii(sc, media) 697 struct sf_softc *sc; 698 int media; 699{ 700 u_int16_t bmcr; 701 struct ifnet *ifp; 702 703 ifp = &sc->arpcom.ac_if; 704 705 /* 706 * If an autoneg session is in progress, stop it. 707 */ 708 if (sc->sf_autoneg) { 709 printf("sf%d: canceling autoneg session\n", sc->sf_unit); 710 ifp->if_timer = sc->sf_autoneg = sc->sf_want_auto = 0; 711 bmcr = sf_phy_readreg(sc, PHY_BMCR); 712 bmcr &= ~PHY_BMCR_AUTONEGENBL; 713 sf_phy_writereg(sc, PHY_BMCR, bmcr); 714 } 715 716 printf("sf%d: selecting MII, ", sc->sf_unit); 717 718 bmcr = sf_phy_readreg(sc, PHY_BMCR); 719 720 bmcr &= ~(PHY_BMCR_AUTONEGENBL|PHY_BMCR_SPEEDSEL| 721 PHY_BMCR_DUPLEX|PHY_BMCR_LOOPBK); 722 723 if (IFM_SUBTYPE(media) == IFM_100_T4) { 724 printf("100Mbps/T4, half-duplex\n"); 725 bmcr |= PHY_BMCR_SPEEDSEL; 726 bmcr &= ~PHY_BMCR_DUPLEX; 727 } 728 729 if (IFM_SUBTYPE(media) == IFM_100_TX) { 730 printf("100Mbps, "); 731 bmcr |= PHY_BMCR_SPEEDSEL; 732 } 733 734 if (IFM_SUBTYPE(media) == IFM_10_T) { 735 printf("10Mbps, "); 736 bmcr &= ~PHY_BMCR_SPEEDSEL; 737 } 738 739 if ((media & IFM_GMASK) == IFM_FDX) { 740 printf("full duplex\n"); 741 bmcr |= PHY_BMCR_DUPLEX; 742 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 743 } else { 744 printf("half duplex\n"); 745 bmcr &= ~PHY_BMCR_DUPLEX; 746 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 747 } 748 749 sf_phy_writereg(sc, PHY_BMCR, bmcr); 750 751 return; 752} 753 754/* 755 * Set media options. 756 */ 757static int sf_ifmedia_upd(ifp) 758 struct ifnet *ifp; 759{ 760 struct sf_softc *sc; 761 struct ifmedia *ifm; 762 763 sc = ifp->if_softc; 764 ifm = &sc->ifmedia; 765 766 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 767 return(EINVAL); 768 769 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) 770 sf_autoneg_mii(sc, SF_FLAG_SCHEDDELAY, 1); 771 else { 772 sf_setmode_mii(sc, ifm->ifm_media); 773 } 774 775 return(0); 776} 777 778/* 779 * Report current media status. 780 */ 781static void sf_ifmedia_sts(ifp, ifmr) 782 struct ifnet *ifp; 783 struct ifmediareq *ifmr; 784{ 785 struct sf_softc *sc; 786 u_int16_t advert = 0, ability = 0; 787 788 sc = ifp->if_softc; 789 790 ifmr->ifm_active = IFM_ETHER; 791 792 if (!(sf_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_AUTONEGENBL)) { 793 if (sf_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_SPEEDSEL) 794 ifmr->ifm_active = IFM_ETHER|IFM_100_TX; 795 else 796 ifmr->ifm_active = IFM_ETHER|IFM_10_T; 797 if (sf_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_DUPLEX) 798 ifmr->ifm_active |= IFM_FDX; 799 else 800 ifmr->ifm_active |= IFM_HDX; 801 return; 802 } 803 804 ability = sf_phy_readreg(sc, PHY_LPAR); 805 advert = sf_phy_readreg(sc, PHY_ANAR); 806 if (advert & PHY_ANAR_100BT4 && 807 ability & PHY_ANAR_100BT4) { 808 ifmr->ifm_active = IFM_ETHER|IFM_100_T4; 809 } else if (advert & PHY_ANAR_100BTXFULL && 810 ability & PHY_ANAR_100BTXFULL) { 811 ifmr->ifm_active = IFM_ETHER|IFM_100_TX|IFM_FDX; 812 } else if (advert & PHY_ANAR_100BTXHALF && 813 ability & PHY_ANAR_100BTXHALF) { 814 ifmr->ifm_active = IFM_ETHER|IFM_100_TX|IFM_HDX; 815 } else if (advert & PHY_ANAR_10BTFULL && 816 ability & PHY_ANAR_10BTFULL) { 817 ifmr->ifm_active = IFM_ETHER|IFM_10_T|IFM_FDX; 818 } else if (advert & PHY_ANAR_10BTHALF && 819 ability & PHY_ANAR_10BTHALF) { 820 ifmr->ifm_active = IFM_ETHER|IFM_10_T|IFM_HDX; 821 } 822 823 return; 824} 825 826static int sf_ioctl(ifp, command, data) 827 struct ifnet *ifp; 828 u_long command; 829 caddr_t data; 830{ 831 struct sf_softc *sc = ifp->if_softc; 832 struct ifreq *ifr = (struct ifreq *) data; 833 int s, error = 0; 834 835 s = splimp(); 836 837 switch(command) { 838 case SIOCSIFADDR: 839 case SIOCGIFADDR: 840 case SIOCSIFMTU: 841 error = ether_ioctl(ifp, command, data); 842 break; 843 case SIOCSIFFLAGS: 844 if (ifp->if_flags & IFF_UP) { 845 sf_init(sc); 846 } else { 847 if (ifp->if_flags & IFF_RUNNING) 848 sf_stop(sc); 849 } 850 error = 0; 851 break; 852 case SIOCADDMULTI: 853 case SIOCDELMULTI: 854 sf_setmulti(sc); 855 error = 0; 856 break; 857 case SIOCGIFMEDIA: 858 case SIOCSIFMEDIA: 859 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 860 break; 861 default: 862 error = EINVAL; 863 break; 864 } 865 866 (void)splx(s); 867 868 return(error); 869} 870 871static void sf_reset(sc) 872 struct sf_softc *sc; 873{ 874 register int i; 875 876 csr_write_4(sc, SF_GEN_ETH_CTL, 0); 877 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 878 DELAY(1000); 879 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 880 881 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_RESET); 882 883 for (i = 0; i < SF_TIMEOUT; i++) { 884 DELAY(10); 885 if (!(csr_read_4(sc, SF_PCI_DEVCFG) & SF_PCIDEVCFG_RESET)) 886 break; 887 } 888 889 if (i == SF_TIMEOUT) 890 printf("sf%d: reset never completed!\n", sc->sf_unit); 891 892 /* Wait a little while for the chip to get its brains in order. */ 893 DELAY(1000); 894 return; 895} 896 897/* 898 * Probe for an Adaptec AIC-6915 chip. Check the PCI vendor and device 899 * IDs against our list and return a device name if we find a match. 900 * We also check the subsystem ID so that we can identify exactly which 901 * NIC has been found, if possible. 902 */ 903static int sf_probe(dev) 904 device_t dev; 905{ 906 struct sf_type *t; 907 908 t = sf_devs; 909 910 while(t->sf_name != NULL) { 911 if ((pci_get_vendor(dev) == t->sf_vid) && 912 (pci_get_device(dev) == t->sf_did)) { 913 switch(pci_read_config(dev, 914 SF_PCI_SUBVEN_ID >> 16, 4) & 0x8FFF) { 915 case AD_SUBSYSID_62011_REV0: 916 case AD_SUBSYSID_62011_REV1: 917 device_set_desc(dev, 918 "Adaptec ANA-62011 10/100BaseTX"); 919 return(0); 920 break; 921 case AD_SUBSYSID_62022: 922 device_set_desc(dev, 923 "Adaptec ANA-62022 10/100BaseTX"); 924 return(0); 925 break; 926 case AD_SUBSYSID_62044: 927 device_set_desc(dev, 928 "Adaptec ANA-62044 10/100BaseTX"); 929 return(0); 930 break; 931 case AD_SUBSYSID_62020: 932 device_set_desc(dev, 933 "Adaptec ANA-62020 10/100BaseFX"); 934 return(0); 935 break; 936 case AD_SUBSYSID_69011: 937 device_set_desc(dev, 938 "Adaptec ANA-69011 10/100BaseTX"); 939 return(0); 940 break; 941 default: 942 device_set_desc(dev, t->sf_name); 943 return(0); 944 break; 945 } 946 } 947 t++; 948 } 949 950 return(ENXIO); 951} 952 953/* 954 * Attach the interface. Allocate softc structures, do ifmedia 955 * setup and ethernet/BPF attach. 956 */ 957static int sf_attach(dev) 958 device_t dev; 959{ 960 int s, i; 961 u_int32_t command; 962 struct sf_softc *sc; 963 struct ifnet *ifp; 964 int media = IFM_ETHER|IFM_100_TX|IFM_FDX; 965 struct sf_type *p; 966 u_int16_t phy_vid, phy_did, phy_sts; 967 int unit, rid, error = 0; 968 969 s = splimp(); 970 971 sc = device_get_softc(dev); 972 unit = device_get_unit(dev); 973 bzero(sc, sizeof(struct sf_softc)); 974 975 /* 976 * Handle power management nonsense. 977 */ 978 command = pci_read_config(dev, SF_PCI_CAPID, 4) & 0x000000FF; 979 if (command == 0x01) { 980 981 command = pci_read_config(dev, SF_PCI_PWRMGMTCTRL, 4); 982 if (command & SF_PSTATE_MASK) { 983 u_int32_t iobase, membase, irq; 984 985 /* Save important PCI config data. */ 986 iobase = pci_read_config(dev, SF_PCI_LOIO, 4); 987 membase = pci_read_config(dev, SF_PCI_LOMEM, 4); 988 irq = pci_read_config(dev, SF_PCI_INTLINE, 4); 989 990 /* Reset the power state. */ 991 printf("sf%d: chip is in D%d power mode " 992 "-- setting to D0\n", unit, command & SF_PSTATE_MASK); 993 command &= 0xFFFFFFFC; 994 pci_write_config(dev, SF_PCI_PWRMGMTCTRL, command, 4); 995 996 /* Restore PCI config data. */ 997 pci_write_config(dev, SF_PCI_LOIO, iobase, 4); 998 pci_write_config(dev, SF_PCI_LOMEM, membase, 4); 999 pci_write_config(dev, SF_PCI_INTLINE, irq, 4); 1000 } 1001 } 1002 1003 /* 1004 * Map control/status registers. 1005 */ 1006 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 1007 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 1008 pci_write_config(dev, PCI_COMMAND_STATUS_REG, command, 4); 1009 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 1010 1011#ifdef SF_USEIOSPACE 1012 if (!(command & PCIM_CMD_PORTEN)) { 1013 printf("sf%d: failed to enable I/O ports!\n", unit); 1014 error = ENXIO; 1015 goto fail; 1016 } 1017#else 1018 if (!(command & PCIM_CMD_MEMEN)) { 1019 printf("sf%d: failed to enable memory mapping!\n", unit); 1020 error = ENXIO; 1021 goto fail; 1022 } 1023#endif 1024 1025 rid = SF_RID; 1026 sc->sf_res = bus_alloc_resource(dev, SF_RES, &rid, 1027 0, ~0, 1, RF_ACTIVE); 1028 1029 if (sc->sf_res == NULL) { 1030 printf ("sf%d: couldn't map ports\n", unit); 1031 error = ENXIO; 1032 goto fail; 1033 } 1034 1035 sc->sf_btag = rman_get_bustag(sc->sf_res); 1036 sc->sf_bhandle = rman_get_bushandle(sc->sf_res); 1037 1038 /* Allocate interrupt */ 1039 rid = 0; 1040 sc->sf_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1041 RF_SHAREABLE | RF_ACTIVE); 1042 1043 if (sc->sf_irq == NULL) { 1044 printf("sf%d: couldn't map interrupt\n", unit); 1045 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 1046 error = ENXIO; 1047 goto fail; 1048 } 1049 1050 error = bus_setup_intr(dev, sc->sf_irq, INTR_TYPE_NET, 1051 sf_intr, sc, &sc->sf_intrhand); 1052 1053 if (error) { 1054 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_res); 1055 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 1056 printf("sf%d: couldn't set up irq\n", unit); 1057 goto fail; 1058 } 1059 1060 callout_handle_init(&sc->sf_stat_ch); 1061 1062 /* Reset the adapter. */ 1063 sf_reset(sc); 1064 1065 /* 1066 * Get station address from the EEPROM. 1067 */ 1068 for (i = 0; i < ETHER_ADDR_LEN; i++) 1069 sc->arpcom.ac_enaddr[i] = 1070 sf_read_eeprom(sc, SF_EE_NODEADDR + ETHER_ADDR_LEN - i); 1071 1072 /* 1073 * An Adaptec chip was detected. Inform the world. 1074 */ 1075 printf("sf%d: Ethernet address: %6D\n", unit, 1076 sc->arpcom.ac_enaddr, ":"); 1077 1078 sc->sf_unit = unit; 1079 1080 /* Allocate the descriptor queues. */ 1081 sc->sf_ldata = contigmalloc(sizeof(struct sf_list_data), M_DEVBUF, 1082 M_NOWAIT, 0x100000, 0xffffffff, PAGE_SIZE, 0); 1083 1084 if (sc->sf_ldata == NULL) { 1085 printf("sf%d: no memory for list buffers!\n", unit); 1086 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand); 1087 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq); 1088 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 1089 error = ENXIO; 1090 goto fail; 1091 } 1092 1093 bzero(sc->sf_ldata, sizeof(struct sf_list_data)); 1094 1095 if (bootverbose) 1096 printf("sf%d: probing for a PHY\n", sc->sf_unit); 1097 for (i = SF_PHYADDR_MIN; i < SF_PHYADDR_MAX + 1; i++) { 1098 if (bootverbose) 1099 printf("sf%d: checking address: %d\n", 1100 sc->sf_unit, i); 1101 sc->sf_phy_addr = i; 1102 sf_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET); 1103 DELAY(500); 1104 while(sf_phy_readreg(sc, PHY_BMCR) 1105 & PHY_BMCR_RESET); 1106 if ((phy_sts = sf_phy_readreg(sc, PHY_BMSR))) 1107 break; 1108 } 1109 if (phy_sts) { 1110 phy_vid = sf_phy_readreg(sc, PHY_VENID); 1111 phy_did = sf_phy_readreg(sc, PHY_DEVID); 1112 if (bootverbose) 1113 printf("sf%d: found PHY at address %d, ", 1114 sc->sf_unit, sc->sf_phy_addr); 1115 if (bootverbose) 1116 printf("vendor id: %x device id: %x\n", 1117 phy_vid, phy_did); 1118 p = sf_phys; 1119 while(p->sf_vid) { 1120 if (phy_vid == p->sf_vid && 1121 (phy_did | 0x000F) == p->sf_did) { 1122 sc->sf_pinfo = p; 1123 break; 1124 } 1125 p++; 1126 } 1127 if (sc->sf_pinfo == NULL) 1128 sc->sf_pinfo = &sf_phys[PHY_UNKNOWN]; 1129 if (bootverbose) 1130 printf("sf%d: PHY type: %s\n", 1131 sc->sf_unit, sc->sf_pinfo->sf_name); 1132 } else { 1133 printf("sf%d: MII without any phy!\n", sc->sf_unit); 1134 free(sc->sf_ldata, M_DEVBUF); 1135 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand); 1136 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq); 1137 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 1138 error = ENXIO; 1139 goto fail; 1140 } 1141 1142 ifp = &sc->arpcom.ac_if; 1143 ifp->if_softc = sc; 1144 ifp->if_unit = unit; 1145 ifp->if_name = "sf"; 1146 ifp->if_mtu = ETHERMTU; 1147 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1148 ifp->if_ioctl = sf_ioctl; 1149 ifp->if_output = ether_output; 1150 ifp->if_start = sf_start; 1151 ifp->if_watchdog = sf_watchdog; 1152 ifp->if_init = sf_init; 1153 ifp->if_baudrate = 10000000; 1154 ifp->if_snd.ifq_maxlen = SF_TX_DLIST_CNT - 1; 1155 1156 /* 1157 * Do ifmedia setup. 1158 */ 1159 ifmedia_init(&sc->ifmedia, 0, sf_ifmedia_upd, sf_ifmedia_sts); 1160 1161 sf_getmode_mii(sc); 1162 if (cold) { 1163 sf_autoneg_mii(sc, SF_FLAG_FORCEDELAY, 1); 1164 sf_stop(sc); 1165 } else { 1166 sf_init(sc); 1167 sf_autoneg_mii(sc, SF_FLAG_SCHEDDELAY, 1); 1168 } 1169 1170 media = sc->ifmedia.ifm_media; 1171 ifmedia_set(&sc->ifmedia, media); 1172 1173 /* 1174 * Call MI attach routines. 1175 */ 1176 if_attach(ifp); 1177 ether_ifattach(ifp); 1178 1179#if NBPF > 0 1180 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header)); 1181#endif 1182 1183fail: 1184 splx(s); 1185 return(error); 1186} 1187 1188static int sf_detach(dev) 1189 device_t dev; 1190{ 1191 struct sf_softc *sc; 1192 struct ifnet *ifp; 1193 int s; 1194 1195 s = splimp(); 1196 1197 sc = device_get_softc(dev); 1198 ifp = &sc->arpcom.ac_if; 1199 1200 if_detach(ifp); 1201 sf_stop(sc); 1202 1203 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand); 1204 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq); 1205 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 1206 1207 free(sc->sf_ldata, M_DEVBUF); 1208 ifmedia_removeall(&sc->ifmedia); 1209 1210 splx(s); 1211 1212 return(0); 1213} 1214 1215static int sf_init_rx_ring(sc) 1216 struct sf_softc *sc; 1217{ 1218 struct sf_list_data *ld; 1219 int i; 1220 1221 ld = sc->sf_ldata; 1222 1223 bzero((char *)ld->sf_rx_dlist_big, 1224 sizeof(struct sf_rx_bufdesc_type0) * SF_RX_DLIST_CNT); 1225 bzero((char *)ld->sf_rx_clist, 1226 sizeof(struct sf_rx_cmpdesc_type3) * SF_RX_CLIST_CNT); 1227 1228 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 1229 if (sf_newbuf(sc, &ld->sf_rx_dlist_big[i], NULL) == ENOBUFS) 1230 return(ENOBUFS); 1231 } 1232 1233 return(0); 1234} 1235 1236static void sf_init_tx_ring(sc) 1237 struct sf_softc *sc; 1238{ 1239 struct sf_list_data *ld; 1240 int i; 1241 1242 ld = sc->sf_ldata; 1243 1244 bzero((char *)ld->sf_tx_dlist, 1245 sizeof(struct sf_tx_bufdesc_type0) * SF_TX_DLIST_CNT); 1246 bzero((char *)ld->sf_tx_clist, 1247 sizeof(struct sf_tx_cmpdesc_type0) * SF_TX_CLIST_CNT); 1248 1249 for (i = 0; i < SF_TX_DLIST_CNT; i++) 1250 ld->sf_tx_dlist[i].sf_id = SF_TX_BUFDESC_ID; 1251 for (i = 0; i < SF_TX_CLIST_CNT; i++) 1252 ld->sf_tx_clist[i].sf_type = SF_TXCMPTYPE_TX; 1253 1254 ld->sf_tx_dlist[SF_TX_DLIST_CNT - 1].sf_end = 1; 1255 sc->sf_tx_cnt = 0; 1256 1257 return; 1258} 1259 1260static int sf_newbuf(sc, c, m) 1261 struct sf_softc *sc; 1262 struct sf_rx_bufdesc_type0 *c; 1263 struct mbuf *m; 1264{ 1265 struct mbuf *m_new = NULL; 1266 1267 if (m == NULL) { 1268 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1269 if (m_new == NULL) { 1270 printf("sf%d: no memory for rx list -- " 1271 "packet dropped!\n", sc->sf_unit); 1272 return(ENOBUFS); 1273 } 1274 1275 MCLGET(m_new, M_DONTWAIT); 1276 if (!(m_new->m_flags & M_EXT)) { 1277 printf("sf%d: no memory for rx list -- " 1278 "packet dropped!\n", sc->sf_unit); 1279 m_freem(m_new); 1280 return(ENOBUFS); 1281 } 1282 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1283 } else { 1284 m_new = m; 1285 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1286 m_new->m_data = m_new->m_ext.ext_buf; 1287 } 1288 1289 m_adj(m_new, sizeof(u_int64_t)); 1290 1291 c->sf_mbuf = m_new; 1292 c->sf_addrlo = SF_RX_HOSTADDR(vtophys(mtod(m_new, caddr_t))); 1293 c->sf_valid = 1; 1294 1295 return(0); 1296} 1297 1298/* 1299 * The starfire is programmed to use 'normal' mode for packet reception, 1300 * which means we use the consumer/producer model for both the buffer 1301 * descriptor queue and the completion descriptor queue. The only problem 1302 * with this is that it involves a lot of register accesses: we have to 1303 * read the RX completion consumer and producer indexes and the RX buffer 1304 * producer index, plus the RX completion consumer and RX buffer producer 1305 * indexes have to be updated. It would have been easier if Adaptec had 1306 * put each index in a separate register, especially given that the damn 1307 * NIC has a 512K register space. 1308 * 1309 * In spite of all the lovely features that Adaptec crammed into the 6915, 1310 * it is marred by one truly stupid design flaw, which is that receive 1311 * buffer addresses must be aligned on a longword boundary. This forces 1312 * the packet payload to be unaligned, which is suboptimal on the x86 and 1313 * completely unuseable on the Alpha. Our only recourse is to copy received 1314 * packets into properly aligned buffers before handing them off. 1315 */ 1316 1317static void sf_rxeof(sc) 1318 struct sf_softc *sc; 1319{ 1320 struct ether_header *eh; 1321 struct mbuf *m; 1322 struct ifnet *ifp; 1323 struct sf_rx_bufdesc_type0 *desc; 1324 struct sf_rx_cmpdesc_type3 *cur_rx; 1325 u_int32_t rxcons, rxprod; 1326 int cmpprodidx, cmpconsidx, bufprodidx; 1327 1328 ifp = &sc->arpcom.ac_if; 1329 1330 rxcons = csr_read_4(sc, SF_CQ_CONSIDX); 1331 rxprod = csr_read_4(sc, SF_RXDQ_PTR_Q1); 1332 cmpprodidx = SF_IDX_LO(csr_read_4(sc, SF_CQ_PRODIDX)); 1333 cmpconsidx = SF_IDX_LO(rxcons); 1334 bufprodidx = SF_IDX_LO(rxprod); 1335 1336 while (cmpconsidx != cmpprodidx) { 1337 struct mbuf *m0; 1338 1339 cur_rx = &sc->sf_ldata->sf_rx_clist[cmpconsidx]; 1340 desc = &sc->sf_ldata->sf_rx_dlist_big[cur_rx->sf_endidx]; 1341 m = desc->sf_mbuf; 1342 SF_INC(cmpconsidx, SF_RX_CLIST_CNT); 1343 SF_INC(bufprodidx, SF_RX_DLIST_CNT); 1344 1345 if (!(cur_rx->sf_status1 & SF_RXSTAT1_OK)) { 1346 ifp->if_ierrors++; 1347 sf_newbuf(sc, desc, m); 1348 continue; 1349 } 1350 1351 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1352 cur_rx->sf_len + ETHER_ALIGN, 0, ifp, NULL); 1353 sf_newbuf(sc, desc, m); 1354 if (m0 == NULL) { 1355 ifp->if_ierrors++; 1356 continue; 1357 } 1358 m_adj(m0, ETHER_ALIGN); 1359 m = m0; 1360 1361 eh = mtod(m, struct ether_header *); 1362 ifp->if_ipackets++; 1363 1364#if NBPF > 0 1365 if (ifp->if_bpf) { 1366 bpf_mtap(ifp, m); 1367 if (ifp->if_flags & IFF_PROMISC && 1368 (bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr, 1369 ETHER_ADDR_LEN) && !(eh->ether_dhost[0] & 1))) { 1370 m_freem(m); 1371 continue; 1372 } 1373 } 1374#endif 1375 1376 /* Remove header from mbuf and pass it on. */ 1377 m_adj(m, sizeof(struct ether_header)); 1378 ether_input(ifp, eh, m); 1379 1380 } 1381 1382 csr_write_4(sc, SF_CQ_CONSIDX, 1383 (rxcons & ~SF_CQ_CONSIDX_RXQ1) | cmpconsidx); 1384 csr_write_4(sc, SF_RXDQ_PTR_Q1, 1385 (rxprod & ~SF_RXDQ_PRODIDX) | bufprodidx); 1386 1387 return; 1388} 1389 1390/* 1391 * Read the transmit status from the completion queue and release 1392 * mbufs. Note that the buffer descriptor index in the completion 1393 * descriptor is an offset from the start of the transmit buffer 1394 * descriptor list in bytes. This is important because the manual 1395 * gives the impression that it should match the producer/consumer 1396 * index, which is the offset in 8 byte blocks. 1397 */ 1398static void sf_txeof(sc) 1399 struct sf_softc *sc; 1400{ 1401 int txcons, cmpprodidx, cmpconsidx; 1402 struct sf_tx_cmpdesc_type1 *cur_cmp; 1403 struct sf_tx_bufdesc_type0 *cur_tx; 1404 struct ifnet *ifp; 1405 1406 ifp = &sc->arpcom.ac_if; 1407 1408 txcons = csr_read_4(sc, SF_CQ_CONSIDX); 1409 cmpprodidx = SF_IDX_HI(csr_read_4(sc, SF_CQ_PRODIDX)); 1410 cmpconsidx = SF_IDX_HI(txcons); 1411 1412 while (cmpconsidx != cmpprodidx) { 1413 cur_cmp = &sc->sf_ldata->sf_tx_clist[cmpconsidx]; 1414 cur_tx = &sc->sf_ldata->sf_tx_dlist[cur_cmp->sf_index >> 7]; 1415 SF_INC(cmpconsidx, SF_TX_CLIST_CNT); 1416 1417 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_OK) 1418 ifp->if_opackets++; 1419 else 1420 ifp->if_oerrors++; 1421 1422 sc->sf_tx_cnt--; 1423 if (cur_tx->sf_mbuf != NULL) { 1424 m_freem(cur_tx->sf_mbuf); 1425 cur_tx->sf_mbuf = NULL; 1426 } 1427 } 1428 1429 ifp->if_timer = 0; 1430 ifp->if_flags &= ~IFF_OACTIVE; 1431 1432 csr_write_4(sc, SF_CQ_CONSIDX, 1433 (txcons & ~SF_CQ_CONSIDX_TXQ) | 1434 ((cmpconsidx << 16) & 0xFFFF0000)); 1435 1436 return; 1437} 1438 1439static void sf_intr(arg) 1440 void *arg; 1441{ 1442 struct sf_softc *sc; 1443 struct ifnet *ifp; 1444 u_int32_t status; 1445 1446 sc = arg; 1447 ifp = &sc->arpcom.ac_if; 1448 1449 if (!(csr_read_4(sc, SF_ISR_SHADOW) & SF_ISR_PCIINT_ASSERTED)) 1450 return; 1451 1452 /* Disable interrupts. */ 1453 csr_write_4(sc, SF_IMR, 0x00000000); 1454 1455 for (;;) { 1456 status = csr_read_4(sc, SF_ISR); 1457 if (status) 1458 csr_write_4(sc, SF_ISR, status); 1459 1460 if (!(status & SF_INTRS)) 1461 break; 1462 1463 if (status & SF_ISR_RXDQ1_DMADONE) 1464 sf_rxeof(sc); 1465 1466 if (status & SF_ISR_TX_TXDONE) 1467 sf_txeof(sc); 1468 1469 if (status & SF_ISR_ABNORMALINTR) { 1470 if (status & SF_ISR_STATSOFLOW) { 1471 untimeout(sf_stats_update, sc, 1472 sc->sf_stat_ch); 1473 sf_stats_update(sc); 1474 } else 1475 sf_init(sc); 1476 } 1477 } 1478 1479 /* Re-enable interrupts. */ 1480 csr_write_4(sc, SF_IMR, SF_INTRS); 1481 1482 if (ifp->if_snd.ifq_head != NULL) 1483 sf_start(ifp); 1484 1485 return; 1486} 1487 1488static void sf_init(xsc) 1489 void *xsc; 1490{ 1491 struct sf_softc *sc; 1492 struct ifnet *ifp; 1493 int i, s; 1494 1495 s = splimp(); 1496 1497 sc = xsc; 1498 ifp = &sc->arpcom.ac_if; 1499 1500 sf_stop(sc); 1501 sf_reset(sc); 1502 1503 /* Init all the receive filter registers */ 1504 for (i = SF_RXFILT_PERFECT_BASE; 1505 i < (SF_RXFILT_HASH_MAX + 1); i += 4) 1506 csr_write_4(sc, i, 0); 1507 1508 /* Empty stats counter registers. */ 1509 for (i = 0; i < sizeof(struct sf_stats)/sizeof(u_int32_t); i++) 1510 csr_write_4(sc, SF_STATS_BASE + 1511 (i + sizeof(u_int32_t)), 0); 1512 1513 /* Init our MAC address */ 1514 csr_write_4(sc, SF_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1515 csr_write_4(sc, SF_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1516 sf_setperf(sc, 0, (caddr_t)&sc->arpcom.ac_enaddr); 1517 1518 if (sf_init_rx_ring(sc) == ENOBUFS) { 1519 printf("sf%d: initialization failed: no " 1520 "memory for rx buffers\n", sc->sf_unit); 1521 (void)splx(s); 1522 return; 1523 } 1524 1525 sf_init_tx_ring(sc); 1526 1527 csr_write_4(sc, SF_RXFILT, SF_PERFMODE_NORMAL|SF_HASHMODE_WITHVLAN); 1528 1529 /* If we want promiscuous mode, set the allframes bit. */ 1530 if (ifp->if_flags & IFF_PROMISC) { 1531 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 1532 } else { 1533 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 1534 } 1535 1536 if (ifp->if_flags & IFF_BROADCAST) { 1537 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_BROAD); 1538 } else { 1539 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_BROAD); 1540 } 1541 1542 /* Init the completion queue indexes */ 1543 csr_write_4(sc, SF_CQ_CONSIDX, 0); 1544 csr_write_4(sc, SF_CQ_PRODIDX, 0); 1545 1546 /* Init the RX completion queue */ 1547 csr_write_4(sc, SF_RXCQ_CTL_1, 1548 vtophys(sc->sf_ldata->sf_rx_clist) & SF_RXCQ_ADDR); 1549 SF_SETBIT(sc, SF_RXCQ_CTL_1, SF_RXCQTYPE_3); 1550 1551 /* Init RX DMA control. */ 1552 SF_SETBIT(sc, SF_RXDMA_CTL, SF_RXDMA_REPORTBADPKTS); 1553 1554 /* Init the RX buffer descriptor queue. */ 1555 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 1556 vtophys(sc->sf_ldata->sf_rx_dlist_big)); 1557 csr_write_4(sc, SF_RXDQ_CTL_1, (MCLBYTES << 16) | SF_DESCSPACE_16BYTES); 1558 csr_write_4(sc, SF_RXDQ_PTR_Q1, SF_RX_DLIST_CNT - 1); 1559 1560 /* Init the TX completion queue */ 1561 csr_write_4(sc, SF_TXCQ_CTL, 1562 vtophys(sc->sf_ldata->sf_tx_clist) & SF_RXCQ_ADDR); 1563 1564 /* Init the TX buffer descriptor queue. */ 1565 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 1566 vtophys(sc->sf_ldata->sf_tx_dlist)); 1567 SF_SETBIT(sc, SF_TX_FRAMCTL, SF_TXFRMCTL_CPLAFTERTX); 1568 csr_write_4(sc, SF_TXDQ_CTL, 1569 SF_TXBUFDESC_TYPE0|SF_TXMINSPACE_128BYTES|SF_TXSKIPLEN_8BYTES); 1570 SF_SETBIT(sc, SF_TXDQ_CTL, SF_TXDQCTL_NODMACMP); 1571 1572 /* Enable autopadding of short TX frames. */ 1573 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_AUTOPAD); 1574 1575 /* Make sure the duplex mode is set correctly. */ 1576 if ((sc->ifmedia.ifm_media & IFM_GMASK) == IFM_FDX) { 1577 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 1578 } else { 1579 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 1580 } 1581 1582 /* Enable interrupts. */ 1583 csr_write_4(sc, SF_IMR, SF_INTRS); 1584 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_INTR_ENB); 1585 1586 /* Enable the RX and TX engines. */ 1587 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_RX_ENB|SF_ETHCTL_RXDMA_ENB); 1588 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_TX_ENB|SF_ETHCTL_TXDMA_ENB); 1589 1590 ifp->if_flags |= IFF_RUNNING; 1591 ifp->if_flags &= ~IFF_OACTIVE; 1592 1593 sc->sf_stat_ch = timeout(sf_stats_update, sc, hz); 1594 1595 splx(s); 1596 1597 return; 1598} 1599 1600static int sf_encap(sc, c, m_head) 1601 struct sf_softc *sc; 1602 struct sf_tx_bufdesc_type0 *c; 1603 struct mbuf *m_head; 1604{ 1605 int frag = 0; 1606 struct sf_frag *f = NULL; 1607 struct mbuf *m; 1608 1609 m = m_head; 1610 1611 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1612 if (m->m_len != 0) { 1613 if (frag == SF_MAXFRAGS) 1614 break; 1615 f = &c->sf_frags[frag]; 1616 if (frag == 0) 1617 f->sf_pktlen = m_head->m_pkthdr.len; 1618 f->sf_fraglen = m->m_len; 1619 f->sf_addr = vtophys(mtod(m, vm_offset_t)); 1620 frag++; 1621 } 1622 } 1623 1624 if (m != NULL) { 1625 struct mbuf *m_new = NULL; 1626 1627 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1628 if (m_new == NULL) { 1629 printf("sf%d: no memory for tx list", sc->sf_unit); 1630 return(1); 1631 } 1632 1633 if (m_head->m_pkthdr.len > MHLEN) { 1634 MCLGET(m_new, M_DONTWAIT); 1635 if (!(m_new->m_flags & M_EXT)) { 1636 m_freem(m_new); 1637 printf("sf%d: no memory for tx list", 1638 sc->sf_unit); 1639 return(1); 1640 } 1641 } 1642 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1643 mtod(m_new, caddr_t)); 1644 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1645 m_freem(m_head); 1646 m_head = m_new; 1647 f = &c->sf_frags[0]; 1648 f->sf_fraglen = f->sf_pktlen = m_head->m_pkthdr.len; 1649 f->sf_addr = vtophys(mtod(m_head, caddr_t)); 1650 frag = 1; 1651 } 1652 1653 c->sf_mbuf = m_head; 1654 c->sf_id = SF_TX_BUFDESC_ID; 1655 c->sf_fragcnt = frag; 1656 c->sf_intr = 1; 1657 c->sf_caltcp = 0; 1658 c->sf_crcen = 1; 1659 1660 return(0); 1661} 1662 1663static void sf_start(ifp) 1664 struct ifnet *ifp; 1665{ 1666 struct sf_softc *sc; 1667 struct sf_tx_bufdesc_type0 *cur_tx = NULL; 1668 struct mbuf *m_head = NULL; 1669 int i, txprod; 1670 1671 sc = ifp->if_softc; 1672 1673 if (ifp->if_flags & IFF_OACTIVE) 1674 return; 1675 1676 if (sc->sf_autoneg) { 1677 sc->sf_tx_pend = 1; 1678 return; 1679 } 1680 1681 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX); 1682 i = SF_IDX_HI(txprod) >> 4; 1683 1684 while(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf == NULL) { 1685 IF_DEQUEUE(&ifp->if_snd, m_head); 1686 if (m_head == NULL) 1687 break; 1688 1689 cur_tx = &sc->sf_ldata->sf_tx_dlist[i]; 1690 sf_encap(sc, cur_tx, m_head); 1691 1692 /* 1693 * If there's a BPF listener, bounce a copy of this frame 1694 * to him. 1695 */ 1696#if NBPF > 0 1697 if (ifp->if_bpf) 1698 bpf_mtap(ifp, m_head); 1699#endif 1700 SF_INC(i, SF_TX_DLIST_CNT); 1701 sc->sf_tx_cnt++; 1702 if (sc->sf_tx_cnt == (SF_TX_DLIST_CNT - 2)) 1703 break; 1704 } 1705 1706 if (cur_tx == NULL) 1707 return; 1708 1709 /* Transmit */ 1710 csr_write_4(sc, SF_TXDQ_PRODIDX, 1711 (txprod & ~SF_TXDQ_PRODIDX_HIPRIO) | 1712 ((i << 20) & 0xFFFF0000)); 1713 1714 ifp->if_timer = 5; 1715 1716 return; 1717} 1718 1719static void sf_stop(sc) 1720 struct sf_softc *sc; 1721{ 1722 int i; 1723 1724 untimeout(sf_stats_update, sc, sc->sf_stat_ch); 1725 1726 csr_write_4(sc, SF_GEN_ETH_CTL, 0); 1727 csr_write_4(sc, SF_CQ_CONSIDX, 0); 1728 csr_write_4(sc, SF_CQ_PRODIDX, 0); 1729 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 0); 1730 csr_write_4(sc, SF_RXDQ_CTL_1, 0); 1731 csr_write_4(sc, SF_RXDQ_PTR_Q1, 0); 1732 csr_write_4(sc, SF_TXCQ_CTL, 0); 1733 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 0); 1734 csr_write_4(sc, SF_TXDQ_CTL, 0); 1735 sf_reset(sc); 1736 1737 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 1738 if (sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf != NULL) { 1739 m_freem(sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf); 1740 sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf = NULL; 1741 } 1742 } 1743 1744 for (i = 0; i < SF_TX_DLIST_CNT; i++) { 1745 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) { 1746 m_freem(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf); 1747 sc->sf_ldata->sf_tx_dlist[i].sf_mbuf = NULL; 1748 } 1749 } 1750 1751 return; 1752} 1753 1754/* 1755 * Note: it is important that this function not be interrupted. We 1756 * use a two-stage register access scheme: if we are interrupted in 1757 * between setting the indirect address register and reading from the 1758 * indirect data register, the contents of the address register could 1759 * be changed out from under us. 1760 */ 1761static void sf_stats_update(xsc) 1762 void *xsc; 1763{ 1764 struct sf_softc *sc; 1765 struct ifnet *ifp; 1766 struct sf_stats stats; 1767 u_int32_t *ptr; 1768 int i, s; 1769 1770 s = splimp(); 1771 1772 sc = xsc; 1773 ifp = &sc->arpcom.ac_if; 1774 1775 ptr = (u_int32_t *)&stats; 1776 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++) 1777 ptr[i] = csr_read_4(sc, SF_STATS_BASE + 1778 (i + sizeof(u_int32_t))); 1779 1780 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++) 1781 csr_write_4(sc, SF_STATS_BASE + 1782 (i + sizeof(u_int32_t)), 0); 1783 1784 ifp->if_collisions += stats.sf_tx_single_colls + 1785 stats.sf_tx_multi_colls + stats.sf_tx_excess_colls; 1786 1787 sc->sf_stat_ch = timeout(sf_stats_update, sc, hz); 1788 1789 splx(s); 1790 1791 return; 1792} 1793 1794static void sf_watchdog(ifp) 1795 struct ifnet *ifp; 1796{ 1797 struct sf_softc *sc; 1798 1799 sc = ifp->if_softc; 1800 1801 if (sc->sf_autoneg) { 1802 sf_autoneg_mii(sc, SF_FLAG_DELAYTIMEO, 1); 1803 if (!(ifp->if_flags & IFF_UP)) 1804 sf_stop(sc); 1805 return; 1806 } 1807 1808 ifp->if_oerrors++; 1809 printf("sf%d: watchdog timeout\n", sc->sf_unit); 1810 1811 if (sc->sf_pinfo != NULL) { 1812 if (!(sf_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT)) 1813 printf("sf%d: no carrier - transceiver " 1814 "cable problem?\n", sc->sf_unit); 1815 } 1816 1817 sf_stop(sc); 1818 sf_reset(sc); 1819 sf_init(sc); 1820 1821 if (ifp->if_snd.ifq_head != NULL) 1822 sf_start(ifp); 1823 1824 return; 1825} 1826 1827static void sf_shutdown(dev) 1828 device_t dev; 1829{ 1830 struct sf_softc *sc; 1831 1832 sc = device_get_softc(dev); 1833 1834 sf_stop(sc); 1835 1836 return; 1837} 1838