if_sf.c revision 232025
1/*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/sf/if_sf.c 232025 2012-02-23 05:23:21Z yongari $"); 35 36/* 37 * Adaptec AIC-6915 "Starfire" PCI fast ethernet driver for FreeBSD. 38 * Programming manual is available from: 39 * http://download.adaptec.com/pdfs/user_guides/aic6915_pg.pdf. 40 * 41 * Written by Bill Paul <wpaul@ctr.columbia.edu> 42 * Department of Electical Engineering 43 * Columbia University, New York City 44 */ 45/* 46 * The Adaptec AIC-6915 "Starfire" is a 64-bit 10/100 PCI ethernet 47 * controller designed with flexibility and reducing CPU load in mind. 48 * The Starfire offers high and low priority buffer queues, a 49 * producer/consumer index mechanism and several different buffer 50 * queue and completion queue descriptor types. Any one of a number 51 * of different driver designs can be used, depending on system and 52 * OS requirements. This driver makes use of type2 transmit frame 53 * descriptors to take full advantage of fragmented packets buffers 54 * and two RX buffer queues prioritized on size (one queue for small 55 * frames that will fit into a single mbuf, another with full size 56 * mbuf clusters for everything else). The producer/consumer indexes 57 * and completion queues are also used. 58 * 59 * One downside to the Starfire has to do with alignment: buffer 60 * queues must be aligned on 256-byte boundaries, and receive buffers 61 * must be aligned on longword boundaries. The receive buffer alignment 62 * causes problems on the strict alignment architecture, where the 63 * packet payload should be longword aligned. There is no simple way 64 * around this. 65 * 66 * For receive filtering, the Starfire offers 16 perfect filter slots 67 * and a 512-bit hash table. 68 * 69 * The Starfire has no internal transceiver, relying instead on an 70 * external MII-based transceiver. Accessing registers on external 71 * PHYs is done through a special register map rather than with the 72 * usual bitbang MDIO method. 73 * 74 * Acesssing the registers on the Starfire is a little tricky. The 75 * Starfire has a 512K internal register space. When programmed for 76 * PCI memory mapped mode, the entire register space can be accessed 77 * directly. However in I/O space mode, only 256 bytes are directly 78 * mapped into PCI I/O space. The other registers can be accessed 79 * indirectly using the SF_INDIRECTIO_ADDR and SF_INDIRECTIO_DATA 80 * registers inside the 256-byte I/O window. 81 */ 82 83#ifdef HAVE_KERNEL_OPTION_HEADERS 84#include "opt_device_polling.h" 85#endif 86 87#include <sys/param.h> 88#include <sys/systm.h> 89#include <sys/bus.h> 90#include <sys/endian.h> 91#include <sys/kernel.h> 92#include <sys/malloc.h> 93#include <sys/mbuf.h> 94#include <sys/rman.h> 95#include <sys/module.h> 96#include <sys/socket.h> 97#include <sys/sockio.h> 98#include <sys/sysctl.h> 99#include <sys/taskqueue.h> 100 101#include <net/bpf.h> 102#include <net/if.h> 103#include <net/if_arp.h> 104#include <net/ethernet.h> 105#include <net/if_dl.h> 106#include <net/if_media.h> 107#include <net/if_types.h> 108#include <net/if_vlan_var.h> 109 110#include <dev/mii/mii.h> 111#include <dev/mii/miivar.h> 112 113#include <dev/pci/pcireg.h> 114#include <dev/pci/pcivar.h> 115 116#include <machine/bus.h> 117 118#include <dev/sf/if_sfreg.h> 119#include <dev/sf/starfire_rx.h> 120#include <dev/sf/starfire_tx.h> 121 122/* "device miibus" required. See GENERIC if you get errors here. */ 123#include "miibus_if.h" 124 125MODULE_DEPEND(sf, pci, 1, 1, 1); 126MODULE_DEPEND(sf, ether, 1, 1, 1); 127MODULE_DEPEND(sf, miibus, 1, 1, 1); 128 129#undef SF_GFP_DEBUG 130#define SF_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 131/* Define this to activate partial TCP/UDP checksum offload. */ 132#undef SF_PARTIAL_CSUM_SUPPORT 133 134static struct sf_type sf_devs[] = { 135 { AD_VENDORID, AD_DEVICEID_STARFIRE, "Adaptec AIC-6915 10/100BaseTX", 136 AD_SUBSYSID_62011_REV0, "Adaptec ANA-62011 (rev 0) 10/100BaseTX" }, 137 { AD_VENDORID, AD_DEVICEID_STARFIRE, "Adaptec AIC-6915 10/100BaseTX", 138 AD_SUBSYSID_62011_REV1, "Adaptec ANA-62011 (rev 1) 10/100BaseTX" }, 139 { AD_VENDORID, AD_DEVICEID_STARFIRE, "Adaptec AIC-6915 10/100BaseTX", 140 AD_SUBSYSID_62022, "Adaptec ANA-62022 10/100BaseTX" }, 141 { AD_VENDORID, AD_DEVICEID_STARFIRE, "Adaptec AIC-6915 10/100BaseTX", 142 AD_SUBSYSID_62044_REV0, "Adaptec ANA-62044 (rev 0) 10/100BaseTX" }, 143 { AD_VENDORID, AD_DEVICEID_STARFIRE, "Adaptec AIC-6915 10/100BaseTX", 144 AD_SUBSYSID_62044_REV1, "Adaptec ANA-62044 (rev 1) 10/100BaseTX" }, 145 { AD_VENDORID, AD_DEVICEID_STARFIRE, "Adaptec AIC-6915 10/100BaseTX", 146 AD_SUBSYSID_62020, "Adaptec ANA-62020 10/100BaseFX" }, 147 { AD_VENDORID, AD_DEVICEID_STARFIRE, "Adaptec AIC-6915 10/100BaseTX", 148 AD_SUBSYSID_69011, "Adaptec ANA-69011 10/100BaseTX" }, 149}; 150 151static int sf_probe(device_t); 152static int sf_attach(device_t); 153static int sf_detach(device_t); 154static int sf_shutdown(device_t); 155static int sf_suspend(device_t); 156static int sf_resume(device_t); 157static void sf_intr(void *); 158static void sf_tick(void *); 159static void sf_stats_update(struct sf_softc *); 160#ifndef __NO_STRICT_ALIGNMENT 161static __inline void sf_fixup_rx(struct mbuf *); 162#endif 163static int sf_rxeof(struct sf_softc *); 164static void sf_txeof(struct sf_softc *); 165static int sf_encap(struct sf_softc *, struct mbuf **); 166static void sf_start(struct ifnet *); 167static void sf_start_locked(struct ifnet *); 168static int sf_ioctl(struct ifnet *, u_long, caddr_t); 169static void sf_download_fw(struct sf_softc *); 170static void sf_init(void *); 171static void sf_init_locked(struct sf_softc *); 172static void sf_stop(struct sf_softc *); 173static void sf_watchdog(struct sf_softc *); 174static int sf_ifmedia_upd(struct ifnet *); 175static int sf_ifmedia_upd_locked(struct ifnet *); 176static void sf_ifmedia_sts(struct ifnet *, struct ifmediareq *); 177static void sf_reset(struct sf_softc *); 178static int sf_dma_alloc(struct sf_softc *); 179static void sf_dma_free(struct sf_softc *); 180static int sf_init_rx_ring(struct sf_softc *); 181static void sf_init_tx_ring(struct sf_softc *); 182static int sf_newbuf(struct sf_softc *, int); 183static void sf_rxfilter(struct sf_softc *); 184static int sf_setperf(struct sf_softc *, int, uint8_t *); 185static int sf_sethash(struct sf_softc *, caddr_t, int); 186#ifdef notdef 187static int sf_setvlan(struct sf_softc *, int, uint32_t); 188#endif 189 190static uint8_t sf_read_eeprom(struct sf_softc *, int); 191 192static int sf_miibus_readreg(device_t, int, int); 193static int sf_miibus_writereg(device_t, int, int, int); 194static void sf_miibus_statchg(device_t); 195static void sf_link_task(void *, int); 196#ifdef DEVICE_POLLING 197static int sf_poll(struct ifnet *ifp, enum poll_cmd cmd, int count); 198#endif 199 200static uint32_t csr_read_4(struct sf_softc *, int); 201static void csr_write_4(struct sf_softc *, int, uint32_t); 202static void sf_txthresh_adjust(struct sf_softc *); 203static int sf_sysctl_stats(SYSCTL_HANDLER_ARGS); 204static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 205static int sysctl_hw_sf_int_mod(SYSCTL_HANDLER_ARGS); 206 207static device_method_t sf_methods[] = { 208 /* Device interface */ 209 DEVMETHOD(device_probe, sf_probe), 210 DEVMETHOD(device_attach, sf_attach), 211 DEVMETHOD(device_detach, sf_detach), 212 DEVMETHOD(device_shutdown, sf_shutdown), 213 DEVMETHOD(device_suspend, sf_suspend), 214 DEVMETHOD(device_resume, sf_resume), 215 216 /* MII interface */ 217 DEVMETHOD(miibus_readreg, sf_miibus_readreg), 218 DEVMETHOD(miibus_writereg, sf_miibus_writereg), 219 DEVMETHOD(miibus_statchg, sf_miibus_statchg), 220 221 DEVMETHOD_END 222}; 223 224static driver_t sf_driver = { 225 "sf", 226 sf_methods, 227 sizeof(struct sf_softc), 228}; 229 230static devclass_t sf_devclass; 231 232DRIVER_MODULE(sf, pci, sf_driver, sf_devclass, 0, 0); 233DRIVER_MODULE(miibus, sf, miibus_driver, miibus_devclass, 0, 0); 234 235#define SF_SETBIT(sc, reg, x) \ 236 csr_write_4(sc, reg, csr_read_4(sc, reg) | (x)) 237 238#define SF_CLRBIT(sc, reg, x) \ 239 csr_write_4(sc, reg, csr_read_4(sc, reg) & ~(x)) 240 241static uint32_t 242csr_read_4(struct sf_softc *sc, int reg) 243{ 244 uint32_t val; 245 246 if (sc->sf_restype == SYS_RES_MEMORY) 247 val = CSR_READ_4(sc, (reg + SF_RMAP_INTREG_BASE)); 248 else { 249 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); 250 val = CSR_READ_4(sc, SF_INDIRECTIO_DATA); 251 } 252 253 return (val); 254} 255 256static uint8_t 257sf_read_eeprom(struct sf_softc *sc, int reg) 258{ 259 uint8_t val; 260 261 val = (csr_read_4(sc, SF_EEADDR_BASE + 262 (reg & 0xFFFFFFFC)) >> (8 * (reg & 3))) & 0xFF; 263 264 return (val); 265} 266 267static void 268csr_write_4(struct sf_softc *sc, int reg, uint32_t val) 269{ 270 271 if (sc->sf_restype == SYS_RES_MEMORY) 272 CSR_WRITE_4(sc, (reg + SF_RMAP_INTREG_BASE), val); 273 else { 274 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); 275 CSR_WRITE_4(sc, SF_INDIRECTIO_DATA, val); 276 } 277} 278 279/* 280 * Copy the address 'mac' into the perfect RX filter entry at 281 * offset 'idx.' The perfect filter only has 16 entries so do 282 * some sanity tests. 283 */ 284static int 285sf_setperf(struct sf_softc *sc, int idx, uint8_t *mac) 286{ 287 288 if (idx < 0 || idx > SF_RXFILT_PERFECT_CNT) 289 return (EINVAL); 290 291 if (mac == NULL) 292 return (EINVAL); 293 294 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 295 (idx * SF_RXFILT_PERFECT_SKIP) + 0, mac[5] | (mac[4] << 8)); 296 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 297 (idx * SF_RXFILT_PERFECT_SKIP) + 4, mac[3] | (mac[2] << 8)); 298 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 299 (idx * SF_RXFILT_PERFECT_SKIP) + 8, mac[1] | (mac[0] << 8)); 300 301 return (0); 302} 303 304/* 305 * Set the bit in the 512-bit hash table that corresponds to the 306 * specified mac address 'mac.' If 'prio' is nonzero, update the 307 * priority hash table instead of the filter hash table. 308 */ 309static int 310sf_sethash(struct sf_softc *sc, caddr_t mac, int prio) 311{ 312 uint32_t h; 313 314 if (mac == NULL) 315 return (EINVAL); 316 317 h = ether_crc32_be(mac, ETHER_ADDR_LEN) >> 23; 318 319 if (prio) { 320 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_PRIOOFF + 321 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); 322 } else { 323 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_ADDROFF + 324 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); 325 } 326 327 return (0); 328} 329 330#ifdef notdef 331/* 332 * Set a VLAN tag in the receive filter. 333 */ 334static int 335sf_setvlan(struct sf_softc *sc, int idx, uint32_t vlan) 336{ 337 338 if (idx < 0 || idx >> SF_RXFILT_HASH_CNT) 339 return (EINVAL); 340 341 csr_write_4(sc, SF_RXFILT_HASH_BASE + 342 (idx * SF_RXFILT_HASH_SKIP) + SF_RXFILT_HASH_VLANOFF, vlan); 343 344 return (0); 345} 346#endif 347 348static int 349sf_miibus_readreg(device_t dev, int phy, int reg) 350{ 351 struct sf_softc *sc; 352 int i; 353 uint32_t val = 0; 354 355 sc = device_get_softc(dev); 356 357 for (i = 0; i < SF_TIMEOUT; i++) { 358 val = csr_read_4(sc, SF_PHY_REG(phy, reg)); 359 if ((val & SF_MII_DATAVALID) != 0) 360 break; 361 } 362 363 if (i == SF_TIMEOUT) 364 return (0); 365 366 val &= SF_MII_DATAPORT; 367 if (val == 0xffff) 368 return (0); 369 370 return (val); 371} 372 373static int 374sf_miibus_writereg(device_t dev, int phy, int reg, int val) 375{ 376 struct sf_softc *sc; 377 int i; 378 int busy; 379 380 sc = device_get_softc(dev); 381 382 csr_write_4(sc, SF_PHY_REG(phy, reg), val); 383 384 for (i = 0; i < SF_TIMEOUT; i++) { 385 busy = csr_read_4(sc, SF_PHY_REG(phy, reg)); 386 if ((busy & SF_MII_BUSY) == 0) 387 break; 388 } 389 390 return (0); 391} 392 393static void 394sf_miibus_statchg(device_t dev) 395{ 396 struct sf_softc *sc; 397 398 sc = device_get_softc(dev); 399 taskqueue_enqueue(taskqueue_swi, &sc->sf_link_task); 400} 401 402static void 403sf_link_task(void *arg, int pending) 404{ 405 struct sf_softc *sc; 406 struct mii_data *mii; 407 struct ifnet *ifp; 408 uint32_t val; 409 410 sc = (struct sf_softc *)arg; 411 412 SF_LOCK(sc); 413 414 mii = device_get_softc(sc->sf_miibus); 415 ifp = sc->sf_ifp; 416 if (mii == NULL || ifp == NULL || 417 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 418 SF_UNLOCK(sc); 419 return; 420 } 421 422 if (mii->mii_media_status & IFM_ACTIVE) { 423 if (IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 424 sc->sf_link = 1; 425 } else 426 sc->sf_link = 0; 427 428 val = csr_read_4(sc, SF_MACCFG_1); 429 val &= ~SF_MACCFG1_FULLDUPLEX; 430 val &= ~(SF_MACCFG1_RX_FLOWENB | SF_MACCFG1_TX_FLOWENB); 431 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 432 val |= SF_MACCFG1_FULLDUPLEX; 433 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_FDX); 434#ifdef notyet 435 /* Configure flow-control bits. */ 436 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & 437 IFM_ETH_RXPAUSE) != 0) 438 val |= SF_MACCFG1_RX_FLOWENB; 439 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & 440 IFM_ETH_TXPAUSE) != 0) 441 val |= SF_MACCFG1_TX_FLOWENB; 442#endif 443 } else 444 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_HDX); 445 446 /* Make sure to reset MAC to take changes effect. */ 447 csr_write_4(sc, SF_MACCFG_1, val | SF_MACCFG1_SOFTRESET); 448 DELAY(1000); 449 csr_write_4(sc, SF_MACCFG_1, val); 450 451 val = csr_read_4(sc, SF_TIMER_CTL); 452 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) 453 val |= SF_TIMER_TIMES_TEN; 454 else 455 val &= ~SF_TIMER_TIMES_TEN; 456 csr_write_4(sc, SF_TIMER_CTL, val); 457 458 SF_UNLOCK(sc); 459} 460 461static void 462sf_rxfilter(struct sf_softc *sc) 463{ 464 struct ifnet *ifp; 465 int i; 466 struct ifmultiaddr *ifma; 467 uint8_t dummy[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 }; 468 uint32_t rxfilt; 469 470 ifp = sc->sf_ifp; 471 472 /* First zot all the existing filters. */ 473 for (i = 1; i < SF_RXFILT_PERFECT_CNT; i++) 474 sf_setperf(sc, i, dummy); 475 for (i = SF_RXFILT_HASH_BASE; i < (SF_RXFILT_HASH_MAX + 1); 476 i += sizeof(uint32_t)) 477 csr_write_4(sc, i, 0); 478 479 rxfilt = csr_read_4(sc, SF_RXFILT); 480 rxfilt &= ~(SF_RXFILT_PROMISC | SF_RXFILT_ALLMULTI | SF_RXFILT_BROAD); 481 if ((ifp->if_flags & IFF_BROADCAST) != 0) 482 rxfilt |= SF_RXFILT_BROAD; 483 if ((ifp->if_flags & IFF_ALLMULTI) != 0 || 484 (ifp->if_flags & IFF_PROMISC) != 0) { 485 if ((ifp->if_flags & IFF_PROMISC) != 0) 486 rxfilt |= SF_RXFILT_PROMISC; 487 if ((ifp->if_flags & IFF_ALLMULTI) != 0) 488 rxfilt |= SF_RXFILT_ALLMULTI; 489 goto done; 490 } 491 492 /* Now program new ones. */ 493 i = 1; 494 if_maddr_rlock(ifp); 495 TAILQ_FOREACH_REVERSE(ifma, &ifp->if_multiaddrs, ifmultihead, 496 ifma_link) { 497 if (ifma->ifma_addr->sa_family != AF_LINK) 498 continue; 499 /* 500 * Program the first 15 multicast groups 501 * into the perfect filter. For all others, 502 * use the hash table. 503 */ 504 if (i < SF_RXFILT_PERFECT_CNT) { 505 sf_setperf(sc, i, 506 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 507 i++; 508 continue; 509 } 510 511 sf_sethash(sc, 512 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 0); 513 } 514 if_maddr_runlock(ifp); 515 516done: 517 csr_write_4(sc, SF_RXFILT, rxfilt); 518} 519 520/* 521 * Set media options. 522 */ 523static int 524sf_ifmedia_upd(struct ifnet *ifp) 525{ 526 struct sf_softc *sc; 527 int error; 528 529 sc = ifp->if_softc; 530 SF_LOCK(sc); 531 error = sf_ifmedia_upd_locked(ifp); 532 SF_UNLOCK(sc); 533 return (error); 534} 535 536static int 537sf_ifmedia_upd_locked(struct ifnet *ifp) 538{ 539 struct sf_softc *sc; 540 struct mii_data *mii; 541 struct mii_softc *miisc; 542 543 sc = ifp->if_softc; 544 mii = device_get_softc(sc->sf_miibus); 545 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 546 PHY_RESET(miisc); 547 return (mii_mediachg(mii)); 548} 549 550/* 551 * Report current media status. 552 */ 553static void 554sf_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 555{ 556 struct sf_softc *sc; 557 struct mii_data *mii; 558 559 sc = ifp->if_softc; 560 SF_LOCK(sc); 561 mii = device_get_softc(sc->sf_miibus); 562 563 mii_pollstat(mii); 564 ifmr->ifm_active = mii->mii_media_active; 565 ifmr->ifm_status = mii->mii_media_status; 566 SF_UNLOCK(sc); 567} 568 569static int 570sf_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 571{ 572 struct sf_softc *sc; 573 struct ifreq *ifr; 574 struct mii_data *mii; 575 int error, mask; 576 577 sc = ifp->if_softc; 578 ifr = (struct ifreq *)data; 579 error = 0; 580 581 switch (command) { 582 case SIOCSIFFLAGS: 583 SF_LOCK(sc); 584 if (ifp->if_flags & IFF_UP) { 585 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 586 if ((ifp->if_flags ^ sc->sf_if_flags) & 587 (IFF_PROMISC | IFF_ALLMULTI)) 588 sf_rxfilter(sc); 589 } else { 590 if (sc->sf_detach == 0) 591 sf_init_locked(sc); 592 } 593 } else { 594 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 595 sf_stop(sc); 596 } 597 sc->sf_if_flags = ifp->if_flags; 598 SF_UNLOCK(sc); 599 break; 600 case SIOCADDMULTI: 601 case SIOCDELMULTI: 602 SF_LOCK(sc); 603 sf_rxfilter(sc); 604 SF_UNLOCK(sc); 605 break; 606 case SIOCGIFMEDIA: 607 case SIOCSIFMEDIA: 608 mii = device_get_softc(sc->sf_miibus); 609 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 610 break; 611 case SIOCSIFCAP: 612 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 613#ifdef DEVICE_POLLING 614 if ((mask & IFCAP_POLLING) != 0) { 615 if ((ifr->ifr_reqcap & IFCAP_POLLING) != 0) { 616 error = ether_poll_register(sf_poll, ifp); 617 if (error != 0) 618 break; 619 SF_LOCK(sc); 620 /* Disable interrupts. */ 621 csr_write_4(sc, SF_IMR, 0); 622 ifp->if_capenable |= IFCAP_POLLING; 623 SF_UNLOCK(sc); 624 } else { 625 error = ether_poll_deregister(ifp); 626 /* Enable interrupts. */ 627 SF_LOCK(sc); 628 csr_write_4(sc, SF_IMR, SF_INTRS); 629 ifp->if_capenable &= ~IFCAP_POLLING; 630 SF_UNLOCK(sc); 631 } 632 } 633#endif /* DEVICE_POLLING */ 634 if ((mask & IFCAP_TXCSUM) != 0) { 635 if ((IFCAP_TXCSUM & ifp->if_capabilities) != 0) { 636 SF_LOCK(sc); 637 ifp->if_capenable ^= IFCAP_TXCSUM; 638 if ((IFCAP_TXCSUM & ifp->if_capenable) != 0) { 639 ifp->if_hwassist |= SF_CSUM_FEATURES; 640 SF_SETBIT(sc, SF_GEN_ETH_CTL, 641 SF_ETHCTL_TXGFP_ENB); 642 } else { 643 ifp->if_hwassist &= ~SF_CSUM_FEATURES; 644 SF_CLRBIT(sc, SF_GEN_ETH_CTL, 645 SF_ETHCTL_TXGFP_ENB); 646 } 647 SF_UNLOCK(sc); 648 } 649 } 650 if ((mask & IFCAP_RXCSUM) != 0) { 651 if ((IFCAP_RXCSUM & ifp->if_capabilities) != 0) { 652 SF_LOCK(sc); 653 ifp->if_capenable ^= IFCAP_RXCSUM; 654 if ((IFCAP_RXCSUM & ifp->if_capenable) != 0) 655 SF_SETBIT(sc, SF_GEN_ETH_CTL, 656 SF_ETHCTL_RXGFP_ENB); 657 else 658 SF_CLRBIT(sc, SF_GEN_ETH_CTL, 659 SF_ETHCTL_RXGFP_ENB); 660 SF_UNLOCK(sc); 661 } 662 } 663 break; 664 default: 665 error = ether_ioctl(ifp, command, data); 666 break; 667 } 668 669 return (error); 670} 671 672static void 673sf_reset(struct sf_softc *sc) 674{ 675 int i; 676 677 csr_write_4(sc, SF_GEN_ETH_CTL, 0); 678 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 679 DELAY(1000); 680 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 681 682 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_RESET); 683 684 for (i = 0; i < SF_TIMEOUT; i++) { 685 DELAY(10); 686 if (!(csr_read_4(sc, SF_PCI_DEVCFG) & SF_PCIDEVCFG_RESET)) 687 break; 688 } 689 690 if (i == SF_TIMEOUT) 691 device_printf(sc->sf_dev, "reset never completed!\n"); 692 693 /* Wait a little while for the chip to get its brains in order. */ 694 DELAY(1000); 695} 696 697/* 698 * Probe for an Adaptec AIC-6915 chip. Check the PCI vendor and device 699 * IDs against our list and return a device name if we find a match. 700 * We also check the subsystem ID so that we can identify exactly which 701 * NIC has been found, if possible. 702 */ 703static int 704sf_probe(device_t dev) 705{ 706 struct sf_type *t; 707 uint16_t vid; 708 uint16_t did; 709 uint16_t sdid; 710 int i; 711 712 vid = pci_get_vendor(dev); 713 did = pci_get_device(dev); 714 sdid = pci_get_subdevice(dev); 715 716 t = sf_devs; 717 for (i = 0; i < sizeof(sf_devs) / sizeof(sf_devs[0]); i++, t++) { 718 if (vid == t->sf_vid && did == t->sf_did) { 719 if (sdid == t->sf_sdid) { 720 device_set_desc(dev, t->sf_sname); 721 return (BUS_PROBE_DEFAULT); 722 } 723 } 724 } 725 726 if (vid == AD_VENDORID && did == AD_DEVICEID_STARFIRE) { 727 /* unkown subdevice */ 728 device_set_desc(dev, sf_devs[0].sf_name); 729 return (BUS_PROBE_DEFAULT); 730 } 731 732 return (ENXIO); 733} 734 735/* 736 * Attach the interface. Allocate softc structures, do ifmedia 737 * setup and ethernet/BPF attach. 738 */ 739static int 740sf_attach(device_t dev) 741{ 742 int i; 743 struct sf_softc *sc; 744 struct ifnet *ifp; 745 uint32_t reg; 746 int rid, error = 0; 747 uint8_t eaddr[ETHER_ADDR_LEN]; 748 749 sc = device_get_softc(dev); 750 sc->sf_dev = dev; 751 752 mtx_init(&sc->sf_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 753 MTX_DEF); 754 callout_init_mtx(&sc->sf_co, &sc->sf_mtx, 0); 755 TASK_INIT(&sc->sf_link_task, 0, sf_link_task, sc); 756 757 /* 758 * Map control/status registers. 759 */ 760 pci_enable_busmaster(dev); 761 762 /* 763 * Prefer memory space register mapping over I/O space as the 764 * hardware requires lots of register access to get various 765 * producer/consumer index during Tx/Rx operation. However this 766 * requires large memory space(512K) to map the entire register 767 * space. 768 */ 769 sc->sf_rid = PCIR_BAR(0); 770 sc->sf_restype = SYS_RES_MEMORY; 771 sc->sf_res = bus_alloc_resource_any(dev, sc->sf_restype, &sc->sf_rid, 772 RF_ACTIVE); 773 if (sc->sf_res == NULL) { 774 reg = pci_read_config(dev, PCIR_BAR(0), 4); 775 if ((reg & PCIM_BAR_MEM_64) == PCIM_BAR_MEM_64) 776 sc->sf_rid = PCIR_BAR(2); 777 else 778 sc->sf_rid = PCIR_BAR(1); 779 sc->sf_restype = SYS_RES_IOPORT; 780 sc->sf_res = bus_alloc_resource_any(dev, sc->sf_restype, 781 &sc->sf_rid, RF_ACTIVE); 782 if (sc->sf_res == NULL) { 783 device_printf(dev, "couldn't allocate resources\n"); 784 mtx_destroy(&sc->sf_mtx); 785 return (ENXIO); 786 } 787 } 788 if (bootverbose) 789 device_printf(dev, "using %s space register mapping\n", 790 sc->sf_restype == SYS_RES_MEMORY ? "memory" : "I/O"); 791 792 reg = pci_read_config(dev, PCIR_CACHELNSZ, 1); 793 if (reg == 0) { 794 /* 795 * If cache line size is 0, MWI is not used at all, so set 796 * reasonable default. AIC-6915 supports 0, 4, 8, 16, 32 797 * and 64. 798 */ 799 reg = 16; 800 device_printf(dev, "setting PCI cache line size to %u\n", reg); 801 pci_write_config(dev, PCIR_CACHELNSZ, reg, 1); 802 } else { 803 if (bootverbose) 804 device_printf(dev, "PCI cache line size : %u\n", reg); 805 } 806 /* Enable MWI. */ 807 reg = pci_read_config(dev, PCIR_COMMAND, 2); 808 reg |= PCIM_CMD_MWRICEN; 809 pci_write_config(dev, PCIR_COMMAND, reg, 2); 810 811 /* Allocate interrupt. */ 812 rid = 0; 813 sc->sf_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 814 RF_SHAREABLE | RF_ACTIVE); 815 816 if (sc->sf_irq == NULL) { 817 device_printf(dev, "couldn't map interrupt\n"); 818 error = ENXIO; 819 goto fail; 820 } 821 822 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 823 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 824 OID_AUTO, "stats", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 825 sf_sysctl_stats, "I", "Statistics"); 826 827 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 828 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 829 OID_AUTO, "int_mod", CTLTYPE_INT | CTLFLAG_RW, 830 &sc->sf_int_mod, 0, sysctl_hw_sf_int_mod, "I", 831 "sf interrupt moderation"); 832 /* Pull in device tunables. */ 833 sc->sf_int_mod = SF_IM_DEFAULT; 834 error = resource_int_value(device_get_name(dev), device_get_unit(dev), 835 "int_mod", &sc->sf_int_mod); 836 if (error == 0) { 837 if (sc->sf_int_mod < SF_IM_MIN || 838 sc->sf_int_mod > SF_IM_MAX) { 839 device_printf(dev, "int_mod value out of range; " 840 "using default: %d\n", SF_IM_DEFAULT); 841 sc->sf_int_mod = SF_IM_DEFAULT; 842 } 843 } 844 845 /* Reset the adapter. */ 846 sf_reset(sc); 847 848 /* 849 * Get station address from the EEPROM. 850 */ 851 for (i = 0; i < ETHER_ADDR_LEN; i++) 852 eaddr[i] = 853 sf_read_eeprom(sc, SF_EE_NODEADDR + ETHER_ADDR_LEN - i); 854 855 /* Allocate DMA resources. */ 856 if (sf_dma_alloc(sc) != 0) { 857 error = ENOSPC; 858 goto fail; 859 } 860 861 sc->sf_txthresh = SF_MIN_TX_THRESHOLD; 862 863 ifp = sc->sf_ifp = if_alloc(IFT_ETHER); 864 if (ifp == NULL) { 865 device_printf(dev, "can not allocate ifnet structure\n"); 866 error = ENOSPC; 867 goto fail; 868 } 869 870 /* Do MII setup. */ 871 error = mii_attach(dev, &sc->sf_miibus, ifp, sf_ifmedia_upd, 872 sf_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0); 873 if (error != 0) { 874 device_printf(dev, "attaching PHYs failed\n"); 875 goto fail; 876 } 877 878 ifp->if_softc = sc; 879 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 880 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 881 ifp->if_ioctl = sf_ioctl; 882 ifp->if_start = sf_start; 883 ifp->if_init = sf_init; 884 IFQ_SET_MAXLEN(&ifp->if_snd, SF_TX_DLIST_CNT - 1); 885 ifp->if_snd.ifq_drv_maxlen = SF_TX_DLIST_CNT - 1; 886 IFQ_SET_READY(&ifp->if_snd); 887 /* 888 * With the help of firmware, AIC-6915 supports 889 * Tx/Rx TCP/UDP checksum offload. 890 */ 891 ifp->if_hwassist = SF_CSUM_FEATURES; 892 ifp->if_capabilities = IFCAP_HWCSUM; 893 894 /* 895 * Call MI attach routine. 896 */ 897 ether_ifattach(ifp, eaddr); 898 899 /* VLAN capability setup. */ 900 ifp->if_capabilities |= IFCAP_VLAN_MTU; 901 ifp->if_capenable = ifp->if_capabilities; 902#ifdef DEVICE_POLLING 903 ifp->if_capabilities |= IFCAP_POLLING; 904#endif 905 /* 906 * Tell the upper layer(s) we support long frames. 907 * Must appear after the call to ether_ifattach() because 908 * ether_ifattach() sets ifi_hdrlen to the default value. 909 */ 910 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 911 912 /* Hook interrupt last to avoid having to lock softc */ 913 error = bus_setup_intr(dev, sc->sf_irq, INTR_TYPE_NET | INTR_MPSAFE, 914 NULL, sf_intr, sc, &sc->sf_intrhand); 915 916 if (error) { 917 device_printf(dev, "couldn't set up irq\n"); 918 ether_ifdetach(ifp); 919 goto fail; 920 } 921 922fail: 923 if (error) 924 sf_detach(dev); 925 926 return (error); 927} 928 929/* 930 * Shutdown hardware and free up resources. This can be called any 931 * time after the mutex has been initialized. It is called in both 932 * the error case in attach and the normal detach case so it needs 933 * to be careful about only freeing resources that have actually been 934 * allocated. 935 */ 936static int 937sf_detach(device_t dev) 938{ 939 struct sf_softc *sc; 940 struct ifnet *ifp; 941 942 sc = device_get_softc(dev); 943 ifp = sc->sf_ifp; 944 945#ifdef DEVICE_POLLING 946 if (ifp != NULL && ifp->if_capenable & IFCAP_POLLING) 947 ether_poll_deregister(ifp); 948#endif 949 950 /* These should only be active if attach succeeded */ 951 if (device_is_attached(dev)) { 952 SF_LOCK(sc); 953 sc->sf_detach = 1; 954 sf_stop(sc); 955 SF_UNLOCK(sc); 956 callout_drain(&sc->sf_co); 957 taskqueue_drain(taskqueue_swi, &sc->sf_link_task); 958 if (ifp != NULL) 959 ether_ifdetach(ifp); 960 } 961 if (sc->sf_miibus) { 962 device_delete_child(dev, sc->sf_miibus); 963 sc->sf_miibus = NULL; 964 } 965 bus_generic_detach(dev); 966 967 if (sc->sf_intrhand != NULL) 968 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand); 969 if (sc->sf_irq != NULL) 970 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq); 971 if (sc->sf_res != NULL) 972 bus_release_resource(dev, sc->sf_restype, sc->sf_rid, 973 sc->sf_res); 974 975 sf_dma_free(sc); 976 if (ifp != NULL) 977 if_free(ifp); 978 979 mtx_destroy(&sc->sf_mtx); 980 981 return (0); 982} 983 984struct sf_dmamap_arg { 985 bus_addr_t sf_busaddr; 986}; 987 988static void 989sf_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 990{ 991 struct sf_dmamap_arg *ctx; 992 993 if (error != 0) 994 return; 995 ctx = arg; 996 ctx->sf_busaddr = segs[0].ds_addr; 997} 998 999static int 1000sf_dma_alloc(struct sf_softc *sc) 1001{ 1002 struct sf_dmamap_arg ctx; 1003 struct sf_txdesc *txd; 1004 struct sf_rxdesc *rxd; 1005 bus_addr_t lowaddr; 1006 bus_addr_t rx_ring_end, rx_cring_end; 1007 bus_addr_t tx_ring_end, tx_cring_end; 1008 int error, i; 1009 1010 lowaddr = BUS_SPACE_MAXADDR; 1011 1012again: 1013 /* Create parent DMA tag. */ 1014 error = bus_dma_tag_create( 1015 bus_get_dma_tag(sc->sf_dev), /* parent */ 1016 1, 0, /* alignment, boundary */ 1017 lowaddr, /* lowaddr */ 1018 BUS_SPACE_MAXADDR, /* highaddr */ 1019 NULL, NULL, /* filter, filterarg */ 1020 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1021 0, /* nsegments */ 1022 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1023 0, /* flags */ 1024 NULL, NULL, /* lockfunc, lockarg */ 1025 &sc->sf_cdata.sf_parent_tag); 1026 if (error != 0) { 1027 device_printf(sc->sf_dev, "failed to create parent DMA tag\n"); 1028 goto fail; 1029 } 1030 /* Create tag for Tx ring. */ 1031 error = bus_dma_tag_create(sc->sf_cdata.sf_parent_tag,/* parent */ 1032 SF_RING_ALIGN, 0, /* alignment, boundary */ 1033 BUS_SPACE_MAXADDR, /* lowaddr */ 1034 BUS_SPACE_MAXADDR, /* highaddr */ 1035 NULL, NULL, /* filter, filterarg */ 1036 SF_TX_DLIST_SIZE, /* maxsize */ 1037 1, /* nsegments */ 1038 SF_TX_DLIST_SIZE, /* maxsegsize */ 1039 0, /* flags */ 1040 NULL, NULL, /* lockfunc, lockarg */ 1041 &sc->sf_cdata.sf_tx_ring_tag); 1042 if (error != 0) { 1043 device_printf(sc->sf_dev, "failed to create Tx ring DMA tag\n"); 1044 goto fail; 1045 } 1046 1047 /* Create tag for Tx completion ring. */ 1048 error = bus_dma_tag_create(sc->sf_cdata.sf_parent_tag,/* parent */ 1049 SF_RING_ALIGN, 0, /* alignment, boundary */ 1050 BUS_SPACE_MAXADDR, /* lowaddr */ 1051 BUS_SPACE_MAXADDR, /* highaddr */ 1052 NULL, NULL, /* filter, filterarg */ 1053 SF_TX_CLIST_SIZE, /* maxsize */ 1054 1, /* nsegments */ 1055 SF_TX_CLIST_SIZE, /* maxsegsize */ 1056 0, /* flags */ 1057 NULL, NULL, /* lockfunc, lockarg */ 1058 &sc->sf_cdata.sf_tx_cring_tag); 1059 if (error != 0) { 1060 device_printf(sc->sf_dev, 1061 "failed to create Tx completion ring DMA tag\n"); 1062 goto fail; 1063 } 1064 1065 /* Create tag for Rx ring. */ 1066 error = bus_dma_tag_create(sc->sf_cdata.sf_parent_tag,/* parent */ 1067 SF_RING_ALIGN, 0, /* alignment, boundary */ 1068 BUS_SPACE_MAXADDR, /* lowaddr */ 1069 BUS_SPACE_MAXADDR, /* highaddr */ 1070 NULL, NULL, /* filter, filterarg */ 1071 SF_RX_DLIST_SIZE, /* maxsize */ 1072 1, /* nsegments */ 1073 SF_RX_DLIST_SIZE, /* maxsegsize */ 1074 0, /* flags */ 1075 NULL, NULL, /* lockfunc, lockarg */ 1076 &sc->sf_cdata.sf_rx_ring_tag); 1077 if (error != 0) { 1078 device_printf(sc->sf_dev, 1079 "failed to create Rx ring DMA tag\n"); 1080 goto fail; 1081 } 1082 1083 /* Create tag for Rx completion ring. */ 1084 error = bus_dma_tag_create(sc->sf_cdata.sf_parent_tag,/* parent */ 1085 SF_RING_ALIGN, 0, /* alignment, boundary */ 1086 BUS_SPACE_MAXADDR, /* lowaddr */ 1087 BUS_SPACE_MAXADDR, /* highaddr */ 1088 NULL, NULL, /* filter, filterarg */ 1089 SF_RX_CLIST_SIZE, /* maxsize */ 1090 1, /* nsegments */ 1091 SF_RX_CLIST_SIZE, /* maxsegsize */ 1092 0, /* flags */ 1093 NULL, NULL, /* lockfunc, lockarg */ 1094 &sc->sf_cdata.sf_rx_cring_tag); 1095 if (error != 0) { 1096 device_printf(sc->sf_dev, 1097 "failed to create Rx completion ring DMA tag\n"); 1098 goto fail; 1099 } 1100 1101 /* Create tag for Tx buffers. */ 1102 error = bus_dma_tag_create(sc->sf_cdata.sf_parent_tag,/* parent */ 1103 1, 0, /* alignment, boundary */ 1104 BUS_SPACE_MAXADDR, /* lowaddr */ 1105 BUS_SPACE_MAXADDR, /* highaddr */ 1106 NULL, NULL, /* filter, filterarg */ 1107 MCLBYTES * SF_MAXTXSEGS, /* maxsize */ 1108 SF_MAXTXSEGS, /* nsegments */ 1109 MCLBYTES, /* maxsegsize */ 1110 0, /* flags */ 1111 NULL, NULL, /* lockfunc, lockarg */ 1112 &sc->sf_cdata.sf_tx_tag); 1113 if (error != 0) { 1114 device_printf(sc->sf_dev, "failed to create Tx DMA tag\n"); 1115 goto fail; 1116 } 1117 1118 /* Create tag for Rx buffers. */ 1119 error = bus_dma_tag_create(sc->sf_cdata.sf_parent_tag,/* parent */ 1120 SF_RX_ALIGN, 0, /* alignment, boundary */ 1121 BUS_SPACE_MAXADDR, /* lowaddr */ 1122 BUS_SPACE_MAXADDR, /* highaddr */ 1123 NULL, NULL, /* filter, filterarg */ 1124 MCLBYTES, /* maxsize */ 1125 1, /* nsegments */ 1126 MCLBYTES, /* maxsegsize */ 1127 0, /* flags */ 1128 NULL, NULL, /* lockfunc, lockarg */ 1129 &sc->sf_cdata.sf_rx_tag); 1130 if (error != 0) { 1131 device_printf(sc->sf_dev, "failed to create Rx DMA tag\n"); 1132 goto fail; 1133 } 1134 1135 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 1136 error = bus_dmamem_alloc(sc->sf_cdata.sf_tx_ring_tag, 1137 (void **)&sc->sf_rdata.sf_tx_ring, BUS_DMA_WAITOK | 1138 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->sf_cdata.sf_tx_ring_map); 1139 if (error != 0) { 1140 device_printf(sc->sf_dev, 1141 "failed to allocate DMA'able memory for Tx ring\n"); 1142 goto fail; 1143 } 1144 1145 ctx.sf_busaddr = 0; 1146 error = bus_dmamap_load(sc->sf_cdata.sf_tx_ring_tag, 1147 sc->sf_cdata.sf_tx_ring_map, sc->sf_rdata.sf_tx_ring, 1148 SF_TX_DLIST_SIZE, sf_dmamap_cb, &ctx, 0); 1149 if (error != 0 || ctx.sf_busaddr == 0) { 1150 device_printf(sc->sf_dev, 1151 "failed to load DMA'able memory for Tx ring\n"); 1152 goto fail; 1153 } 1154 sc->sf_rdata.sf_tx_ring_paddr = ctx.sf_busaddr; 1155 1156 /* 1157 * Allocate DMA'able memory and load the DMA map for Tx completion ring. 1158 */ 1159 error = bus_dmamem_alloc(sc->sf_cdata.sf_tx_cring_tag, 1160 (void **)&sc->sf_rdata.sf_tx_cring, BUS_DMA_WAITOK | 1161 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->sf_cdata.sf_tx_cring_map); 1162 if (error != 0) { 1163 device_printf(sc->sf_dev, 1164 "failed to allocate DMA'able memory for " 1165 "Tx completion ring\n"); 1166 goto fail; 1167 } 1168 1169 ctx.sf_busaddr = 0; 1170 error = bus_dmamap_load(sc->sf_cdata.sf_tx_cring_tag, 1171 sc->sf_cdata.sf_tx_cring_map, sc->sf_rdata.sf_tx_cring, 1172 SF_TX_CLIST_SIZE, sf_dmamap_cb, &ctx, 0); 1173 if (error != 0 || ctx.sf_busaddr == 0) { 1174 device_printf(sc->sf_dev, 1175 "failed to load DMA'able memory for Tx completion ring\n"); 1176 goto fail; 1177 } 1178 sc->sf_rdata.sf_tx_cring_paddr = ctx.sf_busaddr; 1179 1180 /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 1181 error = bus_dmamem_alloc(sc->sf_cdata.sf_rx_ring_tag, 1182 (void **)&sc->sf_rdata.sf_rx_ring, BUS_DMA_WAITOK | 1183 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->sf_cdata.sf_rx_ring_map); 1184 if (error != 0) { 1185 device_printf(sc->sf_dev, 1186 "failed to allocate DMA'able memory for Rx ring\n"); 1187 goto fail; 1188 } 1189 1190 ctx.sf_busaddr = 0; 1191 error = bus_dmamap_load(sc->sf_cdata.sf_rx_ring_tag, 1192 sc->sf_cdata.sf_rx_ring_map, sc->sf_rdata.sf_rx_ring, 1193 SF_RX_DLIST_SIZE, sf_dmamap_cb, &ctx, 0); 1194 if (error != 0 || ctx.sf_busaddr == 0) { 1195 device_printf(sc->sf_dev, 1196 "failed to load DMA'able memory for Rx ring\n"); 1197 goto fail; 1198 } 1199 sc->sf_rdata.sf_rx_ring_paddr = ctx.sf_busaddr; 1200 1201 /* 1202 * Allocate DMA'able memory and load the DMA map for Rx completion ring. 1203 */ 1204 error = bus_dmamem_alloc(sc->sf_cdata.sf_rx_cring_tag, 1205 (void **)&sc->sf_rdata.sf_rx_cring, BUS_DMA_WAITOK | 1206 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->sf_cdata.sf_rx_cring_map); 1207 if (error != 0) { 1208 device_printf(sc->sf_dev, 1209 "failed to allocate DMA'able memory for " 1210 "Rx completion ring\n"); 1211 goto fail; 1212 } 1213 1214 ctx.sf_busaddr = 0; 1215 error = bus_dmamap_load(sc->sf_cdata.sf_rx_cring_tag, 1216 sc->sf_cdata.sf_rx_cring_map, sc->sf_rdata.sf_rx_cring, 1217 SF_RX_CLIST_SIZE, sf_dmamap_cb, &ctx, 0); 1218 if (error != 0 || ctx.sf_busaddr == 0) { 1219 device_printf(sc->sf_dev, 1220 "failed to load DMA'able memory for Rx completion ring\n"); 1221 goto fail; 1222 } 1223 sc->sf_rdata.sf_rx_cring_paddr = ctx.sf_busaddr; 1224 1225 /* 1226 * Tx desciptor ring and Tx completion ring should be addressed in 1227 * the same 4GB space. The same rule applys to Rx ring and Rx 1228 * completion ring. Unfortunately there is no way to specify this 1229 * boundary restriction with bus_dma(9). So just try to allocate 1230 * without the restriction and check the restriction was satisfied. 1231 * If not, fall back to 32bit dma addressing mode which always 1232 * guarantees the restriction. 1233 */ 1234 tx_ring_end = sc->sf_rdata.sf_tx_ring_paddr + SF_TX_DLIST_SIZE; 1235 tx_cring_end = sc->sf_rdata.sf_tx_cring_paddr + SF_TX_CLIST_SIZE; 1236 rx_ring_end = sc->sf_rdata.sf_rx_ring_paddr + SF_RX_DLIST_SIZE; 1237 rx_cring_end = sc->sf_rdata.sf_rx_cring_paddr + SF_RX_CLIST_SIZE; 1238 if ((SF_ADDR_HI(sc->sf_rdata.sf_tx_ring_paddr) != 1239 SF_ADDR_HI(tx_cring_end)) || 1240 (SF_ADDR_HI(sc->sf_rdata.sf_tx_cring_paddr) != 1241 SF_ADDR_HI(tx_ring_end)) || 1242 (SF_ADDR_HI(sc->sf_rdata.sf_rx_ring_paddr) != 1243 SF_ADDR_HI(rx_cring_end)) || 1244 (SF_ADDR_HI(sc->sf_rdata.sf_rx_cring_paddr) != 1245 SF_ADDR_HI(rx_ring_end))) { 1246 device_printf(sc->sf_dev, 1247 "switching to 32bit DMA mode\n"); 1248 sf_dma_free(sc); 1249 /* Limit DMA address space to 32bit and try again. */ 1250 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1251 goto again; 1252 } 1253 1254 /* Create DMA maps for Tx buffers. */ 1255 for (i = 0; i < SF_TX_DLIST_CNT; i++) { 1256 txd = &sc->sf_cdata.sf_txdesc[i]; 1257 txd->tx_m = NULL; 1258 txd->ndesc = 0; 1259 txd->tx_dmamap = NULL; 1260 error = bus_dmamap_create(sc->sf_cdata.sf_tx_tag, 0, 1261 &txd->tx_dmamap); 1262 if (error != 0) { 1263 device_printf(sc->sf_dev, 1264 "failed to create Tx dmamap\n"); 1265 goto fail; 1266 } 1267 } 1268 /* Create DMA maps for Rx buffers. */ 1269 if ((error = bus_dmamap_create(sc->sf_cdata.sf_rx_tag, 0, 1270 &sc->sf_cdata.sf_rx_sparemap)) != 0) { 1271 device_printf(sc->sf_dev, 1272 "failed to create spare Rx dmamap\n"); 1273 goto fail; 1274 } 1275 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 1276 rxd = &sc->sf_cdata.sf_rxdesc[i]; 1277 rxd->rx_m = NULL; 1278 rxd->rx_dmamap = NULL; 1279 error = bus_dmamap_create(sc->sf_cdata.sf_rx_tag, 0, 1280 &rxd->rx_dmamap); 1281 if (error != 0) { 1282 device_printf(sc->sf_dev, 1283 "failed to create Rx dmamap\n"); 1284 goto fail; 1285 } 1286 } 1287 1288fail: 1289 return (error); 1290} 1291 1292static void 1293sf_dma_free(struct sf_softc *sc) 1294{ 1295 struct sf_txdesc *txd; 1296 struct sf_rxdesc *rxd; 1297 int i; 1298 1299 /* Tx ring. */ 1300 if (sc->sf_cdata.sf_tx_ring_tag) { 1301 if (sc->sf_cdata.sf_tx_ring_map) 1302 bus_dmamap_unload(sc->sf_cdata.sf_tx_ring_tag, 1303 sc->sf_cdata.sf_tx_ring_map); 1304 if (sc->sf_cdata.sf_tx_ring_map && 1305 sc->sf_rdata.sf_tx_ring) 1306 bus_dmamem_free(sc->sf_cdata.sf_tx_ring_tag, 1307 sc->sf_rdata.sf_tx_ring, 1308 sc->sf_cdata.sf_tx_ring_map); 1309 sc->sf_rdata.sf_tx_ring = NULL; 1310 sc->sf_cdata.sf_tx_ring_map = NULL; 1311 bus_dma_tag_destroy(sc->sf_cdata.sf_tx_ring_tag); 1312 sc->sf_cdata.sf_tx_ring_tag = NULL; 1313 } 1314 /* Tx completion ring. */ 1315 if (sc->sf_cdata.sf_tx_cring_tag) { 1316 if (sc->sf_cdata.sf_tx_cring_map) 1317 bus_dmamap_unload(sc->sf_cdata.sf_tx_cring_tag, 1318 sc->sf_cdata.sf_tx_cring_map); 1319 if (sc->sf_cdata.sf_tx_cring_map && 1320 sc->sf_rdata.sf_tx_cring) 1321 bus_dmamem_free(sc->sf_cdata.sf_tx_cring_tag, 1322 sc->sf_rdata.sf_tx_cring, 1323 sc->sf_cdata.sf_tx_cring_map); 1324 sc->sf_rdata.sf_tx_cring = NULL; 1325 sc->sf_cdata.sf_tx_cring_map = NULL; 1326 bus_dma_tag_destroy(sc->sf_cdata.sf_tx_cring_tag); 1327 sc->sf_cdata.sf_tx_cring_tag = NULL; 1328 } 1329 /* Rx ring. */ 1330 if (sc->sf_cdata.sf_rx_ring_tag) { 1331 if (sc->sf_cdata.sf_rx_ring_map) 1332 bus_dmamap_unload(sc->sf_cdata.sf_rx_ring_tag, 1333 sc->sf_cdata.sf_rx_ring_map); 1334 if (sc->sf_cdata.sf_rx_ring_map && 1335 sc->sf_rdata.sf_rx_ring) 1336 bus_dmamem_free(sc->sf_cdata.sf_rx_ring_tag, 1337 sc->sf_rdata.sf_rx_ring, 1338 sc->sf_cdata.sf_rx_ring_map); 1339 sc->sf_rdata.sf_rx_ring = NULL; 1340 sc->sf_cdata.sf_rx_ring_map = NULL; 1341 bus_dma_tag_destroy(sc->sf_cdata.sf_rx_ring_tag); 1342 sc->sf_cdata.sf_rx_ring_tag = NULL; 1343 } 1344 /* Rx completion ring. */ 1345 if (sc->sf_cdata.sf_rx_cring_tag) { 1346 if (sc->sf_cdata.sf_rx_cring_map) 1347 bus_dmamap_unload(sc->sf_cdata.sf_rx_cring_tag, 1348 sc->sf_cdata.sf_rx_cring_map); 1349 if (sc->sf_cdata.sf_rx_cring_map && 1350 sc->sf_rdata.sf_rx_cring) 1351 bus_dmamem_free(sc->sf_cdata.sf_rx_cring_tag, 1352 sc->sf_rdata.sf_rx_cring, 1353 sc->sf_cdata.sf_rx_cring_map); 1354 sc->sf_rdata.sf_rx_cring = NULL; 1355 sc->sf_cdata.sf_rx_cring_map = NULL; 1356 bus_dma_tag_destroy(sc->sf_cdata.sf_rx_cring_tag); 1357 sc->sf_cdata.sf_rx_cring_tag = NULL; 1358 } 1359 /* Tx buffers. */ 1360 if (sc->sf_cdata.sf_tx_tag) { 1361 for (i = 0; i < SF_TX_DLIST_CNT; i++) { 1362 txd = &sc->sf_cdata.sf_txdesc[i]; 1363 if (txd->tx_dmamap) { 1364 bus_dmamap_destroy(sc->sf_cdata.sf_tx_tag, 1365 txd->tx_dmamap); 1366 txd->tx_dmamap = NULL; 1367 } 1368 } 1369 bus_dma_tag_destroy(sc->sf_cdata.sf_tx_tag); 1370 sc->sf_cdata.sf_tx_tag = NULL; 1371 } 1372 /* Rx buffers. */ 1373 if (sc->sf_cdata.sf_rx_tag) { 1374 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 1375 rxd = &sc->sf_cdata.sf_rxdesc[i]; 1376 if (rxd->rx_dmamap) { 1377 bus_dmamap_destroy(sc->sf_cdata.sf_rx_tag, 1378 rxd->rx_dmamap); 1379 rxd->rx_dmamap = NULL; 1380 } 1381 } 1382 if (sc->sf_cdata.sf_rx_sparemap) { 1383 bus_dmamap_destroy(sc->sf_cdata.sf_rx_tag, 1384 sc->sf_cdata.sf_rx_sparemap); 1385 sc->sf_cdata.sf_rx_sparemap = 0; 1386 } 1387 bus_dma_tag_destroy(sc->sf_cdata.sf_rx_tag); 1388 sc->sf_cdata.sf_rx_tag = NULL; 1389 } 1390 1391 if (sc->sf_cdata.sf_parent_tag) { 1392 bus_dma_tag_destroy(sc->sf_cdata.sf_parent_tag); 1393 sc->sf_cdata.sf_parent_tag = NULL; 1394 } 1395} 1396 1397static int 1398sf_init_rx_ring(struct sf_softc *sc) 1399{ 1400 struct sf_ring_data *rd; 1401 int i; 1402 1403 sc->sf_cdata.sf_rxc_cons = 0; 1404 1405 rd = &sc->sf_rdata; 1406 bzero(rd->sf_rx_ring, SF_RX_DLIST_SIZE); 1407 bzero(rd->sf_rx_cring, SF_RX_CLIST_SIZE); 1408 1409 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 1410 if (sf_newbuf(sc, i) != 0) 1411 return (ENOBUFS); 1412 } 1413 1414 bus_dmamap_sync(sc->sf_cdata.sf_rx_cring_tag, 1415 sc->sf_cdata.sf_rx_cring_map, 1416 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1417 bus_dmamap_sync(sc->sf_cdata.sf_rx_ring_tag, 1418 sc->sf_cdata.sf_rx_ring_map, 1419 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1420 1421 return (0); 1422} 1423 1424static void 1425sf_init_tx_ring(struct sf_softc *sc) 1426{ 1427 struct sf_ring_data *rd; 1428 int i; 1429 1430 sc->sf_cdata.sf_tx_prod = 0; 1431 sc->sf_cdata.sf_tx_cnt = 0; 1432 sc->sf_cdata.sf_txc_cons = 0; 1433 1434 rd = &sc->sf_rdata; 1435 bzero(rd->sf_tx_ring, SF_TX_DLIST_SIZE); 1436 bzero(rd->sf_tx_cring, SF_TX_CLIST_SIZE); 1437 for (i = 0; i < SF_TX_DLIST_CNT; i++) { 1438 rd->sf_tx_ring[i].sf_tx_ctrl = htole32(SF_TX_DESC_ID); 1439 sc->sf_cdata.sf_txdesc[i].tx_m = NULL; 1440 sc->sf_cdata.sf_txdesc[i].ndesc = 0; 1441 } 1442 rd->sf_tx_ring[i].sf_tx_ctrl |= htole32(SF_TX_DESC_END); 1443 1444 bus_dmamap_sync(sc->sf_cdata.sf_tx_ring_tag, 1445 sc->sf_cdata.sf_tx_ring_map, 1446 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1447 bus_dmamap_sync(sc->sf_cdata.sf_tx_cring_tag, 1448 sc->sf_cdata.sf_tx_cring_map, 1449 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1450} 1451 1452/* 1453 * Initialize an RX descriptor and attach an MBUF cluster. 1454 */ 1455static int 1456sf_newbuf(struct sf_softc *sc, int idx) 1457{ 1458 struct sf_rx_rdesc *desc; 1459 struct sf_rxdesc *rxd; 1460 struct mbuf *m; 1461 bus_dma_segment_t segs[1]; 1462 bus_dmamap_t map; 1463 int nsegs; 1464 1465 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1466 if (m == NULL) 1467 return (ENOBUFS); 1468 m->m_len = m->m_pkthdr.len = MCLBYTES; 1469 m_adj(m, sizeof(uint32_t)); 1470 1471 if (bus_dmamap_load_mbuf_sg(sc->sf_cdata.sf_rx_tag, 1472 sc->sf_cdata.sf_rx_sparemap, m, segs, &nsegs, 0) != 0) { 1473 m_freem(m); 1474 return (ENOBUFS); 1475 } 1476 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1477 1478 rxd = &sc->sf_cdata.sf_rxdesc[idx]; 1479 if (rxd->rx_m != NULL) { 1480 bus_dmamap_sync(sc->sf_cdata.sf_rx_tag, rxd->rx_dmamap, 1481 BUS_DMASYNC_POSTREAD); 1482 bus_dmamap_unload(sc->sf_cdata.sf_rx_tag, rxd->rx_dmamap); 1483 } 1484 map = rxd->rx_dmamap; 1485 rxd->rx_dmamap = sc->sf_cdata.sf_rx_sparemap; 1486 sc->sf_cdata.sf_rx_sparemap = map; 1487 bus_dmamap_sync(sc->sf_cdata.sf_rx_tag, rxd->rx_dmamap, 1488 BUS_DMASYNC_PREREAD); 1489 rxd->rx_m = m; 1490 desc = &sc->sf_rdata.sf_rx_ring[idx]; 1491 desc->sf_addr = htole64(segs[0].ds_addr); 1492 1493 return (0); 1494} 1495 1496#ifndef __NO_STRICT_ALIGNMENT 1497static __inline void 1498sf_fixup_rx(struct mbuf *m) 1499{ 1500 int i; 1501 uint16_t *src, *dst; 1502 1503 src = mtod(m, uint16_t *); 1504 dst = src - 1; 1505 1506 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1507 *dst++ = *src++; 1508 1509 m->m_data -= ETHER_ALIGN; 1510} 1511#endif 1512 1513/* 1514 * The starfire is programmed to use 'normal' mode for packet reception, 1515 * which means we use the consumer/producer model for both the buffer 1516 * descriptor queue and the completion descriptor queue. The only problem 1517 * with this is that it involves a lot of register accesses: we have to 1518 * read the RX completion consumer and producer indexes and the RX buffer 1519 * producer index, plus the RX completion consumer and RX buffer producer 1520 * indexes have to be updated. It would have been easier if Adaptec had 1521 * put each index in a separate register, especially given that the damn 1522 * NIC has a 512K register space. 1523 * 1524 * In spite of all the lovely features that Adaptec crammed into the 6915, 1525 * it is marred by one truly stupid design flaw, which is that receive 1526 * buffer addresses must be aligned on a longword boundary. This forces 1527 * the packet payload to be unaligned, which is suboptimal on the x86 and 1528 * completely unuseable on the Alpha. Our only recourse is to copy received 1529 * packets into properly aligned buffers before handing them off. 1530 */ 1531static int 1532sf_rxeof(struct sf_softc *sc) 1533{ 1534 struct mbuf *m; 1535 struct ifnet *ifp; 1536 struct sf_rxdesc *rxd; 1537 struct sf_rx_rcdesc *cur_cmp; 1538 int cons, eidx, prog, rx_npkts; 1539 uint32_t status, status2; 1540 1541 SF_LOCK_ASSERT(sc); 1542 1543 ifp = sc->sf_ifp; 1544 rx_npkts = 0; 1545 1546 bus_dmamap_sync(sc->sf_cdata.sf_rx_ring_tag, 1547 sc->sf_cdata.sf_rx_ring_map, 1548 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1549 bus_dmamap_sync(sc->sf_cdata.sf_rx_cring_tag, 1550 sc->sf_cdata.sf_rx_cring_map, 1551 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1552 1553 /* 1554 * To reduce register access, directly read Receive completion 1555 * queue entry. 1556 */ 1557 eidx = 0; 1558 prog = 0; 1559 for (cons = sc->sf_cdata.sf_rxc_cons; ; SF_INC(cons, SF_RX_CLIST_CNT)) { 1560 cur_cmp = &sc->sf_rdata.sf_rx_cring[cons]; 1561 status = le32toh(cur_cmp->sf_rx_status1); 1562 if (status == 0) 1563 break; 1564#ifdef DEVICE_POLLING 1565 if ((ifp->if_capenable & IFCAP_POLLING) != 0) { 1566 if (sc->rxcycles <= 0) 1567 break; 1568 sc->rxcycles--; 1569 } 1570#endif 1571 prog++; 1572 eidx = (status & SF_RX_CMPDESC_EIDX) >> 16; 1573 rxd = &sc->sf_cdata.sf_rxdesc[eidx]; 1574 m = rxd->rx_m; 1575 1576 /* 1577 * Note, if_ipackets and if_ierrors counters 1578 * are handled in sf_stats_update(). 1579 */ 1580 if ((status & SF_RXSTAT1_OK) == 0) { 1581 cur_cmp->sf_rx_status1 = 0; 1582 continue; 1583 } 1584 1585 if (sf_newbuf(sc, eidx) != 0) { 1586 ifp->if_iqdrops++; 1587 cur_cmp->sf_rx_status1 = 0; 1588 continue; 1589 } 1590 1591 /* AIC-6915 supports TCP/UDP checksum offload. */ 1592 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) { 1593 status2 = le32toh(cur_cmp->sf_rx_status2); 1594 /* 1595 * Sometimes AIC-6915 generates an interrupt to 1596 * warn RxGFP stall with bad checksum bit set 1597 * in status word. I'm not sure what conditioan 1598 * triggers it but recevied packet's checksum 1599 * was correct even though AIC-6915 does not 1600 * agree on this. This may be an indication of 1601 * firmware bug. To fix the issue, do not rely 1602 * on bad checksum bit in status word and let 1603 * upper layer verify integrity of received 1604 * frame. 1605 * Another nice feature of AIC-6915 is hardware 1606 * assistance of checksum calculation by 1607 * providing partial checksum value for received 1608 * frame. The partial checksum value can be used 1609 * to accelerate checksum computation for 1610 * fragmented TCP/UDP packets. Upper network 1611 * stack already takes advantage of the partial 1612 * checksum value in IP reassembly stage. But 1613 * I'm not sure the correctness of the partial 1614 * hardware checksum assistance as frequent 1615 * RxGFP stalls are seen on non-fragmented 1616 * frames. Due to the nature of the complexity 1617 * of checksum computation code in firmware it's 1618 * possible to see another bug in RxGFP so 1619 * ignore checksum assistance for fragmented 1620 * frames. This can be changed in future. 1621 */ 1622 if ((status2 & SF_RXSTAT2_FRAG) == 0) { 1623 if ((status2 & (SF_RXSTAT2_TCP | 1624 SF_RXSTAT2_UDP)) != 0) { 1625 if ((status2 & SF_RXSTAT2_CSUM_OK)) { 1626 m->m_pkthdr.csum_flags = 1627 CSUM_DATA_VALID | 1628 CSUM_PSEUDO_HDR; 1629 m->m_pkthdr.csum_data = 0xffff; 1630 } 1631 } 1632 } 1633#ifdef SF_PARTIAL_CSUM_SUPPORT 1634 else if ((status2 & SF_RXSTAT2_FRAG) != 0) { 1635 if ((status2 & (SF_RXSTAT2_TCP | 1636 SF_RXSTAT2_UDP)) != 0) { 1637 if ((status2 & SF_RXSTAT2_PCSUM_OK)) { 1638 m->m_pkthdr.csum_flags = 1639 CSUM_DATA_VALID; 1640 m->m_pkthdr.csum_data = 1641 (status & 1642 SF_RX_CMPDESC_CSUM2); 1643 } 1644 } 1645 } 1646#endif 1647 } 1648 1649 m->m_pkthdr.len = m->m_len = status & SF_RX_CMPDESC_LEN; 1650#ifndef __NO_STRICT_ALIGNMENT 1651 sf_fixup_rx(m); 1652#endif 1653 m->m_pkthdr.rcvif = ifp; 1654 1655 SF_UNLOCK(sc); 1656 (*ifp->if_input)(ifp, m); 1657 SF_LOCK(sc); 1658 rx_npkts++; 1659 1660 /* Clear completion status. */ 1661 cur_cmp->sf_rx_status1 = 0; 1662 } 1663 1664 if (prog > 0) { 1665 sc->sf_cdata.sf_rxc_cons = cons; 1666 bus_dmamap_sync(sc->sf_cdata.sf_rx_ring_tag, 1667 sc->sf_cdata.sf_rx_ring_map, 1668 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1669 bus_dmamap_sync(sc->sf_cdata.sf_rx_cring_tag, 1670 sc->sf_cdata.sf_rx_cring_map, 1671 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1672 1673 /* Update Rx completion Q1 consumer index. */ 1674 csr_write_4(sc, SF_CQ_CONSIDX, 1675 (csr_read_4(sc, SF_CQ_CONSIDX) & ~SF_CQ_CONSIDX_RXQ1) | 1676 (cons & SF_CQ_CONSIDX_RXQ1)); 1677 /* Update Rx descriptor Q1 ptr. */ 1678 csr_write_4(sc, SF_RXDQ_PTR_Q1, 1679 (csr_read_4(sc, SF_RXDQ_PTR_Q1) & ~SF_RXDQ_PRODIDX) | 1680 (eidx & SF_RXDQ_PRODIDX)); 1681 } 1682 return (rx_npkts); 1683} 1684 1685/* 1686 * Read the transmit status from the completion queue and release 1687 * mbufs. Note that the buffer descriptor index in the completion 1688 * descriptor is an offset from the start of the transmit buffer 1689 * descriptor list in bytes. This is important because the manual 1690 * gives the impression that it should match the producer/consumer 1691 * index, which is the offset in 8 byte blocks. 1692 */ 1693static void 1694sf_txeof(struct sf_softc *sc) 1695{ 1696 struct sf_txdesc *txd; 1697 struct sf_tx_rcdesc *cur_cmp; 1698 struct ifnet *ifp; 1699 uint32_t status; 1700 int cons, idx, prod; 1701 1702 SF_LOCK_ASSERT(sc); 1703 1704 ifp = sc->sf_ifp; 1705 1706 bus_dmamap_sync(sc->sf_cdata.sf_tx_cring_tag, 1707 sc->sf_cdata.sf_tx_cring_map, 1708 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1709 1710 cons = sc->sf_cdata.sf_txc_cons; 1711 prod = (csr_read_4(sc, SF_CQ_PRODIDX) & SF_TXDQ_PRODIDX_HIPRIO) >> 16; 1712 if (prod == cons) 1713 return; 1714 1715 for (; cons != prod; SF_INC(cons, SF_TX_CLIST_CNT)) { 1716 cur_cmp = &sc->sf_rdata.sf_tx_cring[cons]; 1717 status = le32toh(cur_cmp->sf_tx_status1); 1718 if (status == 0) 1719 break; 1720 switch (status & SF_TX_CMPDESC_TYPE) { 1721 case SF_TXCMPTYPE_TX: 1722 /* Tx complete entry. */ 1723 break; 1724 case SF_TXCMPTYPE_DMA: 1725 /* DMA complete entry. */ 1726 idx = status & SF_TX_CMPDESC_IDX; 1727 idx = idx / sizeof(struct sf_tx_rdesc); 1728 /* 1729 * We don't need to check Tx status here. 1730 * SF_ISR_TX_LOFIFO intr would handle this. 1731 * Note, if_opackets, if_collisions and if_oerrors 1732 * counters are handled in sf_stats_update(). 1733 */ 1734 txd = &sc->sf_cdata.sf_txdesc[idx]; 1735 if (txd->tx_m != NULL) { 1736 bus_dmamap_sync(sc->sf_cdata.sf_tx_tag, 1737 txd->tx_dmamap, 1738 BUS_DMASYNC_POSTWRITE); 1739 bus_dmamap_unload(sc->sf_cdata.sf_tx_tag, 1740 txd->tx_dmamap); 1741 m_freem(txd->tx_m); 1742 txd->tx_m = NULL; 1743 } 1744 sc->sf_cdata.sf_tx_cnt -= txd->ndesc; 1745 KASSERT(sc->sf_cdata.sf_tx_cnt >= 0, 1746 ("%s: Active Tx desc counter was garbled\n", 1747 __func__)); 1748 txd->ndesc = 0; 1749 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1750 break; 1751 default: 1752 /* It should not happen. */ 1753 device_printf(sc->sf_dev, 1754 "unknown Tx completion type : 0x%08x : %d : %d\n", 1755 status, cons, prod); 1756 break; 1757 } 1758 cur_cmp->sf_tx_status1 = 0; 1759 } 1760 1761 sc->sf_cdata.sf_txc_cons = cons; 1762 bus_dmamap_sync(sc->sf_cdata.sf_tx_cring_tag, 1763 sc->sf_cdata.sf_tx_cring_map, 1764 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1765 1766 if (sc->sf_cdata.sf_tx_cnt == 0) 1767 sc->sf_watchdog_timer = 0; 1768 1769 /* Update Tx completion consumer index. */ 1770 csr_write_4(sc, SF_CQ_CONSIDX, 1771 (csr_read_4(sc, SF_CQ_CONSIDX) & 0xffff) | 1772 ((cons << 16) & 0xffff0000)); 1773} 1774 1775static void 1776sf_txthresh_adjust(struct sf_softc *sc) 1777{ 1778 uint32_t txfctl; 1779 1780 device_printf(sc->sf_dev, "Tx underrun -- "); 1781 if (sc->sf_txthresh < SF_MAX_TX_THRESHOLD) { 1782 txfctl = csr_read_4(sc, SF_TX_FRAMCTL); 1783 /* Increase Tx threshold 256 bytes. */ 1784 sc->sf_txthresh += 16; 1785 if (sc->sf_txthresh > SF_MAX_TX_THRESHOLD) 1786 sc->sf_txthresh = SF_MAX_TX_THRESHOLD; 1787 txfctl &= ~SF_TXFRMCTL_TXTHRESH; 1788 txfctl |= sc->sf_txthresh; 1789 printf("increasing Tx threshold to %d bytes\n", 1790 sc->sf_txthresh * SF_TX_THRESHOLD_UNIT); 1791 csr_write_4(sc, SF_TX_FRAMCTL, txfctl); 1792 } else 1793 printf("\n"); 1794} 1795 1796#ifdef DEVICE_POLLING 1797static int 1798sf_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1799{ 1800 struct sf_softc *sc; 1801 uint32_t status; 1802 int rx_npkts; 1803 1804 sc = ifp->if_softc; 1805 rx_npkts = 0; 1806 SF_LOCK(sc); 1807 1808 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1809 SF_UNLOCK(sc); 1810 return (rx_npkts); 1811 } 1812 1813 sc->rxcycles = count; 1814 rx_npkts = sf_rxeof(sc); 1815 sf_txeof(sc); 1816 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1817 sf_start_locked(ifp); 1818 1819 if (cmd == POLL_AND_CHECK_STATUS) { 1820 /* Reading the ISR register clears all interrrupts. */ 1821 status = csr_read_4(sc, SF_ISR); 1822 1823 if ((status & SF_ISR_ABNORMALINTR) != 0) { 1824 if ((status & SF_ISR_STATSOFLOW) != 0) 1825 sf_stats_update(sc); 1826 else if ((status & SF_ISR_TX_LOFIFO) != 0) 1827 sf_txthresh_adjust(sc); 1828 else if ((status & SF_ISR_DMAERR) != 0) { 1829 device_printf(sc->sf_dev, 1830 "DMA error, resetting\n"); 1831 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1832 sf_init_locked(sc); 1833 SF_UNLOCK(sc); 1834 return (rx_npkts); 1835 } else if ((status & SF_ISR_NO_TX_CSUM) != 0) { 1836 sc->sf_statistics.sf_tx_gfp_stall++; 1837#ifdef SF_GFP_DEBUG 1838 device_printf(sc->sf_dev, 1839 "TxGFP is not responding!\n"); 1840#endif 1841 } else if ((status & SF_ISR_RXGFP_NORESP) != 0) { 1842 sc->sf_statistics.sf_rx_gfp_stall++; 1843#ifdef SF_GFP_DEBUG 1844 device_printf(sc->sf_dev, 1845 "RxGFP is not responding!\n"); 1846#endif 1847 } 1848 } 1849 } 1850 1851 SF_UNLOCK(sc); 1852 return (rx_npkts); 1853} 1854#endif /* DEVICE_POLLING */ 1855 1856static void 1857sf_intr(void *arg) 1858{ 1859 struct sf_softc *sc; 1860 struct ifnet *ifp; 1861 uint32_t status; 1862 1863 sc = (struct sf_softc *)arg; 1864 SF_LOCK(sc); 1865 1866 if (sc->sf_suspended != 0) 1867 goto done_locked; 1868 1869 /* Reading the ISR register clears all interrrupts. */ 1870 status = csr_read_4(sc, SF_ISR); 1871 if (status == 0 || status == 0xffffffff || 1872 (status & SF_ISR_PCIINT_ASSERTED) == 0) 1873 goto done_locked; 1874 1875 ifp = sc->sf_ifp; 1876#ifdef DEVICE_POLLING 1877 if ((ifp->if_capenable & IFCAP_POLLING) != 0) 1878 goto done_locked; 1879#endif 1880 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1881 goto done_locked; 1882 1883 /* Disable interrupts. */ 1884 csr_write_4(sc, SF_IMR, 0x00000000); 1885 1886 for (; (status & SF_INTRS) != 0;) { 1887 if ((status & SF_ISR_RXDQ1_DMADONE) != 0) 1888 sf_rxeof(sc); 1889 1890 if ((status & (SF_ISR_TX_TXDONE | SF_ISR_TX_DMADONE | 1891 SF_ISR_TX_QUEUEDONE)) != 0) 1892 sf_txeof(sc); 1893 1894 if ((status & SF_ISR_ABNORMALINTR) != 0) { 1895 if ((status & SF_ISR_STATSOFLOW) != 0) 1896 sf_stats_update(sc); 1897 else if ((status & SF_ISR_TX_LOFIFO) != 0) 1898 sf_txthresh_adjust(sc); 1899 else if ((status & SF_ISR_DMAERR) != 0) { 1900 device_printf(sc->sf_dev, 1901 "DMA error, resetting\n"); 1902 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1903 sf_init_locked(sc); 1904 SF_UNLOCK(sc); 1905 return; 1906 } else if ((status & SF_ISR_NO_TX_CSUM) != 0) { 1907 sc->sf_statistics.sf_tx_gfp_stall++; 1908#ifdef SF_GFP_DEBUG 1909 device_printf(sc->sf_dev, 1910 "TxGFP is not responding!\n"); 1911#endif 1912 } 1913 else if ((status & SF_ISR_RXGFP_NORESP) != 0) { 1914 sc->sf_statistics.sf_rx_gfp_stall++; 1915#ifdef SF_GFP_DEBUG 1916 device_printf(sc->sf_dev, 1917 "RxGFP is not responding!\n"); 1918#endif 1919 } 1920 } 1921 /* Reading the ISR register clears all interrrupts. */ 1922 status = csr_read_4(sc, SF_ISR); 1923 } 1924 1925 /* Re-enable interrupts. */ 1926 csr_write_4(sc, SF_IMR, SF_INTRS); 1927 1928 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1929 sf_start_locked(ifp); 1930done_locked: 1931 SF_UNLOCK(sc); 1932} 1933 1934static void 1935sf_download_fw(struct sf_softc *sc) 1936{ 1937 uint32_t gfpinst; 1938 int i, ndx; 1939 uint8_t *p; 1940 1941 /* 1942 * A FP instruction is composed of 48bits so we have to 1943 * write it with two parts. 1944 */ 1945 p = txfwdata; 1946 ndx = 0; 1947 for (i = 0; i < sizeof(txfwdata) / SF_GFP_INST_BYTES; i++) { 1948 gfpinst = p[2] << 24 | p[3] << 16 | p[4] << 8 | p[5]; 1949 csr_write_4(sc, SF_TXGFP_MEM_BASE + ndx * 4, gfpinst); 1950 gfpinst = p[0] << 8 | p[1]; 1951 csr_write_4(sc, SF_TXGFP_MEM_BASE + (ndx + 1) * 4, gfpinst); 1952 p += SF_GFP_INST_BYTES; 1953 ndx += 2; 1954 } 1955 if (bootverbose) 1956 device_printf(sc->sf_dev, "%d Tx instructions downloaded\n", i); 1957 1958 p = rxfwdata; 1959 ndx = 0; 1960 for (i = 0; i < sizeof(rxfwdata) / SF_GFP_INST_BYTES; i++) { 1961 gfpinst = p[2] << 24 | p[3] << 16 | p[4] << 8 | p[5]; 1962 csr_write_4(sc, SF_RXGFP_MEM_BASE + (ndx * 4), gfpinst); 1963 gfpinst = p[0] << 8 | p[1]; 1964 csr_write_4(sc, SF_RXGFP_MEM_BASE + (ndx + 1) * 4, gfpinst); 1965 p += SF_GFP_INST_BYTES; 1966 ndx += 2; 1967 } 1968 if (bootverbose) 1969 device_printf(sc->sf_dev, "%d Rx instructions downloaded\n", i); 1970} 1971 1972static void 1973sf_init(void *xsc) 1974{ 1975 struct sf_softc *sc; 1976 1977 sc = (struct sf_softc *)xsc; 1978 SF_LOCK(sc); 1979 sf_init_locked(sc); 1980 SF_UNLOCK(sc); 1981} 1982 1983static void 1984sf_init_locked(struct sf_softc *sc) 1985{ 1986 struct ifnet *ifp; 1987 struct mii_data *mii; 1988 uint8_t eaddr[ETHER_ADDR_LEN]; 1989 bus_addr_t addr; 1990 int i; 1991 1992 SF_LOCK_ASSERT(sc); 1993 ifp = sc->sf_ifp; 1994 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1995 return; 1996 mii = device_get_softc(sc->sf_miibus); 1997 1998 sf_stop(sc); 1999 /* Reset the hardware to a known state. */ 2000 sf_reset(sc); 2001 2002 /* Init all the receive filter registers */ 2003 for (i = SF_RXFILT_PERFECT_BASE; 2004 i < (SF_RXFILT_HASH_MAX + 1); i += sizeof(uint32_t)) 2005 csr_write_4(sc, i, 0); 2006 2007 /* Empty stats counter registers. */ 2008 for (i = SF_STATS_BASE; i < (SF_STATS_END + 1); i += sizeof(uint32_t)) 2009 csr_write_4(sc, i, 0); 2010 2011 /* Init our MAC address. */ 2012 bcopy(IF_LLADDR(sc->sf_ifp), eaddr, sizeof(eaddr)); 2013 csr_write_4(sc, SF_PAR0, 2014 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 2015 csr_write_4(sc, SF_PAR1, eaddr[0] << 8 | eaddr[1]); 2016 sf_setperf(sc, 0, eaddr); 2017 2018 if (sf_init_rx_ring(sc) == ENOBUFS) { 2019 device_printf(sc->sf_dev, 2020 "initialization failed: no memory for rx buffers\n"); 2021 sf_stop(sc); 2022 return; 2023 } 2024 2025 sf_init_tx_ring(sc); 2026 2027 /* 2028 * 16 perfect address filtering. 2029 * Hash only multicast destination address, Accept matching 2030 * frames regardless of VLAN ID. 2031 */ 2032 csr_write_4(sc, SF_RXFILT, SF_PERFMODE_NORMAL | SF_HASHMODE_ANYVLAN); 2033 2034 /* 2035 * Set Rx filter. 2036 */ 2037 sf_rxfilter(sc); 2038 2039 /* Init the completion queue indexes. */ 2040 csr_write_4(sc, SF_CQ_CONSIDX, 0); 2041 csr_write_4(sc, SF_CQ_PRODIDX, 0); 2042 2043 /* Init the RX completion queue. */ 2044 addr = sc->sf_rdata.sf_rx_cring_paddr; 2045 csr_write_4(sc, SF_CQ_ADDR_HI, SF_ADDR_HI(addr)); 2046 csr_write_4(sc, SF_RXCQ_CTL_1, SF_ADDR_LO(addr) & SF_RXCQ_ADDR); 2047 if (SF_ADDR_HI(addr) != 0) 2048 SF_SETBIT(sc, SF_RXCQ_CTL_1, SF_RXCQ_USE_64BIT); 2049 /* Set RX completion queue type 2. */ 2050 SF_SETBIT(sc, SF_RXCQ_CTL_1, SF_RXCQTYPE_2); 2051 csr_write_4(sc, SF_RXCQ_CTL_2, 0); 2052 2053 /* 2054 * Init RX DMA control. 2055 * default RxHighPriority Threshold, 2056 * default RxBurstSize, 128bytes. 2057 */ 2058 SF_SETBIT(sc, SF_RXDMA_CTL, 2059 SF_RXDMA_REPORTBADPKTS | 2060 (SF_RXDMA_HIGHPRIO_THRESH << 8) | 2061 SF_RXDMA_BURST); 2062 2063 /* Init the RX buffer descriptor queue. */ 2064 addr = sc->sf_rdata.sf_rx_ring_paddr; 2065 csr_write_4(sc, SF_RXDQ_ADDR_HI, SF_ADDR_HI(addr)); 2066 csr_write_4(sc, SF_RXDQ_ADDR_Q1, SF_ADDR_LO(addr)); 2067 2068 /* Set RX queue buffer length. */ 2069 csr_write_4(sc, SF_RXDQ_CTL_1, 2070 ((MCLBYTES - sizeof(uint32_t)) << 16) | 2071 SF_RXDQCTL_64BITBADDR | SF_RXDQCTL_VARIABLE); 2072 2073 if (SF_ADDR_HI(addr) != 0) 2074 SF_SETBIT(sc, SF_RXDQ_CTL_1, SF_RXDQCTL_64BITDADDR); 2075 csr_write_4(sc, SF_RXDQ_PTR_Q1, SF_RX_DLIST_CNT - 1); 2076 csr_write_4(sc, SF_RXDQ_CTL_2, 0); 2077 2078 /* Init the TX completion queue */ 2079 addr = sc->sf_rdata.sf_tx_cring_paddr; 2080 csr_write_4(sc, SF_TXCQ_CTL, SF_ADDR_LO(addr) & SF_TXCQ_ADDR); 2081 if (SF_ADDR_HI(addr) != 0) 2082 SF_SETBIT(sc, SF_TXCQ_CTL, SF_TXCQ_USE_64BIT); 2083 2084 /* Init the TX buffer descriptor queue. */ 2085 addr = sc->sf_rdata.sf_tx_ring_paddr; 2086 csr_write_4(sc, SF_TXDQ_ADDR_HI, SF_ADDR_HI(addr)); 2087 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 0); 2088 csr_write_4(sc, SF_TXDQ_ADDR_LOPRIO, SF_ADDR_LO(addr)); 2089 csr_write_4(sc, SF_TX_FRAMCTL, 2090 SF_TXFRMCTL_CPLAFTERTX | sc->sf_txthresh); 2091 csr_write_4(sc, SF_TXDQ_CTL, 2092 SF_TXDMA_HIPRIO_THRESH << 24 | 2093 SF_TXSKIPLEN_0BYTES << 16 | 2094 SF_TXDDMA_BURST << 8 | 2095 SF_TXBUFDESC_TYPE2 | SF_TXMINSPACE_UNLIMIT); 2096 if (SF_ADDR_HI(addr) != 0) 2097 SF_SETBIT(sc, SF_TXDQ_CTL, SF_TXDQCTL_64BITADDR); 2098 2099 /* Set VLAN Type register. */ 2100 csr_write_4(sc, SF_VLANTYPE, ETHERTYPE_VLAN); 2101 2102 /* Set TxPause Timer. */ 2103 csr_write_4(sc, SF_TXPAUSETIMER, 0xffff); 2104 2105 /* Enable autopadding of short TX frames. */ 2106 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_AUTOPAD); 2107 SF_SETBIT(sc, SF_MACCFG_2, SF_MACCFG2_AUTOVLANPAD); 2108 /* Make sure to reset MAC to take changes effect. */ 2109 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 2110 DELAY(1000); 2111 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 2112 2113 /* Enable PCI bus master. */ 2114 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_PCIMEN); 2115 2116 /* Load StarFire firmware. */ 2117 sf_download_fw(sc); 2118 2119 /* Intialize interrupt moderation. */ 2120 csr_write_4(sc, SF_TIMER_CTL, SF_TIMER_IMASK_MODE | SF_TIMER_TIMES_TEN | 2121 (sc->sf_int_mod & SF_TIMER_IMASK_INTERVAL)); 2122 2123#ifdef DEVICE_POLLING 2124 /* Disable interrupts if we are polling. */ 2125 if ((ifp->if_capenable & IFCAP_POLLING) != 0) 2126 csr_write_4(sc, SF_IMR, 0x00000000); 2127 else 2128#endif 2129 /* Enable interrupts. */ 2130 csr_write_4(sc, SF_IMR, SF_INTRS); 2131 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_INTR_ENB); 2132 2133 /* Enable the RX and TX engines. */ 2134 csr_write_4(sc, SF_GEN_ETH_CTL, 2135 SF_ETHCTL_RX_ENB | SF_ETHCTL_RXDMA_ENB | 2136 SF_ETHCTL_TX_ENB | SF_ETHCTL_TXDMA_ENB); 2137 2138 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 2139 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_TXGFP_ENB); 2140 else 2141 SF_CLRBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_TXGFP_ENB); 2142 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 2143 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_RXGFP_ENB); 2144 else 2145 SF_CLRBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_RXGFP_ENB); 2146 2147 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2148 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2149 2150 sc->sf_link = 0; 2151 sf_ifmedia_upd_locked(ifp); 2152 2153 callout_reset(&sc->sf_co, hz, sf_tick, sc); 2154} 2155 2156static int 2157sf_encap(struct sf_softc *sc, struct mbuf **m_head) 2158{ 2159 struct sf_txdesc *txd; 2160 struct sf_tx_rdesc *desc; 2161 struct mbuf *m; 2162 bus_dmamap_t map; 2163 bus_dma_segment_t txsegs[SF_MAXTXSEGS]; 2164 int error, i, nsegs, prod, si; 2165 int avail, nskip; 2166 2167 SF_LOCK_ASSERT(sc); 2168 2169 m = *m_head; 2170 prod = sc->sf_cdata.sf_tx_prod; 2171 txd = &sc->sf_cdata.sf_txdesc[prod]; 2172 map = txd->tx_dmamap; 2173 error = bus_dmamap_load_mbuf_sg(sc->sf_cdata.sf_tx_tag, map, 2174 *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT); 2175 if (error == EFBIG) { 2176 m = m_collapse(*m_head, M_DONTWAIT, SF_MAXTXSEGS); 2177 if (m == NULL) { 2178 m_freem(*m_head); 2179 *m_head = NULL; 2180 return (ENOBUFS); 2181 } 2182 *m_head = m; 2183 error = bus_dmamap_load_mbuf_sg(sc->sf_cdata.sf_tx_tag, 2184 map, *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT); 2185 if (error != 0) { 2186 m_freem(*m_head); 2187 *m_head = NULL; 2188 return (error); 2189 } 2190 } else if (error != 0) 2191 return (error); 2192 if (nsegs == 0) { 2193 m_freem(*m_head); 2194 *m_head = NULL; 2195 return (EIO); 2196 } 2197 2198 /* Check number of available descriptors. */ 2199 avail = (SF_TX_DLIST_CNT - 1) - sc->sf_cdata.sf_tx_cnt; 2200 if (avail < nsegs) { 2201 bus_dmamap_unload(sc->sf_cdata.sf_tx_tag, map); 2202 return (ENOBUFS); 2203 } 2204 nskip = 0; 2205 if (prod + nsegs >= SF_TX_DLIST_CNT) { 2206 nskip = SF_TX_DLIST_CNT - prod - 1; 2207 if (avail < nsegs + nskip) { 2208 bus_dmamap_unload(sc->sf_cdata.sf_tx_tag, map); 2209 return (ENOBUFS); 2210 } 2211 } 2212 2213 bus_dmamap_sync(sc->sf_cdata.sf_tx_tag, map, BUS_DMASYNC_PREWRITE); 2214 2215 si = prod; 2216 for (i = 0; i < nsegs; i++) { 2217 desc = &sc->sf_rdata.sf_tx_ring[prod]; 2218 desc->sf_tx_ctrl = htole32(SF_TX_DESC_ID | 2219 (txsegs[i].ds_len & SF_TX_DESC_FRAGLEN)); 2220 desc->sf_tx_reserved = 0; 2221 desc->sf_addr = htole64(txsegs[i].ds_addr); 2222 if (i == 0 && prod + nsegs >= SF_TX_DLIST_CNT) { 2223 /* Queue wraps! */ 2224 desc->sf_tx_ctrl |= htole32(SF_TX_DESC_END); 2225 prod = 0; 2226 } else 2227 SF_INC(prod, SF_TX_DLIST_CNT); 2228 } 2229 /* Update producer index. */ 2230 sc->sf_cdata.sf_tx_prod = prod; 2231 sc->sf_cdata.sf_tx_cnt += nsegs + nskip; 2232 2233 desc = &sc->sf_rdata.sf_tx_ring[si]; 2234 /* Check TDP/UDP checksum offload request. */ 2235 if ((m->m_pkthdr.csum_flags & SF_CSUM_FEATURES) != 0) 2236 desc->sf_tx_ctrl |= htole32(SF_TX_DESC_CALTCP); 2237 desc->sf_tx_ctrl |= 2238 htole32(SF_TX_DESC_CRCEN | SF_TX_DESC_INTR | (nsegs << 16)); 2239 2240 txd->tx_dmamap = map; 2241 txd->tx_m = m; 2242 txd->ndesc = nsegs + nskip; 2243 2244 return (0); 2245} 2246 2247static void 2248sf_start(struct ifnet *ifp) 2249{ 2250 struct sf_softc *sc; 2251 2252 sc = ifp->if_softc; 2253 SF_LOCK(sc); 2254 sf_start_locked(ifp); 2255 SF_UNLOCK(sc); 2256} 2257 2258static void 2259sf_start_locked(struct ifnet *ifp) 2260{ 2261 struct sf_softc *sc; 2262 struct mbuf *m_head; 2263 int enq; 2264 2265 sc = ifp->if_softc; 2266 SF_LOCK_ASSERT(sc); 2267 2268 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2269 IFF_DRV_RUNNING || sc->sf_link == 0) 2270 return; 2271 2272 /* 2273 * Since we don't know when descriptor wrap occurrs in advance 2274 * limit available number of active Tx descriptor counter to be 2275 * higher than maximum number of DMA segments allowed in driver. 2276 */ 2277 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2278 sc->sf_cdata.sf_tx_cnt < SF_TX_DLIST_CNT - SF_MAXTXSEGS; ) { 2279 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2280 if (m_head == NULL) 2281 break; 2282 /* 2283 * Pack the data into the transmit ring. If we 2284 * don't have room, set the OACTIVE flag and wait 2285 * for the NIC to drain the ring. 2286 */ 2287 if (sf_encap(sc, &m_head)) { 2288 if (m_head == NULL) 2289 break; 2290 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2291 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2292 break; 2293 } 2294 2295 enq++; 2296 /* 2297 * If there's a BPF listener, bounce a copy of this frame 2298 * to him. 2299 */ 2300 ETHER_BPF_MTAP(ifp, m_head); 2301 } 2302 2303 if (enq > 0) { 2304 bus_dmamap_sync(sc->sf_cdata.sf_tx_ring_tag, 2305 sc->sf_cdata.sf_tx_ring_map, 2306 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2307 /* Kick transmit. */ 2308 csr_write_4(sc, SF_TXDQ_PRODIDX, 2309 sc->sf_cdata.sf_tx_prod * (sizeof(struct sf_tx_rdesc) / 8)); 2310 2311 /* Set a timeout in case the chip goes out to lunch. */ 2312 sc->sf_watchdog_timer = 5; 2313 } 2314} 2315 2316static void 2317sf_stop(struct sf_softc *sc) 2318{ 2319 struct sf_txdesc *txd; 2320 struct sf_rxdesc *rxd; 2321 struct ifnet *ifp; 2322 int i; 2323 2324 SF_LOCK_ASSERT(sc); 2325 2326 ifp = sc->sf_ifp; 2327 2328 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2329 sc->sf_link = 0; 2330 callout_stop(&sc->sf_co); 2331 sc->sf_watchdog_timer = 0; 2332 2333 /* Reading the ISR register clears all interrrupts. */ 2334 csr_read_4(sc, SF_ISR); 2335 /* Disable further interrupts. */ 2336 csr_write_4(sc, SF_IMR, 0); 2337 2338 /* Disable Tx/Rx egine. */ 2339 csr_write_4(sc, SF_GEN_ETH_CTL, 0); 2340 2341 /* Give hardware chance to drain active DMA cycles. */ 2342 DELAY(1000); 2343 2344 csr_write_4(sc, SF_CQ_CONSIDX, 0); 2345 csr_write_4(sc, SF_CQ_PRODIDX, 0); 2346 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 0); 2347 csr_write_4(sc, SF_RXDQ_CTL_1, 0); 2348 csr_write_4(sc, SF_RXDQ_PTR_Q1, 0); 2349 csr_write_4(sc, SF_TXCQ_CTL, 0); 2350 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 0); 2351 csr_write_4(sc, SF_TXDQ_CTL, 0); 2352 2353 /* 2354 * Free RX and TX mbufs still in the queues. 2355 */ 2356 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 2357 rxd = &sc->sf_cdata.sf_rxdesc[i]; 2358 if (rxd->rx_m != NULL) { 2359 bus_dmamap_sync(sc->sf_cdata.sf_rx_tag, 2360 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 2361 bus_dmamap_unload(sc->sf_cdata.sf_rx_tag, 2362 rxd->rx_dmamap); 2363 m_freem(rxd->rx_m); 2364 rxd->rx_m = NULL; 2365 } 2366 } 2367 for (i = 0; i < SF_TX_DLIST_CNT; i++) { 2368 txd = &sc->sf_cdata.sf_txdesc[i]; 2369 if (txd->tx_m != NULL) { 2370 bus_dmamap_sync(sc->sf_cdata.sf_tx_tag, 2371 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2372 bus_dmamap_unload(sc->sf_cdata.sf_tx_tag, 2373 txd->tx_dmamap); 2374 m_freem(txd->tx_m); 2375 txd->tx_m = NULL; 2376 txd->ndesc = 0; 2377 } 2378 } 2379} 2380 2381static void 2382sf_tick(void *xsc) 2383{ 2384 struct sf_softc *sc; 2385 struct mii_data *mii; 2386 2387 sc = xsc; 2388 SF_LOCK_ASSERT(sc); 2389 mii = device_get_softc(sc->sf_miibus); 2390 mii_tick(mii); 2391 sf_stats_update(sc); 2392 sf_watchdog(sc); 2393 callout_reset(&sc->sf_co, hz, sf_tick, sc); 2394} 2395 2396/* 2397 * Note: it is important that this function not be interrupted. We 2398 * use a two-stage register access scheme: if we are interrupted in 2399 * between setting the indirect address register and reading from the 2400 * indirect data register, the contents of the address register could 2401 * be changed out from under us. 2402 */ 2403static void 2404sf_stats_update(struct sf_softc *sc) 2405{ 2406 struct ifnet *ifp; 2407 struct sf_stats now, *stats, *nstats; 2408 int i; 2409 2410 SF_LOCK_ASSERT(sc); 2411 2412 ifp = sc->sf_ifp; 2413 stats = &now; 2414 2415 stats->sf_tx_frames = 2416 csr_read_4(sc, SF_STATS_BASE + SF_STATS_TX_FRAMES); 2417 stats->sf_tx_single_colls = 2418 csr_read_4(sc, SF_STATS_BASE + SF_STATS_TX_SINGLE_COL); 2419 stats->sf_tx_multi_colls = 2420 csr_read_4(sc, SF_STATS_BASE + SF_STATS_TX_MULTI_COL); 2421 stats->sf_tx_crcerrs = 2422 csr_read_4(sc, SF_STATS_BASE + SF_STATS_TX_CRC_ERRS); 2423 stats->sf_tx_bytes = 2424 csr_read_4(sc, SF_STATS_BASE + SF_STATS_TX_BYTES); 2425 stats->sf_tx_deferred = 2426 csr_read_4(sc, SF_STATS_BASE + SF_STATS_TX_DEFERRED); 2427 stats->sf_tx_late_colls = 2428 csr_read_4(sc, SF_STATS_BASE + SF_STATS_TX_LATE_COL); 2429 stats->sf_tx_pause_frames = 2430 csr_read_4(sc, SF_STATS_BASE + SF_STATS_TX_PAUSE); 2431 stats->sf_tx_control_frames = 2432 csr_read_4(sc, SF_STATS_BASE + SF_STATS_TX_CTL_FRAME); 2433 stats->sf_tx_excess_colls = 2434 csr_read_4(sc, SF_STATS_BASE + SF_STATS_TX_EXCESS_COL); 2435 stats->sf_tx_excess_defer = 2436 csr_read_4(sc, SF_STATS_BASE + SF_STATS_TX_EXCESS_DEF); 2437 stats->sf_tx_mcast_frames = 2438 csr_read_4(sc, SF_STATS_BASE + SF_STATS_TX_MULTI); 2439 stats->sf_tx_bcast_frames = 2440 csr_read_4(sc, SF_STATS_BASE + SF_STATS_TX_BCAST); 2441 stats->sf_tx_frames_lost = 2442 csr_read_4(sc, SF_STATS_BASE + SF_STATS_TX_FRAME_LOST); 2443 stats->sf_rx_frames = 2444 csr_read_4(sc, SF_STATS_BASE + SF_STATS_RX_FRAMES); 2445 stats->sf_rx_crcerrs = 2446 csr_read_4(sc, SF_STATS_BASE + SF_STATS_RX_CRC_ERRS); 2447 stats->sf_rx_alignerrs = 2448 csr_read_4(sc, SF_STATS_BASE + SF_STATS_RX_ALIGN_ERRS); 2449 stats->sf_rx_bytes = 2450 csr_read_4(sc, SF_STATS_BASE + SF_STATS_RX_BYTES); 2451 stats->sf_rx_pause_frames = 2452 csr_read_4(sc, SF_STATS_BASE + SF_STATS_RX_PAUSE); 2453 stats->sf_rx_control_frames = 2454 csr_read_4(sc, SF_STATS_BASE + SF_STATS_RX_CTL_FRAME); 2455 stats->sf_rx_unsup_control_frames = 2456 csr_read_4(sc, SF_STATS_BASE + SF_STATS_RX_UNSUP_FRAME); 2457 stats->sf_rx_giants = 2458 csr_read_4(sc, SF_STATS_BASE + SF_STATS_RX_GIANTS); 2459 stats->sf_rx_runts = 2460 csr_read_4(sc, SF_STATS_BASE + SF_STATS_RX_RUNTS); 2461 stats->sf_rx_jabbererrs = 2462 csr_read_4(sc, SF_STATS_BASE + SF_STATS_RX_JABBER); 2463 stats->sf_rx_fragments = 2464 csr_read_4(sc, SF_STATS_BASE + SF_STATS_RX_FRAGMENTS); 2465 stats->sf_rx_pkts_64 = 2466 csr_read_4(sc, SF_STATS_BASE + SF_STATS_RX_64); 2467 stats->sf_rx_pkts_65_127 = 2468 csr_read_4(sc, SF_STATS_BASE + SF_STATS_RX_65_127); 2469 stats->sf_rx_pkts_128_255 = 2470 csr_read_4(sc, SF_STATS_BASE + SF_STATS_RX_128_255); 2471 stats->sf_rx_pkts_256_511 = 2472 csr_read_4(sc, SF_STATS_BASE + SF_STATS_RX_256_511); 2473 stats->sf_rx_pkts_512_1023 = 2474 csr_read_4(sc, SF_STATS_BASE + SF_STATS_RX_512_1023); 2475 stats->sf_rx_pkts_1024_1518 = 2476 csr_read_4(sc, SF_STATS_BASE + SF_STATS_RX_1024_1518); 2477 stats->sf_rx_frames_lost = 2478 csr_read_4(sc, SF_STATS_BASE + SF_STATS_RX_FRAME_LOST); 2479 /* Lower 16bits are valid. */ 2480 stats->sf_tx_underruns = 2481 (csr_read_4(sc, SF_STATS_BASE + SF_STATS_TX_UNDERRUN) & 0xffff); 2482 2483 /* Empty stats counter registers. */ 2484 for (i = SF_STATS_BASE; i < (SF_STATS_END + 1); i += sizeof(uint32_t)) 2485 csr_write_4(sc, i, 0); 2486 2487 ifp->if_opackets += (u_long)stats->sf_tx_frames; 2488 2489 ifp->if_collisions += (u_long)stats->sf_tx_single_colls + 2490 (u_long)stats->sf_tx_multi_colls; 2491 2492 ifp->if_oerrors += (u_long)stats->sf_tx_excess_colls + 2493 (u_long)stats->sf_tx_excess_defer + 2494 (u_long)stats->sf_tx_frames_lost; 2495 2496 ifp->if_ipackets += (u_long)stats->sf_rx_frames; 2497 2498 ifp->if_ierrors += (u_long)stats->sf_rx_crcerrs + 2499 (u_long)stats->sf_rx_alignerrs + 2500 (u_long)stats->sf_rx_giants + 2501 (u_long)stats->sf_rx_runts + 2502 (u_long)stats->sf_rx_jabbererrs + 2503 (u_long)stats->sf_rx_frames_lost; 2504 2505 nstats = &sc->sf_statistics; 2506 2507 nstats->sf_tx_frames += stats->sf_tx_frames; 2508 nstats->sf_tx_single_colls += stats->sf_tx_single_colls; 2509 nstats->sf_tx_multi_colls += stats->sf_tx_multi_colls; 2510 nstats->sf_tx_crcerrs += stats->sf_tx_crcerrs; 2511 nstats->sf_tx_bytes += stats->sf_tx_bytes; 2512 nstats->sf_tx_deferred += stats->sf_tx_deferred; 2513 nstats->sf_tx_late_colls += stats->sf_tx_late_colls; 2514 nstats->sf_tx_pause_frames += stats->sf_tx_pause_frames; 2515 nstats->sf_tx_control_frames += stats->sf_tx_control_frames; 2516 nstats->sf_tx_excess_colls += stats->sf_tx_excess_colls; 2517 nstats->sf_tx_excess_defer += stats->sf_tx_excess_defer; 2518 nstats->sf_tx_mcast_frames += stats->sf_tx_mcast_frames; 2519 nstats->sf_tx_bcast_frames += stats->sf_tx_bcast_frames; 2520 nstats->sf_tx_frames_lost += stats->sf_tx_frames_lost; 2521 nstats->sf_rx_frames += stats->sf_rx_frames; 2522 nstats->sf_rx_crcerrs += stats->sf_rx_crcerrs; 2523 nstats->sf_rx_alignerrs += stats->sf_rx_alignerrs; 2524 nstats->sf_rx_bytes += stats->sf_rx_bytes; 2525 nstats->sf_rx_pause_frames += stats->sf_rx_pause_frames; 2526 nstats->sf_rx_control_frames += stats->sf_rx_control_frames; 2527 nstats->sf_rx_unsup_control_frames += stats->sf_rx_unsup_control_frames; 2528 nstats->sf_rx_giants += stats->sf_rx_giants; 2529 nstats->sf_rx_runts += stats->sf_rx_runts; 2530 nstats->sf_rx_jabbererrs += stats->sf_rx_jabbererrs; 2531 nstats->sf_rx_fragments += stats->sf_rx_fragments; 2532 nstats->sf_rx_pkts_64 += stats->sf_rx_pkts_64; 2533 nstats->sf_rx_pkts_65_127 += stats->sf_rx_pkts_65_127; 2534 nstats->sf_rx_pkts_128_255 += stats->sf_rx_pkts_128_255; 2535 nstats->sf_rx_pkts_256_511 += stats->sf_rx_pkts_256_511; 2536 nstats->sf_rx_pkts_512_1023 += stats->sf_rx_pkts_512_1023; 2537 nstats->sf_rx_pkts_1024_1518 += stats->sf_rx_pkts_1024_1518; 2538 nstats->sf_rx_frames_lost += stats->sf_rx_frames_lost; 2539 nstats->sf_tx_underruns += stats->sf_tx_underruns; 2540} 2541 2542static void 2543sf_watchdog(struct sf_softc *sc) 2544{ 2545 struct ifnet *ifp; 2546 2547 SF_LOCK_ASSERT(sc); 2548 2549 if (sc->sf_watchdog_timer == 0 || --sc->sf_watchdog_timer) 2550 return; 2551 2552 ifp = sc->sf_ifp; 2553 2554 ifp->if_oerrors++; 2555 if (sc->sf_link == 0) { 2556 if (bootverbose) 2557 if_printf(sc->sf_ifp, "watchdog timeout " 2558 "(missed link)\n"); 2559 } else 2560 if_printf(ifp, "watchdog timeout, %d Tx descs are active\n", 2561 sc->sf_cdata.sf_tx_cnt); 2562 2563 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2564 sf_init_locked(sc); 2565 2566 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2567 sf_start_locked(ifp); 2568} 2569 2570static int 2571sf_shutdown(device_t dev) 2572{ 2573 struct sf_softc *sc; 2574 2575 sc = device_get_softc(dev); 2576 2577 SF_LOCK(sc); 2578 sf_stop(sc); 2579 SF_UNLOCK(sc); 2580 2581 return (0); 2582} 2583 2584static int 2585sf_suspend(device_t dev) 2586{ 2587 struct sf_softc *sc; 2588 2589 sc = device_get_softc(dev); 2590 2591 SF_LOCK(sc); 2592 sf_stop(sc); 2593 sc->sf_suspended = 1; 2594 bus_generic_suspend(dev); 2595 SF_UNLOCK(sc); 2596 2597 return (0); 2598} 2599 2600static int 2601sf_resume(device_t dev) 2602{ 2603 struct sf_softc *sc; 2604 struct ifnet *ifp; 2605 2606 sc = device_get_softc(dev); 2607 2608 SF_LOCK(sc); 2609 bus_generic_resume(dev); 2610 ifp = sc->sf_ifp; 2611 if ((ifp->if_flags & IFF_UP) != 0) 2612 sf_init_locked(sc); 2613 2614 sc->sf_suspended = 0; 2615 SF_UNLOCK(sc); 2616 2617 return (0); 2618} 2619 2620static int 2621sf_sysctl_stats(SYSCTL_HANDLER_ARGS) 2622{ 2623 struct sf_softc *sc; 2624 struct sf_stats *stats; 2625 int error; 2626 int result; 2627 2628 result = -1; 2629 error = sysctl_handle_int(oidp, &result, 0, req); 2630 2631 if (error != 0 || req->newptr == NULL) 2632 return (error); 2633 2634 if (result != 1) 2635 return (error); 2636 2637 sc = (struct sf_softc *)arg1; 2638 stats = &sc->sf_statistics; 2639 2640 printf("%s statistics:\n", device_get_nameunit(sc->sf_dev)); 2641 printf("Transmit good frames : %ju\n", 2642 (uintmax_t)stats->sf_tx_frames); 2643 printf("Transmit good octets : %ju\n", 2644 (uintmax_t)stats->sf_tx_bytes); 2645 printf("Transmit single collisions : %u\n", 2646 stats->sf_tx_single_colls); 2647 printf("Transmit multiple collisions : %u\n", 2648 stats->sf_tx_multi_colls); 2649 printf("Transmit late collisions : %u\n", 2650 stats->sf_tx_late_colls); 2651 printf("Transmit abort due to excessive collisions : %u\n", 2652 stats->sf_tx_excess_colls); 2653 printf("Transmit CRC errors : %u\n", 2654 stats->sf_tx_crcerrs); 2655 printf("Transmit deferrals : %u\n", 2656 stats->sf_tx_deferred); 2657 printf("Transmit abort due to excessive deferrals : %u\n", 2658 stats->sf_tx_excess_defer); 2659 printf("Transmit pause control frames : %u\n", 2660 stats->sf_tx_pause_frames); 2661 printf("Transmit control frames : %u\n", 2662 stats->sf_tx_control_frames); 2663 printf("Transmit good multicast frames : %u\n", 2664 stats->sf_tx_mcast_frames); 2665 printf("Transmit good broadcast frames : %u\n", 2666 stats->sf_tx_bcast_frames); 2667 printf("Transmit frames lost due to internal transmit errors : %u\n", 2668 stats->sf_tx_frames_lost); 2669 printf("Transmit FIFO underflows : %u\n", 2670 stats->sf_tx_underruns); 2671 printf("Transmit GFP stalls : %u\n", stats->sf_tx_gfp_stall); 2672 printf("Receive good frames : %ju\n", 2673 (uint64_t)stats->sf_rx_frames); 2674 printf("Receive good octets : %ju\n", 2675 (uint64_t)stats->sf_rx_bytes); 2676 printf("Receive CRC errors : %u\n", 2677 stats->sf_rx_crcerrs); 2678 printf("Receive alignment errors : %u\n", 2679 stats->sf_rx_alignerrs); 2680 printf("Receive pause frames : %u\n", 2681 stats->sf_rx_pause_frames); 2682 printf("Receive control frames : %u\n", 2683 stats->sf_rx_control_frames); 2684 printf("Receive control frames with unsupported opcode : %u\n", 2685 stats->sf_rx_unsup_control_frames); 2686 printf("Receive frames too long : %u\n", 2687 stats->sf_rx_giants); 2688 printf("Receive frames too short : %u\n", 2689 stats->sf_rx_runts); 2690 printf("Receive frames jabber errors : %u\n", 2691 stats->sf_rx_jabbererrs); 2692 printf("Receive frames fragments : %u\n", 2693 stats->sf_rx_fragments); 2694 printf("Receive packets 64 bytes : %ju\n", 2695 (uint64_t)stats->sf_rx_pkts_64); 2696 printf("Receive packets 65 to 127 bytes : %ju\n", 2697 (uint64_t)stats->sf_rx_pkts_65_127); 2698 printf("Receive packets 128 to 255 bytes : %ju\n", 2699 (uint64_t)stats->sf_rx_pkts_128_255); 2700 printf("Receive packets 256 to 511 bytes : %ju\n", 2701 (uint64_t)stats->sf_rx_pkts_256_511); 2702 printf("Receive packets 512 to 1023 bytes : %ju\n", 2703 (uint64_t)stats->sf_rx_pkts_512_1023); 2704 printf("Receive packets 1024 to 1518 bytes : %ju\n", 2705 (uint64_t)stats->sf_rx_pkts_1024_1518); 2706 printf("Receive frames lost due to internal receive errors : %u\n", 2707 stats->sf_rx_frames_lost); 2708 printf("Receive GFP stalls : %u\n", stats->sf_rx_gfp_stall); 2709 2710 return (error); 2711} 2712 2713static int 2714sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 2715{ 2716 int error, value; 2717 2718 if (!arg1) 2719 return (EINVAL); 2720 value = *(int *)arg1; 2721 error = sysctl_handle_int(oidp, &value, 0, req); 2722 if (error || !req->newptr) 2723 return (error); 2724 if (value < low || value > high) 2725 return (EINVAL); 2726 *(int *)arg1 = value; 2727 2728 return (0); 2729} 2730 2731static int 2732sysctl_hw_sf_int_mod(SYSCTL_HANDLER_ARGS) 2733{ 2734 2735 return (sysctl_int_range(oidp, arg1, arg2, req, SF_IM_MIN, SF_IM_MAX)); 2736} 2737