if_sf.c revision 166901
1/*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/sf/if_sf.c 166901 2007-02-23 12:19:07Z piso $"); 35 36/* 37 * Adaptec AIC-6915 "Starfire" PCI fast ethernet driver for FreeBSD. 38 * Programming manual is available from: 39 * http://download.adaptec.com/pdfs/user_guides/aic6915_pg.pdf. 40 * 41 * Written by Bill Paul <wpaul@ctr.columbia.edu> 42 * Department of Electical Engineering 43 * Columbia University, New York City 44 */ 45/* 46 * The Adaptec AIC-6915 "Starfire" is a 64-bit 10/100 PCI ethernet 47 * controller designed with flexibility and reducing CPU load in mind. 48 * The Starfire offers high and low priority buffer queues, a 49 * producer/consumer index mechanism and several different buffer 50 * queue and completion queue descriptor types. Any one of a number 51 * of different driver designs can be used, depending on system and 52 * OS requirements. This driver makes use of type0 transmit frame 53 * descriptors (since BSD fragments packets across an mbuf chain) 54 * and two RX buffer queues prioritized on size (one queue for small 55 * frames that will fit into a single mbuf, another with full size 56 * mbuf clusters for everything else). The producer/consumer indexes 57 * and completion queues are also used. 58 * 59 * One downside to the Starfire has to do with alignment: buffer 60 * queues must be aligned on 256-byte boundaries, and receive buffers 61 * must be aligned on longword boundaries. The receive buffer alignment 62 * causes problems on the Alpha platform, where the packet payload 63 * should be longword aligned. There is no simple way around this. 64 * 65 * For receive filtering, the Starfire offers 16 perfect filter slots 66 * and a 512-bit hash table. 67 * 68 * The Starfire has no internal transceiver, relying instead on an 69 * external MII-based transceiver. Accessing registers on external 70 * PHYs is done through a special register map rather than with the 71 * usual bitbang MDIO method. 72 * 73 * Acesssing the registers on the Starfire is a little tricky. The 74 * Starfire has a 512K internal register space. When programmed for 75 * PCI memory mapped mode, the entire register space can be accessed 76 * directly. However in I/O space mode, only 256 bytes are directly 77 * mapped into PCI I/O space. The other registers can be accessed 78 * indirectly using the SF_INDIRECTIO_ADDR and SF_INDIRECTIO_DATA 79 * registers inside the 256-byte I/O window. 80 */ 81 82#ifdef HAVE_KERNEL_OPTION_HEADERS 83#include "opt_device_polling.h" 84#endif 85 86#include <sys/param.h> 87#include <sys/systm.h> 88#include <sys/sockio.h> 89#include <sys/mbuf.h> 90#include <sys/malloc.h> 91#include <sys/kernel.h> 92#include <sys/module.h> 93#include <sys/socket.h> 94 95#include <net/if.h> 96#include <net/if_arp.h> 97#include <net/ethernet.h> 98#include <net/if_dl.h> 99#include <net/if_media.h> 100#include <net/if_types.h> 101 102#include <net/bpf.h> 103 104#include <vm/vm.h> /* for vtophys */ 105#include <vm/pmap.h> /* for vtophys */ 106#include <machine/bus.h> 107#include <machine/resource.h> 108#include <sys/bus.h> 109#include <sys/rman.h> 110 111#include <dev/mii/mii.h> 112#include <dev/mii/miivar.h> 113 114/* "device miibus" required. See GENERIC if you get errors here. */ 115#include "miibus_if.h" 116 117#include <dev/pci/pcireg.h> 118#include <dev/pci/pcivar.h> 119 120#define SF_USEIOSPACE 121 122#include <pci/if_sfreg.h> 123 124MODULE_DEPEND(sf, pci, 1, 1, 1); 125MODULE_DEPEND(sf, ether, 1, 1, 1); 126MODULE_DEPEND(sf, miibus, 1, 1, 1); 127 128static struct sf_type sf_devs[] = { 129 { AD_VENDORID, AD_DEVICEID_STARFIRE, 130 "Adaptec AIC-6915 10/100BaseTX" }, 131 { 0, 0, NULL } 132}; 133 134static int sf_probe(device_t); 135static int sf_attach(device_t); 136static int sf_detach(device_t); 137static void sf_intr(void *); 138static void sf_stats_update(void *); 139static void sf_rxeof(struct sf_softc *); 140static void sf_txeof(struct sf_softc *); 141static int sf_encap(struct sf_softc *, struct sf_tx_bufdesc_type0 *, 142 struct mbuf *); 143static void sf_start(struct ifnet *); 144static void sf_start_locked(struct ifnet *); 145static int sf_ioctl(struct ifnet *, u_long, caddr_t); 146static void sf_init(void *); 147static void sf_init_locked(struct sf_softc *); 148static void sf_stop(struct sf_softc *); 149static void sf_watchdog(struct ifnet *); 150static void sf_shutdown(device_t); 151static int sf_ifmedia_upd(struct ifnet *); 152static void sf_ifmedia_upd_locked(struct ifnet *); 153static void sf_ifmedia_sts(struct ifnet *, struct ifmediareq *); 154static void sf_reset(struct sf_softc *); 155static int sf_init_rx_ring(struct sf_softc *); 156static void sf_init_tx_ring(struct sf_softc *); 157static int sf_newbuf(struct sf_softc *, struct sf_rx_bufdesc_type0 *, 158 struct mbuf *); 159static void sf_setmulti(struct sf_softc *); 160static int sf_setperf(struct sf_softc *, int, caddr_t); 161static int sf_sethash(struct sf_softc *, caddr_t, int); 162#ifdef notdef 163static int sf_setvlan(struct sf_softc *, int, u_int32_t); 164#endif 165 166static u_int8_t sf_read_eeprom(struct sf_softc *, int); 167 168static int sf_miibus_readreg(device_t, int, int); 169static int sf_miibus_writereg(device_t, int, int, int); 170static void sf_miibus_statchg(device_t); 171#ifdef DEVICE_POLLING 172static void sf_poll(struct ifnet *ifp, enum poll_cmd cmd, int count); 173static void sf_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count); 174#endif 175 176static u_int32_t csr_read_4(struct sf_softc *, int); 177static void csr_write_4(struct sf_softc *, int, u_int32_t); 178static void sf_txthresh_adjust(struct sf_softc *); 179 180#ifdef SF_USEIOSPACE 181#define SF_RES SYS_RES_IOPORT 182#define SF_RID SF_PCI_LOIO 183#else 184#define SF_RES SYS_RES_MEMORY 185#define SF_RID SF_PCI_LOMEM 186#endif 187 188static device_method_t sf_methods[] = { 189 /* Device interface */ 190 DEVMETHOD(device_probe, sf_probe), 191 DEVMETHOD(device_attach, sf_attach), 192 DEVMETHOD(device_detach, sf_detach), 193 DEVMETHOD(device_shutdown, sf_shutdown), 194 195 /* bus interface */ 196 DEVMETHOD(bus_print_child, bus_generic_print_child), 197 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 198 199 /* MII interface */ 200 DEVMETHOD(miibus_readreg, sf_miibus_readreg), 201 DEVMETHOD(miibus_writereg, sf_miibus_writereg), 202 DEVMETHOD(miibus_statchg, sf_miibus_statchg), 203 204 { 0, 0 } 205}; 206 207static driver_t sf_driver = { 208 "sf", 209 sf_methods, 210 sizeof(struct sf_softc), 211}; 212 213static devclass_t sf_devclass; 214 215DRIVER_MODULE(sf, pci, sf_driver, sf_devclass, 0, 0); 216DRIVER_MODULE(miibus, sf, miibus_driver, miibus_devclass, 0, 0); 217 218#define SF_SETBIT(sc, reg, x) \ 219 csr_write_4(sc, reg, csr_read_4(sc, reg) | (x)) 220 221#define SF_CLRBIT(sc, reg, x) \ 222 csr_write_4(sc, reg, csr_read_4(sc, reg) & ~(x)) 223 224static u_int32_t 225csr_read_4(sc, reg) 226 struct sf_softc *sc; 227 int reg; 228{ 229 u_int32_t val; 230 231#ifdef SF_USEIOSPACE 232 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); 233 val = CSR_READ_4(sc, SF_INDIRECTIO_DATA); 234#else 235 val = CSR_READ_4(sc, (reg + SF_RMAP_INTREG_BASE)); 236#endif 237 238 return(val); 239} 240 241static u_int8_t 242sf_read_eeprom(sc, reg) 243 struct sf_softc *sc; 244 int reg; 245{ 246 u_int8_t val; 247 248 val = (csr_read_4(sc, SF_EEADDR_BASE + 249 (reg & 0xFFFFFFFC)) >> (8 * (reg & 3))) & 0xFF; 250 251 return(val); 252} 253 254static void 255csr_write_4(sc, reg, val) 256 struct sf_softc *sc; 257 int reg; 258 u_int32_t val; 259{ 260#ifdef SF_USEIOSPACE 261 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); 262 CSR_WRITE_4(sc, SF_INDIRECTIO_DATA, val); 263#else 264 CSR_WRITE_4(sc, (reg + SF_RMAP_INTREG_BASE), val); 265#endif 266} 267 268/* 269 * Copy the address 'mac' into the perfect RX filter entry at 270 * offset 'idx.' The perfect filter only has 16 entries so do 271 * some sanity tests. 272 */ 273static int 274sf_setperf(sc, idx, mac) 275 struct sf_softc *sc; 276 int idx; 277 caddr_t mac; 278{ 279 u_int16_t *p; 280 281 if (idx < 0 || idx > SF_RXFILT_PERFECT_CNT) 282 return(EINVAL); 283 284 if (mac == NULL) 285 return(EINVAL); 286 287 p = (u_int16_t *)mac; 288 289 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 290 (idx * SF_RXFILT_PERFECT_SKIP), htons(p[2])); 291 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 292 (idx * SF_RXFILT_PERFECT_SKIP) + 4, htons(p[1])); 293 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 294 (idx * SF_RXFILT_PERFECT_SKIP) + 8, htons(p[0])); 295 296 return(0); 297} 298 299/* 300 * Set the bit in the 512-bit hash table that corresponds to the 301 * specified mac address 'mac.' If 'prio' is nonzero, update the 302 * priority hash table instead of the filter hash table. 303 */ 304static int 305sf_sethash(sc, mac, prio) 306 struct sf_softc *sc; 307 caddr_t mac; 308 int prio; 309{ 310 u_int32_t h; 311 312 if (mac == NULL) 313 return(EINVAL); 314 315 h = ether_crc32_be(mac, ETHER_ADDR_LEN) >> 23; 316 317 if (prio) { 318 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_PRIOOFF + 319 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); 320 } else { 321 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_ADDROFF + 322 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); 323 } 324 325 return(0); 326} 327 328#ifdef notdef 329/* 330 * Set a VLAN tag in the receive filter. 331 */ 332static int 333sf_setvlan(sc, idx, vlan) 334 struct sf_softc *sc; 335 int idx; 336 u_int32_t vlan; 337{ 338 if (idx < 0 || idx >> SF_RXFILT_HASH_CNT) 339 return(EINVAL); 340 341 csr_write_4(sc, SF_RXFILT_HASH_BASE + 342 (idx * SF_RXFILT_HASH_SKIP) + SF_RXFILT_HASH_VLANOFF, vlan); 343 344 return(0); 345} 346#endif 347 348static int 349sf_miibus_readreg(dev, phy, reg) 350 device_t dev; 351 int phy, reg; 352{ 353 struct sf_softc *sc; 354 int i; 355 u_int32_t val = 0; 356 357 sc = device_get_softc(dev); 358 359 for (i = 0; i < SF_TIMEOUT; i++) { 360 val = csr_read_4(sc, SF_PHY_REG(phy, reg)); 361 if (val & SF_MII_DATAVALID) 362 break; 363 } 364 365 if (i == SF_TIMEOUT) 366 return(0); 367 368 if ((val & 0x0000FFFF) == 0xFFFF) 369 return(0); 370 371 return(val & 0x0000FFFF); 372} 373 374static int 375sf_miibus_writereg(dev, phy, reg, val) 376 device_t dev; 377 int phy, reg, val; 378{ 379 struct sf_softc *sc; 380 int i; 381 int busy; 382 383 sc = device_get_softc(dev); 384 385 csr_write_4(sc, SF_PHY_REG(phy, reg), val); 386 387 for (i = 0; i < SF_TIMEOUT; i++) { 388 busy = csr_read_4(sc, SF_PHY_REG(phy, reg)); 389 if (!(busy & SF_MII_BUSY)) 390 break; 391 } 392 393 return(0); 394} 395 396static void 397sf_miibus_statchg(dev) 398 device_t dev; 399{ 400 struct sf_softc *sc; 401 struct mii_data *mii; 402 403 sc = device_get_softc(dev); 404 mii = device_get_softc(sc->sf_miibus); 405 406 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 407 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 408 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_FDX); 409 } else { 410 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 411 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_HDX); 412 } 413} 414 415static void 416sf_setmulti(sc) 417 struct sf_softc *sc; 418{ 419 struct ifnet *ifp; 420 int i; 421 struct ifmultiaddr *ifma; 422 u_int8_t dummy[] = { 0, 0, 0, 0, 0, 0 }; 423 424 ifp = sc->sf_ifp; 425 426 /* First zot all the existing filters. */ 427 for (i = 1; i < SF_RXFILT_PERFECT_CNT; i++) 428 sf_setperf(sc, i, (char *)&dummy); 429 for (i = SF_RXFILT_HASH_BASE; 430 i < (SF_RXFILT_HASH_MAX + 1); i += 4) 431 csr_write_4(sc, i, 0); 432 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI); 433 434 /* Now program new ones. */ 435 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 436 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI); 437 } else { 438 i = 1; 439 IF_ADDR_LOCK(ifp); 440 TAILQ_FOREACH_REVERSE(ifma, &ifp->if_multiaddrs, ifmultihead, ifma_link) { 441 if (ifma->ifma_addr->sa_family != AF_LINK) 442 continue; 443 /* 444 * Program the first 15 multicast groups 445 * into the perfect filter. For all others, 446 * use the hash table. 447 */ 448 if (i < SF_RXFILT_PERFECT_CNT) { 449 sf_setperf(sc, i, 450 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 451 i++; 452 continue; 453 } 454 455 sf_sethash(sc, 456 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 0); 457 } 458 IF_ADDR_UNLOCK(ifp); 459 } 460} 461 462/* 463 * Set media options. 464 */ 465static int 466sf_ifmedia_upd(ifp) 467 struct ifnet *ifp; 468{ 469 struct sf_softc *sc; 470 471 sc = ifp->if_softc; 472 SF_LOCK(sc); 473 sf_ifmedia_upd_locked(ifp); 474 SF_UNLOCK(sc); 475 476 return(0); 477} 478 479static void 480sf_ifmedia_upd_locked(ifp) 481 struct ifnet *ifp; 482{ 483 struct sf_softc *sc; 484 struct mii_data *mii; 485 486 sc = ifp->if_softc; 487 mii = device_get_softc(sc->sf_miibus); 488 SF_LOCK_ASSERT(sc); 489 sc->sf_link = 0; 490 if (mii->mii_instance) { 491 struct mii_softc *miisc; 492 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 493 mii_phy_reset(miisc); 494 } 495 mii_mediachg(mii); 496} 497 498/* 499 * Report current media status. 500 */ 501static void 502sf_ifmedia_sts(ifp, ifmr) 503 struct ifnet *ifp; 504 struct ifmediareq *ifmr; 505{ 506 struct sf_softc *sc; 507 struct mii_data *mii; 508 509 sc = ifp->if_softc; 510 SF_LOCK(sc); 511 mii = device_get_softc(sc->sf_miibus); 512 513 mii_pollstat(mii); 514 ifmr->ifm_active = mii->mii_media_active; 515 ifmr->ifm_status = mii->mii_media_status; 516 SF_UNLOCK(sc); 517} 518 519static int 520sf_ioctl(ifp, command, data) 521 struct ifnet *ifp; 522 u_long command; 523 caddr_t data; 524{ 525 struct sf_softc *sc = ifp->if_softc; 526 struct ifreq *ifr = (struct ifreq *) data; 527 struct mii_data *mii; 528 int error = 0; 529 530 switch(command) { 531 case SIOCSIFFLAGS: 532 SF_LOCK(sc); 533 if (ifp->if_flags & IFF_UP) { 534 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 535 ifp->if_flags & IFF_PROMISC && 536 !(sc->sf_if_flags & IFF_PROMISC)) { 537 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 538 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING && 539 !(ifp->if_flags & IFF_PROMISC) && 540 sc->sf_if_flags & IFF_PROMISC) { 541 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 542 } else if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 543 sf_init_locked(sc); 544 } else { 545 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 546 sf_stop(sc); 547 } 548 sc->sf_if_flags = ifp->if_flags; 549 SF_UNLOCK(sc); 550 error = 0; 551 break; 552 case SIOCADDMULTI: 553 case SIOCDELMULTI: 554 SF_LOCK(sc); 555 sf_setmulti(sc); 556 SF_UNLOCK(sc); 557 error = 0; 558 break; 559 case SIOCGIFMEDIA: 560 case SIOCSIFMEDIA: 561 mii = device_get_softc(sc->sf_miibus); 562 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 563 break; 564 case SIOCSIFCAP: 565#ifdef DEVICE_POLLING 566 if (ifr->ifr_reqcap & IFCAP_POLLING && 567 !(ifp->if_capenable & IFCAP_POLLING)) { 568 error = ether_poll_register(sf_poll, ifp); 569 if (error) 570 return(error); 571 SF_LOCK(sc); 572 /* Disable interrupts */ 573 csr_write_4(sc, SF_IMR, 0x00000000); 574 ifp->if_capenable |= IFCAP_POLLING; 575 SF_UNLOCK(sc); 576 return (error); 577 578 } 579 if (!(ifr->ifr_reqcap & IFCAP_POLLING) && 580 ifp->if_capenable & IFCAP_POLLING) { 581 error = ether_poll_deregister(ifp); 582 /* Enable interrupts. */ 583 SF_LOCK(sc); 584 csr_write_4(sc, SF_IMR, SF_INTRS); 585 ifp->if_capenable &= ~IFCAP_POLLING; 586 SF_UNLOCK(sc); 587 return (error); 588 } 589#endif /* DEVICE_POLLING */ 590 break; 591 default: 592 error = ether_ioctl(ifp, command, data); 593 break; 594 } 595 596 return(error); 597} 598 599static void 600sf_reset(sc) 601 struct sf_softc *sc; 602{ 603 register int i; 604 605 csr_write_4(sc, SF_GEN_ETH_CTL, 0); 606 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 607 DELAY(1000); 608 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 609 610 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_RESET); 611 612 for (i = 0; i < SF_TIMEOUT; i++) { 613 DELAY(10); 614 if (!(csr_read_4(sc, SF_PCI_DEVCFG) & SF_PCIDEVCFG_RESET)) 615 break; 616 } 617 618 if (i == SF_TIMEOUT) 619 device_printf(sc->sf_dev, "reset never completed!\n"); 620 621 /* Wait a little while for the chip to get its brains in order. */ 622 DELAY(1000); 623} 624 625/* 626 * Probe for an Adaptec AIC-6915 chip. Check the PCI vendor and device 627 * IDs against our list and return a device name if we find a match. 628 * We also check the subsystem ID so that we can identify exactly which 629 * NIC has been found, if possible. 630 */ 631static int 632sf_probe(dev) 633 device_t dev; 634{ 635 struct sf_type *t; 636 637 t = sf_devs; 638 639 while(t->sf_name != NULL) { 640 if ((pci_get_vendor(dev) == t->sf_vid) && 641 (pci_get_device(dev) == t->sf_did)) { 642 switch((pci_read_config(dev, 643 SF_PCI_SUBVEN_ID, 4) >> 16) & 0xFFFF) { 644 case AD_SUBSYSID_62011_REV0: 645 case AD_SUBSYSID_62011_REV1: 646 device_set_desc(dev, 647 "Adaptec ANA-62011 10/100BaseTX"); 648 return (BUS_PROBE_DEFAULT); 649 case AD_SUBSYSID_62022: 650 device_set_desc(dev, 651 "Adaptec ANA-62022 10/100BaseTX"); 652 return (BUS_PROBE_DEFAULT); 653 case AD_SUBSYSID_62044_REV0: 654 case AD_SUBSYSID_62044_REV1: 655 device_set_desc(dev, 656 "Adaptec ANA-62044 10/100BaseTX"); 657 return (BUS_PROBE_DEFAULT); 658 case AD_SUBSYSID_62020: 659 device_set_desc(dev, 660 "Adaptec ANA-62020 10/100BaseFX"); 661 return (BUS_PROBE_DEFAULT); 662 case AD_SUBSYSID_69011: 663 device_set_desc(dev, 664 "Adaptec ANA-69011 10/100BaseTX"); 665 return (BUS_PROBE_DEFAULT); 666 default: 667 device_set_desc(dev, t->sf_name); 668 return (BUS_PROBE_DEFAULT); 669 break; 670 } 671 } 672 t++; 673 } 674 675 return(ENXIO); 676} 677 678/* 679 * Attach the interface. Allocate softc structures, do ifmedia 680 * setup and ethernet/BPF attach. 681 */ 682static int 683sf_attach(dev) 684 device_t dev; 685{ 686 int i; 687 struct sf_softc *sc; 688 struct ifnet *ifp; 689 int rid, error = 0; 690 u_char eaddr[6]; 691 692 sc = device_get_softc(dev); 693 sc->sf_dev = dev; 694 695 mtx_init(&sc->sf_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 696 MTX_DEF); 697 /* 698 * Map control/status registers. 699 */ 700 pci_enable_busmaster(dev); 701 702 rid = SF_RID; 703 sc->sf_res = bus_alloc_resource_any(dev, SF_RES, &rid, RF_ACTIVE); 704 705 if (sc->sf_res == NULL) { 706 device_printf(dev, "couldn't map ports\n"); 707 error = ENXIO; 708 goto fail; 709 } 710 711 sc->sf_btag = rman_get_bustag(sc->sf_res); 712 sc->sf_bhandle = rman_get_bushandle(sc->sf_res); 713 714 /* Allocate interrupt */ 715 rid = 0; 716 sc->sf_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 717 RF_SHAREABLE | RF_ACTIVE); 718 719 if (sc->sf_irq == NULL) { 720 device_printf(dev, "couldn't map interrupt\n"); 721 error = ENXIO; 722 goto fail; 723 } 724 725 callout_init_mtx(&sc->sf_stat_callout, &sc->sf_mtx, 0); 726 727 /* Reset the adapter. */ 728 sf_reset(sc); 729 730 /* 731 * Get station address from the EEPROM. 732 */ 733 for (i = 0; i < ETHER_ADDR_LEN; i++) 734 eaddr[i] = 735 sf_read_eeprom(sc, SF_EE_NODEADDR + ETHER_ADDR_LEN - i); 736 737 /* Allocate the descriptor queues. */ 738 sc->sf_ldata = contigmalloc(sizeof(struct sf_list_data), M_DEVBUF, 739 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 740 741 if (sc->sf_ldata == NULL) { 742 device_printf(dev, "no memory for list buffers!\n"); 743 error = ENXIO; 744 goto fail; 745 } 746 747 bzero(sc->sf_ldata, sizeof(struct sf_list_data)); 748 749 ifp = sc->sf_ifp = if_alloc(IFT_ETHER); 750 if (ifp == NULL) { 751 device_printf(dev, "can not if_alloc()\n"); 752 error = ENOSPC; 753 goto fail; 754 } 755 756 /* Do MII setup. */ 757 if (mii_phy_probe(dev, &sc->sf_miibus, 758 sf_ifmedia_upd, sf_ifmedia_sts)) { 759 device_printf(dev, "MII without any phy!\n"); 760 error = ENXIO; 761 goto fail; 762 } 763 764 ifp->if_softc = sc; 765 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 766 ifp->if_mtu = ETHERMTU; 767 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 768 ifp->if_ioctl = sf_ioctl; 769 ifp->if_start = sf_start; 770 ifp->if_watchdog = sf_watchdog; 771 ifp->if_init = sf_init; 772 IFQ_SET_MAXLEN(&ifp->if_snd, SF_TX_DLIST_CNT - 1); 773 ifp->if_snd.ifq_drv_maxlen = SF_TX_DLIST_CNT - 1; 774 IFQ_SET_READY(&ifp->if_snd); 775 ifp->if_capenable = ifp->if_capabilities; 776#ifdef DEVICE_POLLING 777 ifp->if_capabilities |= IFCAP_POLLING; 778#endif 779 780 /* 781 * Call MI attach routine. 782 */ 783 ether_ifattach(ifp, eaddr); 784 785 /* Hook interrupt last to avoid having to lock softc */ 786 error = bus_setup_intr(dev, sc->sf_irq, INTR_TYPE_NET | INTR_MPSAFE, 787 NULL, sf_intr, sc, &sc->sf_intrhand); 788 789 if (error) { 790 device_printf(dev, "couldn't set up irq\n"); 791 ether_ifdetach(ifp); 792 goto fail; 793 } 794 795fail: 796 if (error) 797 sf_detach(dev); 798 799 return(error); 800} 801 802/* 803 * Shutdown hardware and free up resources. This can be called any 804 * time after the mutex has been initialized. It is called in both 805 * the error case in attach and the normal detach case so it needs 806 * to be careful about only freeing resources that have actually been 807 * allocated. 808 */ 809static int 810sf_detach(dev) 811 device_t dev; 812{ 813 struct sf_softc *sc; 814 struct ifnet *ifp; 815 816 sc = device_get_softc(dev); 817 KASSERT(mtx_initialized(&sc->sf_mtx), ("sf mutex not initialized")); 818 ifp = sc->sf_ifp; 819 820#ifdef DEVICE_POLLING 821 if (ifp->if_capenable & IFCAP_POLLING) 822 ether_poll_deregister(ifp); 823#endif 824 825 /* These should only be active if attach succeeded */ 826 if (device_is_attached(dev)) { 827 SF_LOCK(sc); 828 sf_stop(sc); 829 SF_UNLOCK(sc); 830 callout_drain(&sc->sf_stat_callout); 831 ether_ifdetach(ifp); 832 } 833 if (sc->sf_miibus) 834 device_delete_child(dev, sc->sf_miibus); 835 bus_generic_detach(dev); 836 837 if (sc->sf_intrhand) 838 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand); 839 if (sc->sf_irq) 840 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq); 841 if (sc->sf_res) 842 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 843 844 if (ifp) 845 if_free(ifp); 846 847 if (sc->sf_ldata) 848 contigfree(sc->sf_ldata, sizeof(struct sf_list_data), M_DEVBUF); 849 850 mtx_destroy(&sc->sf_mtx); 851 852 return(0); 853} 854 855static int 856sf_init_rx_ring(sc) 857 struct sf_softc *sc; 858{ 859 struct sf_list_data *ld; 860 int i; 861 862 ld = sc->sf_ldata; 863 864 bzero((char *)ld->sf_rx_dlist_big, 865 sizeof(struct sf_rx_bufdesc_type0) * SF_RX_DLIST_CNT); 866 bzero((char *)ld->sf_rx_clist, 867 sizeof(struct sf_rx_cmpdesc_type3) * SF_RX_CLIST_CNT); 868 869 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 870 if (sf_newbuf(sc, &ld->sf_rx_dlist_big[i], NULL) == ENOBUFS) 871 return(ENOBUFS); 872 } 873 874 return(0); 875} 876 877static void 878sf_init_tx_ring(sc) 879 struct sf_softc *sc; 880{ 881 struct sf_list_data *ld; 882 int i; 883 884 ld = sc->sf_ldata; 885 886 bzero((char *)ld->sf_tx_dlist, 887 sizeof(struct sf_tx_bufdesc_type0) * SF_TX_DLIST_CNT); 888 bzero((char *)ld->sf_tx_clist, 889 sizeof(struct sf_tx_cmpdesc_type0) * SF_TX_CLIST_CNT); 890 891 for (i = 0; i < SF_TX_DLIST_CNT; i++) 892 ld->sf_tx_dlist[i].sf_id = SF_TX_BUFDESC_ID; 893 for (i = 0; i < SF_TX_CLIST_CNT; i++) 894 ld->sf_tx_clist[i].sf_type = SF_TXCMPTYPE_TX; 895 896 ld->sf_tx_dlist[SF_TX_DLIST_CNT - 1].sf_end = 1; 897 sc->sf_tx_cnt = 0; 898} 899 900static int 901sf_newbuf(sc, c, m) 902 struct sf_softc *sc; 903 struct sf_rx_bufdesc_type0 *c; 904 struct mbuf *m; 905{ 906 struct mbuf *m_new = NULL; 907 908 if (m == NULL) { 909 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 910 if (m_new == NULL) 911 return(ENOBUFS); 912 913 MCLGET(m_new, M_DONTWAIT); 914 if (!(m_new->m_flags & M_EXT)) { 915 m_freem(m_new); 916 return(ENOBUFS); 917 } 918 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 919 } else { 920 m_new = m; 921 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 922 m_new->m_data = m_new->m_ext.ext_buf; 923 } 924 925 m_adj(m_new, sizeof(u_int64_t)); 926 927 c->sf_mbuf = m_new; 928 c->sf_addrlo = SF_RX_HOSTADDR(vtophys(mtod(m_new, caddr_t))); 929 c->sf_valid = 1; 930 931 return(0); 932} 933 934/* 935 * The starfire is programmed to use 'normal' mode for packet reception, 936 * which means we use the consumer/producer model for both the buffer 937 * descriptor queue and the completion descriptor queue. The only problem 938 * with this is that it involves a lot of register accesses: we have to 939 * read the RX completion consumer and producer indexes and the RX buffer 940 * producer index, plus the RX completion consumer and RX buffer producer 941 * indexes have to be updated. It would have been easier if Adaptec had 942 * put each index in a separate register, especially given that the damn 943 * NIC has a 512K register space. 944 * 945 * In spite of all the lovely features that Adaptec crammed into the 6915, 946 * it is marred by one truly stupid design flaw, which is that receive 947 * buffer addresses must be aligned on a longword boundary. This forces 948 * the packet payload to be unaligned, which is suboptimal on the x86 and 949 * completely unuseable on the Alpha. Our only recourse is to copy received 950 * packets into properly aligned buffers before handing them off. 951 */ 952 953static void 954sf_rxeof(sc) 955 struct sf_softc *sc; 956{ 957 struct mbuf *m; 958 struct ifnet *ifp; 959 struct sf_rx_bufdesc_type0 *desc; 960 struct sf_rx_cmpdesc_type3 *cur_rx; 961 u_int32_t rxcons, rxprod; 962 int cmpprodidx, cmpconsidx, bufprodidx; 963 964 SF_LOCK_ASSERT(sc); 965 966 ifp = sc->sf_ifp; 967 968 rxcons = csr_read_4(sc, SF_CQ_CONSIDX); 969 rxprod = csr_read_4(sc, SF_RXDQ_PTR_Q1); 970 cmpprodidx = SF_IDX_LO(csr_read_4(sc, SF_CQ_PRODIDX)); 971 cmpconsidx = SF_IDX_LO(rxcons); 972 bufprodidx = SF_IDX_LO(rxprod); 973 974 while (cmpconsidx != cmpprodidx) { 975 struct mbuf *m0; 976 977#ifdef DEVICE_POLLING 978 if (ifp->if_capenable & IFCAP_POLLING) { 979 if (sc->rxcycles <= 0) 980 break; 981 sc->rxcycles--; 982 } 983#endif 984 985 cur_rx = &sc->sf_ldata->sf_rx_clist[cmpconsidx]; 986 desc = &sc->sf_ldata->sf_rx_dlist_big[cur_rx->sf_endidx]; 987 m = desc->sf_mbuf; 988 SF_INC(cmpconsidx, SF_RX_CLIST_CNT); 989 SF_INC(bufprodidx, SF_RX_DLIST_CNT); 990 991 if (!(cur_rx->sf_status1 & SF_RXSTAT1_OK)) { 992 ifp->if_ierrors++; 993 sf_newbuf(sc, desc, m); 994 continue; 995 } 996 997 m0 = m_devget(mtod(m, char *), cur_rx->sf_len, ETHER_ALIGN, 998 ifp, NULL); 999 sf_newbuf(sc, desc, m); 1000 if (m0 == NULL) { 1001 ifp->if_ierrors++; 1002 continue; 1003 } 1004 m = m0; 1005 1006 ifp->if_ipackets++; 1007 SF_UNLOCK(sc); 1008 (*ifp->if_input)(ifp, m); 1009 SF_LOCK(sc); 1010 } 1011 1012 csr_write_4(sc, SF_CQ_CONSIDX, 1013 (rxcons & ~SF_CQ_CONSIDX_RXQ1) | cmpconsidx); 1014 csr_write_4(sc, SF_RXDQ_PTR_Q1, 1015 (rxprod & ~SF_RXDQ_PRODIDX) | bufprodidx); 1016} 1017 1018/* 1019 * Read the transmit status from the completion queue and release 1020 * mbufs. Note that the buffer descriptor index in the completion 1021 * descriptor is an offset from the start of the transmit buffer 1022 * descriptor list in bytes. This is important because the manual 1023 * gives the impression that it should match the producer/consumer 1024 * index, which is the offset in 8 byte blocks. 1025 */ 1026static void 1027sf_txeof(sc) 1028 struct sf_softc *sc; 1029{ 1030 int txcons, cmpprodidx, cmpconsidx; 1031 struct sf_tx_cmpdesc_type1 *cur_cmp; 1032 struct sf_tx_bufdesc_type0 *cur_tx; 1033 struct ifnet *ifp; 1034 1035 ifp = sc->sf_ifp; 1036 1037 SF_LOCK_ASSERT(sc); 1038 txcons = csr_read_4(sc, SF_CQ_CONSIDX); 1039 cmpprodidx = SF_IDX_HI(csr_read_4(sc, SF_CQ_PRODIDX)); 1040 cmpconsidx = SF_IDX_HI(txcons); 1041 1042 while (cmpconsidx != cmpprodidx) { 1043 cur_cmp = &sc->sf_ldata->sf_tx_clist[cmpconsidx]; 1044 cur_tx = &sc->sf_ldata->sf_tx_dlist[cur_cmp->sf_index >> 7]; 1045 1046 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_OK) 1047 ifp->if_opackets++; 1048 else { 1049 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_UNDERRUN) 1050 sf_txthresh_adjust(sc); 1051 ifp->if_oerrors++; 1052 } 1053 1054 sc->sf_tx_cnt--; 1055 if (cur_tx->sf_mbuf != NULL) { 1056 m_freem(cur_tx->sf_mbuf); 1057 cur_tx->sf_mbuf = NULL; 1058 } else 1059 break; 1060 SF_INC(cmpconsidx, SF_TX_CLIST_CNT); 1061 } 1062 1063 ifp->if_timer = 0; 1064 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1065 1066 csr_write_4(sc, SF_CQ_CONSIDX, 1067 (txcons & ~SF_CQ_CONSIDX_TXQ) | 1068 ((cmpconsidx << 16) & 0xFFFF0000)); 1069} 1070 1071static void 1072sf_txthresh_adjust(sc) 1073 struct sf_softc *sc; 1074{ 1075 u_int32_t txfctl; 1076 u_int8_t txthresh; 1077 1078 txfctl = csr_read_4(sc, SF_TX_FRAMCTL); 1079 txthresh = txfctl & SF_TXFRMCTL_TXTHRESH; 1080 if (txthresh < 0xFF) { 1081 txthresh++; 1082 txfctl &= ~SF_TXFRMCTL_TXTHRESH; 1083 txfctl |= txthresh; 1084#ifdef DIAGNOSTIC 1085 device_printf(sc->sf_dev, "tx underrun, increasing " 1086 "tx threshold to %d bytes\n", 1087 txthresh * 4); 1088#endif 1089 csr_write_4(sc, SF_TX_FRAMCTL, txfctl); 1090 } 1091} 1092 1093#ifdef DEVICE_POLLING 1094static void 1095sf_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1096{ 1097 struct sf_softc *sc = ifp->if_softc; 1098 1099 SF_LOCK(sc); 1100 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1101 sf_poll_locked(ifp, cmd, count); 1102 SF_UNLOCK(sc); 1103} 1104 1105static void 1106sf_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 1107{ 1108 struct sf_softc *sc = ifp->if_softc; 1109 1110 SF_LOCK_ASSERT(sc); 1111 1112 sc->rxcycles = count; 1113 sf_rxeof(sc); 1114 sf_txeof(sc); 1115 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1116 sf_start_locked(ifp); 1117 1118 if (cmd == POLL_AND_CHECK_STATUS) { 1119 u_int32_t status; 1120 1121 status = csr_read_4(sc, SF_ISR); 1122 if (status) 1123 csr_write_4(sc, SF_ISR, status); 1124 1125 if (status & SF_ISR_TX_LOFIFO) 1126 sf_txthresh_adjust(sc); 1127 1128 if (status & SF_ISR_ABNORMALINTR) { 1129 if (status & SF_ISR_STATSOFLOW) { 1130 callout_stop(&sc->sf_stat_callout); 1131 sf_stats_update(sc); 1132 } else 1133 sf_init_locked(sc); 1134 } 1135 } 1136} 1137#endif /* DEVICE_POLLING */ 1138 1139static void 1140sf_intr(arg) 1141 void *arg; 1142{ 1143 struct sf_softc *sc; 1144 struct ifnet *ifp; 1145 u_int32_t status; 1146 1147 sc = arg; 1148 SF_LOCK(sc); 1149 1150 ifp = sc->sf_ifp; 1151 1152#ifdef DEVICE_POLLING 1153 if (ifp->if_capenable & IFCAP_POLLING) { 1154 SF_UNLOCK(sc); 1155 return; 1156 } 1157#endif 1158 1159 if (!(csr_read_4(sc, SF_ISR_SHADOW) & SF_ISR_PCIINT_ASSERTED)) { 1160 SF_UNLOCK(sc); 1161 return; 1162 } 1163 1164 /* Disable interrupts. */ 1165 csr_write_4(sc, SF_IMR, 0x00000000); 1166 1167 for (;;) { 1168 status = csr_read_4(sc, SF_ISR); 1169 if (status) 1170 csr_write_4(sc, SF_ISR, status); 1171 1172 if (!(status & SF_INTRS)) 1173 break; 1174 1175 if (status & SF_ISR_RXDQ1_DMADONE) 1176 sf_rxeof(sc); 1177 1178 if (status & SF_ISR_TX_TXDONE || 1179 status & SF_ISR_TX_DMADONE || 1180 status & SF_ISR_TX_QUEUEDONE) 1181 sf_txeof(sc); 1182 1183 if (status & SF_ISR_TX_LOFIFO) 1184 sf_txthresh_adjust(sc); 1185 1186 if (status & SF_ISR_ABNORMALINTR) { 1187 if (status & SF_ISR_STATSOFLOW) { 1188 callout_stop(&sc->sf_stat_callout); 1189 sf_stats_update(sc); 1190 } else 1191 sf_init_locked(sc); 1192 } 1193 } 1194 1195 /* Re-enable interrupts. */ 1196 csr_write_4(sc, SF_IMR, SF_INTRS); 1197 1198 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1199 sf_start_locked(ifp); 1200 1201 SF_UNLOCK(sc); 1202} 1203 1204static void 1205sf_init(xsc) 1206 void *xsc; 1207{ 1208 struct sf_softc *sc; 1209 1210 sc = xsc; 1211 SF_LOCK(sc); 1212 sf_init_locked(sc); 1213 SF_UNLOCK(sc); 1214} 1215 1216static void 1217sf_init_locked(sc) 1218 struct sf_softc *sc; 1219{ 1220 struct ifnet *ifp; 1221 struct mii_data *mii; 1222 int i; 1223 1224 SF_LOCK_ASSERT(sc); 1225 ifp = sc->sf_ifp; 1226 mii = device_get_softc(sc->sf_miibus); 1227 1228 sf_stop(sc); 1229 sf_reset(sc); 1230 1231 /* Init all the receive filter registers */ 1232 for (i = SF_RXFILT_PERFECT_BASE; 1233 i < (SF_RXFILT_HASH_MAX + 1); i += 4) 1234 csr_write_4(sc, i, 0); 1235 1236 /* Empty stats counter registers. */ 1237 for (i = 0; i < sizeof(struct sf_stats)/sizeof(u_int32_t); i++) 1238 csr_write_4(sc, SF_STATS_BASE + 1239 (i + sizeof(u_int32_t)), 0); 1240 1241 /* Init our MAC address */ 1242 csr_write_4(sc, SF_PAR0, *(u_int32_t *)(&IF_LLADDR(sc->sf_ifp)[0])); 1243 csr_write_4(sc, SF_PAR1, *(u_int32_t *)(&IF_LLADDR(sc->sf_ifp)[4])); 1244 sf_setperf(sc, 0, IF_LLADDR(sc->sf_ifp)); 1245 1246 if (sf_init_rx_ring(sc) == ENOBUFS) { 1247 device_printf(sc->sf_dev, 1248 "initialization failed: no memory for rx buffers\n"); 1249 return; 1250 } 1251 1252 sf_init_tx_ring(sc); 1253 1254 csr_write_4(sc, SF_RXFILT, SF_PERFMODE_NORMAL|SF_HASHMODE_WITHVLAN); 1255 1256 /* If we want promiscuous mode, set the allframes bit. */ 1257 if (ifp->if_flags & IFF_PROMISC) { 1258 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 1259 } else { 1260 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 1261 } 1262 1263 if (ifp->if_flags & IFF_BROADCAST) { 1264 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_BROAD); 1265 } else { 1266 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_BROAD); 1267 } 1268 1269 /* 1270 * Load the multicast filter. 1271 */ 1272 sf_setmulti(sc); 1273 1274 /* Init the completion queue indexes */ 1275 csr_write_4(sc, SF_CQ_CONSIDX, 0); 1276 csr_write_4(sc, SF_CQ_PRODIDX, 0); 1277 1278 /* Init the RX completion queue */ 1279 csr_write_4(sc, SF_RXCQ_CTL_1, 1280 vtophys(sc->sf_ldata->sf_rx_clist) & SF_RXCQ_ADDR); 1281 SF_SETBIT(sc, SF_RXCQ_CTL_1, SF_RXCQTYPE_3); 1282 1283 /* Init RX DMA control. */ 1284 SF_SETBIT(sc, SF_RXDMA_CTL, SF_RXDMA_REPORTBADPKTS); 1285 1286 /* Init the RX buffer descriptor queue. */ 1287 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 1288 vtophys(sc->sf_ldata->sf_rx_dlist_big)); 1289 csr_write_4(sc, SF_RXDQ_CTL_1, (MCLBYTES << 16) | SF_DESCSPACE_16BYTES); 1290 csr_write_4(sc, SF_RXDQ_PTR_Q1, SF_RX_DLIST_CNT - 1); 1291 1292 /* Init the TX completion queue */ 1293 csr_write_4(sc, SF_TXCQ_CTL, 1294 vtophys(sc->sf_ldata->sf_tx_clist) & SF_RXCQ_ADDR); 1295 1296 /* Init the TX buffer descriptor queue. */ 1297 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 1298 vtophys(sc->sf_ldata->sf_tx_dlist)); 1299 SF_SETBIT(sc, SF_TX_FRAMCTL, SF_TXFRMCTL_CPLAFTERTX); 1300 csr_write_4(sc, SF_TXDQ_CTL, 1301 SF_TXBUFDESC_TYPE0|SF_TXMINSPACE_128BYTES|SF_TXSKIPLEN_8BYTES); 1302 SF_SETBIT(sc, SF_TXDQ_CTL, SF_TXDQCTL_NODMACMP); 1303 1304 /* Enable autopadding of short TX frames. */ 1305 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_AUTOPAD); 1306 1307#ifdef DEVICE_POLLING 1308 /* Disable interrupts if we are polling. */ 1309 if (ifp->if_capenable & IFCAP_POLLING) 1310 csr_write_4(sc, SF_IMR, 0x00000000); 1311 else 1312#endif 1313 1314 /* Enable interrupts. */ 1315 csr_write_4(sc, SF_IMR, SF_INTRS); 1316 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_INTR_ENB); 1317 1318 /* Enable the RX and TX engines. */ 1319 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_RX_ENB|SF_ETHCTL_RXDMA_ENB); 1320 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_TX_ENB|SF_ETHCTL_TXDMA_ENB); 1321 1322 /*mii_mediachg(mii);*/ 1323 sf_ifmedia_upd_locked(ifp); 1324 1325 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1326 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1327 1328 callout_reset(&sc->sf_stat_callout, hz, sf_stats_update, sc); 1329} 1330 1331static int 1332sf_encap(sc, c, m_head) 1333 struct sf_softc *sc; 1334 struct sf_tx_bufdesc_type0 *c; 1335 struct mbuf *m_head; 1336{ 1337 int frag = 0; 1338 struct sf_frag *f = NULL; 1339 struct mbuf *m; 1340 1341 m = m_head; 1342 1343 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1344 if (m->m_len != 0) { 1345 if (frag == SF_MAXFRAGS) 1346 break; 1347 f = &c->sf_frags[frag]; 1348 if (frag == 0) 1349 f->sf_pktlen = m_head->m_pkthdr.len; 1350 f->sf_fraglen = m->m_len; 1351 f->sf_addr = vtophys(mtod(m, vm_offset_t)); 1352 frag++; 1353 } 1354 } 1355 1356 if (m != NULL) { 1357 struct mbuf *m_new = NULL; 1358 1359 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1360 if (m_new == NULL) { 1361 if_printf(sc->sf_ifp, "no memory for tx list\n"); 1362 return(1); 1363 } 1364 1365 if (m_head->m_pkthdr.len > MHLEN) { 1366 MCLGET(m_new, M_DONTWAIT); 1367 if (!(m_new->m_flags & M_EXT)) { 1368 m_freem(m_new); 1369 if_printf(sc->sf_ifp, "no memory for tx list\n"); 1370 return(1); 1371 } 1372 } 1373 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1374 mtod(m_new, caddr_t)); 1375 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1376 m_freem(m_head); 1377 m_head = m_new; 1378 f = &c->sf_frags[0]; 1379 f->sf_fraglen = f->sf_pktlen = m_head->m_pkthdr.len; 1380 f->sf_addr = vtophys(mtod(m_head, caddr_t)); 1381 frag = 1; 1382 } 1383 1384 c->sf_mbuf = m_head; 1385 c->sf_id = SF_TX_BUFDESC_ID; 1386 c->sf_fragcnt = frag; 1387 c->sf_intr = 1; 1388 c->sf_caltcp = 0; 1389 c->sf_crcen = 1; 1390 1391 return(0); 1392} 1393 1394static void 1395sf_start(ifp) 1396 struct ifnet *ifp; 1397{ 1398 struct sf_softc *sc; 1399 1400 sc = ifp->if_softc; 1401 SF_LOCK(sc); 1402 sf_start_locked(ifp); 1403 SF_UNLOCK(sc); 1404} 1405 1406static void 1407sf_start_locked(ifp) 1408 struct ifnet *ifp; 1409{ 1410 struct sf_softc *sc; 1411 struct sf_tx_bufdesc_type0 *cur_tx = NULL; 1412 struct mbuf *m_head = NULL; 1413 int i, txprod; 1414 1415 sc = ifp->if_softc; 1416 SF_LOCK_ASSERT(sc); 1417 1418 if (!sc->sf_link && ifp->if_snd.ifq_len < 10) 1419 return; 1420 1421 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 1422 return; 1423 1424 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX); 1425 i = SF_IDX_HI(txprod) >> 4; 1426 1427 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) { 1428 if_printf(ifp, "TX ring full, resetting\n"); 1429 sf_init_locked(sc); 1430 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX); 1431 i = SF_IDX_HI(txprod) >> 4; 1432 } 1433 1434 while(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf == NULL) { 1435 if (sc->sf_tx_cnt >= (SF_TX_DLIST_CNT - 5)) { 1436 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1437 cur_tx = NULL; 1438 break; 1439 } 1440 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1441 if (m_head == NULL) 1442 break; 1443 1444 cur_tx = &sc->sf_ldata->sf_tx_dlist[i]; 1445 if (sf_encap(sc, cur_tx, m_head)) { 1446 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1447 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1448 cur_tx = NULL; 1449 break; 1450 } 1451 1452 /* 1453 * If there's a BPF listener, bounce a copy of this frame 1454 * to him. 1455 */ 1456 BPF_MTAP(ifp, m_head); 1457 1458 SF_INC(i, SF_TX_DLIST_CNT); 1459 sc->sf_tx_cnt++; 1460 /* 1461 * Don't get the TX DMA queue get too full. 1462 */ 1463 if (sc->sf_tx_cnt > 64) 1464 break; 1465 } 1466 1467 if (cur_tx == NULL) 1468 return; 1469 1470 /* Transmit */ 1471 csr_write_4(sc, SF_TXDQ_PRODIDX, 1472 (txprod & ~SF_TXDQ_PRODIDX_HIPRIO) | 1473 ((i << 20) & 0xFFFF0000)); 1474 1475 ifp->if_timer = 5; 1476} 1477 1478static void 1479sf_stop(sc) 1480 struct sf_softc *sc; 1481{ 1482 int i; 1483 struct ifnet *ifp; 1484 1485 SF_LOCK_ASSERT(sc); 1486 1487 ifp = sc->sf_ifp; 1488 1489 callout_stop(&sc->sf_stat_callout); 1490 1491 csr_write_4(sc, SF_GEN_ETH_CTL, 0); 1492 csr_write_4(sc, SF_CQ_CONSIDX, 0); 1493 csr_write_4(sc, SF_CQ_PRODIDX, 0); 1494 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 0); 1495 csr_write_4(sc, SF_RXDQ_CTL_1, 0); 1496 csr_write_4(sc, SF_RXDQ_PTR_Q1, 0); 1497 csr_write_4(sc, SF_TXCQ_CTL, 0); 1498 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 0); 1499 csr_write_4(sc, SF_TXDQ_CTL, 0); 1500 sf_reset(sc); 1501 1502 sc->sf_link = 0; 1503 1504 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 1505 if (sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf != NULL) { 1506 m_freem(sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf); 1507 sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf = NULL; 1508 } 1509 } 1510 1511 for (i = 0; i < SF_TX_DLIST_CNT; i++) { 1512 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) { 1513 m_freem(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf); 1514 sc->sf_ldata->sf_tx_dlist[i].sf_mbuf = NULL; 1515 } 1516 } 1517 1518 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING|IFF_DRV_OACTIVE); 1519} 1520 1521/* 1522 * Note: it is important that this function not be interrupted. We 1523 * use a two-stage register access scheme: if we are interrupted in 1524 * between setting the indirect address register and reading from the 1525 * indirect data register, the contents of the address register could 1526 * be changed out from under us. 1527 */ 1528static void 1529sf_stats_update(xsc) 1530 void *xsc; 1531{ 1532 struct sf_softc *sc; 1533 struct ifnet *ifp; 1534 struct mii_data *mii; 1535 struct sf_stats stats; 1536 u_int32_t *ptr; 1537 int i; 1538 1539 sc = xsc; 1540 SF_LOCK_ASSERT(sc); 1541 ifp = sc->sf_ifp; 1542 mii = device_get_softc(sc->sf_miibus); 1543 1544 ptr = (u_int32_t *)&stats; 1545 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++) 1546 ptr[i] = csr_read_4(sc, SF_STATS_BASE + 1547 (i + sizeof(u_int32_t))); 1548 1549 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++) 1550 csr_write_4(sc, SF_STATS_BASE + 1551 (i + sizeof(u_int32_t)), 0); 1552 1553 ifp->if_collisions += stats.sf_tx_single_colls + 1554 stats.sf_tx_multi_colls + stats.sf_tx_excess_colls; 1555 1556 mii_tick(mii); 1557 1558 if (!sc->sf_link && mii->mii_media_status & IFM_ACTIVE && 1559 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1560 sc->sf_link++; 1561 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1562 sf_start_locked(ifp); 1563 } 1564 1565 callout_reset(&sc->sf_stat_callout, hz, sf_stats_update, sc); 1566} 1567 1568static void 1569sf_watchdog(ifp) 1570 struct ifnet *ifp; 1571{ 1572 struct sf_softc *sc; 1573 1574 sc = ifp->if_softc; 1575 1576 SF_LOCK(sc); 1577 1578 ifp->if_oerrors++; 1579 if_printf(ifp, "watchdog timeout\n"); 1580 1581 sf_stop(sc); 1582 sf_reset(sc); 1583 sf_init_locked(sc); 1584 1585 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1586 sf_start_locked(ifp); 1587 1588 SF_UNLOCK(sc); 1589} 1590 1591static void 1592sf_shutdown(dev) 1593 device_t dev; 1594{ 1595 struct sf_softc *sc; 1596 1597 sc = device_get_softc(dev); 1598 1599 SF_LOCK(sc); 1600 sf_stop(sc); 1601 SF_UNLOCK(sc); 1602} 1603