if_sf.c revision 149240
1/*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/sf/if_sf.c 149240 2005-08-18 17:09:16Z jhb $"); 35 36/* 37 * Adaptec AIC-6915 "Starfire" PCI fast ethernet driver for FreeBSD. 38 * Programming manual is available from: 39 * http://download.adaptec.com/pdfs/user_guides/aic6915_pg.pdf. 40 * 41 * Written by Bill Paul <wpaul@ctr.columbia.edu> 42 * Department of Electical Engineering 43 * Columbia University, New York City 44 */ 45/* 46 * The Adaptec AIC-6915 "Starfire" is a 64-bit 10/100 PCI ethernet 47 * controller designed with flexibility and reducing CPU load in mind. 48 * The Starfire offers high and low priority buffer queues, a 49 * producer/consumer index mechanism and several different buffer 50 * queue and completion queue descriptor types. Any one of a number 51 * of different driver designs can be used, depending on system and 52 * OS requirements. This driver makes use of type0 transmit frame 53 * descriptors (since BSD fragments packets across an mbuf chain) 54 * and two RX buffer queues prioritized on size (one queue for small 55 * frames that will fit into a single mbuf, another with full size 56 * mbuf clusters for everything else). The producer/consumer indexes 57 * and completion queues are also used. 58 * 59 * One downside to the Starfire has to do with alignment: buffer 60 * queues must be aligned on 256-byte boundaries, and receive buffers 61 * must be aligned on longword boundaries. The receive buffer alignment 62 * causes problems on the Alpha platform, where the packet payload 63 * should be longword aligned. There is no simple way around this. 64 * 65 * For receive filtering, the Starfire offers 16 perfect filter slots 66 * and a 512-bit hash table. 67 * 68 * The Starfire has no internal transceiver, relying instead on an 69 * external MII-based transceiver. Accessing registers on external 70 * PHYs is done through a special register map rather than with the 71 * usual bitbang MDIO method. 72 * 73 * Acesssing the registers on the Starfire is a little tricky. The 74 * Starfire has a 512K internal register space. When programmed for 75 * PCI memory mapped mode, the entire register space can be accessed 76 * directly. However in I/O space mode, only 256 bytes are directly 77 * mapped into PCI I/O space. The other registers can be accessed 78 * indirectly using the SF_INDIRECTIO_ADDR and SF_INDIRECTIO_DATA 79 * registers inside the 256-byte I/O window. 80 */ 81 82#include <sys/param.h> 83#include <sys/systm.h> 84#include <sys/sockio.h> 85#include <sys/mbuf.h> 86#include <sys/malloc.h> 87#include <sys/kernel.h> 88#include <sys/module.h> 89#include <sys/socket.h> 90 91#include <net/if.h> 92#include <net/if_arp.h> 93#include <net/ethernet.h> 94#include <net/if_dl.h> 95#include <net/if_media.h> 96#include <net/if_types.h> 97 98#include <net/bpf.h> 99 100#include <vm/vm.h> /* for vtophys */ 101#include <vm/pmap.h> /* for vtophys */ 102#include <machine/bus.h> 103#include <machine/resource.h> 104#include <sys/bus.h> 105#include <sys/rman.h> 106 107#include <dev/mii/mii.h> 108#include <dev/mii/miivar.h> 109 110/* "controller miibus0" required. See GENERIC if you get errors here. */ 111#include "miibus_if.h" 112 113#include <dev/pci/pcireg.h> 114#include <dev/pci/pcivar.h> 115 116#define SF_USEIOSPACE 117 118#include <pci/if_sfreg.h> 119 120MODULE_DEPEND(sf, pci, 1, 1, 1); 121MODULE_DEPEND(sf, ether, 1, 1, 1); 122MODULE_DEPEND(sf, miibus, 1, 1, 1); 123 124static struct sf_type sf_devs[] = { 125 { AD_VENDORID, AD_DEVICEID_STARFIRE, 126 "Adaptec AIC-6915 10/100BaseTX" }, 127 { 0, 0, NULL } 128}; 129 130static int sf_probe(device_t); 131static int sf_attach(device_t); 132static int sf_detach(device_t); 133static void sf_intr(void *); 134static void sf_stats_update(void *); 135static void sf_rxeof(struct sf_softc *); 136static void sf_txeof(struct sf_softc *); 137static int sf_encap(struct sf_softc *, struct sf_tx_bufdesc_type0 *, 138 struct mbuf *); 139static void sf_start(struct ifnet *); 140static void sf_start_locked(struct ifnet *); 141static int sf_ioctl(struct ifnet *, u_long, caddr_t); 142static void sf_init(void *); 143static void sf_init_locked(struct sf_softc *); 144static void sf_stop(struct sf_softc *); 145static void sf_watchdog(struct ifnet *); 146static void sf_shutdown(device_t); 147static int sf_ifmedia_upd(struct ifnet *); 148static void sf_ifmedia_upd_locked(struct ifnet *); 149static void sf_ifmedia_sts(struct ifnet *, struct ifmediareq *); 150static void sf_reset(struct sf_softc *); 151static int sf_init_rx_ring(struct sf_softc *); 152static void sf_init_tx_ring(struct sf_softc *); 153static int sf_newbuf(struct sf_softc *, struct sf_rx_bufdesc_type0 *, 154 struct mbuf *); 155static void sf_setmulti(struct sf_softc *); 156static int sf_setperf(struct sf_softc *, int, caddr_t); 157static int sf_sethash(struct sf_softc *, caddr_t, int); 158#ifdef notdef 159static int sf_setvlan(struct sf_softc *, int, u_int32_t); 160#endif 161 162static u_int8_t sf_read_eeprom(struct sf_softc *, int); 163 164static int sf_miibus_readreg(device_t, int, int); 165static int sf_miibus_writereg(device_t, int, int, int); 166static void sf_miibus_statchg(device_t); 167#ifdef DEVICE_POLLING 168static void sf_poll(struct ifnet *ifp, enum poll_cmd cmd, 169 int count); 170static void sf_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, 171 int count); 172#endif /* DEVICE_POLLING */ 173 174static u_int32_t csr_read_4(struct sf_softc *, int); 175static void csr_write_4(struct sf_softc *, int, u_int32_t); 176static void sf_txthresh_adjust(struct sf_softc *); 177 178#ifdef SF_USEIOSPACE 179#define SF_RES SYS_RES_IOPORT 180#define SF_RID SF_PCI_LOIO 181#else 182#define SF_RES SYS_RES_MEMORY 183#define SF_RID SF_PCI_LOMEM 184#endif 185 186static device_method_t sf_methods[] = { 187 /* Device interface */ 188 DEVMETHOD(device_probe, sf_probe), 189 DEVMETHOD(device_attach, sf_attach), 190 DEVMETHOD(device_detach, sf_detach), 191 DEVMETHOD(device_shutdown, sf_shutdown), 192 193 /* bus interface */ 194 DEVMETHOD(bus_print_child, bus_generic_print_child), 195 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 196 197 /* MII interface */ 198 DEVMETHOD(miibus_readreg, sf_miibus_readreg), 199 DEVMETHOD(miibus_writereg, sf_miibus_writereg), 200 DEVMETHOD(miibus_statchg, sf_miibus_statchg), 201 202 { 0, 0 } 203}; 204 205static driver_t sf_driver = { 206 "sf", 207 sf_methods, 208 sizeof(struct sf_softc), 209}; 210 211static devclass_t sf_devclass; 212 213DRIVER_MODULE(sf, pci, sf_driver, sf_devclass, 0, 0); 214DRIVER_MODULE(miibus, sf, miibus_driver, miibus_devclass, 0, 0); 215 216#define SF_SETBIT(sc, reg, x) \ 217 csr_write_4(sc, reg, csr_read_4(sc, reg) | (x)) 218 219#define SF_CLRBIT(sc, reg, x) \ 220 csr_write_4(sc, reg, csr_read_4(sc, reg) & ~(x)) 221 222static u_int32_t 223csr_read_4(sc, reg) 224 struct sf_softc *sc; 225 int reg; 226{ 227 u_int32_t val; 228 229#ifdef SF_USEIOSPACE 230 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); 231 val = CSR_READ_4(sc, SF_INDIRECTIO_DATA); 232#else 233 val = CSR_READ_4(sc, (reg + SF_RMAP_INTREG_BASE)); 234#endif 235 236 return(val); 237} 238 239static u_int8_t 240sf_read_eeprom(sc, reg) 241 struct sf_softc *sc; 242 int reg; 243{ 244 u_int8_t val; 245 246 val = (csr_read_4(sc, SF_EEADDR_BASE + 247 (reg & 0xFFFFFFFC)) >> (8 * (reg & 3))) & 0xFF; 248 249 return(val); 250} 251 252static void 253csr_write_4(sc, reg, val) 254 struct sf_softc *sc; 255 int reg; 256 u_int32_t val; 257{ 258#ifdef SF_USEIOSPACE 259 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); 260 CSR_WRITE_4(sc, SF_INDIRECTIO_DATA, val); 261#else 262 CSR_WRITE_4(sc, (reg + SF_RMAP_INTREG_BASE), val); 263#endif 264} 265 266/* 267 * Copy the address 'mac' into the perfect RX filter entry at 268 * offset 'idx.' The perfect filter only has 16 entries so do 269 * some sanity tests. 270 */ 271static int 272sf_setperf(sc, idx, mac) 273 struct sf_softc *sc; 274 int idx; 275 caddr_t mac; 276{ 277 u_int16_t *p; 278 279 if (idx < 0 || idx > SF_RXFILT_PERFECT_CNT) 280 return(EINVAL); 281 282 if (mac == NULL) 283 return(EINVAL); 284 285 p = (u_int16_t *)mac; 286 287 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 288 (idx * SF_RXFILT_PERFECT_SKIP), htons(p[2])); 289 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 290 (idx * SF_RXFILT_PERFECT_SKIP) + 4, htons(p[1])); 291 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 292 (idx * SF_RXFILT_PERFECT_SKIP) + 8, htons(p[0])); 293 294 return(0); 295} 296 297/* 298 * Set the bit in the 512-bit hash table that corresponds to the 299 * specified mac address 'mac.' If 'prio' is nonzero, update the 300 * priority hash table instead of the filter hash table. 301 */ 302static int 303sf_sethash(sc, mac, prio) 304 struct sf_softc *sc; 305 caddr_t mac; 306 int prio; 307{ 308 u_int32_t h; 309 310 if (mac == NULL) 311 return(EINVAL); 312 313 h = ether_crc32_be(mac, ETHER_ADDR_LEN) >> 23; 314 315 if (prio) { 316 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_PRIOOFF + 317 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); 318 } else { 319 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_ADDROFF + 320 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); 321 } 322 323 return(0); 324} 325 326#ifdef notdef 327/* 328 * Set a VLAN tag in the receive filter. 329 */ 330static int 331sf_setvlan(sc, idx, vlan) 332 struct sf_softc *sc; 333 int idx; 334 u_int32_t vlan; 335{ 336 if (idx < 0 || idx >> SF_RXFILT_HASH_CNT) 337 return(EINVAL); 338 339 csr_write_4(sc, SF_RXFILT_HASH_BASE + 340 (idx * SF_RXFILT_HASH_SKIP) + SF_RXFILT_HASH_VLANOFF, vlan); 341 342 return(0); 343} 344#endif 345 346static int 347sf_miibus_readreg(dev, phy, reg) 348 device_t dev; 349 int phy, reg; 350{ 351 struct sf_softc *sc; 352 int i; 353 u_int32_t val = 0; 354 355 sc = device_get_softc(dev); 356 357 for (i = 0; i < SF_TIMEOUT; i++) { 358 val = csr_read_4(sc, SF_PHY_REG(phy, reg)); 359 if (val & SF_MII_DATAVALID) 360 break; 361 } 362 363 if (i == SF_TIMEOUT) 364 return(0); 365 366 if ((val & 0x0000FFFF) == 0xFFFF) 367 return(0); 368 369 return(val & 0x0000FFFF); 370} 371 372static int 373sf_miibus_writereg(dev, phy, reg, val) 374 device_t dev; 375 int phy, reg, val; 376{ 377 struct sf_softc *sc; 378 int i; 379 int busy; 380 381 sc = device_get_softc(dev); 382 383 csr_write_4(sc, SF_PHY_REG(phy, reg), val); 384 385 for (i = 0; i < SF_TIMEOUT; i++) { 386 busy = csr_read_4(sc, SF_PHY_REG(phy, reg)); 387 if (!(busy & SF_MII_BUSY)) 388 break; 389 } 390 391 return(0); 392} 393 394static void 395sf_miibus_statchg(dev) 396 device_t dev; 397{ 398 struct sf_softc *sc; 399 struct mii_data *mii; 400 401 sc = device_get_softc(dev); 402 mii = device_get_softc(sc->sf_miibus); 403 404 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 405 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 406 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_FDX); 407 } else { 408 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 409 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_HDX); 410 } 411} 412 413static void 414sf_setmulti(sc) 415 struct sf_softc *sc; 416{ 417 struct ifnet *ifp; 418 int i; 419 struct ifmultiaddr *ifma; 420 u_int8_t dummy[] = { 0, 0, 0, 0, 0, 0 }; 421 422 ifp = sc->sf_ifp; 423 424 /* First zot all the existing filters. */ 425 for (i = 1; i < SF_RXFILT_PERFECT_CNT; i++) 426 sf_setperf(sc, i, (char *)&dummy); 427 for (i = SF_RXFILT_HASH_BASE; 428 i < (SF_RXFILT_HASH_MAX + 1); i += 4) 429 csr_write_4(sc, i, 0); 430 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI); 431 432 /* Now program new ones. */ 433 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 434 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI); 435 } else { 436 i = 1; 437 IF_ADDR_LOCK(ifp); 438 TAILQ_FOREACH_REVERSE(ifma, &ifp->if_multiaddrs, ifmultihead, ifma_link) { 439 if (ifma->ifma_addr->sa_family != AF_LINK) 440 continue; 441 /* 442 * Program the first 15 multicast groups 443 * into the perfect filter. For all others, 444 * use the hash table. 445 */ 446 if (i < SF_RXFILT_PERFECT_CNT) { 447 sf_setperf(sc, i, 448 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 449 i++; 450 continue; 451 } 452 453 sf_sethash(sc, 454 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 0); 455 } 456 IF_ADDR_UNLOCK(ifp); 457 } 458} 459 460/* 461 * Set media options. 462 */ 463static int 464sf_ifmedia_upd(ifp) 465 struct ifnet *ifp; 466{ 467 struct sf_softc *sc; 468 469 sc = ifp->if_softc; 470 SF_LOCK(sc); 471 sf_ifmedia_upd_locked(ifp); 472 SF_UNLOCK(sc); 473 474 return(0); 475} 476 477static void 478sf_ifmedia_upd_locked(ifp) 479 struct ifnet *ifp; 480{ 481 struct sf_softc *sc; 482 struct mii_data *mii; 483 484 sc = ifp->if_softc; 485 mii = device_get_softc(sc->sf_miibus); 486 SF_LOCK_ASSERT(sc); 487 sc->sf_link = 0; 488 if (mii->mii_instance) { 489 struct mii_softc *miisc; 490 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 491 mii_phy_reset(miisc); 492 } 493 mii_mediachg(mii); 494} 495 496/* 497 * Report current media status. 498 */ 499static void 500sf_ifmedia_sts(ifp, ifmr) 501 struct ifnet *ifp; 502 struct ifmediareq *ifmr; 503{ 504 struct sf_softc *sc; 505 struct mii_data *mii; 506 507 sc = ifp->if_softc; 508 SF_LOCK(sc); 509 mii = device_get_softc(sc->sf_miibus); 510 511 mii_pollstat(mii); 512 ifmr->ifm_active = mii->mii_media_active; 513 ifmr->ifm_status = mii->mii_media_status; 514 SF_UNLOCK(sc); 515} 516 517static int 518sf_ioctl(ifp, command, data) 519 struct ifnet *ifp; 520 u_long command; 521 caddr_t data; 522{ 523 struct sf_softc *sc = ifp->if_softc; 524 struct ifreq *ifr = (struct ifreq *) data; 525 struct mii_data *mii; 526 int error = 0; 527 528 switch(command) { 529 case SIOCSIFFLAGS: 530 SF_LOCK(sc); 531 if (ifp->if_flags & IFF_UP) { 532 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 533 ifp->if_flags & IFF_PROMISC && 534 !(sc->sf_if_flags & IFF_PROMISC)) { 535 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 536 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING && 537 !(ifp->if_flags & IFF_PROMISC) && 538 sc->sf_if_flags & IFF_PROMISC) { 539 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 540 } else if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 541 sf_init_locked(sc); 542 } else { 543 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 544 sf_stop(sc); 545 } 546 sc->sf_if_flags = ifp->if_flags; 547 SF_UNLOCK(sc); 548 error = 0; 549 break; 550 case SIOCADDMULTI: 551 case SIOCDELMULTI: 552 SF_LOCK(sc); 553 sf_setmulti(sc); 554 SF_UNLOCK(sc); 555 error = 0; 556 break; 557 case SIOCGIFMEDIA: 558 case SIOCSIFMEDIA: 559 mii = device_get_softc(sc->sf_miibus); 560 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 561 break; 562 case SIOCSIFCAP: 563 SF_LOCK(sc); 564 ifp->if_capenable &= ~IFCAP_POLLING; 565 ifp->if_capenable |= ifr->ifr_reqcap & IFCAP_POLLING; 566 SF_UNLOCK(sc); 567 break; 568 default: 569 error = ether_ioctl(ifp, command, data); 570 break; 571 } 572 573 return(error); 574} 575 576static void 577sf_reset(sc) 578 struct sf_softc *sc; 579{ 580 register int i; 581 582 csr_write_4(sc, SF_GEN_ETH_CTL, 0); 583 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 584 DELAY(1000); 585 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 586 587 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_RESET); 588 589 for (i = 0; i < SF_TIMEOUT; i++) { 590 DELAY(10); 591 if (!(csr_read_4(sc, SF_PCI_DEVCFG) & SF_PCIDEVCFG_RESET)) 592 break; 593 } 594 595 if (i == SF_TIMEOUT) 596 if_printf(sc->sf_ifp, "reset never completed!\n"); 597 598 /* Wait a little while for the chip to get its brains in order. */ 599 DELAY(1000); 600} 601 602/* 603 * Probe for an Adaptec AIC-6915 chip. Check the PCI vendor and device 604 * IDs against our list and return a device name if we find a match. 605 * We also check the subsystem ID so that we can identify exactly which 606 * NIC has been found, if possible. 607 */ 608static int 609sf_probe(dev) 610 device_t dev; 611{ 612 struct sf_type *t; 613 614 t = sf_devs; 615 616 while(t->sf_name != NULL) { 617 if ((pci_get_vendor(dev) == t->sf_vid) && 618 (pci_get_device(dev) == t->sf_did)) { 619 switch((pci_read_config(dev, 620 SF_PCI_SUBVEN_ID, 4) >> 16) & 0xFFFF) { 621 case AD_SUBSYSID_62011_REV0: 622 case AD_SUBSYSID_62011_REV1: 623 device_set_desc(dev, 624 "Adaptec ANA-62011 10/100BaseTX"); 625 return (BUS_PROBE_DEFAULT); 626 case AD_SUBSYSID_62022: 627 device_set_desc(dev, 628 "Adaptec ANA-62022 10/100BaseTX"); 629 return (BUS_PROBE_DEFAULT); 630 case AD_SUBSYSID_62044_REV0: 631 case AD_SUBSYSID_62044_REV1: 632 device_set_desc(dev, 633 "Adaptec ANA-62044 10/100BaseTX"); 634 return (BUS_PROBE_DEFAULT); 635 case AD_SUBSYSID_62020: 636 device_set_desc(dev, 637 "Adaptec ANA-62020 10/100BaseFX"); 638 return (BUS_PROBE_DEFAULT); 639 case AD_SUBSYSID_69011: 640 device_set_desc(dev, 641 "Adaptec ANA-69011 10/100BaseTX"); 642 return (BUS_PROBE_DEFAULT); 643 default: 644 device_set_desc(dev, t->sf_name); 645 return (BUS_PROBE_DEFAULT); 646 break; 647 } 648 } 649 t++; 650 } 651 652 return(ENXIO); 653} 654 655/* 656 * Attach the interface. Allocate softc structures, do ifmedia 657 * setup and ethernet/BPF attach. 658 */ 659static int 660sf_attach(dev) 661 device_t dev; 662{ 663 int i; 664 struct sf_softc *sc; 665 struct ifnet *ifp; 666 int rid, error = 0; 667 u_char eaddr[6]; 668 669 sc = device_get_softc(dev); 670 671 mtx_init(&sc->sf_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 672 MTX_DEF); 673 /* 674 * Map control/status registers. 675 */ 676 pci_enable_busmaster(dev); 677 678 rid = SF_RID; 679 sc->sf_res = bus_alloc_resource_any(dev, SF_RES, &rid, RF_ACTIVE); 680 681 if (sc->sf_res == NULL) { 682 device_printf(dev, "couldn't map ports\n"); 683 error = ENXIO; 684 goto fail; 685 } 686 687 sc->sf_btag = rman_get_bustag(sc->sf_res); 688 sc->sf_bhandle = rman_get_bushandle(sc->sf_res); 689 690 /* Allocate interrupt */ 691 rid = 0; 692 sc->sf_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 693 RF_SHAREABLE | RF_ACTIVE); 694 695 if (sc->sf_irq == NULL) { 696 device_printf(dev, "couldn't map interrupt\n"); 697 error = ENXIO; 698 goto fail; 699 } 700 701 callout_init_mtx(&sc->sf_stat_callout, &sc->sf_mtx, 0); 702 703 /* Reset the adapter. */ 704 sf_reset(sc); 705 706 /* 707 * Get station address from the EEPROM. 708 */ 709 for (i = 0; i < ETHER_ADDR_LEN; i++) 710 eaddr[i] = 711 sf_read_eeprom(sc, SF_EE_NODEADDR + ETHER_ADDR_LEN - i); 712 713 /* Allocate the descriptor queues. */ 714 sc->sf_ldata = contigmalloc(sizeof(struct sf_list_data), M_DEVBUF, 715 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 716 717 if (sc->sf_ldata == NULL) { 718 device_printf(dev, "no memory for list buffers!\n"); 719 error = ENXIO; 720 goto fail; 721 } 722 723 bzero(sc->sf_ldata, sizeof(struct sf_list_data)); 724 725 ifp = sc->sf_ifp = if_alloc(IFT_ETHER); 726 if (ifp == NULL) { 727 device_printf(dev, "can not if_alloc()\n"); 728 error = ENOSPC; 729 goto fail; 730 } 731 732 /* Do MII setup. */ 733 if (mii_phy_probe(dev, &sc->sf_miibus, 734 sf_ifmedia_upd, sf_ifmedia_sts)) { 735 device_printf(dev, "MII without any phy!\n"); 736 error = ENXIO; 737 goto fail; 738 } 739 740 ifp->if_softc = sc; 741 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 742 ifp->if_mtu = ETHERMTU; 743 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 744 ifp->if_ioctl = sf_ioctl; 745 ifp->if_start = sf_start; 746 ifp->if_watchdog = sf_watchdog; 747 ifp->if_init = sf_init; 748 ifp->if_baudrate = 10000000; 749 IFQ_SET_MAXLEN(&ifp->if_snd, SF_TX_DLIST_CNT - 1); 750 ifp->if_snd.ifq_drv_maxlen = SF_TX_DLIST_CNT - 1; 751 IFQ_SET_READY(&ifp->if_snd); 752#ifdef DEVICE_POLLING 753 ifp->if_capabilities |= IFCAP_POLLING; 754#endif /* DEVICE_POLLING */ 755 ifp->if_capenable = ifp->if_capabilities; 756 757 /* 758 * Call MI attach routine. 759 */ 760 ether_ifattach(ifp, eaddr); 761 762 /* Hook interrupt last to avoid having to lock softc */ 763 error = bus_setup_intr(dev, sc->sf_irq, INTR_TYPE_NET | INTR_MPSAFE, 764 sf_intr, sc, &sc->sf_intrhand); 765 766 if (error) { 767 device_printf(dev, "couldn't set up irq\n"); 768 ether_ifdetach(ifp); 769 if_free(ifp); 770 goto fail; 771 } 772 773fail: 774 if (error) 775 sf_detach(dev); 776 777 return(error); 778} 779 780/* 781 * Shutdown hardware and free up resources. This can be called any 782 * time after the mutex has been initialized. It is called in both 783 * the error case in attach and the normal detach case so it needs 784 * to be careful about only freeing resources that have actually been 785 * allocated. 786 */ 787static int 788sf_detach(dev) 789 device_t dev; 790{ 791 struct sf_softc *sc; 792 struct ifnet *ifp; 793 794 sc = device_get_softc(dev); 795 KASSERT(mtx_initialized(&sc->sf_mtx), ("sf mutex not initialized")); 796 ifp = sc->sf_ifp; 797 798 /* These should only be active if attach succeeded */ 799 if (device_is_attached(dev)) { 800 SF_LOCK(sc); 801 sf_stop(sc); 802 SF_UNLOCK(sc); 803 callout_drain(&sc->sf_stat_callout); 804 ether_ifdetach(ifp); 805 if_free(ifp); 806 } 807 if (sc->sf_miibus) 808 device_delete_child(dev, sc->sf_miibus); 809 bus_generic_detach(dev); 810 811 if (sc->sf_intrhand) 812 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand); 813 if (sc->sf_irq) 814 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq); 815 if (sc->sf_res) 816 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 817 818 if (sc->sf_ldata) 819 contigfree(sc->sf_ldata, sizeof(struct sf_list_data), M_DEVBUF); 820 821 mtx_destroy(&sc->sf_mtx); 822 823 return(0); 824} 825 826static int 827sf_init_rx_ring(sc) 828 struct sf_softc *sc; 829{ 830 struct sf_list_data *ld; 831 int i; 832 833 ld = sc->sf_ldata; 834 835 bzero((char *)ld->sf_rx_dlist_big, 836 sizeof(struct sf_rx_bufdesc_type0) * SF_RX_DLIST_CNT); 837 bzero((char *)ld->sf_rx_clist, 838 sizeof(struct sf_rx_cmpdesc_type3) * SF_RX_CLIST_CNT); 839 840 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 841 if (sf_newbuf(sc, &ld->sf_rx_dlist_big[i], NULL) == ENOBUFS) 842 return(ENOBUFS); 843 } 844 845 return(0); 846} 847 848static void 849sf_init_tx_ring(sc) 850 struct sf_softc *sc; 851{ 852 struct sf_list_data *ld; 853 int i; 854 855 ld = sc->sf_ldata; 856 857 bzero((char *)ld->sf_tx_dlist, 858 sizeof(struct sf_tx_bufdesc_type0) * SF_TX_DLIST_CNT); 859 bzero((char *)ld->sf_tx_clist, 860 sizeof(struct sf_tx_cmpdesc_type0) * SF_TX_CLIST_CNT); 861 862 for (i = 0; i < SF_TX_DLIST_CNT; i++) 863 ld->sf_tx_dlist[i].sf_id = SF_TX_BUFDESC_ID; 864 for (i = 0; i < SF_TX_CLIST_CNT; i++) 865 ld->sf_tx_clist[i].sf_type = SF_TXCMPTYPE_TX; 866 867 ld->sf_tx_dlist[SF_TX_DLIST_CNT - 1].sf_end = 1; 868 sc->sf_tx_cnt = 0; 869} 870 871static int 872sf_newbuf(sc, c, m) 873 struct sf_softc *sc; 874 struct sf_rx_bufdesc_type0 *c; 875 struct mbuf *m; 876{ 877 struct mbuf *m_new = NULL; 878 879 if (m == NULL) { 880 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 881 if (m_new == NULL) 882 return(ENOBUFS); 883 884 MCLGET(m_new, M_DONTWAIT); 885 if (!(m_new->m_flags & M_EXT)) { 886 m_freem(m_new); 887 return(ENOBUFS); 888 } 889 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 890 } else { 891 m_new = m; 892 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 893 m_new->m_data = m_new->m_ext.ext_buf; 894 } 895 896 m_adj(m_new, sizeof(u_int64_t)); 897 898 c->sf_mbuf = m_new; 899 c->sf_addrlo = SF_RX_HOSTADDR(vtophys(mtod(m_new, caddr_t))); 900 c->sf_valid = 1; 901 902 return(0); 903} 904 905/* 906 * The starfire is programmed to use 'normal' mode for packet reception, 907 * which means we use the consumer/producer model for both the buffer 908 * descriptor queue and the completion descriptor queue. The only problem 909 * with this is that it involves a lot of register accesses: we have to 910 * read the RX completion consumer and producer indexes and the RX buffer 911 * producer index, plus the RX completion consumer and RX buffer producer 912 * indexes have to be updated. It would have been easier if Adaptec had 913 * put each index in a separate register, especially given that the damn 914 * NIC has a 512K register space. 915 * 916 * In spite of all the lovely features that Adaptec crammed into the 6915, 917 * it is marred by one truly stupid design flaw, which is that receive 918 * buffer addresses must be aligned on a longword boundary. This forces 919 * the packet payload to be unaligned, which is suboptimal on the x86 and 920 * completely unuseable on the Alpha. Our only recourse is to copy received 921 * packets into properly aligned buffers before handing them off. 922 */ 923 924static void 925sf_rxeof(sc) 926 struct sf_softc *sc; 927{ 928 struct mbuf *m; 929 struct ifnet *ifp; 930 struct sf_rx_bufdesc_type0 *desc; 931 struct sf_rx_cmpdesc_type3 *cur_rx; 932 u_int32_t rxcons, rxprod; 933 int cmpprodidx, cmpconsidx, bufprodidx; 934 935 SF_LOCK_ASSERT(sc); 936 937 ifp = sc->sf_ifp; 938 939 rxcons = csr_read_4(sc, SF_CQ_CONSIDX); 940 rxprod = csr_read_4(sc, SF_RXDQ_PTR_Q1); 941 cmpprodidx = SF_IDX_LO(csr_read_4(sc, SF_CQ_PRODIDX)); 942 cmpconsidx = SF_IDX_LO(rxcons); 943 bufprodidx = SF_IDX_LO(rxprod); 944 945 while (cmpconsidx != cmpprodidx) { 946 struct mbuf *m0; 947 948#ifdef DEVICE_POLLING 949 if (ifp->if_flags & IFF_POLLING) { 950 if (sc->rxcycles <= 0) 951 break; 952 sc->rxcycles--; 953 } 954#endif /* DEVICE_POLLING */ 955 956 cur_rx = &sc->sf_ldata->sf_rx_clist[cmpconsidx]; 957 desc = &sc->sf_ldata->sf_rx_dlist_big[cur_rx->sf_endidx]; 958 m = desc->sf_mbuf; 959 SF_INC(cmpconsidx, SF_RX_CLIST_CNT); 960 SF_INC(bufprodidx, SF_RX_DLIST_CNT); 961 962 if (!(cur_rx->sf_status1 & SF_RXSTAT1_OK)) { 963 ifp->if_ierrors++; 964 sf_newbuf(sc, desc, m); 965 continue; 966 } 967 968 m0 = m_devget(mtod(m, char *), cur_rx->sf_len, ETHER_ALIGN, 969 ifp, NULL); 970 sf_newbuf(sc, desc, m); 971 if (m0 == NULL) { 972 ifp->if_ierrors++; 973 continue; 974 } 975 m = m0; 976 977 ifp->if_ipackets++; 978 SF_UNLOCK(sc); 979 (*ifp->if_input)(ifp, m); 980 SF_LOCK(sc); 981 } 982 983 csr_write_4(sc, SF_CQ_CONSIDX, 984 (rxcons & ~SF_CQ_CONSIDX_RXQ1) | cmpconsidx); 985 csr_write_4(sc, SF_RXDQ_PTR_Q1, 986 (rxprod & ~SF_RXDQ_PRODIDX) | bufprodidx); 987} 988 989/* 990 * Read the transmit status from the completion queue and release 991 * mbufs. Note that the buffer descriptor index in the completion 992 * descriptor is an offset from the start of the transmit buffer 993 * descriptor list in bytes. This is important because the manual 994 * gives the impression that it should match the producer/consumer 995 * index, which is the offset in 8 byte blocks. 996 */ 997static void 998sf_txeof(sc) 999 struct sf_softc *sc; 1000{ 1001 int txcons, cmpprodidx, cmpconsidx; 1002 struct sf_tx_cmpdesc_type1 *cur_cmp; 1003 struct sf_tx_bufdesc_type0 *cur_tx; 1004 struct ifnet *ifp; 1005 1006 ifp = sc->sf_ifp; 1007 1008 SF_LOCK_ASSERT(sc); 1009 txcons = csr_read_4(sc, SF_CQ_CONSIDX); 1010 cmpprodidx = SF_IDX_HI(csr_read_4(sc, SF_CQ_PRODIDX)); 1011 cmpconsidx = SF_IDX_HI(txcons); 1012 1013 while (cmpconsidx != cmpprodidx) { 1014 cur_cmp = &sc->sf_ldata->sf_tx_clist[cmpconsidx]; 1015 cur_tx = &sc->sf_ldata->sf_tx_dlist[cur_cmp->sf_index >> 7]; 1016 1017 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_OK) 1018 ifp->if_opackets++; 1019 else { 1020 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_UNDERRUN) 1021 sf_txthresh_adjust(sc); 1022 ifp->if_oerrors++; 1023 } 1024 1025 sc->sf_tx_cnt--; 1026 if (cur_tx->sf_mbuf != NULL) { 1027 m_freem(cur_tx->sf_mbuf); 1028 cur_tx->sf_mbuf = NULL; 1029 } else 1030 break; 1031 SF_INC(cmpconsidx, SF_TX_CLIST_CNT); 1032 } 1033 1034 ifp->if_timer = 0; 1035 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1036 1037 csr_write_4(sc, SF_CQ_CONSIDX, 1038 (txcons & ~SF_CQ_CONSIDX_TXQ) | 1039 ((cmpconsidx << 16) & 0xFFFF0000)); 1040} 1041 1042static void 1043sf_txthresh_adjust(sc) 1044 struct sf_softc *sc; 1045{ 1046 u_int32_t txfctl; 1047 u_int8_t txthresh; 1048 1049 txfctl = csr_read_4(sc, SF_TX_FRAMCTL); 1050 txthresh = txfctl & SF_TXFRMCTL_TXTHRESH; 1051 if (txthresh < 0xFF) { 1052 txthresh++; 1053 txfctl &= ~SF_TXFRMCTL_TXTHRESH; 1054 txfctl |= txthresh; 1055#ifdef DIAGNOSTIC 1056 if_printf(sc->sf_ifp, "tx underrun, increasing " 1057 "tx threshold to %d bytes\n", 1058 txthresh * 4); 1059#endif 1060 csr_write_4(sc, SF_TX_FRAMCTL, txfctl); 1061 } 1062} 1063 1064#ifdef DEVICE_POLLING 1065static void 1066sf_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1067{ 1068 struct sf_softc *sc = ifp->if_softc; 1069 1070 SF_LOCK(sc); 1071 sf_poll_locked(ifp, cmd, count); 1072 SF_UNLOCK(sc); 1073} 1074 1075static void 1076sf_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 1077{ 1078 struct sf_softc *sc = ifp->if_softc; 1079 1080 SF_LOCK_ASSERT(sc); 1081 1082 if (!(ifp->if_capenable & IFCAP_POLLING)) { 1083 ether_poll_deregister(ifp); 1084 cmd = POLL_DEREGISTER; 1085 } 1086 1087 if (cmd == POLL_DEREGISTER) { 1088 /* Final call, enable interrupts. */ 1089 csr_write_4(sc, SF_IMR, SF_INTRS); 1090 return; 1091 } 1092 1093 sc->rxcycles = count; 1094 sf_rxeof(sc); 1095 sf_txeof(sc); 1096 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1097 sf_start_locked(ifp); 1098 1099 if (cmd == POLL_AND_CHECK_STATUS) { 1100 u_int32_t status; 1101 1102 status = csr_read_4(sc, SF_ISR); 1103 if (status) 1104 csr_write_4(sc, SF_ISR, status); 1105 1106 if (status & SF_ISR_TX_LOFIFO) 1107 sf_txthresh_adjust(sc); 1108 1109 if (status & SF_ISR_ABNORMALINTR) { 1110 if (status & SF_ISR_STATSOFLOW) { 1111 callout_stop(&sc->sf_stat_callout); 1112 sf_stats_update(sc); 1113 } else 1114 sf_init_locked(sc); 1115 } 1116 } 1117} 1118#endif /* DEVICE_POLLING */ 1119 1120static void 1121sf_intr(arg) 1122 void *arg; 1123{ 1124 struct sf_softc *sc; 1125 struct ifnet *ifp; 1126 u_int32_t status; 1127 1128 sc = arg; 1129 SF_LOCK(sc); 1130 1131 ifp = sc->sf_ifp; 1132 1133#ifdef DEVICE_POLLING 1134 if (ifp->if_flags & IFF_POLLING) 1135 goto done_locked; 1136 1137 if ((ifp->if_capenable & IFCAP_POLLING) && 1138 ether_poll_register(sf_poll, ifp)) { 1139 /* OK, disable interrupts. */ 1140 csr_write_4(sc, SF_IMR, 0x00000000); 1141 sf_poll_locked(ifp, 0, 1); 1142 goto done_locked; 1143 } 1144#endif /* DEVICE_POLLING */ 1145 1146 if (!(csr_read_4(sc, SF_ISR_SHADOW) & SF_ISR_PCIINT_ASSERTED)) { 1147 SF_UNLOCK(sc); 1148 return; 1149 } 1150 1151 /* Disable interrupts. */ 1152 csr_write_4(sc, SF_IMR, 0x00000000); 1153 1154 for (;;) { 1155 status = csr_read_4(sc, SF_ISR); 1156 if (status) 1157 csr_write_4(sc, SF_ISR, status); 1158 1159 if (!(status & SF_INTRS)) 1160 break; 1161 1162 if (status & SF_ISR_RXDQ1_DMADONE) 1163 sf_rxeof(sc); 1164 1165 if (status & SF_ISR_TX_TXDONE || 1166 status & SF_ISR_TX_DMADONE || 1167 status & SF_ISR_TX_QUEUEDONE) 1168 sf_txeof(sc); 1169 1170 if (status & SF_ISR_TX_LOFIFO) 1171 sf_txthresh_adjust(sc); 1172 1173 if (status & SF_ISR_ABNORMALINTR) { 1174 if (status & SF_ISR_STATSOFLOW) { 1175 callout_stop(&sc->sf_stat_callout); 1176 sf_stats_update(sc); 1177 } else 1178 sf_init_locked(sc); 1179 } 1180 } 1181 1182 /* Re-enable interrupts. */ 1183 csr_write_4(sc, SF_IMR, SF_INTRS); 1184 1185 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1186 sf_start_locked(ifp); 1187 1188#ifdef DEVICE_POLLING 1189done_locked: 1190#endif /* DEVICE_POLLING */ 1191 SF_UNLOCK(sc); 1192} 1193 1194static void 1195sf_init(xsc) 1196 void *xsc; 1197{ 1198 struct sf_softc *sc; 1199 1200 sc = xsc; 1201 SF_LOCK(sc); 1202 sf_init_locked(sc); 1203 SF_UNLOCK(sc); 1204} 1205 1206static void 1207sf_init_locked(sc) 1208 struct sf_softc *sc; 1209{ 1210 struct ifnet *ifp; 1211 struct mii_data *mii; 1212 int i; 1213 1214 SF_LOCK_ASSERT(sc); 1215 ifp = sc->sf_ifp; 1216 mii = device_get_softc(sc->sf_miibus); 1217 1218 sf_stop(sc); 1219 sf_reset(sc); 1220 1221 /* Init all the receive filter registers */ 1222 for (i = SF_RXFILT_PERFECT_BASE; 1223 i < (SF_RXFILT_HASH_MAX + 1); i += 4) 1224 csr_write_4(sc, i, 0); 1225 1226 /* Empty stats counter registers. */ 1227 for (i = 0; i < sizeof(struct sf_stats)/sizeof(u_int32_t); i++) 1228 csr_write_4(sc, SF_STATS_BASE + 1229 (i + sizeof(u_int32_t)), 0); 1230 1231 /* Init our MAC address */ 1232 csr_write_4(sc, SF_PAR0, *(u_int32_t *)(&IFP2ENADDR(sc->sf_ifp)[0])); 1233 csr_write_4(sc, SF_PAR1, *(u_int32_t *)(&IFP2ENADDR(sc->sf_ifp)[4])); 1234 sf_setperf(sc, 0, (caddr_t)&IFP2ENADDR(sc->sf_ifp)); 1235 1236 if (sf_init_rx_ring(sc) == ENOBUFS) { 1237 if_printf(sc->sf_ifp, 1238 "initialization failed: no memory for rx buffers\n"); 1239 return; 1240 } 1241 1242 sf_init_tx_ring(sc); 1243 1244 csr_write_4(sc, SF_RXFILT, SF_PERFMODE_NORMAL|SF_HASHMODE_WITHVLAN); 1245 1246 /* If we want promiscuous mode, set the allframes bit. */ 1247 if (ifp->if_flags & IFF_PROMISC) { 1248 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 1249 } else { 1250 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 1251 } 1252 1253 if (ifp->if_flags & IFF_BROADCAST) { 1254 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_BROAD); 1255 } else { 1256 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_BROAD); 1257 } 1258 1259 /* 1260 * Load the multicast filter. 1261 */ 1262 sf_setmulti(sc); 1263 1264 /* Init the completion queue indexes */ 1265 csr_write_4(sc, SF_CQ_CONSIDX, 0); 1266 csr_write_4(sc, SF_CQ_PRODIDX, 0); 1267 1268 /* Init the RX completion queue */ 1269 csr_write_4(sc, SF_RXCQ_CTL_1, 1270 vtophys(sc->sf_ldata->sf_rx_clist) & SF_RXCQ_ADDR); 1271 SF_SETBIT(sc, SF_RXCQ_CTL_1, SF_RXCQTYPE_3); 1272 1273 /* Init RX DMA control. */ 1274 SF_SETBIT(sc, SF_RXDMA_CTL, SF_RXDMA_REPORTBADPKTS); 1275 1276 /* Init the RX buffer descriptor queue. */ 1277 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 1278 vtophys(sc->sf_ldata->sf_rx_dlist_big)); 1279 csr_write_4(sc, SF_RXDQ_CTL_1, (MCLBYTES << 16) | SF_DESCSPACE_16BYTES); 1280 csr_write_4(sc, SF_RXDQ_PTR_Q1, SF_RX_DLIST_CNT - 1); 1281 1282 /* Init the TX completion queue */ 1283 csr_write_4(sc, SF_TXCQ_CTL, 1284 vtophys(sc->sf_ldata->sf_tx_clist) & SF_RXCQ_ADDR); 1285 1286 /* Init the TX buffer descriptor queue. */ 1287 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 1288 vtophys(sc->sf_ldata->sf_tx_dlist)); 1289 SF_SETBIT(sc, SF_TX_FRAMCTL, SF_TXFRMCTL_CPLAFTERTX); 1290 csr_write_4(sc, SF_TXDQ_CTL, 1291 SF_TXBUFDESC_TYPE0|SF_TXMINSPACE_128BYTES|SF_TXSKIPLEN_8BYTES); 1292 SF_SETBIT(sc, SF_TXDQ_CTL, SF_TXDQCTL_NODMACMP); 1293 1294 /* Enable autopadding of short TX frames. */ 1295 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_AUTOPAD); 1296 1297#ifdef DEVICE_POLLING 1298 /* Disable interrupts if we are polling. */ 1299 if (ifp->if_flags & IFF_POLLING) 1300 csr_write_4(sc, SF_IMR, 0x00000000); 1301 else 1302#endif /* DEVICE_POLLING */ 1303 1304 /* Enable interrupts. */ 1305 csr_write_4(sc, SF_IMR, SF_INTRS); 1306 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_INTR_ENB); 1307 1308 /* Enable the RX and TX engines. */ 1309 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_RX_ENB|SF_ETHCTL_RXDMA_ENB); 1310 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_TX_ENB|SF_ETHCTL_TXDMA_ENB); 1311 1312 /*mii_mediachg(mii);*/ 1313 sf_ifmedia_upd_locked(ifp); 1314 1315 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1316 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1317 1318 callout_reset(&sc->sf_stat_callout, hz, sf_stats_update, sc); 1319} 1320 1321static int 1322sf_encap(sc, c, m_head) 1323 struct sf_softc *sc; 1324 struct sf_tx_bufdesc_type0 *c; 1325 struct mbuf *m_head; 1326{ 1327 int frag = 0; 1328 struct sf_frag *f = NULL; 1329 struct mbuf *m; 1330 1331 m = m_head; 1332 1333 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1334 if (m->m_len != 0) { 1335 if (frag == SF_MAXFRAGS) 1336 break; 1337 f = &c->sf_frags[frag]; 1338 if (frag == 0) 1339 f->sf_pktlen = m_head->m_pkthdr.len; 1340 f->sf_fraglen = m->m_len; 1341 f->sf_addr = vtophys(mtod(m, vm_offset_t)); 1342 frag++; 1343 } 1344 } 1345 1346 if (m != NULL) { 1347 struct mbuf *m_new = NULL; 1348 1349 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1350 if (m_new == NULL) { 1351 if_printf(sc->sf_ifp, "no memory for tx list\n"); 1352 return(1); 1353 } 1354 1355 if (m_head->m_pkthdr.len > MHLEN) { 1356 MCLGET(m_new, M_DONTWAIT); 1357 if (!(m_new->m_flags & M_EXT)) { 1358 m_freem(m_new); 1359 if_printf(sc->sf_ifp, "no memory for tx list\n"); 1360 return(1); 1361 } 1362 } 1363 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1364 mtod(m_new, caddr_t)); 1365 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1366 m_freem(m_head); 1367 m_head = m_new; 1368 f = &c->sf_frags[0]; 1369 f->sf_fraglen = f->sf_pktlen = m_head->m_pkthdr.len; 1370 f->sf_addr = vtophys(mtod(m_head, caddr_t)); 1371 frag = 1; 1372 } 1373 1374 c->sf_mbuf = m_head; 1375 c->sf_id = SF_TX_BUFDESC_ID; 1376 c->sf_fragcnt = frag; 1377 c->sf_intr = 1; 1378 c->sf_caltcp = 0; 1379 c->sf_crcen = 1; 1380 1381 return(0); 1382} 1383 1384static void 1385sf_start(ifp) 1386 struct ifnet *ifp; 1387{ 1388 struct sf_softc *sc; 1389 1390 sc = ifp->if_softc; 1391 SF_LOCK(sc); 1392 sf_start_locked(ifp); 1393 SF_UNLOCK(sc); 1394} 1395 1396static void 1397sf_start_locked(ifp) 1398 struct ifnet *ifp; 1399{ 1400 struct sf_softc *sc; 1401 struct sf_tx_bufdesc_type0 *cur_tx = NULL; 1402 struct mbuf *m_head = NULL; 1403 int i, txprod; 1404 1405 sc = ifp->if_softc; 1406 SF_LOCK_ASSERT(sc); 1407 1408 if (!sc->sf_link && ifp->if_snd.ifq_len < 10) 1409 return; 1410 1411 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 1412 return; 1413 1414 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX); 1415 i = SF_IDX_HI(txprod) >> 4; 1416 1417 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) { 1418 if_printf(ifp, "TX ring full, resetting\n"); 1419 sf_init_locked(sc); 1420 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX); 1421 i = SF_IDX_HI(txprod) >> 4; 1422 } 1423 1424 while(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf == NULL) { 1425 if (sc->sf_tx_cnt >= (SF_TX_DLIST_CNT - 5)) { 1426 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1427 cur_tx = NULL; 1428 break; 1429 } 1430 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1431 if (m_head == NULL) 1432 break; 1433 1434 cur_tx = &sc->sf_ldata->sf_tx_dlist[i]; 1435 if (sf_encap(sc, cur_tx, m_head)) { 1436 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1437 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1438 cur_tx = NULL; 1439 break; 1440 } 1441 1442 /* 1443 * If there's a BPF listener, bounce a copy of this frame 1444 * to him. 1445 */ 1446 BPF_MTAP(ifp, m_head); 1447 1448 SF_INC(i, SF_TX_DLIST_CNT); 1449 sc->sf_tx_cnt++; 1450 /* 1451 * Don't get the TX DMA queue get too full. 1452 */ 1453 if (sc->sf_tx_cnt > 64) 1454 break; 1455 } 1456 1457 if (cur_tx == NULL) 1458 return; 1459 1460 /* Transmit */ 1461 csr_write_4(sc, SF_TXDQ_PRODIDX, 1462 (txprod & ~SF_TXDQ_PRODIDX_HIPRIO) | 1463 ((i << 20) & 0xFFFF0000)); 1464 1465 ifp->if_timer = 5; 1466} 1467 1468static void 1469sf_stop(sc) 1470 struct sf_softc *sc; 1471{ 1472 int i; 1473 struct ifnet *ifp; 1474 1475 SF_LOCK_ASSERT(sc); 1476 1477 ifp = sc->sf_ifp; 1478 1479 callout_stop(&sc->sf_stat_callout); 1480 1481#ifdef DEVICE_POLLING 1482 ether_poll_deregister(ifp); 1483#endif /* DEVICE_POLLING */ 1484 1485 csr_write_4(sc, SF_GEN_ETH_CTL, 0); 1486 csr_write_4(sc, SF_CQ_CONSIDX, 0); 1487 csr_write_4(sc, SF_CQ_PRODIDX, 0); 1488 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 0); 1489 csr_write_4(sc, SF_RXDQ_CTL_1, 0); 1490 csr_write_4(sc, SF_RXDQ_PTR_Q1, 0); 1491 csr_write_4(sc, SF_TXCQ_CTL, 0); 1492 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 0); 1493 csr_write_4(sc, SF_TXDQ_CTL, 0); 1494 sf_reset(sc); 1495 1496 sc->sf_link = 0; 1497 1498 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 1499 if (sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf != NULL) { 1500 m_freem(sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf); 1501 sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf = NULL; 1502 } 1503 } 1504 1505 for (i = 0; i < SF_TX_DLIST_CNT; i++) { 1506 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) { 1507 m_freem(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf); 1508 sc->sf_ldata->sf_tx_dlist[i].sf_mbuf = NULL; 1509 } 1510 } 1511 1512 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING|IFF_DRV_OACTIVE); 1513} 1514 1515/* 1516 * Note: it is important that this function not be interrupted. We 1517 * use a two-stage register access scheme: if we are interrupted in 1518 * between setting the indirect address register and reading from the 1519 * indirect data register, the contents of the address register could 1520 * be changed out from under us. 1521 */ 1522static void 1523sf_stats_update(xsc) 1524 void *xsc; 1525{ 1526 struct sf_softc *sc; 1527 struct ifnet *ifp; 1528 struct mii_data *mii; 1529 struct sf_stats stats; 1530 u_int32_t *ptr; 1531 int i; 1532 1533 sc = xsc; 1534 SF_LOCK_ASSERT(sc); 1535 ifp = sc->sf_ifp; 1536 mii = device_get_softc(sc->sf_miibus); 1537 1538 ptr = (u_int32_t *)&stats; 1539 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++) 1540 ptr[i] = csr_read_4(sc, SF_STATS_BASE + 1541 (i + sizeof(u_int32_t))); 1542 1543 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++) 1544 csr_write_4(sc, SF_STATS_BASE + 1545 (i + sizeof(u_int32_t)), 0); 1546 1547 ifp->if_collisions += stats.sf_tx_single_colls + 1548 stats.sf_tx_multi_colls + stats.sf_tx_excess_colls; 1549 1550 mii_tick(mii); 1551 1552 if (!sc->sf_link && mii->mii_media_status & IFM_ACTIVE && 1553 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1554 sc->sf_link++; 1555 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1556 sf_start_locked(ifp); 1557 } 1558 1559 callout_reset(&sc->sf_stat_callout, hz, sf_stats_update, sc); 1560} 1561 1562static void 1563sf_watchdog(ifp) 1564 struct ifnet *ifp; 1565{ 1566 struct sf_softc *sc; 1567 1568 sc = ifp->if_softc; 1569 1570 SF_LOCK(sc); 1571 1572 ifp->if_oerrors++; 1573 if_printf(ifp, "watchdog timeout\n"); 1574 1575 sf_stop(sc); 1576 sf_reset(sc); 1577 sf_init_locked(sc); 1578 1579 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1580 sf_start_locked(ifp); 1581 1582 SF_UNLOCK(sc); 1583} 1584 1585static void 1586sf_shutdown(dev) 1587 device_t dev; 1588{ 1589 struct sf_softc *sc; 1590 1591 sc = device_get_softc(dev); 1592 1593 SF_LOCK(sc); 1594 sf_stop(sc); 1595 SF_UNLOCK(sc); 1596} 1597