if_sf.c revision 148947
1/*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/sf/if_sf.c 148947 2005-08-10 20:24:39Z jhb $"); 35 36/* 37 * Adaptec AIC-6915 "Starfire" PCI fast ethernet driver for FreeBSD. 38 * Programming manual is available from: 39 * http://download.adaptec.com/pdfs/user_guides/aic6915_pg.pdf. 40 * 41 * Written by Bill Paul <wpaul@ctr.columbia.edu> 42 * Department of Electical Engineering 43 * Columbia University, New York City 44 */ 45/* 46 * The Adaptec AIC-6915 "Starfire" is a 64-bit 10/100 PCI ethernet 47 * controller designed with flexibility and reducing CPU load in mind. 48 * The Starfire offers high and low priority buffer queues, a 49 * producer/consumer index mechanism and several different buffer 50 * queue and completion queue descriptor types. Any one of a number 51 * of different driver designs can be used, depending on system and 52 * OS requirements. This driver makes use of type0 transmit frame 53 * descriptors (since BSD fragments packets across an mbuf chain) 54 * and two RX buffer queues prioritized on size (one queue for small 55 * frames that will fit into a single mbuf, another with full size 56 * mbuf clusters for everything else). The producer/consumer indexes 57 * and completion queues are also used. 58 * 59 * One downside to the Starfire has to do with alignment: buffer 60 * queues must be aligned on 256-byte boundaries, and receive buffers 61 * must be aligned on longword boundaries. The receive buffer alignment 62 * causes problems on the Alpha platform, where the packet payload 63 * should be longword aligned. There is no simple way around this. 64 * 65 * For receive filtering, the Starfire offers 16 perfect filter slots 66 * and a 512-bit hash table. 67 * 68 * The Starfire has no internal transceiver, relying instead on an 69 * external MII-based transceiver. Accessing registers on external 70 * PHYs is done through a special register map rather than with the 71 * usual bitbang MDIO method. 72 * 73 * Acesssing the registers on the Starfire is a little tricky. The 74 * Starfire has a 512K internal register space. When programmed for 75 * PCI memory mapped mode, the entire register space can be accessed 76 * directly. However in I/O space mode, only 256 bytes are directly 77 * mapped into PCI I/O space. The other registers can be accessed 78 * indirectly using the SF_INDIRECTIO_ADDR and SF_INDIRECTIO_DATA 79 * registers inside the 256-byte I/O window. 80 */ 81 82#include <sys/param.h> 83#include <sys/systm.h> 84#include <sys/sockio.h> 85#include <sys/mbuf.h> 86#include <sys/malloc.h> 87#include <sys/kernel.h> 88#include <sys/module.h> 89#include <sys/socket.h> 90 91#include <net/if.h> 92#include <net/if_arp.h> 93#include <net/ethernet.h> 94#include <net/if_dl.h> 95#include <net/if_media.h> 96#include <net/if_types.h> 97 98#include <net/bpf.h> 99 100#include <vm/vm.h> /* for vtophys */ 101#include <vm/pmap.h> /* for vtophys */ 102#include <machine/bus.h> 103#include <machine/resource.h> 104#include <sys/bus.h> 105#include <sys/rman.h> 106 107#include <dev/mii/mii.h> 108#include <dev/mii/miivar.h> 109 110/* "controller miibus0" required. See GENERIC if you get errors here. */ 111#include "miibus_if.h" 112 113#include <dev/pci/pcireg.h> 114#include <dev/pci/pcivar.h> 115 116#define SF_USEIOSPACE 117 118#include <pci/if_sfreg.h> 119 120MODULE_DEPEND(sf, pci, 1, 1, 1); 121MODULE_DEPEND(sf, ether, 1, 1, 1); 122MODULE_DEPEND(sf, miibus, 1, 1, 1); 123 124static struct sf_type sf_devs[] = { 125 { AD_VENDORID, AD_DEVICEID_STARFIRE, 126 "Adaptec AIC-6915 10/100BaseTX" }, 127 { 0, 0, NULL } 128}; 129 130static int sf_probe(device_t); 131static int sf_attach(device_t); 132static int sf_detach(device_t); 133static void sf_intr(void *); 134static void sf_stats_update(void *); 135static void sf_rxeof(struct sf_softc *); 136static void sf_txeof(struct sf_softc *); 137static int sf_encap(struct sf_softc *, struct sf_tx_bufdesc_type0 *, 138 struct mbuf *); 139static void sf_start(struct ifnet *); 140static int sf_ioctl(struct ifnet *, u_long, caddr_t); 141static void sf_init(void *); 142static void sf_stop(struct sf_softc *); 143static void sf_watchdog(struct ifnet *); 144static void sf_shutdown(device_t); 145static int sf_ifmedia_upd(struct ifnet *); 146static void sf_ifmedia_sts(struct ifnet *, struct ifmediareq *); 147static void sf_reset(struct sf_softc *); 148static int sf_init_rx_ring(struct sf_softc *); 149static void sf_init_tx_ring(struct sf_softc *); 150static int sf_newbuf(struct sf_softc *, struct sf_rx_bufdesc_type0 *, 151 struct mbuf *); 152static void sf_setmulti(struct sf_softc *); 153static int sf_setperf(struct sf_softc *, int, caddr_t); 154static int sf_sethash(struct sf_softc *, caddr_t, int); 155#ifdef notdef 156static int sf_setvlan(struct sf_softc *, int, u_int32_t); 157#endif 158 159static u_int8_t sf_read_eeprom(struct sf_softc *, int); 160 161static int sf_miibus_readreg(device_t, int, int); 162static int sf_miibus_writereg(device_t, int, int, int); 163static void sf_miibus_statchg(device_t); 164#ifdef DEVICE_POLLING 165static void sf_poll(struct ifnet *ifp, enum poll_cmd cmd, 166 int count); 167static void sf_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, 168 int count); 169#endif /* DEVICE_POLLING */ 170 171static u_int32_t csr_read_4(struct sf_softc *, int); 172static void csr_write_4(struct sf_softc *, int, u_int32_t); 173static void sf_txthresh_adjust(struct sf_softc *); 174 175#ifdef SF_USEIOSPACE 176#define SF_RES SYS_RES_IOPORT 177#define SF_RID SF_PCI_LOIO 178#else 179#define SF_RES SYS_RES_MEMORY 180#define SF_RID SF_PCI_LOMEM 181#endif 182 183static device_method_t sf_methods[] = { 184 /* Device interface */ 185 DEVMETHOD(device_probe, sf_probe), 186 DEVMETHOD(device_attach, sf_attach), 187 DEVMETHOD(device_detach, sf_detach), 188 DEVMETHOD(device_shutdown, sf_shutdown), 189 190 /* bus interface */ 191 DEVMETHOD(bus_print_child, bus_generic_print_child), 192 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 193 194 /* MII interface */ 195 DEVMETHOD(miibus_readreg, sf_miibus_readreg), 196 DEVMETHOD(miibus_writereg, sf_miibus_writereg), 197 DEVMETHOD(miibus_statchg, sf_miibus_statchg), 198 199 { 0, 0 } 200}; 201 202static driver_t sf_driver = { 203 "sf", 204 sf_methods, 205 sizeof(struct sf_softc), 206}; 207 208static devclass_t sf_devclass; 209 210DRIVER_MODULE(sf, pci, sf_driver, sf_devclass, 0, 0); 211DRIVER_MODULE(miibus, sf, miibus_driver, miibus_devclass, 0, 0); 212 213#define SF_SETBIT(sc, reg, x) \ 214 csr_write_4(sc, reg, csr_read_4(sc, reg) | (x)) 215 216#define SF_CLRBIT(sc, reg, x) \ 217 csr_write_4(sc, reg, csr_read_4(sc, reg) & ~(x)) 218 219static u_int32_t 220csr_read_4(sc, reg) 221 struct sf_softc *sc; 222 int reg; 223{ 224 u_int32_t val; 225 226#ifdef SF_USEIOSPACE 227 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); 228 val = CSR_READ_4(sc, SF_INDIRECTIO_DATA); 229#else 230 val = CSR_READ_4(sc, (reg + SF_RMAP_INTREG_BASE)); 231#endif 232 233 return(val); 234} 235 236static u_int8_t 237sf_read_eeprom(sc, reg) 238 struct sf_softc *sc; 239 int reg; 240{ 241 u_int8_t val; 242 243 val = (csr_read_4(sc, SF_EEADDR_BASE + 244 (reg & 0xFFFFFFFC)) >> (8 * (reg & 3))) & 0xFF; 245 246 return(val); 247} 248 249static void 250csr_write_4(sc, reg, val) 251 struct sf_softc *sc; 252 int reg; 253 u_int32_t val; 254{ 255#ifdef SF_USEIOSPACE 256 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); 257 CSR_WRITE_4(sc, SF_INDIRECTIO_DATA, val); 258#else 259 CSR_WRITE_4(sc, (reg + SF_RMAP_INTREG_BASE), val); 260#endif 261} 262 263/* 264 * Copy the address 'mac' into the perfect RX filter entry at 265 * offset 'idx.' The perfect filter only has 16 entries so do 266 * some sanity tests. 267 */ 268static int 269sf_setperf(sc, idx, mac) 270 struct sf_softc *sc; 271 int idx; 272 caddr_t mac; 273{ 274 u_int16_t *p; 275 276 if (idx < 0 || idx > SF_RXFILT_PERFECT_CNT) 277 return(EINVAL); 278 279 if (mac == NULL) 280 return(EINVAL); 281 282 p = (u_int16_t *)mac; 283 284 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 285 (idx * SF_RXFILT_PERFECT_SKIP), htons(p[2])); 286 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 287 (idx * SF_RXFILT_PERFECT_SKIP) + 4, htons(p[1])); 288 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 289 (idx * SF_RXFILT_PERFECT_SKIP) + 8, htons(p[0])); 290 291 return(0); 292} 293 294/* 295 * Set the bit in the 512-bit hash table that corresponds to the 296 * specified mac address 'mac.' If 'prio' is nonzero, update the 297 * priority hash table instead of the filter hash table. 298 */ 299static int 300sf_sethash(sc, mac, prio) 301 struct sf_softc *sc; 302 caddr_t mac; 303 int prio; 304{ 305 u_int32_t h; 306 307 if (mac == NULL) 308 return(EINVAL); 309 310 h = ether_crc32_be(mac, ETHER_ADDR_LEN) >> 23; 311 312 if (prio) { 313 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_PRIOOFF + 314 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); 315 } else { 316 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_ADDROFF + 317 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); 318 } 319 320 return(0); 321} 322 323#ifdef notdef 324/* 325 * Set a VLAN tag in the receive filter. 326 */ 327static int 328sf_setvlan(sc, idx, vlan) 329 struct sf_softc *sc; 330 int idx; 331 u_int32_t vlan; 332{ 333 if (idx < 0 || idx >> SF_RXFILT_HASH_CNT) 334 return(EINVAL); 335 336 csr_write_4(sc, SF_RXFILT_HASH_BASE + 337 (idx * SF_RXFILT_HASH_SKIP) + SF_RXFILT_HASH_VLANOFF, vlan); 338 339 return(0); 340} 341#endif 342 343static int 344sf_miibus_readreg(dev, phy, reg) 345 device_t dev; 346 int phy, reg; 347{ 348 struct sf_softc *sc; 349 int i; 350 u_int32_t val = 0; 351 352 sc = device_get_softc(dev); 353 354 for (i = 0; i < SF_TIMEOUT; i++) { 355 val = csr_read_4(sc, SF_PHY_REG(phy, reg)); 356 if (val & SF_MII_DATAVALID) 357 break; 358 } 359 360 if (i == SF_TIMEOUT) 361 return(0); 362 363 if ((val & 0x0000FFFF) == 0xFFFF) 364 return(0); 365 366 return(val & 0x0000FFFF); 367} 368 369static int 370sf_miibus_writereg(dev, phy, reg, val) 371 device_t dev; 372 int phy, reg, val; 373{ 374 struct sf_softc *sc; 375 int i; 376 int busy; 377 378 sc = device_get_softc(dev); 379 380 csr_write_4(sc, SF_PHY_REG(phy, reg), val); 381 382 for (i = 0; i < SF_TIMEOUT; i++) { 383 busy = csr_read_4(sc, SF_PHY_REG(phy, reg)); 384 if (!(busy & SF_MII_BUSY)) 385 break; 386 } 387 388 return(0); 389} 390 391static void 392sf_miibus_statchg(dev) 393 device_t dev; 394{ 395 struct sf_softc *sc; 396 struct mii_data *mii; 397 398 sc = device_get_softc(dev); 399 mii = device_get_softc(sc->sf_miibus); 400 401 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 402 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 403 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_FDX); 404 } else { 405 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 406 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_HDX); 407 } 408} 409 410static void 411sf_setmulti(sc) 412 struct sf_softc *sc; 413{ 414 struct ifnet *ifp; 415 int i; 416 struct ifmultiaddr *ifma; 417 u_int8_t dummy[] = { 0, 0, 0, 0, 0, 0 }; 418 419 ifp = sc->sf_ifp; 420 421 /* First zot all the existing filters. */ 422 for (i = 1; i < SF_RXFILT_PERFECT_CNT; i++) 423 sf_setperf(sc, i, (char *)&dummy); 424 for (i = SF_RXFILT_HASH_BASE; 425 i < (SF_RXFILT_HASH_MAX + 1); i += 4) 426 csr_write_4(sc, i, 0); 427 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI); 428 429 /* Now program new ones. */ 430 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 431 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI); 432 } else { 433 i = 1; 434 IF_ADDR_LOCK(ifp); 435 TAILQ_FOREACH_REVERSE(ifma, &ifp->if_multiaddrs, ifmultihead, ifma_link) { 436 if (ifma->ifma_addr->sa_family != AF_LINK) 437 continue; 438 /* 439 * Program the first 15 multicast groups 440 * into the perfect filter. For all others, 441 * use the hash table. 442 */ 443 if (i < SF_RXFILT_PERFECT_CNT) { 444 sf_setperf(sc, i, 445 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 446 i++; 447 continue; 448 } 449 450 sf_sethash(sc, 451 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 0); 452 } 453 IF_ADDR_UNLOCK(ifp); 454 } 455} 456 457/* 458 * Set media options. 459 */ 460static int 461sf_ifmedia_upd(ifp) 462 struct ifnet *ifp; 463{ 464 struct sf_softc *sc; 465 struct mii_data *mii; 466 467 sc = ifp->if_softc; 468 mii = device_get_softc(sc->sf_miibus); 469 sc->sf_link = 0; 470 if (mii->mii_instance) { 471 struct mii_softc *miisc; 472 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 473 mii_phy_reset(miisc); 474 } 475 mii_mediachg(mii); 476 477 return(0); 478} 479 480/* 481 * Report current media status. 482 */ 483static void 484sf_ifmedia_sts(ifp, ifmr) 485 struct ifnet *ifp; 486 struct ifmediareq *ifmr; 487{ 488 struct sf_softc *sc; 489 struct mii_data *mii; 490 491 sc = ifp->if_softc; 492 mii = device_get_softc(sc->sf_miibus); 493 494 mii_pollstat(mii); 495 ifmr->ifm_active = mii->mii_media_active; 496 ifmr->ifm_status = mii->mii_media_status; 497} 498 499static int 500sf_ioctl(ifp, command, data) 501 struct ifnet *ifp; 502 u_long command; 503 caddr_t data; 504{ 505 struct sf_softc *sc = ifp->if_softc; 506 struct ifreq *ifr = (struct ifreq *) data; 507 struct mii_data *mii; 508 int error = 0; 509 510 SF_LOCK(sc); 511 512 switch(command) { 513 case SIOCSIFFLAGS: 514 if (ifp->if_flags & IFF_UP) { 515 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 516 ifp->if_flags & IFF_PROMISC && 517 !(sc->sf_if_flags & IFF_PROMISC)) { 518 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 519 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING && 520 !(ifp->if_flags & IFF_PROMISC) && 521 sc->sf_if_flags & IFF_PROMISC) { 522 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 523 } else if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 524 sf_init(sc); 525 } else { 526 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 527 sf_stop(sc); 528 } 529 sc->sf_if_flags = ifp->if_flags; 530 error = 0; 531 break; 532 case SIOCADDMULTI: 533 case SIOCDELMULTI: 534 sf_setmulti(sc); 535 error = 0; 536 break; 537 case SIOCGIFMEDIA: 538 case SIOCSIFMEDIA: 539 mii = device_get_softc(sc->sf_miibus); 540 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 541 break; 542 case SIOCSIFCAP: 543 ifp->if_capenable &= ~IFCAP_POLLING; 544 ifp->if_capenable |= ifr->ifr_reqcap & IFCAP_POLLING; 545 break; 546 default: 547 error = ether_ioctl(ifp, command, data); 548 break; 549 } 550 551 SF_UNLOCK(sc); 552 553 return(error); 554} 555 556static void 557sf_reset(sc) 558 struct sf_softc *sc; 559{ 560 register int i; 561 562 csr_write_4(sc, SF_GEN_ETH_CTL, 0); 563 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 564 DELAY(1000); 565 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 566 567 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_RESET); 568 569 for (i = 0; i < SF_TIMEOUT; i++) { 570 DELAY(10); 571 if (!(csr_read_4(sc, SF_PCI_DEVCFG) & SF_PCIDEVCFG_RESET)) 572 break; 573 } 574 575 if (i == SF_TIMEOUT) 576 if_printf(sc->sf_ifp, "reset never completed!\n"); 577 578 /* Wait a little while for the chip to get its brains in order. */ 579 DELAY(1000); 580} 581 582/* 583 * Probe for an Adaptec AIC-6915 chip. Check the PCI vendor and device 584 * IDs against our list and return a device name if we find a match. 585 * We also check the subsystem ID so that we can identify exactly which 586 * NIC has been found, if possible. 587 */ 588static int 589sf_probe(dev) 590 device_t dev; 591{ 592 struct sf_type *t; 593 594 t = sf_devs; 595 596 while(t->sf_name != NULL) { 597 if ((pci_get_vendor(dev) == t->sf_vid) && 598 (pci_get_device(dev) == t->sf_did)) { 599 switch((pci_read_config(dev, 600 SF_PCI_SUBVEN_ID, 4) >> 16) & 0xFFFF) { 601 case AD_SUBSYSID_62011_REV0: 602 case AD_SUBSYSID_62011_REV1: 603 device_set_desc(dev, 604 "Adaptec ANA-62011 10/100BaseTX"); 605 return (BUS_PROBE_DEFAULT); 606 case AD_SUBSYSID_62022: 607 device_set_desc(dev, 608 "Adaptec ANA-62022 10/100BaseTX"); 609 return (BUS_PROBE_DEFAULT); 610 case AD_SUBSYSID_62044_REV0: 611 case AD_SUBSYSID_62044_REV1: 612 device_set_desc(dev, 613 "Adaptec ANA-62044 10/100BaseTX"); 614 return (BUS_PROBE_DEFAULT); 615 case AD_SUBSYSID_62020: 616 device_set_desc(dev, 617 "Adaptec ANA-62020 10/100BaseFX"); 618 return (BUS_PROBE_DEFAULT); 619 case AD_SUBSYSID_69011: 620 device_set_desc(dev, 621 "Adaptec ANA-69011 10/100BaseTX"); 622 return (BUS_PROBE_DEFAULT); 623 default: 624 device_set_desc(dev, t->sf_name); 625 return (BUS_PROBE_DEFAULT); 626 break; 627 } 628 } 629 t++; 630 } 631 632 return(ENXIO); 633} 634 635/* 636 * Attach the interface. Allocate softc structures, do ifmedia 637 * setup and ethernet/BPF attach. 638 */ 639static int 640sf_attach(dev) 641 device_t dev; 642{ 643 int i; 644 struct sf_softc *sc; 645 struct ifnet *ifp; 646 int rid, error = 0; 647 u_char eaddr[6]; 648 649 sc = device_get_softc(dev); 650 651 mtx_init(&sc->sf_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 652 MTX_DEF | MTX_RECURSE); 653 /* 654 * Map control/status registers. 655 */ 656 pci_enable_busmaster(dev); 657 658 rid = SF_RID; 659 sc->sf_res = bus_alloc_resource_any(dev, SF_RES, &rid, RF_ACTIVE); 660 661 if (sc->sf_res == NULL) { 662 device_printf(dev, "couldn't map ports\n"); 663 error = ENXIO; 664 goto fail; 665 } 666 667 sc->sf_btag = rman_get_bustag(sc->sf_res); 668 sc->sf_bhandle = rman_get_bushandle(sc->sf_res); 669 670 /* Allocate interrupt */ 671 rid = 0; 672 sc->sf_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 673 RF_SHAREABLE | RF_ACTIVE); 674 675 if (sc->sf_irq == NULL) { 676 device_printf(dev, "couldn't map interrupt\n"); 677 error = ENXIO; 678 goto fail; 679 } 680 681 callout_handle_init(&sc->sf_stat_ch); 682 /* Reset the adapter. */ 683 sf_reset(sc); 684 685 /* 686 * Get station address from the EEPROM. 687 */ 688 for (i = 0; i < ETHER_ADDR_LEN; i++) 689 eaddr[i] = 690 sf_read_eeprom(sc, SF_EE_NODEADDR + ETHER_ADDR_LEN - i); 691 692 /* Allocate the descriptor queues. */ 693 sc->sf_ldata = contigmalloc(sizeof(struct sf_list_data), M_DEVBUF, 694 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 695 696 if (sc->sf_ldata == NULL) { 697 device_printf(dev, "no memory for list buffers!\n"); 698 error = ENXIO; 699 goto fail; 700 } 701 702 bzero(sc->sf_ldata, sizeof(struct sf_list_data)); 703 704 ifp = sc->sf_ifp = if_alloc(IFT_ETHER); 705 if (ifp == NULL) { 706 device_printf(dev, "can not if_alloc()\n"); 707 error = ENOSPC; 708 goto fail; 709 } 710 711 /* Do MII setup. */ 712 if (mii_phy_probe(dev, &sc->sf_miibus, 713 sf_ifmedia_upd, sf_ifmedia_sts)) { 714 device_printf(dev, "MII without any phy!\n"); 715 error = ENXIO; 716 goto fail; 717 } 718 719 ifp->if_softc = sc; 720 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 721 ifp->if_mtu = ETHERMTU; 722 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST | 723 IFF_NEEDSGIANT; 724 ifp->if_ioctl = sf_ioctl; 725 ifp->if_start = sf_start; 726 ifp->if_watchdog = sf_watchdog; 727 ifp->if_init = sf_init; 728 ifp->if_baudrate = 10000000; 729 IFQ_SET_MAXLEN(&ifp->if_snd, SF_TX_DLIST_CNT - 1); 730 ifp->if_snd.ifq_drv_maxlen = SF_TX_DLIST_CNT - 1; 731 IFQ_SET_READY(&ifp->if_snd); 732#ifdef DEVICE_POLLING 733 ifp->if_capabilities |= IFCAP_POLLING; 734#endif /* DEVICE_POLLING */ 735 ifp->if_capenable = ifp->if_capabilities; 736 737 /* 738 * Call MI attach routine. 739 */ 740 ether_ifattach(ifp, eaddr); 741 742 /* Hook interrupt last to avoid having to lock softc */ 743 error = bus_setup_intr(dev, sc->sf_irq, INTR_TYPE_NET, 744 sf_intr, sc, &sc->sf_intrhand); 745 746 if (error) { 747 device_printf(dev, "couldn't set up irq\n"); 748 ether_ifdetach(ifp); 749 if_free(ifp); 750 goto fail; 751 } 752 753fail: 754 if (error) 755 sf_detach(dev); 756 757 return(error); 758} 759 760/* 761 * Shutdown hardware and free up resources. This can be called any 762 * time after the mutex has been initialized. It is called in both 763 * the error case in attach and the normal detach case so it needs 764 * to be careful about only freeing resources that have actually been 765 * allocated. 766 */ 767static int 768sf_detach(dev) 769 device_t dev; 770{ 771 struct sf_softc *sc; 772 struct ifnet *ifp; 773 774 sc = device_get_softc(dev); 775 KASSERT(mtx_initialized(&sc->sf_mtx), ("sf mutex not initialized")); 776 SF_LOCK(sc); 777 ifp = sc->sf_ifp; 778 779 /* These should only be active if attach succeeded */ 780 if (device_is_attached(dev)) { 781 sf_stop(sc); 782 ether_ifdetach(ifp); 783 if_free(ifp); 784 } 785 if (sc->sf_miibus) 786 device_delete_child(dev, sc->sf_miibus); 787 bus_generic_detach(dev); 788 789 if (sc->sf_intrhand) 790 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand); 791 if (sc->sf_irq) 792 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq); 793 if (sc->sf_res) 794 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 795 796 if (sc->sf_ldata) 797 contigfree(sc->sf_ldata, sizeof(struct sf_list_data), M_DEVBUF); 798 799 SF_UNLOCK(sc); 800 mtx_destroy(&sc->sf_mtx); 801 802 return(0); 803} 804 805static int 806sf_init_rx_ring(sc) 807 struct sf_softc *sc; 808{ 809 struct sf_list_data *ld; 810 int i; 811 812 ld = sc->sf_ldata; 813 814 bzero((char *)ld->sf_rx_dlist_big, 815 sizeof(struct sf_rx_bufdesc_type0) * SF_RX_DLIST_CNT); 816 bzero((char *)ld->sf_rx_clist, 817 sizeof(struct sf_rx_cmpdesc_type3) * SF_RX_CLIST_CNT); 818 819 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 820 if (sf_newbuf(sc, &ld->sf_rx_dlist_big[i], NULL) == ENOBUFS) 821 return(ENOBUFS); 822 } 823 824 return(0); 825} 826 827static void 828sf_init_tx_ring(sc) 829 struct sf_softc *sc; 830{ 831 struct sf_list_data *ld; 832 int i; 833 834 ld = sc->sf_ldata; 835 836 bzero((char *)ld->sf_tx_dlist, 837 sizeof(struct sf_tx_bufdesc_type0) * SF_TX_DLIST_CNT); 838 bzero((char *)ld->sf_tx_clist, 839 sizeof(struct sf_tx_cmpdesc_type0) * SF_TX_CLIST_CNT); 840 841 for (i = 0; i < SF_TX_DLIST_CNT; i++) 842 ld->sf_tx_dlist[i].sf_id = SF_TX_BUFDESC_ID; 843 for (i = 0; i < SF_TX_CLIST_CNT; i++) 844 ld->sf_tx_clist[i].sf_type = SF_TXCMPTYPE_TX; 845 846 ld->sf_tx_dlist[SF_TX_DLIST_CNT - 1].sf_end = 1; 847 sc->sf_tx_cnt = 0; 848} 849 850static int 851sf_newbuf(sc, c, m) 852 struct sf_softc *sc; 853 struct sf_rx_bufdesc_type0 *c; 854 struct mbuf *m; 855{ 856 struct mbuf *m_new = NULL; 857 858 if (m == NULL) { 859 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 860 if (m_new == NULL) 861 return(ENOBUFS); 862 863 MCLGET(m_new, M_DONTWAIT); 864 if (!(m_new->m_flags & M_EXT)) { 865 m_freem(m_new); 866 return(ENOBUFS); 867 } 868 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 869 } else { 870 m_new = m; 871 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 872 m_new->m_data = m_new->m_ext.ext_buf; 873 } 874 875 m_adj(m_new, sizeof(u_int64_t)); 876 877 c->sf_mbuf = m_new; 878 c->sf_addrlo = SF_RX_HOSTADDR(vtophys(mtod(m_new, caddr_t))); 879 c->sf_valid = 1; 880 881 return(0); 882} 883 884/* 885 * The starfire is programmed to use 'normal' mode for packet reception, 886 * which means we use the consumer/producer model for both the buffer 887 * descriptor queue and the completion descriptor queue. The only problem 888 * with this is that it involves a lot of register accesses: we have to 889 * read the RX completion consumer and producer indexes and the RX buffer 890 * producer index, plus the RX completion consumer and RX buffer producer 891 * indexes have to be updated. It would have been easier if Adaptec had 892 * put each index in a separate register, especially given that the damn 893 * NIC has a 512K register space. 894 * 895 * In spite of all the lovely features that Adaptec crammed into the 6915, 896 * it is marred by one truly stupid design flaw, which is that receive 897 * buffer addresses must be aligned on a longword boundary. This forces 898 * the packet payload to be unaligned, which is suboptimal on the x86 and 899 * completely unuseable on the Alpha. Our only recourse is to copy received 900 * packets into properly aligned buffers before handing them off. 901 */ 902 903static void 904sf_rxeof(sc) 905 struct sf_softc *sc; 906{ 907 struct mbuf *m; 908 struct ifnet *ifp; 909 struct sf_rx_bufdesc_type0 *desc; 910 struct sf_rx_cmpdesc_type3 *cur_rx; 911 u_int32_t rxcons, rxprod; 912 int cmpprodidx, cmpconsidx, bufprodidx; 913 914 SF_LOCK_ASSERT(sc); 915 916 ifp = sc->sf_ifp; 917 918 rxcons = csr_read_4(sc, SF_CQ_CONSIDX); 919 rxprod = csr_read_4(sc, SF_RXDQ_PTR_Q1); 920 cmpprodidx = SF_IDX_LO(csr_read_4(sc, SF_CQ_PRODIDX)); 921 cmpconsidx = SF_IDX_LO(rxcons); 922 bufprodidx = SF_IDX_LO(rxprod); 923 924 while (cmpconsidx != cmpprodidx) { 925 struct mbuf *m0; 926 927#ifdef DEVICE_POLLING 928 if (ifp->if_flags & IFF_POLLING) { 929 if (sc->rxcycles <= 0) 930 break; 931 sc->rxcycles--; 932 } 933#endif /* DEVICE_POLLING */ 934 935 cur_rx = &sc->sf_ldata->sf_rx_clist[cmpconsidx]; 936 desc = &sc->sf_ldata->sf_rx_dlist_big[cur_rx->sf_endidx]; 937 m = desc->sf_mbuf; 938 SF_INC(cmpconsidx, SF_RX_CLIST_CNT); 939 SF_INC(bufprodidx, SF_RX_DLIST_CNT); 940 941 if (!(cur_rx->sf_status1 & SF_RXSTAT1_OK)) { 942 ifp->if_ierrors++; 943 sf_newbuf(sc, desc, m); 944 continue; 945 } 946 947 m0 = m_devget(mtod(m, char *), cur_rx->sf_len, ETHER_ALIGN, 948 ifp, NULL); 949 sf_newbuf(sc, desc, m); 950 if (m0 == NULL) { 951 ifp->if_ierrors++; 952 continue; 953 } 954 m = m0; 955 956 ifp->if_ipackets++; 957 SF_UNLOCK(sc); 958 (*ifp->if_input)(ifp, m); 959 SF_LOCK(sc); 960 } 961 962 csr_write_4(sc, SF_CQ_CONSIDX, 963 (rxcons & ~SF_CQ_CONSIDX_RXQ1) | cmpconsidx); 964 csr_write_4(sc, SF_RXDQ_PTR_Q1, 965 (rxprod & ~SF_RXDQ_PRODIDX) | bufprodidx); 966} 967 968/* 969 * Read the transmit status from the completion queue and release 970 * mbufs. Note that the buffer descriptor index in the completion 971 * descriptor is an offset from the start of the transmit buffer 972 * descriptor list in bytes. This is important because the manual 973 * gives the impression that it should match the producer/consumer 974 * index, which is the offset in 8 byte blocks. 975 */ 976static void 977sf_txeof(sc) 978 struct sf_softc *sc; 979{ 980 int txcons, cmpprodidx, cmpconsidx; 981 struct sf_tx_cmpdesc_type1 *cur_cmp; 982 struct sf_tx_bufdesc_type0 *cur_tx; 983 struct ifnet *ifp; 984 985 ifp = sc->sf_ifp; 986 987 txcons = csr_read_4(sc, SF_CQ_CONSIDX); 988 cmpprodidx = SF_IDX_HI(csr_read_4(sc, SF_CQ_PRODIDX)); 989 cmpconsidx = SF_IDX_HI(txcons); 990 991 while (cmpconsidx != cmpprodidx) { 992 cur_cmp = &sc->sf_ldata->sf_tx_clist[cmpconsidx]; 993 cur_tx = &sc->sf_ldata->sf_tx_dlist[cur_cmp->sf_index >> 7]; 994 995 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_OK) 996 ifp->if_opackets++; 997 else { 998 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_UNDERRUN) 999 sf_txthresh_adjust(sc); 1000 ifp->if_oerrors++; 1001 } 1002 1003 sc->sf_tx_cnt--; 1004 if (cur_tx->sf_mbuf != NULL) { 1005 m_freem(cur_tx->sf_mbuf); 1006 cur_tx->sf_mbuf = NULL; 1007 } else 1008 break; 1009 SF_INC(cmpconsidx, SF_TX_CLIST_CNT); 1010 } 1011 1012 ifp->if_timer = 0; 1013 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1014 1015 csr_write_4(sc, SF_CQ_CONSIDX, 1016 (txcons & ~SF_CQ_CONSIDX_TXQ) | 1017 ((cmpconsidx << 16) & 0xFFFF0000)); 1018} 1019 1020static void 1021sf_txthresh_adjust(sc) 1022 struct sf_softc *sc; 1023{ 1024 u_int32_t txfctl; 1025 u_int8_t txthresh; 1026 1027 txfctl = csr_read_4(sc, SF_TX_FRAMCTL); 1028 txthresh = txfctl & SF_TXFRMCTL_TXTHRESH; 1029 if (txthresh < 0xFF) { 1030 txthresh++; 1031 txfctl &= ~SF_TXFRMCTL_TXTHRESH; 1032 txfctl |= txthresh; 1033#ifdef DIAGNOSTIC 1034 if_printf(sc->sf_ifp, "tx underrun, increasing " 1035 "tx threshold to %d bytes\n", 1036 txthresh * 4); 1037#endif 1038 csr_write_4(sc, SF_TX_FRAMCTL, txfctl); 1039 } 1040} 1041 1042#ifdef DEVICE_POLLING 1043static void 1044sf_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1045{ 1046 struct sf_softc *sc = ifp->if_softc; 1047 1048 SF_LOCK(sc); 1049 sf_poll_locked(ifp, cmd, count); 1050 SF_UNLOCK(sc); 1051} 1052 1053static void 1054sf_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 1055{ 1056 struct sf_softc *sc = ifp->if_softc; 1057 1058 SF_LOCK_ASSERT(sc); 1059 1060 if (!(ifp->if_capenable & IFCAP_POLLING)) { 1061 ether_poll_deregister(ifp); 1062 cmd = POLL_DEREGISTER; 1063 } 1064 1065 if (cmd == POLL_DEREGISTER) { 1066 /* Final call, enable interrupts. */ 1067 csr_write_4(sc, SF_IMR, SF_INTRS); 1068 return; 1069 } 1070 1071 sc->rxcycles = count; 1072 sf_rxeof(sc); 1073 sf_txeof(sc); 1074 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1075 sf_start(ifp); 1076 1077 if (cmd == POLL_AND_CHECK_STATUS) { 1078 u_int32_t status; 1079 1080 status = csr_read_4(sc, SF_ISR); 1081 if (status) 1082 csr_write_4(sc, SF_ISR, status); 1083 1084 if (status & SF_ISR_TX_LOFIFO) 1085 sf_txthresh_adjust(sc); 1086 1087 if (status & SF_ISR_ABNORMALINTR) { 1088 if (status & SF_ISR_STATSOFLOW) { 1089 untimeout(sf_stats_update, sc, 1090 sc->sf_stat_ch); 1091 sf_stats_update(sc); 1092 } else 1093 sf_init(sc); 1094 } 1095 } 1096} 1097#endif /* DEVICE_POLLING */ 1098 1099static void 1100sf_intr(arg) 1101 void *arg; 1102{ 1103 struct sf_softc *sc; 1104 struct ifnet *ifp; 1105 u_int32_t status; 1106 1107 sc = arg; 1108 SF_LOCK(sc); 1109 1110 ifp = sc->sf_ifp; 1111 1112#ifdef DEVICE_POLLING 1113 if (ifp->if_flags & IFF_POLLING) 1114 goto done_locked; 1115 1116 if ((ifp->if_capenable & IFCAP_POLLING) && 1117 ether_poll_register(sf_poll, ifp)) { 1118 /* OK, disable interrupts. */ 1119 csr_write_4(sc, SF_IMR, 0x00000000); 1120 sf_poll_locked(ifp, 0, 1); 1121 goto done_locked; 1122 } 1123#endif /* DEVICE_POLLING */ 1124 1125 if (!(csr_read_4(sc, SF_ISR_SHADOW) & SF_ISR_PCIINT_ASSERTED)) { 1126 SF_UNLOCK(sc); 1127 return; 1128 } 1129 1130 /* Disable interrupts. */ 1131 csr_write_4(sc, SF_IMR, 0x00000000); 1132 1133 for (;;) { 1134 status = csr_read_4(sc, SF_ISR); 1135 if (status) 1136 csr_write_4(sc, SF_ISR, status); 1137 1138 if (!(status & SF_INTRS)) 1139 break; 1140 1141 if (status & SF_ISR_RXDQ1_DMADONE) 1142 sf_rxeof(sc); 1143 1144 if (status & SF_ISR_TX_TXDONE || 1145 status & SF_ISR_TX_DMADONE || 1146 status & SF_ISR_TX_QUEUEDONE) 1147 sf_txeof(sc); 1148 1149 if (status & SF_ISR_TX_LOFIFO) 1150 sf_txthresh_adjust(sc); 1151 1152 if (status & SF_ISR_ABNORMALINTR) { 1153 if (status & SF_ISR_STATSOFLOW) { 1154 untimeout(sf_stats_update, sc, 1155 sc->sf_stat_ch); 1156 sf_stats_update(sc); 1157 } else 1158 sf_init(sc); 1159 } 1160 } 1161 1162 /* Re-enable interrupts. */ 1163 csr_write_4(sc, SF_IMR, SF_INTRS); 1164 1165 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1166 sf_start(ifp); 1167 1168#ifdef DEVICE_POLLING 1169done_locked: 1170#endif /* DEVICE_POLLING */ 1171 SF_UNLOCK(sc); 1172} 1173 1174static void 1175sf_init(xsc) 1176 void *xsc; 1177{ 1178 struct sf_softc *sc; 1179 struct ifnet *ifp; 1180 struct mii_data *mii; 1181 int i; 1182 1183 sc = xsc; 1184 SF_LOCK(sc); 1185 ifp = sc->sf_ifp; 1186 mii = device_get_softc(sc->sf_miibus); 1187 1188 sf_stop(sc); 1189 sf_reset(sc); 1190 1191 /* Init all the receive filter registers */ 1192 for (i = SF_RXFILT_PERFECT_BASE; 1193 i < (SF_RXFILT_HASH_MAX + 1); i += 4) 1194 csr_write_4(sc, i, 0); 1195 1196 /* Empty stats counter registers. */ 1197 for (i = 0; i < sizeof(struct sf_stats)/sizeof(u_int32_t); i++) 1198 csr_write_4(sc, SF_STATS_BASE + 1199 (i + sizeof(u_int32_t)), 0); 1200 1201 /* Init our MAC address */ 1202 csr_write_4(sc, SF_PAR0, *(u_int32_t *)(&IFP2ENADDR(sc->sf_ifp)[0])); 1203 csr_write_4(sc, SF_PAR1, *(u_int32_t *)(&IFP2ENADDR(sc->sf_ifp)[4])); 1204 sf_setperf(sc, 0, (caddr_t)&IFP2ENADDR(sc->sf_ifp)); 1205 1206 if (sf_init_rx_ring(sc) == ENOBUFS) { 1207 if_printf(sc->sf_ifp, 1208 "initialization failed: no memory for rx buffers\n"); 1209 SF_UNLOCK(sc); 1210 return; 1211 } 1212 1213 sf_init_tx_ring(sc); 1214 1215 csr_write_4(sc, SF_RXFILT, SF_PERFMODE_NORMAL|SF_HASHMODE_WITHVLAN); 1216 1217 /* If we want promiscuous mode, set the allframes bit. */ 1218 if (ifp->if_flags & IFF_PROMISC) { 1219 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 1220 } else { 1221 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 1222 } 1223 1224 if (ifp->if_flags & IFF_BROADCAST) { 1225 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_BROAD); 1226 } else { 1227 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_BROAD); 1228 } 1229 1230 /* 1231 * Load the multicast filter. 1232 */ 1233 sf_setmulti(sc); 1234 1235 /* Init the completion queue indexes */ 1236 csr_write_4(sc, SF_CQ_CONSIDX, 0); 1237 csr_write_4(sc, SF_CQ_PRODIDX, 0); 1238 1239 /* Init the RX completion queue */ 1240 csr_write_4(sc, SF_RXCQ_CTL_1, 1241 vtophys(sc->sf_ldata->sf_rx_clist) & SF_RXCQ_ADDR); 1242 SF_SETBIT(sc, SF_RXCQ_CTL_1, SF_RXCQTYPE_3); 1243 1244 /* Init RX DMA control. */ 1245 SF_SETBIT(sc, SF_RXDMA_CTL, SF_RXDMA_REPORTBADPKTS); 1246 1247 /* Init the RX buffer descriptor queue. */ 1248 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 1249 vtophys(sc->sf_ldata->sf_rx_dlist_big)); 1250 csr_write_4(sc, SF_RXDQ_CTL_1, (MCLBYTES << 16) | SF_DESCSPACE_16BYTES); 1251 csr_write_4(sc, SF_RXDQ_PTR_Q1, SF_RX_DLIST_CNT - 1); 1252 1253 /* Init the TX completion queue */ 1254 csr_write_4(sc, SF_TXCQ_CTL, 1255 vtophys(sc->sf_ldata->sf_tx_clist) & SF_RXCQ_ADDR); 1256 1257 /* Init the TX buffer descriptor queue. */ 1258 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 1259 vtophys(sc->sf_ldata->sf_tx_dlist)); 1260 SF_SETBIT(sc, SF_TX_FRAMCTL, SF_TXFRMCTL_CPLAFTERTX); 1261 csr_write_4(sc, SF_TXDQ_CTL, 1262 SF_TXBUFDESC_TYPE0|SF_TXMINSPACE_128BYTES|SF_TXSKIPLEN_8BYTES); 1263 SF_SETBIT(sc, SF_TXDQ_CTL, SF_TXDQCTL_NODMACMP); 1264 1265 /* Enable autopadding of short TX frames. */ 1266 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_AUTOPAD); 1267 1268#ifdef DEVICE_POLLING 1269 /* Disable interrupts if we are polling. */ 1270 if (ifp->if_flags & IFF_POLLING) 1271 csr_write_4(sc, SF_IMR, 0x00000000); 1272 else 1273#endif /* DEVICE_POLLING */ 1274 1275 /* Enable interrupts. */ 1276 csr_write_4(sc, SF_IMR, SF_INTRS); 1277 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_INTR_ENB); 1278 1279 /* Enable the RX and TX engines. */ 1280 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_RX_ENB|SF_ETHCTL_RXDMA_ENB); 1281 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_TX_ENB|SF_ETHCTL_TXDMA_ENB); 1282 1283 /*mii_mediachg(mii);*/ 1284 sf_ifmedia_upd(ifp); 1285 1286 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1287 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1288 1289 sc->sf_stat_ch = timeout(sf_stats_update, sc, hz); 1290 1291 SF_UNLOCK(sc); 1292} 1293 1294static int 1295sf_encap(sc, c, m_head) 1296 struct sf_softc *sc; 1297 struct sf_tx_bufdesc_type0 *c; 1298 struct mbuf *m_head; 1299{ 1300 int frag = 0; 1301 struct sf_frag *f = NULL; 1302 struct mbuf *m; 1303 1304 m = m_head; 1305 1306 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1307 if (m->m_len != 0) { 1308 if (frag == SF_MAXFRAGS) 1309 break; 1310 f = &c->sf_frags[frag]; 1311 if (frag == 0) 1312 f->sf_pktlen = m_head->m_pkthdr.len; 1313 f->sf_fraglen = m->m_len; 1314 f->sf_addr = vtophys(mtod(m, vm_offset_t)); 1315 frag++; 1316 } 1317 } 1318 1319 if (m != NULL) { 1320 struct mbuf *m_new = NULL; 1321 1322 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1323 if (m_new == NULL) { 1324 if_printf(sc->sf_ifp, "no memory for tx list\n"); 1325 return(1); 1326 } 1327 1328 if (m_head->m_pkthdr.len > MHLEN) { 1329 MCLGET(m_new, M_DONTWAIT); 1330 if (!(m_new->m_flags & M_EXT)) { 1331 m_freem(m_new); 1332 if_printf(sc->sf_ifp, "no memory for tx list\n"); 1333 return(1); 1334 } 1335 } 1336 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1337 mtod(m_new, caddr_t)); 1338 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1339 m_freem(m_head); 1340 m_head = m_new; 1341 f = &c->sf_frags[0]; 1342 f->sf_fraglen = f->sf_pktlen = m_head->m_pkthdr.len; 1343 f->sf_addr = vtophys(mtod(m_head, caddr_t)); 1344 frag = 1; 1345 } 1346 1347 c->sf_mbuf = m_head; 1348 c->sf_id = SF_TX_BUFDESC_ID; 1349 c->sf_fragcnt = frag; 1350 c->sf_intr = 1; 1351 c->sf_caltcp = 0; 1352 c->sf_crcen = 1; 1353 1354 return(0); 1355} 1356 1357static void 1358sf_start(ifp) 1359 struct ifnet *ifp; 1360{ 1361 struct sf_softc *sc; 1362 struct sf_tx_bufdesc_type0 *cur_tx = NULL; 1363 struct mbuf *m_head = NULL; 1364 int i, txprod; 1365 1366 sc = ifp->if_softc; 1367 SF_LOCK(sc); 1368 1369 if (!sc->sf_link && ifp->if_snd.ifq_len < 10) { 1370 SF_UNLOCK(sc); 1371 return; 1372 } 1373 1374 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) { 1375 SF_UNLOCK(sc); 1376 return; 1377 } 1378 1379 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX); 1380 i = SF_IDX_HI(txprod) >> 4; 1381 1382 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) { 1383 if_printf(ifp, "TX ring full, resetting\n"); 1384 sf_init(sc); 1385 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX); 1386 i = SF_IDX_HI(txprod) >> 4; 1387 } 1388 1389 while(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf == NULL) { 1390 if (sc->sf_tx_cnt >= (SF_TX_DLIST_CNT - 5)) { 1391 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1392 cur_tx = NULL; 1393 break; 1394 } 1395 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1396 if (m_head == NULL) 1397 break; 1398 1399 cur_tx = &sc->sf_ldata->sf_tx_dlist[i]; 1400 if (sf_encap(sc, cur_tx, m_head)) { 1401 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1402 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1403 cur_tx = NULL; 1404 break; 1405 } 1406 1407 /* 1408 * If there's a BPF listener, bounce a copy of this frame 1409 * to him. 1410 */ 1411 BPF_MTAP(ifp, m_head); 1412 1413 SF_INC(i, SF_TX_DLIST_CNT); 1414 sc->sf_tx_cnt++; 1415 /* 1416 * Don't get the TX DMA queue get too full. 1417 */ 1418 if (sc->sf_tx_cnt > 64) 1419 break; 1420 } 1421 1422 if (cur_tx == NULL) { 1423 SF_UNLOCK(sc); 1424 return; 1425 } 1426 1427 /* Transmit */ 1428 csr_write_4(sc, SF_TXDQ_PRODIDX, 1429 (txprod & ~SF_TXDQ_PRODIDX_HIPRIO) | 1430 ((i << 20) & 0xFFFF0000)); 1431 1432 ifp->if_timer = 5; 1433 1434 SF_UNLOCK(sc); 1435} 1436 1437static void 1438sf_stop(sc) 1439 struct sf_softc *sc; 1440{ 1441 int i; 1442 struct ifnet *ifp; 1443 1444 SF_LOCK(sc); 1445 1446 ifp = sc->sf_ifp; 1447 1448 untimeout(sf_stats_update, sc, sc->sf_stat_ch); 1449 1450#ifdef DEVICE_POLLING 1451 ether_poll_deregister(ifp); 1452#endif /* DEVICE_POLLING */ 1453 1454 csr_write_4(sc, SF_GEN_ETH_CTL, 0); 1455 csr_write_4(sc, SF_CQ_CONSIDX, 0); 1456 csr_write_4(sc, SF_CQ_PRODIDX, 0); 1457 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 0); 1458 csr_write_4(sc, SF_RXDQ_CTL_1, 0); 1459 csr_write_4(sc, SF_RXDQ_PTR_Q1, 0); 1460 csr_write_4(sc, SF_TXCQ_CTL, 0); 1461 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 0); 1462 csr_write_4(sc, SF_TXDQ_CTL, 0); 1463 sf_reset(sc); 1464 1465 sc->sf_link = 0; 1466 1467 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 1468 if (sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf != NULL) { 1469 m_freem(sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf); 1470 sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf = NULL; 1471 } 1472 } 1473 1474 for (i = 0; i < SF_TX_DLIST_CNT; i++) { 1475 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) { 1476 m_freem(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf); 1477 sc->sf_ldata->sf_tx_dlist[i].sf_mbuf = NULL; 1478 } 1479 } 1480 1481 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING|IFF_DRV_OACTIVE); 1482 SF_UNLOCK(sc); 1483} 1484 1485/* 1486 * Note: it is important that this function not be interrupted. We 1487 * use a two-stage register access scheme: if we are interrupted in 1488 * between setting the indirect address register and reading from the 1489 * indirect data register, the contents of the address register could 1490 * be changed out from under us. 1491 */ 1492static void 1493sf_stats_update(xsc) 1494 void *xsc; 1495{ 1496 struct sf_softc *sc; 1497 struct ifnet *ifp; 1498 struct mii_data *mii; 1499 struct sf_stats stats; 1500 u_int32_t *ptr; 1501 int i; 1502 1503 sc = xsc; 1504 SF_LOCK(sc); 1505 ifp = sc->sf_ifp; 1506 mii = device_get_softc(sc->sf_miibus); 1507 1508 ptr = (u_int32_t *)&stats; 1509 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++) 1510 ptr[i] = csr_read_4(sc, SF_STATS_BASE + 1511 (i + sizeof(u_int32_t))); 1512 1513 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++) 1514 csr_write_4(sc, SF_STATS_BASE + 1515 (i + sizeof(u_int32_t)), 0); 1516 1517 ifp->if_collisions += stats.sf_tx_single_colls + 1518 stats.sf_tx_multi_colls + stats.sf_tx_excess_colls; 1519 1520 mii_tick(mii); 1521 1522 if (!sc->sf_link && mii->mii_media_status & IFM_ACTIVE && 1523 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1524 sc->sf_link++; 1525 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1526 sf_start(ifp); 1527 } 1528 1529 sc->sf_stat_ch = timeout(sf_stats_update, sc, hz); 1530 1531 SF_UNLOCK(sc); 1532} 1533 1534static void 1535sf_watchdog(ifp) 1536 struct ifnet *ifp; 1537{ 1538 struct sf_softc *sc; 1539 1540 sc = ifp->if_softc; 1541 1542 SF_LOCK(sc); 1543 1544 ifp->if_oerrors++; 1545 if_printf(ifp, "watchdog timeout\n"); 1546 1547 sf_stop(sc); 1548 sf_reset(sc); 1549 sf_init(sc); 1550 1551 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1552 sf_start(ifp); 1553 1554 SF_UNLOCK(sc); 1555} 1556 1557static void 1558sf_shutdown(dev) 1559 device_t dev; 1560{ 1561 struct sf_softc *sc; 1562 1563 sc = device_get_softc(dev); 1564 1565 sf_stop(sc); 1566} 1567