if_sf.c revision 147291
1/*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/sf/if_sf.c 147291 2005-06-11 01:37:46Z brooks $"); 35 36/* 37 * Adaptec AIC-6915 "Starfire" PCI fast ethernet driver for FreeBSD. 38 * Programming manual is available from: 39 * http://download.adaptec.com/pdfs/user_guides/aic6915_pg.pdf. 40 * 41 * Written by Bill Paul <wpaul@ctr.columbia.edu> 42 * Department of Electical Engineering 43 * Columbia University, New York City 44 */ 45/* 46 * The Adaptec AIC-6915 "Starfire" is a 64-bit 10/100 PCI ethernet 47 * controller designed with flexibility and reducing CPU load in mind. 48 * The Starfire offers high and low priority buffer queues, a 49 * producer/consumer index mechanism and several different buffer 50 * queue and completion queue descriptor types. Any one of a number 51 * of different driver designs can be used, depending on system and 52 * OS requirements. This driver makes use of type0 transmit frame 53 * descriptors (since BSD fragments packets across an mbuf chain) 54 * and two RX buffer queues prioritized on size (one queue for small 55 * frames that will fit into a single mbuf, another with full size 56 * mbuf clusters for everything else). The producer/consumer indexes 57 * and completion queues are also used. 58 * 59 * One downside to the Starfire has to do with alignment: buffer 60 * queues must be aligned on 256-byte boundaries, and receive buffers 61 * must be aligned on longword boundaries. The receive buffer alignment 62 * causes problems on the Alpha platform, where the packet payload 63 * should be longword aligned. There is no simple way around this. 64 * 65 * For receive filtering, the Starfire offers 16 perfect filter slots 66 * and a 512-bit hash table. 67 * 68 * The Starfire has no internal transceiver, relying instead on an 69 * external MII-based transceiver. Accessing registers on external 70 * PHYs is done through a special register map rather than with the 71 * usual bitbang MDIO method. 72 * 73 * Acesssing the registers on the Starfire is a little tricky. The 74 * Starfire has a 512K internal register space. When programmed for 75 * PCI memory mapped mode, the entire register space can be accessed 76 * directly. However in I/O space mode, only 256 bytes are directly 77 * mapped into PCI I/O space. The other registers can be accessed 78 * indirectly using the SF_INDIRECTIO_ADDR and SF_INDIRECTIO_DATA 79 * registers inside the 256-byte I/O window. 80 */ 81 82#include <sys/param.h> 83#include <sys/systm.h> 84#include <sys/sockio.h> 85#include <sys/mbuf.h> 86#include <sys/malloc.h> 87#include <sys/kernel.h> 88#include <sys/module.h> 89#include <sys/socket.h> 90 91#include <net/if.h> 92#include <net/if_arp.h> 93#include <net/ethernet.h> 94#include <net/if_dl.h> 95#include <net/if_media.h> 96#include <net/if_types.h> 97 98#include <net/bpf.h> 99 100#include <vm/vm.h> /* for vtophys */ 101#include <vm/pmap.h> /* for vtophys */ 102#include <machine/bus.h> 103#include <machine/resource.h> 104#include <sys/bus.h> 105#include <sys/rman.h> 106 107#include <dev/mii/mii.h> 108#include <dev/mii/miivar.h> 109 110/* "controller miibus0" required. See GENERIC if you get errors here. */ 111#include "miibus_if.h" 112 113#include <dev/pci/pcireg.h> 114#include <dev/pci/pcivar.h> 115 116#define SF_USEIOSPACE 117 118#include <pci/if_sfreg.h> 119 120MODULE_DEPEND(sf, pci, 1, 1, 1); 121MODULE_DEPEND(sf, ether, 1, 1, 1); 122MODULE_DEPEND(sf, miibus, 1, 1, 1); 123 124static struct sf_type sf_devs[] = { 125 { AD_VENDORID, AD_DEVICEID_STARFIRE, 126 "Adaptec AIC-6915 10/100BaseTX" }, 127 { 0, 0, NULL } 128}; 129 130static int sf_probe(device_t); 131static int sf_attach(device_t); 132static int sf_detach(device_t); 133static void sf_intr(void *); 134static void sf_stats_update(void *); 135static void sf_rxeof(struct sf_softc *); 136static void sf_txeof(struct sf_softc *); 137static int sf_encap(struct sf_softc *, struct sf_tx_bufdesc_type0 *, 138 struct mbuf *); 139static void sf_start(struct ifnet *); 140static int sf_ioctl(struct ifnet *, u_long, caddr_t); 141static void sf_init(void *); 142static void sf_stop(struct sf_softc *); 143static void sf_watchdog(struct ifnet *); 144static void sf_shutdown(device_t); 145static int sf_ifmedia_upd(struct ifnet *); 146static void sf_ifmedia_sts(struct ifnet *, struct ifmediareq *); 147static void sf_reset(struct sf_softc *); 148static int sf_init_rx_ring(struct sf_softc *); 149static void sf_init_tx_ring(struct sf_softc *); 150static int sf_newbuf(struct sf_softc *, struct sf_rx_bufdesc_type0 *, 151 struct mbuf *); 152static void sf_setmulti(struct sf_softc *); 153static int sf_setperf(struct sf_softc *, int, caddr_t); 154static int sf_sethash(struct sf_softc *, caddr_t, int); 155#ifdef notdef 156static int sf_setvlan(struct sf_softc *, int, u_int32_t); 157#endif 158 159static u_int8_t sf_read_eeprom(struct sf_softc *, int); 160 161static int sf_miibus_readreg(device_t, int, int); 162static int sf_miibus_writereg(device_t, int, int, int); 163static void sf_miibus_statchg(device_t); 164#ifdef DEVICE_POLLING 165static void sf_poll(struct ifnet *ifp, enum poll_cmd cmd, 166 int count); 167static void sf_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, 168 int count); 169#endif /* DEVICE_POLLING */ 170 171static u_int32_t csr_read_4(struct sf_softc *, int); 172static void csr_write_4(struct sf_softc *, int, u_int32_t); 173static void sf_txthresh_adjust(struct sf_softc *); 174 175#ifdef SF_USEIOSPACE 176#define SF_RES SYS_RES_IOPORT 177#define SF_RID SF_PCI_LOIO 178#else 179#define SF_RES SYS_RES_MEMORY 180#define SF_RID SF_PCI_LOMEM 181#endif 182 183static device_method_t sf_methods[] = { 184 /* Device interface */ 185 DEVMETHOD(device_probe, sf_probe), 186 DEVMETHOD(device_attach, sf_attach), 187 DEVMETHOD(device_detach, sf_detach), 188 DEVMETHOD(device_shutdown, sf_shutdown), 189 190 /* bus interface */ 191 DEVMETHOD(bus_print_child, bus_generic_print_child), 192 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 193 194 /* MII interface */ 195 DEVMETHOD(miibus_readreg, sf_miibus_readreg), 196 DEVMETHOD(miibus_writereg, sf_miibus_writereg), 197 DEVMETHOD(miibus_statchg, sf_miibus_statchg), 198 199 { 0, 0 } 200}; 201 202static driver_t sf_driver = { 203 "sf", 204 sf_methods, 205 sizeof(struct sf_softc), 206}; 207 208static devclass_t sf_devclass; 209 210DRIVER_MODULE(sf, pci, sf_driver, sf_devclass, 0, 0); 211DRIVER_MODULE(miibus, sf, miibus_driver, miibus_devclass, 0, 0); 212 213#define SF_SETBIT(sc, reg, x) \ 214 csr_write_4(sc, reg, csr_read_4(sc, reg) | (x)) 215 216#define SF_CLRBIT(sc, reg, x) \ 217 csr_write_4(sc, reg, csr_read_4(sc, reg) & ~(x)) 218 219static u_int32_t 220csr_read_4(sc, reg) 221 struct sf_softc *sc; 222 int reg; 223{ 224 u_int32_t val; 225 226#ifdef SF_USEIOSPACE 227 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); 228 val = CSR_READ_4(sc, SF_INDIRECTIO_DATA); 229#else 230 val = CSR_READ_4(sc, (reg + SF_RMAP_INTREG_BASE)); 231#endif 232 233 return(val); 234} 235 236static u_int8_t 237sf_read_eeprom(sc, reg) 238 struct sf_softc *sc; 239 int reg; 240{ 241 u_int8_t val; 242 243 val = (csr_read_4(sc, SF_EEADDR_BASE + 244 (reg & 0xFFFFFFFC)) >> (8 * (reg & 3))) & 0xFF; 245 246 return(val); 247} 248 249static void 250csr_write_4(sc, reg, val) 251 struct sf_softc *sc; 252 int reg; 253 u_int32_t val; 254{ 255#ifdef SF_USEIOSPACE 256 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); 257 CSR_WRITE_4(sc, SF_INDIRECTIO_DATA, val); 258#else 259 CSR_WRITE_4(sc, (reg + SF_RMAP_INTREG_BASE), val); 260#endif 261} 262 263/* 264 * Copy the address 'mac' into the perfect RX filter entry at 265 * offset 'idx.' The perfect filter only has 16 entries so do 266 * some sanity tests. 267 */ 268static int 269sf_setperf(sc, idx, mac) 270 struct sf_softc *sc; 271 int idx; 272 caddr_t mac; 273{ 274 u_int16_t *p; 275 276 if (idx < 0 || idx > SF_RXFILT_PERFECT_CNT) 277 return(EINVAL); 278 279 if (mac == NULL) 280 return(EINVAL); 281 282 p = (u_int16_t *)mac; 283 284 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 285 (idx * SF_RXFILT_PERFECT_SKIP), htons(p[2])); 286 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 287 (idx * SF_RXFILT_PERFECT_SKIP) + 4, htons(p[1])); 288 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 289 (idx * SF_RXFILT_PERFECT_SKIP) + 8, htons(p[0])); 290 291 return(0); 292} 293 294/* 295 * Set the bit in the 512-bit hash table that corresponds to the 296 * specified mac address 'mac.' If 'prio' is nonzero, update the 297 * priority hash table instead of the filter hash table. 298 */ 299static int 300sf_sethash(sc, mac, prio) 301 struct sf_softc *sc; 302 caddr_t mac; 303 int prio; 304{ 305 u_int32_t h; 306 307 if (mac == NULL) 308 return(EINVAL); 309 310 h = ether_crc32_be(mac, ETHER_ADDR_LEN) >> 23; 311 312 if (prio) { 313 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_PRIOOFF + 314 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); 315 } else { 316 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_ADDROFF + 317 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); 318 } 319 320 return(0); 321} 322 323#ifdef notdef 324/* 325 * Set a VLAN tag in the receive filter. 326 */ 327static int 328sf_setvlan(sc, idx, vlan) 329 struct sf_softc *sc; 330 int idx; 331 u_int32_t vlan; 332{ 333 if (idx < 0 || idx >> SF_RXFILT_HASH_CNT) 334 return(EINVAL); 335 336 csr_write_4(sc, SF_RXFILT_HASH_BASE + 337 (idx * SF_RXFILT_HASH_SKIP) + SF_RXFILT_HASH_VLANOFF, vlan); 338 339 return(0); 340} 341#endif 342 343static int 344sf_miibus_readreg(dev, phy, reg) 345 device_t dev; 346 int phy, reg; 347{ 348 struct sf_softc *sc; 349 int i; 350 u_int32_t val = 0; 351 352 sc = device_get_softc(dev); 353 354 for (i = 0; i < SF_TIMEOUT; i++) { 355 val = csr_read_4(sc, SF_PHY_REG(phy, reg)); 356 if (val & SF_MII_DATAVALID) 357 break; 358 } 359 360 if (i == SF_TIMEOUT) 361 return(0); 362 363 if ((val & 0x0000FFFF) == 0xFFFF) 364 return(0); 365 366 return(val & 0x0000FFFF); 367} 368 369static int 370sf_miibus_writereg(dev, phy, reg, val) 371 device_t dev; 372 int phy, reg, val; 373{ 374 struct sf_softc *sc; 375 int i; 376 int busy; 377 378 sc = device_get_softc(dev); 379 380 csr_write_4(sc, SF_PHY_REG(phy, reg), val); 381 382 for (i = 0; i < SF_TIMEOUT; i++) { 383 busy = csr_read_4(sc, SF_PHY_REG(phy, reg)); 384 if (!(busy & SF_MII_BUSY)) 385 break; 386 } 387 388 return(0); 389} 390 391static void 392sf_miibus_statchg(dev) 393 device_t dev; 394{ 395 struct sf_softc *sc; 396 struct mii_data *mii; 397 398 sc = device_get_softc(dev); 399 mii = device_get_softc(sc->sf_miibus); 400 401 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 402 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 403 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_FDX); 404 } else { 405 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 406 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_HDX); 407 } 408} 409 410static void 411sf_setmulti(sc) 412 struct sf_softc *sc; 413{ 414 struct ifnet *ifp; 415 int i; 416 struct ifmultiaddr *ifma; 417 u_int8_t dummy[] = { 0, 0, 0, 0, 0, 0 }; 418 419 ifp = sc->sf_ifp; 420 421 /* First zot all the existing filters. */ 422 for (i = 1; i < SF_RXFILT_PERFECT_CNT; i++) 423 sf_setperf(sc, i, (char *)&dummy); 424 for (i = SF_RXFILT_HASH_BASE; 425 i < (SF_RXFILT_HASH_MAX + 1); i += 4) 426 csr_write_4(sc, i, 0); 427 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI); 428 429 /* Now program new ones. */ 430 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 431 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI); 432 } else { 433 i = 1; 434 TAILQ_FOREACH_REVERSE(ifma, &ifp->if_multiaddrs, ifmultihead, ifma_link) { 435 if (ifma->ifma_addr->sa_family != AF_LINK) 436 continue; 437 /* 438 * Program the first 15 multicast groups 439 * into the perfect filter. For all others, 440 * use the hash table. 441 */ 442 if (i < SF_RXFILT_PERFECT_CNT) { 443 sf_setperf(sc, i, 444 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 445 i++; 446 continue; 447 } 448 449 sf_sethash(sc, 450 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 0); 451 } 452 } 453} 454 455/* 456 * Set media options. 457 */ 458static int 459sf_ifmedia_upd(ifp) 460 struct ifnet *ifp; 461{ 462 struct sf_softc *sc; 463 struct mii_data *mii; 464 465 sc = ifp->if_softc; 466 mii = device_get_softc(sc->sf_miibus); 467 sc->sf_link = 0; 468 if (mii->mii_instance) { 469 struct mii_softc *miisc; 470 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 471 mii_phy_reset(miisc); 472 } 473 mii_mediachg(mii); 474 475 return(0); 476} 477 478/* 479 * Report current media status. 480 */ 481static void 482sf_ifmedia_sts(ifp, ifmr) 483 struct ifnet *ifp; 484 struct ifmediareq *ifmr; 485{ 486 struct sf_softc *sc; 487 struct mii_data *mii; 488 489 sc = ifp->if_softc; 490 mii = device_get_softc(sc->sf_miibus); 491 492 mii_pollstat(mii); 493 ifmr->ifm_active = mii->mii_media_active; 494 ifmr->ifm_status = mii->mii_media_status; 495} 496 497static int 498sf_ioctl(ifp, command, data) 499 struct ifnet *ifp; 500 u_long command; 501 caddr_t data; 502{ 503 struct sf_softc *sc = ifp->if_softc; 504 struct ifreq *ifr = (struct ifreq *) data; 505 struct mii_data *mii; 506 int error = 0; 507 508 SF_LOCK(sc); 509 510 switch(command) { 511 case SIOCSIFFLAGS: 512 if (ifp->if_flags & IFF_UP) { 513 if (ifp->if_flags & IFF_RUNNING && 514 ifp->if_flags & IFF_PROMISC && 515 !(sc->sf_if_flags & IFF_PROMISC)) { 516 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 517 } else if (ifp->if_flags & IFF_RUNNING && 518 !(ifp->if_flags & IFF_PROMISC) && 519 sc->sf_if_flags & IFF_PROMISC) { 520 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 521 } else if (!(ifp->if_flags & IFF_RUNNING)) 522 sf_init(sc); 523 } else { 524 if (ifp->if_flags & IFF_RUNNING) 525 sf_stop(sc); 526 } 527 sc->sf_if_flags = ifp->if_flags; 528 error = 0; 529 break; 530 case SIOCADDMULTI: 531 case SIOCDELMULTI: 532 sf_setmulti(sc); 533 error = 0; 534 break; 535 case SIOCGIFMEDIA: 536 case SIOCSIFMEDIA: 537 mii = device_get_softc(sc->sf_miibus); 538 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 539 break; 540 case SIOCSIFCAP: 541 ifp->if_capenable &= ~IFCAP_POLLING; 542 ifp->if_capenable |= ifr->ifr_reqcap & IFCAP_POLLING; 543 break; 544 default: 545 error = ether_ioctl(ifp, command, data); 546 break; 547 } 548 549 SF_UNLOCK(sc); 550 551 return(error); 552} 553 554static void 555sf_reset(sc) 556 struct sf_softc *sc; 557{ 558 register int i; 559 560 csr_write_4(sc, SF_GEN_ETH_CTL, 0); 561 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 562 DELAY(1000); 563 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 564 565 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_RESET); 566 567 for (i = 0; i < SF_TIMEOUT; i++) { 568 DELAY(10); 569 if (!(csr_read_4(sc, SF_PCI_DEVCFG) & SF_PCIDEVCFG_RESET)) 570 break; 571 } 572 573 if (i == SF_TIMEOUT) 574 printf("sf%d: reset never completed!\n", sc->sf_unit); 575 576 /* Wait a little while for the chip to get its brains in order. */ 577 DELAY(1000); 578} 579 580/* 581 * Probe for an Adaptec AIC-6915 chip. Check the PCI vendor and device 582 * IDs against our list and return a device name if we find a match. 583 * We also check the subsystem ID so that we can identify exactly which 584 * NIC has been found, if possible. 585 */ 586static int 587sf_probe(dev) 588 device_t dev; 589{ 590 struct sf_type *t; 591 592 t = sf_devs; 593 594 while(t->sf_name != NULL) { 595 if ((pci_get_vendor(dev) == t->sf_vid) && 596 (pci_get_device(dev) == t->sf_did)) { 597 switch((pci_read_config(dev, 598 SF_PCI_SUBVEN_ID, 4) >> 16) & 0xFFFF) { 599 case AD_SUBSYSID_62011_REV0: 600 case AD_SUBSYSID_62011_REV1: 601 device_set_desc(dev, 602 "Adaptec ANA-62011 10/100BaseTX"); 603 return (BUS_PROBE_DEFAULT); 604 case AD_SUBSYSID_62022: 605 device_set_desc(dev, 606 "Adaptec ANA-62022 10/100BaseTX"); 607 return (BUS_PROBE_DEFAULT); 608 case AD_SUBSYSID_62044_REV0: 609 case AD_SUBSYSID_62044_REV1: 610 device_set_desc(dev, 611 "Adaptec ANA-62044 10/100BaseTX"); 612 return (BUS_PROBE_DEFAULT); 613 case AD_SUBSYSID_62020: 614 device_set_desc(dev, 615 "Adaptec ANA-62020 10/100BaseFX"); 616 return (BUS_PROBE_DEFAULT); 617 case AD_SUBSYSID_69011: 618 device_set_desc(dev, 619 "Adaptec ANA-69011 10/100BaseTX"); 620 return (BUS_PROBE_DEFAULT); 621 default: 622 device_set_desc(dev, t->sf_name); 623 return (BUS_PROBE_DEFAULT); 624 break; 625 } 626 } 627 t++; 628 } 629 630 return(ENXIO); 631} 632 633/* 634 * Attach the interface. Allocate softc structures, do ifmedia 635 * setup and ethernet/BPF attach. 636 */ 637static int 638sf_attach(dev) 639 device_t dev; 640{ 641 int i; 642 struct sf_softc *sc; 643 struct ifnet *ifp; 644 int unit, rid, error = 0; 645 u_char eaddr[6]; 646 647 sc = device_get_softc(dev); 648 unit = device_get_unit(dev); 649 650 mtx_init(&sc->sf_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 651 MTX_DEF | MTX_RECURSE); 652 /* 653 * Map control/status registers. 654 */ 655 pci_enable_busmaster(dev); 656 657 rid = SF_RID; 658 sc->sf_res = bus_alloc_resource_any(dev, SF_RES, &rid, RF_ACTIVE); 659 660 if (sc->sf_res == NULL) { 661 printf ("sf%d: couldn't map ports\n", unit); 662 error = ENXIO; 663 goto fail; 664 } 665 666 sc->sf_btag = rman_get_bustag(sc->sf_res); 667 sc->sf_bhandle = rman_get_bushandle(sc->sf_res); 668 669 /* Allocate interrupt */ 670 rid = 0; 671 sc->sf_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 672 RF_SHAREABLE | RF_ACTIVE); 673 674 if (sc->sf_irq == NULL) { 675 printf("sf%d: couldn't map interrupt\n", unit); 676 error = ENXIO; 677 goto fail; 678 } 679 680 callout_handle_init(&sc->sf_stat_ch); 681 /* Reset the adapter. */ 682 sf_reset(sc); 683 684 /* 685 * Get station address from the EEPROM. 686 */ 687 for (i = 0; i < ETHER_ADDR_LEN; i++) 688 eaddr[i] = 689 sf_read_eeprom(sc, SF_EE_NODEADDR + ETHER_ADDR_LEN - i); 690 691 sc->sf_unit = unit; 692 693 /* Allocate the descriptor queues. */ 694 sc->sf_ldata = contigmalloc(sizeof(struct sf_list_data), M_DEVBUF, 695 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 696 697 if (sc->sf_ldata == NULL) { 698 printf("sf%d: no memory for list buffers!\n", unit); 699 error = ENXIO; 700 goto fail; 701 } 702 703 bzero(sc->sf_ldata, sizeof(struct sf_list_data)); 704 705 ifp = sc->sf_ifp = if_alloc(IFT_ETHER); 706 if (ifp == NULL) { 707 printf("sf%d: can not if_alloc()\n", sc->sf_unit); 708 error = ENOSPC; 709 goto fail; 710 } 711 712 /* Do MII setup. */ 713 if (mii_phy_probe(dev, &sc->sf_miibus, 714 sf_ifmedia_upd, sf_ifmedia_sts)) { 715 printf("sf%d: MII without any phy!\n", sc->sf_unit); 716 error = ENXIO; 717 goto fail; 718 } 719 720 ifp->if_softc = sc; 721 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 722 ifp->if_mtu = ETHERMTU; 723 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST | 724 IFF_NEEDSGIANT; 725 ifp->if_ioctl = sf_ioctl; 726 ifp->if_start = sf_start; 727 ifp->if_watchdog = sf_watchdog; 728 ifp->if_init = sf_init; 729 ifp->if_baudrate = 10000000; 730 IFQ_SET_MAXLEN(&ifp->if_snd, SF_TX_DLIST_CNT - 1); 731 ifp->if_snd.ifq_drv_maxlen = SF_TX_DLIST_CNT - 1; 732 IFQ_SET_READY(&ifp->if_snd); 733#ifdef DEVICE_POLLING 734 ifp->if_capabilities |= IFCAP_POLLING; 735#endif /* DEVICE_POLLING */ 736 ifp->if_capenable = ifp->if_capabilities; 737 738 /* 739 * Call MI attach routine. 740 */ 741 ether_ifattach(ifp, eaddr); 742 743 /* Hook interrupt last to avoid having to lock softc */ 744 error = bus_setup_intr(dev, sc->sf_irq, INTR_TYPE_NET, 745 sf_intr, sc, &sc->sf_intrhand); 746 747 if (error) { 748 printf("sf%d: couldn't set up irq\n", unit); 749 ether_ifdetach(ifp); 750 if_free(ifp); 751 goto fail; 752 } 753 754fail: 755 if (error) 756 sf_detach(dev); 757 758 return(error); 759} 760 761/* 762 * Shutdown hardware and free up resources. This can be called any 763 * time after the mutex has been initialized. It is called in both 764 * the error case in attach and the normal detach case so it needs 765 * to be careful about only freeing resources that have actually been 766 * allocated. 767 */ 768static int 769sf_detach(dev) 770 device_t dev; 771{ 772 struct sf_softc *sc; 773 struct ifnet *ifp; 774 775 sc = device_get_softc(dev); 776 KASSERT(mtx_initialized(&sc->sf_mtx), ("sf mutex not initialized")); 777 SF_LOCK(sc); 778 ifp = sc->sf_ifp; 779 780 /* These should only be active if attach succeeded */ 781 if (device_is_attached(dev)) { 782 sf_stop(sc); 783 ether_ifdetach(ifp); 784 if_free(ifp); 785 } 786 if (sc->sf_miibus) 787 device_delete_child(dev, sc->sf_miibus); 788 bus_generic_detach(dev); 789 790 if (sc->sf_intrhand) 791 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand); 792 if (sc->sf_irq) 793 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq); 794 if (sc->sf_res) 795 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 796 797 if (sc->sf_ldata) 798 contigfree(sc->sf_ldata, sizeof(struct sf_list_data), M_DEVBUF); 799 800 SF_UNLOCK(sc); 801 mtx_destroy(&sc->sf_mtx); 802 803 return(0); 804} 805 806static int 807sf_init_rx_ring(sc) 808 struct sf_softc *sc; 809{ 810 struct sf_list_data *ld; 811 int i; 812 813 ld = sc->sf_ldata; 814 815 bzero((char *)ld->sf_rx_dlist_big, 816 sizeof(struct sf_rx_bufdesc_type0) * SF_RX_DLIST_CNT); 817 bzero((char *)ld->sf_rx_clist, 818 sizeof(struct sf_rx_cmpdesc_type3) * SF_RX_CLIST_CNT); 819 820 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 821 if (sf_newbuf(sc, &ld->sf_rx_dlist_big[i], NULL) == ENOBUFS) 822 return(ENOBUFS); 823 } 824 825 return(0); 826} 827 828static void 829sf_init_tx_ring(sc) 830 struct sf_softc *sc; 831{ 832 struct sf_list_data *ld; 833 int i; 834 835 ld = sc->sf_ldata; 836 837 bzero((char *)ld->sf_tx_dlist, 838 sizeof(struct sf_tx_bufdesc_type0) * SF_TX_DLIST_CNT); 839 bzero((char *)ld->sf_tx_clist, 840 sizeof(struct sf_tx_cmpdesc_type0) * SF_TX_CLIST_CNT); 841 842 for (i = 0; i < SF_TX_DLIST_CNT; i++) 843 ld->sf_tx_dlist[i].sf_id = SF_TX_BUFDESC_ID; 844 for (i = 0; i < SF_TX_CLIST_CNT; i++) 845 ld->sf_tx_clist[i].sf_type = SF_TXCMPTYPE_TX; 846 847 ld->sf_tx_dlist[SF_TX_DLIST_CNT - 1].sf_end = 1; 848 sc->sf_tx_cnt = 0; 849} 850 851static int 852sf_newbuf(sc, c, m) 853 struct sf_softc *sc; 854 struct sf_rx_bufdesc_type0 *c; 855 struct mbuf *m; 856{ 857 struct mbuf *m_new = NULL; 858 859 if (m == NULL) { 860 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 861 if (m_new == NULL) 862 return(ENOBUFS); 863 864 MCLGET(m_new, M_DONTWAIT); 865 if (!(m_new->m_flags & M_EXT)) { 866 m_freem(m_new); 867 return(ENOBUFS); 868 } 869 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 870 } else { 871 m_new = m; 872 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 873 m_new->m_data = m_new->m_ext.ext_buf; 874 } 875 876 m_adj(m_new, sizeof(u_int64_t)); 877 878 c->sf_mbuf = m_new; 879 c->sf_addrlo = SF_RX_HOSTADDR(vtophys(mtod(m_new, caddr_t))); 880 c->sf_valid = 1; 881 882 return(0); 883} 884 885/* 886 * The starfire is programmed to use 'normal' mode for packet reception, 887 * which means we use the consumer/producer model for both the buffer 888 * descriptor queue and the completion descriptor queue. The only problem 889 * with this is that it involves a lot of register accesses: we have to 890 * read the RX completion consumer and producer indexes and the RX buffer 891 * producer index, plus the RX completion consumer and RX buffer producer 892 * indexes have to be updated. It would have been easier if Adaptec had 893 * put each index in a separate register, especially given that the damn 894 * NIC has a 512K register space. 895 * 896 * In spite of all the lovely features that Adaptec crammed into the 6915, 897 * it is marred by one truly stupid design flaw, which is that receive 898 * buffer addresses must be aligned on a longword boundary. This forces 899 * the packet payload to be unaligned, which is suboptimal on the x86 and 900 * completely unuseable on the Alpha. Our only recourse is to copy received 901 * packets into properly aligned buffers before handing them off. 902 */ 903 904static void 905sf_rxeof(sc) 906 struct sf_softc *sc; 907{ 908 struct mbuf *m; 909 struct ifnet *ifp; 910 struct sf_rx_bufdesc_type0 *desc; 911 struct sf_rx_cmpdesc_type3 *cur_rx; 912 u_int32_t rxcons, rxprod; 913 int cmpprodidx, cmpconsidx, bufprodidx; 914 915 SF_LOCK_ASSERT(sc); 916 917 ifp = sc->sf_ifp; 918 919 rxcons = csr_read_4(sc, SF_CQ_CONSIDX); 920 rxprod = csr_read_4(sc, SF_RXDQ_PTR_Q1); 921 cmpprodidx = SF_IDX_LO(csr_read_4(sc, SF_CQ_PRODIDX)); 922 cmpconsidx = SF_IDX_LO(rxcons); 923 bufprodidx = SF_IDX_LO(rxprod); 924 925 while (cmpconsidx != cmpprodidx) { 926 struct mbuf *m0; 927 928#ifdef DEVICE_POLLING 929 if (ifp->if_flags & IFF_POLLING) { 930 if (sc->rxcycles <= 0) 931 break; 932 sc->rxcycles--; 933 } 934#endif /* DEVICE_POLLING */ 935 936 cur_rx = &sc->sf_ldata->sf_rx_clist[cmpconsidx]; 937 desc = &sc->sf_ldata->sf_rx_dlist_big[cur_rx->sf_endidx]; 938 m = desc->sf_mbuf; 939 SF_INC(cmpconsidx, SF_RX_CLIST_CNT); 940 SF_INC(bufprodidx, SF_RX_DLIST_CNT); 941 942 if (!(cur_rx->sf_status1 & SF_RXSTAT1_OK)) { 943 ifp->if_ierrors++; 944 sf_newbuf(sc, desc, m); 945 continue; 946 } 947 948 m0 = m_devget(mtod(m, char *), cur_rx->sf_len, ETHER_ALIGN, 949 ifp, NULL); 950 sf_newbuf(sc, desc, m); 951 if (m0 == NULL) { 952 ifp->if_ierrors++; 953 continue; 954 } 955 m = m0; 956 957 ifp->if_ipackets++; 958 SF_UNLOCK(sc); 959 (*ifp->if_input)(ifp, m); 960 SF_LOCK(sc); 961 } 962 963 csr_write_4(sc, SF_CQ_CONSIDX, 964 (rxcons & ~SF_CQ_CONSIDX_RXQ1) | cmpconsidx); 965 csr_write_4(sc, SF_RXDQ_PTR_Q1, 966 (rxprod & ~SF_RXDQ_PRODIDX) | bufprodidx); 967} 968 969/* 970 * Read the transmit status from the completion queue and release 971 * mbufs. Note that the buffer descriptor index in the completion 972 * descriptor is an offset from the start of the transmit buffer 973 * descriptor list in bytes. This is important because the manual 974 * gives the impression that it should match the producer/consumer 975 * index, which is the offset in 8 byte blocks. 976 */ 977static void 978sf_txeof(sc) 979 struct sf_softc *sc; 980{ 981 int txcons, cmpprodidx, cmpconsidx; 982 struct sf_tx_cmpdesc_type1 *cur_cmp; 983 struct sf_tx_bufdesc_type0 *cur_tx; 984 struct ifnet *ifp; 985 986 ifp = sc->sf_ifp; 987 988 txcons = csr_read_4(sc, SF_CQ_CONSIDX); 989 cmpprodidx = SF_IDX_HI(csr_read_4(sc, SF_CQ_PRODIDX)); 990 cmpconsidx = SF_IDX_HI(txcons); 991 992 while (cmpconsidx != cmpprodidx) { 993 cur_cmp = &sc->sf_ldata->sf_tx_clist[cmpconsidx]; 994 cur_tx = &sc->sf_ldata->sf_tx_dlist[cur_cmp->sf_index >> 7]; 995 996 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_OK) 997 ifp->if_opackets++; 998 else { 999 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_UNDERRUN) 1000 sf_txthresh_adjust(sc); 1001 ifp->if_oerrors++; 1002 } 1003 1004 sc->sf_tx_cnt--; 1005 if (cur_tx->sf_mbuf != NULL) { 1006 m_freem(cur_tx->sf_mbuf); 1007 cur_tx->sf_mbuf = NULL; 1008 } else 1009 break; 1010 SF_INC(cmpconsidx, SF_TX_CLIST_CNT); 1011 } 1012 1013 ifp->if_timer = 0; 1014 ifp->if_flags &= ~IFF_OACTIVE; 1015 1016 csr_write_4(sc, SF_CQ_CONSIDX, 1017 (txcons & ~SF_CQ_CONSIDX_TXQ) | 1018 ((cmpconsidx << 16) & 0xFFFF0000)); 1019} 1020 1021static void 1022sf_txthresh_adjust(sc) 1023 struct sf_softc *sc; 1024{ 1025 u_int32_t txfctl; 1026 u_int8_t txthresh; 1027 1028 txfctl = csr_read_4(sc, SF_TX_FRAMCTL); 1029 txthresh = txfctl & SF_TXFRMCTL_TXTHRESH; 1030 if (txthresh < 0xFF) { 1031 txthresh++; 1032 txfctl &= ~SF_TXFRMCTL_TXTHRESH; 1033 txfctl |= txthresh; 1034#ifdef DIAGNOSTIC 1035 printf("sf%d: tx underrun, increasing " 1036 "tx threshold to %d bytes\n", 1037 sc->sf_unit, txthresh * 4); 1038#endif 1039 csr_write_4(sc, SF_TX_FRAMCTL, txfctl); 1040 } 1041} 1042 1043#ifdef DEVICE_POLLING 1044static void 1045sf_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1046{ 1047 struct sf_softc *sc = ifp->if_softc; 1048 1049 SF_LOCK(sc); 1050 sf_poll_locked(ifp, cmd, count); 1051 SF_UNLOCK(sc); 1052} 1053 1054static void 1055sf_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 1056{ 1057 struct sf_softc *sc = ifp->if_softc; 1058 1059 SF_LOCK_ASSERT(sc); 1060 1061 if (!(ifp->if_capenable & IFCAP_POLLING)) { 1062 ether_poll_deregister(ifp); 1063 cmd = POLL_DEREGISTER; 1064 } 1065 1066 if (cmd == POLL_DEREGISTER) { 1067 /* Final call, enable interrupts. */ 1068 csr_write_4(sc, SF_IMR, SF_INTRS); 1069 return; 1070 } 1071 1072 sc->rxcycles = count; 1073 sf_rxeof(sc); 1074 sf_txeof(sc); 1075 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1076 sf_start(ifp); 1077 1078 if (cmd == POLL_AND_CHECK_STATUS) { 1079 u_int32_t status; 1080 1081 status = csr_read_4(sc, SF_ISR); 1082 if (status) 1083 csr_write_4(sc, SF_ISR, status); 1084 1085 if (status & SF_ISR_TX_LOFIFO) 1086 sf_txthresh_adjust(sc); 1087 1088 if (status & SF_ISR_ABNORMALINTR) { 1089 if (status & SF_ISR_STATSOFLOW) { 1090 untimeout(sf_stats_update, sc, 1091 sc->sf_stat_ch); 1092 sf_stats_update(sc); 1093 } else 1094 sf_init(sc); 1095 } 1096 } 1097} 1098#endif /* DEVICE_POLLING */ 1099 1100static void 1101sf_intr(arg) 1102 void *arg; 1103{ 1104 struct sf_softc *sc; 1105 struct ifnet *ifp; 1106 u_int32_t status; 1107 1108 sc = arg; 1109 SF_LOCK(sc); 1110 1111 ifp = sc->sf_ifp; 1112 1113#ifdef DEVICE_POLLING 1114 if (ifp->if_flags & IFF_POLLING) 1115 goto done_locked; 1116 1117 if ((ifp->if_capenable & IFCAP_POLLING) && 1118 ether_poll_register(sf_poll, ifp)) { 1119 /* OK, disable interrupts. */ 1120 csr_write_4(sc, SF_IMR, 0x00000000); 1121 sf_poll_locked(ifp, 0, 1); 1122 goto done_locked; 1123 } 1124#endif /* DEVICE_POLLING */ 1125 1126 if (!(csr_read_4(sc, SF_ISR_SHADOW) & SF_ISR_PCIINT_ASSERTED)) { 1127 SF_UNLOCK(sc); 1128 return; 1129 } 1130 1131 /* Disable interrupts. */ 1132 csr_write_4(sc, SF_IMR, 0x00000000); 1133 1134 for (;;) { 1135 status = csr_read_4(sc, SF_ISR); 1136 if (status) 1137 csr_write_4(sc, SF_ISR, status); 1138 1139 if (!(status & SF_INTRS)) 1140 break; 1141 1142 if (status & SF_ISR_RXDQ1_DMADONE) 1143 sf_rxeof(sc); 1144 1145 if (status & SF_ISR_TX_TXDONE || 1146 status & SF_ISR_TX_DMADONE || 1147 status & SF_ISR_TX_QUEUEDONE) 1148 sf_txeof(sc); 1149 1150 if (status & SF_ISR_TX_LOFIFO) 1151 sf_txthresh_adjust(sc); 1152 1153 if (status & SF_ISR_ABNORMALINTR) { 1154 if (status & SF_ISR_STATSOFLOW) { 1155 untimeout(sf_stats_update, sc, 1156 sc->sf_stat_ch); 1157 sf_stats_update(sc); 1158 } else 1159 sf_init(sc); 1160 } 1161 } 1162 1163 /* Re-enable interrupts. */ 1164 csr_write_4(sc, SF_IMR, SF_INTRS); 1165 1166 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1167 sf_start(ifp); 1168 1169#ifdef DEVICE_POLLING 1170done_locked: 1171#endif /* DEVICE_POLLING */ 1172 SF_UNLOCK(sc); 1173} 1174 1175static void 1176sf_init(xsc) 1177 void *xsc; 1178{ 1179 struct sf_softc *sc; 1180 struct ifnet *ifp; 1181 struct mii_data *mii; 1182 int i; 1183 1184 sc = xsc; 1185 SF_LOCK(sc); 1186 ifp = sc->sf_ifp; 1187 mii = device_get_softc(sc->sf_miibus); 1188 1189 sf_stop(sc); 1190 sf_reset(sc); 1191 1192 /* Init all the receive filter registers */ 1193 for (i = SF_RXFILT_PERFECT_BASE; 1194 i < (SF_RXFILT_HASH_MAX + 1); i += 4) 1195 csr_write_4(sc, i, 0); 1196 1197 /* Empty stats counter registers. */ 1198 for (i = 0; i < sizeof(struct sf_stats)/sizeof(u_int32_t); i++) 1199 csr_write_4(sc, SF_STATS_BASE + 1200 (i + sizeof(u_int32_t)), 0); 1201 1202 /* Init our MAC address */ 1203 csr_write_4(sc, SF_PAR0, *(u_int32_t *)(&IFP2ENADDR(sc->sf_ifp)[0])); 1204 csr_write_4(sc, SF_PAR1, *(u_int32_t *)(&IFP2ENADDR(sc->sf_ifp)[4])); 1205 sf_setperf(sc, 0, (caddr_t)&IFP2ENADDR(sc->sf_ifp)); 1206 1207 if (sf_init_rx_ring(sc) == ENOBUFS) { 1208 printf("sf%d: initialization failed: no " 1209 "memory for rx buffers\n", sc->sf_unit); 1210 SF_UNLOCK(sc); 1211 return; 1212 } 1213 1214 sf_init_tx_ring(sc); 1215 1216 csr_write_4(sc, SF_RXFILT, SF_PERFMODE_NORMAL|SF_HASHMODE_WITHVLAN); 1217 1218 /* If we want promiscuous mode, set the allframes bit. */ 1219 if (ifp->if_flags & IFF_PROMISC) { 1220 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 1221 } else { 1222 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 1223 } 1224 1225 if (ifp->if_flags & IFF_BROADCAST) { 1226 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_BROAD); 1227 } else { 1228 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_BROAD); 1229 } 1230 1231 /* 1232 * Load the multicast filter. 1233 */ 1234 sf_setmulti(sc); 1235 1236 /* Init the completion queue indexes */ 1237 csr_write_4(sc, SF_CQ_CONSIDX, 0); 1238 csr_write_4(sc, SF_CQ_PRODIDX, 0); 1239 1240 /* Init the RX completion queue */ 1241 csr_write_4(sc, SF_RXCQ_CTL_1, 1242 vtophys(sc->sf_ldata->sf_rx_clist) & SF_RXCQ_ADDR); 1243 SF_SETBIT(sc, SF_RXCQ_CTL_1, SF_RXCQTYPE_3); 1244 1245 /* Init RX DMA control. */ 1246 SF_SETBIT(sc, SF_RXDMA_CTL, SF_RXDMA_REPORTBADPKTS); 1247 1248 /* Init the RX buffer descriptor queue. */ 1249 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 1250 vtophys(sc->sf_ldata->sf_rx_dlist_big)); 1251 csr_write_4(sc, SF_RXDQ_CTL_1, (MCLBYTES << 16) | SF_DESCSPACE_16BYTES); 1252 csr_write_4(sc, SF_RXDQ_PTR_Q1, SF_RX_DLIST_CNT - 1); 1253 1254 /* Init the TX completion queue */ 1255 csr_write_4(sc, SF_TXCQ_CTL, 1256 vtophys(sc->sf_ldata->sf_tx_clist) & SF_RXCQ_ADDR); 1257 1258 /* Init the TX buffer descriptor queue. */ 1259 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 1260 vtophys(sc->sf_ldata->sf_tx_dlist)); 1261 SF_SETBIT(sc, SF_TX_FRAMCTL, SF_TXFRMCTL_CPLAFTERTX); 1262 csr_write_4(sc, SF_TXDQ_CTL, 1263 SF_TXBUFDESC_TYPE0|SF_TXMINSPACE_128BYTES|SF_TXSKIPLEN_8BYTES); 1264 SF_SETBIT(sc, SF_TXDQ_CTL, SF_TXDQCTL_NODMACMP); 1265 1266 /* Enable autopadding of short TX frames. */ 1267 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_AUTOPAD); 1268 1269#ifdef DEVICE_POLLING 1270 /* Disable interrupts if we are polling. */ 1271 if (ifp->if_flags & IFF_POLLING) 1272 csr_write_4(sc, SF_IMR, 0x00000000); 1273 else 1274#endif /* DEVICE_POLLING */ 1275 1276 /* Enable interrupts. */ 1277 csr_write_4(sc, SF_IMR, SF_INTRS); 1278 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_INTR_ENB); 1279 1280 /* Enable the RX and TX engines. */ 1281 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_RX_ENB|SF_ETHCTL_RXDMA_ENB); 1282 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_TX_ENB|SF_ETHCTL_TXDMA_ENB); 1283 1284 /*mii_mediachg(mii);*/ 1285 sf_ifmedia_upd(ifp); 1286 1287 ifp->if_flags |= IFF_RUNNING; 1288 ifp->if_flags &= ~IFF_OACTIVE; 1289 1290 sc->sf_stat_ch = timeout(sf_stats_update, sc, hz); 1291 1292 SF_UNLOCK(sc); 1293} 1294 1295static int 1296sf_encap(sc, c, m_head) 1297 struct sf_softc *sc; 1298 struct sf_tx_bufdesc_type0 *c; 1299 struct mbuf *m_head; 1300{ 1301 int frag = 0; 1302 struct sf_frag *f = NULL; 1303 struct mbuf *m; 1304 1305 m = m_head; 1306 1307 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1308 if (m->m_len != 0) { 1309 if (frag == SF_MAXFRAGS) 1310 break; 1311 f = &c->sf_frags[frag]; 1312 if (frag == 0) 1313 f->sf_pktlen = m_head->m_pkthdr.len; 1314 f->sf_fraglen = m->m_len; 1315 f->sf_addr = vtophys(mtod(m, vm_offset_t)); 1316 frag++; 1317 } 1318 } 1319 1320 if (m != NULL) { 1321 struct mbuf *m_new = NULL; 1322 1323 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1324 if (m_new == NULL) { 1325 printf("sf%d: no memory for tx list\n", sc->sf_unit); 1326 return(1); 1327 } 1328 1329 if (m_head->m_pkthdr.len > MHLEN) { 1330 MCLGET(m_new, M_DONTWAIT); 1331 if (!(m_new->m_flags & M_EXT)) { 1332 m_freem(m_new); 1333 printf("sf%d: no memory for tx list\n", 1334 sc->sf_unit); 1335 return(1); 1336 } 1337 } 1338 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1339 mtod(m_new, caddr_t)); 1340 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1341 m_freem(m_head); 1342 m_head = m_new; 1343 f = &c->sf_frags[0]; 1344 f->sf_fraglen = f->sf_pktlen = m_head->m_pkthdr.len; 1345 f->sf_addr = vtophys(mtod(m_head, caddr_t)); 1346 frag = 1; 1347 } 1348 1349 c->sf_mbuf = m_head; 1350 c->sf_id = SF_TX_BUFDESC_ID; 1351 c->sf_fragcnt = frag; 1352 c->sf_intr = 1; 1353 c->sf_caltcp = 0; 1354 c->sf_crcen = 1; 1355 1356 return(0); 1357} 1358 1359static void 1360sf_start(ifp) 1361 struct ifnet *ifp; 1362{ 1363 struct sf_softc *sc; 1364 struct sf_tx_bufdesc_type0 *cur_tx = NULL; 1365 struct mbuf *m_head = NULL; 1366 int i, txprod; 1367 1368 sc = ifp->if_softc; 1369 SF_LOCK(sc); 1370 1371 if (!sc->sf_link && ifp->if_snd.ifq_len < 10) { 1372 SF_UNLOCK(sc); 1373 return; 1374 } 1375 1376 if (ifp->if_flags & IFF_OACTIVE) { 1377 SF_UNLOCK(sc); 1378 return; 1379 } 1380 1381 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX); 1382 i = SF_IDX_HI(txprod) >> 4; 1383 1384 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) { 1385 printf("sf%d: TX ring full, resetting\n", sc->sf_unit); 1386 sf_init(sc); 1387 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX); 1388 i = SF_IDX_HI(txprod) >> 4; 1389 } 1390 1391 while(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf == NULL) { 1392 if (sc->sf_tx_cnt >= (SF_TX_DLIST_CNT - 5)) { 1393 ifp->if_flags |= IFF_OACTIVE; 1394 cur_tx = NULL; 1395 break; 1396 } 1397 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1398 if (m_head == NULL) 1399 break; 1400 1401 cur_tx = &sc->sf_ldata->sf_tx_dlist[i]; 1402 if (sf_encap(sc, cur_tx, m_head)) { 1403 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1404 ifp->if_flags |= IFF_OACTIVE; 1405 cur_tx = NULL; 1406 break; 1407 } 1408 1409 /* 1410 * If there's a BPF listener, bounce a copy of this frame 1411 * to him. 1412 */ 1413 BPF_MTAP(ifp, m_head); 1414 1415 SF_INC(i, SF_TX_DLIST_CNT); 1416 sc->sf_tx_cnt++; 1417 /* 1418 * Don't get the TX DMA queue get too full. 1419 */ 1420 if (sc->sf_tx_cnt > 64) 1421 break; 1422 } 1423 1424 if (cur_tx == NULL) { 1425 SF_UNLOCK(sc); 1426 return; 1427 } 1428 1429 /* Transmit */ 1430 csr_write_4(sc, SF_TXDQ_PRODIDX, 1431 (txprod & ~SF_TXDQ_PRODIDX_HIPRIO) | 1432 ((i << 20) & 0xFFFF0000)); 1433 1434 ifp->if_timer = 5; 1435 1436 SF_UNLOCK(sc); 1437} 1438 1439static void 1440sf_stop(sc) 1441 struct sf_softc *sc; 1442{ 1443 int i; 1444 struct ifnet *ifp; 1445 1446 SF_LOCK(sc); 1447 1448 ifp = sc->sf_ifp; 1449 1450 untimeout(sf_stats_update, sc, sc->sf_stat_ch); 1451 1452#ifdef DEVICE_POLLING 1453 ether_poll_deregister(ifp); 1454#endif /* DEVICE_POLLING */ 1455 1456 csr_write_4(sc, SF_GEN_ETH_CTL, 0); 1457 csr_write_4(sc, SF_CQ_CONSIDX, 0); 1458 csr_write_4(sc, SF_CQ_PRODIDX, 0); 1459 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 0); 1460 csr_write_4(sc, SF_RXDQ_CTL_1, 0); 1461 csr_write_4(sc, SF_RXDQ_PTR_Q1, 0); 1462 csr_write_4(sc, SF_TXCQ_CTL, 0); 1463 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 0); 1464 csr_write_4(sc, SF_TXDQ_CTL, 0); 1465 sf_reset(sc); 1466 1467 sc->sf_link = 0; 1468 1469 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 1470 if (sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf != NULL) { 1471 m_freem(sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf); 1472 sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf = NULL; 1473 } 1474 } 1475 1476 for (i = 0; i < SF_TX_DLIST_CNT; i++) { 1477 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) { 1478 m_freem(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf); 1479 sc->sf_ldata->sf_tx_dlist[i].sf_mbuf = NULL; 1480 } 1481 } 1482 1483 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 1484 SF_UNLOCK(sc); 1485} 1486 1487/* 1488 * Note: it is important that this function not be interrupted. We 1489 * use a two-stage register access scheme: if we are interrupted in 1490 * between setting the indirect address register and reading from the 1491 * indirect data register, the contents of the address register could 1492 * be changed out from under us. 1493 */ 1494static void 1495sf_stats_update(xsc) 1496 void *xsc; 1497{ 1498 struct sf_softc *sc; 1499 struct ifnet *ifp; 1500 struct mii_data *mii; 1501 struct sf_stats stats; 1502 u_int32_t *ptr; 1503 int i; 1504 1505 sc = xsc; 1506 SF_LOCK(sc); 1507 ifp = sc->sf_ifp; 1508 mii = device_get_softc(sc->sf_miibus); 1509 1510 ptr = (u_int32_t *)&stats; 1511 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++) 1512 ptr[i] = csr_read_4(sc, SF_STATS_BASE + 1513 (i + sizeof(u_int32_t))); 1514 1515 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++) 1516 csr_write_4(sc, SF_STATS_BASE + 1517 (i + sizeof(u_int32_t)), 0); 1518 1519 ifp->if_collisions += stats.sf_tx_single_colls + 1520 stats.sf_tx_multi_colls + stats.sf_tx_excess_colls; 1521 1522 mii_tick(mii); 1523 1524 if (!sc->sf_link && mii->mii_media_status & IFM_ACTIVE && 1525 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1526 sc->sf_link++; 1527 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1528 sf_start(ifp); 1529 } 1530 1531 sc->sf_stat_ch = timeout(sf_stats_update, sc, hz); 1532 1533 SF_UNLOCK(sc); 1534} 1535 1536static void 1537sf_watchdog(ifp) 1538 struct ifnet *ifp; 1539{ 1540 struct sf_softc *sc; 1541 1542 sc = ifp->if_softc; 1543 1544 SF_LOCK(sc); 1545 1546 ifp->if_oerrors++; 1547 printf("sf%d: watchdog timeout\n", sc->sf_unit); 1548 1549 sf_stop(sc); 1550 sf_reset(sc); 1551 sf_init(sc); 1552 1553 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1554 sf_start(ifp); 1555 1556 SF_UNLOCK(sc); 1557} 1558 1559static void 1560sf_shutdown(dev) 1561 device_t dev; 1562{ 1563 struct sf_softc *sc; 1564 1565 sc = device_get_softc(dev); 1566 1567 sf_stop(sc); 1568} 1569