if_sf.c revision 146734
1/*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/sf/if_sf.c 146734 2005-05-29 04:42:30Z nyan $"); 35 36/* 37 * Adaptec AIC-6915 "Starfire" PCI fast ethernet driver for FreeBSD. 38 * Programming manual is available from: 39 * http://download.adaptec.com/pdfs/user_guides/aic6915_pg.pdf. 40 * 41 * Written by Bill Paul <wpaul@ctr.columbia.edu> 42 * Department of Electical Engineering 43 * Columbia University, New York City 44 */ 45/* 46 * The Adaptec AIC-6915 "Starfire" is a 64-bit 10/100 PCI ethernet 47 * controller designed with flexibility and reducing CPU load in mind. 48 * The Starfire offers high and low priority buffer queues, a 49 * producer/consumer index mechanism and several different buffer 50 * queue and completion queue descriptor types. Any one of a number 51 * of different driver designs can be used, depending on system and 52 * OS requirements. This driver makes use of type0 transmit frame 53 * descriptors (since BSD fragments packets across an mbuf chain) 54 * and two RX buffer queues prioritized on size (one queue for small 55 * frames that will fit into a single mbuf, another with full size 56 * mbuf clusters for everything else). The producer/consumer indexes 57 * and completion queues are also used. 58 * 59 * One downside to the Starfire has to do with alignment: buffer 60 * queues must be aligned on 256-byte boundaries, and receive buffers 61 * must be aligned on longword boundaries. The receive buffer alignment 62 * causes problems on the Alpha platform, where the packet payload 63 * should be longword aligned. There is no simple way around this. 64 * 65 * For receive filtering, the Starfire offers 16 perfect filter slots 66 * and a 512-bit hash table. 67 * 68 * The Starfire has no internal transceiver, relying instead on an 69 * external MII-based transceiver. Accessing registers on external 70 * PHYs is done through a special register map rather than with the 71 * usual bitbang MDIO method. 72 * 73 * Acesssing the registers on the Starfire is a little tricky. The 74 * Starfire has a 512K internal register space. When programmed for 75 * PCI memory mapped mode, the entire register space can be accessed 76 * directly. However in I/O space mode, only 256 bytes are directly 77 * mapped into PCI I/O space. The other registers can be accessed 78 * indirectly using the SF_INDIRECTIO_ADDR and SF_INDIRECTIO_DATA 79 * registers inside the 256-byte I/O window. 80 */ 81 82#include <sys/param.h> 83#include <sys/systm.h> 84#include <sys/sockio.h> 85#include <sys/mbuf.h> 86#include <sys/malloc.h> 87#include <sys/kernel.h> 88#include <sys/module.h> 89#include <sys/socket.h> 90 91#include <net/if.h> 92#include <net/if_arp.h> 93#include <net/ethernet.h> 94#include <net/if_dl.h> 95#include <net/if_media.h> 96 97#include <net/bpf.h> 98 99#include <vm/vm.h> /* for vtophys */ 100#include <vm/pmap.h> /* for vtophys */ 101#include <machine/bus.h> 102#include <machine/resource.h> 103#include <sys/bus.h> 104#include <sys/rman.h> 105 106#include <dev/mii/mii.h> 107#include <dev/mii/miivar.h> 108 109/* "controller miibus0" required. See GENERIC if you get errors here. */ 110#include "miibus_if.h" 111 112#include <dev/pci/pcireg.h> 113#include <dev/pci/pcivar.h> 114 115#define SF_USEIOSPACE 116 117#include <pci/if_sfreg.h> 118 119MODULE_DEPEND(sf, pci, 1, 1, 1); 120MODULE_DEPEND(sf, ether, 1, 1, 1); 121MODULE_DEPEND(sf, miibus, 1, 1, 1); 122 123static struct sf_type sf_devs[] = { 124 { AD_VENDORID, AD_DEVICEID_STARFIRE, 125 "Adaptec AIC-6915 10/100BaseTX" }, 126 { 0, 0, NULL } 127}; 128 129static int sf_probe(device_t); 130static int sf_attach(device_t); 131static int sf_detach(device_t); 132static void sf_intr(void *); 133static void sf_stats_update(void *); 134static void sf_rxeof(struct sf_softc *); 135static void sf_txeof(struct sf_softc *); 136static int sf_encap(struct sf_softc *, struct sf_tx_bufdesc_type0 *, 137 struct mbuf *); 138static void sf_start(struct ifnet *); 139static int sf_ioctl(struct ifnet *, u_long, caddr_t); 140static void sf_init(void *); 141static void sf_stop(struct sf_softc *); 142static void sf_watchdog(struct ifnet *); 143static void sf_shutdown(device_t); 144static int sf_ifmedia_upd(struct ifnet *); 145static void sf_ifmedia_sts(struct ifnet *, struct ifmediareq *); 146static void sf_reset(struct sf_softc *); 147static int sf_init_rx_ring(struct sf_softc *); 148static void sf_init_tx_ring(struct sf_softc *); 149static int sf_newbuf(struct sf_softc *, struct sf_rx_bufdesc_type0 *, 150 struct mbuf *); 151static void sf_setmulti(struct sf_softc *); 152static int sf_setperf(struct sf_softc *, int, caddr_t); 153static int sf_sethash(struct sf_softc *, caddr_t, int); 154#ifdef notdef 155static int sf_setvlan(struct sf_softc *, int, u_int32_t); 156#endif 157 158static u_int8_t sf_read_eeprom(struct sf_softc *, int); 159 160static int sf_miibus_readreg(device_t, int, int); 161static int sf_miibus_writereg(device_t, int, int, int); 162static void sf_miibus_statchg(device_t); 163#ifdef DEVICE_POLLING 164static void sf_poll(struct ifnet *ifp, enum poll_cmd cmd, 165 int count); 166static void sf_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, 167 int count); 168#endif /* DEVICE_POLLING */ 169 170static u_int32_t csr_read_4(struct sf_softc *, int); 171static void csr_write_4(struct sf_softc *, int, u_int32_t); 172static void sf_txthresh_adjust(struct sf_softc *); 173 174#ifdef SF_USEIOSPACE 175#define SF_RES SYS_RES_IOPORT 176#define SF_RID SF_PCI_LOIO 177#else 178#define SF_RES SYS_RES_MEMORY 179#define SF_RID SF_PCI_LOMEM 180#endif 181 182static device_method_t sf_methods[] = { 183 /* Device interface */ 184 DEVMETHOD(device_probe, sf_probe), 185 DEVMETHOD(device_attach, sf_attach), 186 DEVMETHOD(device_detach, sf_detach), 187 DEVMETHOD(device_shutdown, sf_shutdown), 188 189 /* bus interface */ 190 DEVMETHOD(bus_print_child, bus_generic_print_child), 191 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 192 193 /* MII interface */ 194 DEVMETHOD(miibus_readreg, sf_miibus_readreg), 195 DEVMETHOD(miibus_writereg, sf_miibus_writereg), 196 DEVMETHOD(miibus_statchg, sf_miibus_statchg), 197 198 { 0, 0 } 199}; 200 201static driver_t sf_driver = { 202 "sf", 203 sf_methods, 204 sizeof(struct sf_softc), 205}; 206 207static devclass_t sf_devclass; 208 209DRIVER_MODULE(sf, pci, sf_driver, sf_devclass, 0, 0); 210DRIVER_MODULE(miibus, sf, miibus_driver, miibus_devclass, 0, 0); 211 212#define SF_SETBIT(sc, reg, x) \ 213 csr_write_4(sc, reg, csr_read_4(sc, reg) | (x)) 214 215#define SF_CLRBIT(sc, reg, x) \ 216 csr_write_4(sc, reg, csr_read_4(sc, reg) & ~(x)) 217 218static u_int32_t 219csr_read_4(sc, reg) 220 struct sf_softc *sc; 221 int reg; 222{ 223 u_int32_t val; 224 225#ifdef SF_USEIOSPACE 226 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); 227 val = CSR_READ_4(sc, SF_INDIRECTIO_DATA); 228#else 229 val = CSR_READ_4(sc, (reg + SF_RMAP_INTREG_BASE)); 230#endif 231 232 return(val); 233} 234 235static u_int8_t 236sf_read_eeprom(sc, reg) 237 struct sf_softc *sc; 238 int reg; 239{ 240 u_int8_t val; 241 242 val = (csr_read_4(sc, SF_EEADDR_BASE + 243 (reg & 0xFFFFFFFC)) >> (8 * (reg & 3))) & 0xFF; 244 245 return(val); 246} 247 248static void 249csr_write_4(sc, reg, val) 250 struct sf_softc *sc; 251 int reg; 252 u_int32_t val; 253{ 254#ifdef SF_USEIOSPACE 255 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); 256 CSR_WRITE_4(sc, SF_INDIRECTIO_DATA, val); 257#else 258 CSR_WRITE_4(sc, (reg + SF_RMAP_INTREG_BASE), val); 259#endif 260} 261 262/* 263 * Copy the address 'mac' into the perfect RX filter entry at 264 * offset 'idx.' The perfect filter only has 16 entries so do 265 * some sanity tests. 266 */ 267static int 268sf_setperf(sc, idx, mac) 269 struct sf_softc *sc; 270 int idx; 271 caddr_t mac; 272{ 273 u_int16_t *p; 274 275 if (idx < 0 || idx > SF_RXFILT_PERFECT_CNT) 276 return(EINVAL); 277 278 if (mac == NULL) 279 return(EINVAL); 280 281 p = (u_int16_t *)mac; 282 283 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 284 (idx * SF_RXFILT_PERFECT_SKIP), htons(p[2])); 285 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 286 (idx * SF_RXFILT_PERFECT_SKIP) + 4, htons(p[1])); 287 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 288 (idx * SF_RXFILT_PERFECT_SKIP) + 8, htons(p[0])); 289 290 return(0); 291} 292 293/* 294 * Set the bit in the 512-bit hash table that corresponds to the 295 * specified mac address 'mac.' If 'prio' is nonzero, update the 296 * priority hash table instead of the filter hash table. 297 */ 298static int 299sf_sethash(sc, mac, prio) 300 struct sf_softc *sc; 301 caddr_t mac; 302 int prio; 303{ 304 u_int32_t h; 305 306 if (mac == NULL) 307 return(EINVAL); 308 309 h = ether_crc32_be(mac, ETHER_ADDR_LEN) >> 23; 310 311 if (prio) { 312 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_PRIOOFF + 313 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); 314 } else { 315 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_ADDROFF + 316 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); 317 } 318 319 return(0); 320} 321 322#ifdef notdef 323/* 324 * Set a VLAN tag in the receive filter. 325 */ 326static int 327sf_setvlan(sc, idx, vlan) 328 struct sf_softc *sc; 329 int idx; 330 u_int32_t vlan; 331{ 332 if (idx < 0 || idx >> SF_RXFILT_HASH_CNT) 333 return(EINVAL); 334 335 csr_write_4(sc, SF_RXFILT_HASH_BASE + 336 (idx * SF_RXFILT_HASH_SKIP) + SF_RXFILT_HASH_VLANOFF, vlan); 337 338 return(0); 339} 340#endif 341 342static int 343sf_miibus_readreg(dev, phy, reg) 344 device_t dev; 345 int phy, reg; 346{ 347 struct sf_softc *sc; 348 int i; 349 u_int32_t val = 0; 350 351 sc = device_get_softc(dev); 352 353 for (i = 0; i < SF_TIMEOUT; i++) { 354 val = csr_read_4(sc, SF_PHY_REG(phy, reg)); 355 if (val & SF_MII_DATAVALID) 356 break; 357 } 358 359 if (i == SF_TIMEOUT) 360 return(0); 361 362 if ((val & 0x0000FFFF) == 0xFFFF) 363 return(0); 364 365 return(val & 0x0000FFFF); 366} 367 368static int 369sf_miibus_writereg(dev, phy, reg, val) 370 device_t dev; 371 int phy, reg, val; 372{ 373 struct sf_softc *sc; 374 int i; 375 int busy; 376 377 sc = device_get_softc(dev); 378 379 csr_write_4(sc, SF_PHY_REG(phy, reg), val); 380 381 for (i = 0; i < SF_TIMEOUT; i++) { 382 busy = csr_read_4(sc, SF_PHY_REG(phy, reg)); 383 if (!(busy & SF_MII_BUSY)) 384 break; 385 } 386 387 return(0); 388} 389 390static void 391sf_miibus_statchg(dev) 392 device_t dev; 393{ 394 struct sf_softc *sc; 395 struct mii_data *mii; 396 397 sc = device_get_softc(dev); 398 mii = device_get_softc(sc->sf_miibus); 399 400 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 401 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 402 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_FDX); 403 } else { 404 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 405 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_HDX); 406 } 407} 408 409static void 410sf_setmulti(sc) 411 struct sf_softc *sc; 412{ 413 struct ifnet *ifp; 414 int i; 415 struct ifmultiaddr *ifma; 416 u_int8_t dummy[] = { 0, 0, 0, 0, 0, 0 }; 417 418 ifp = &sc->arpcom.ac_if; 419 420 /* First zot all the existing filters. */ 421 for (i = 1; i < SF_RXFILT_PERFECT_CNT; i++) 422 sf_setperf(sc, i, (char *)&dummy); 423 for (i = SF_RXFILT_HASH_BASE; 424 i < (SF_RXFILT_HASH_MAX + 1); i += 4) 425 csr_write_4(sc, i, 0); 426 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI); 427 428 /* Now program new ones. */ 429 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 430 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI); 431 } else { 432 i = 1; 433 TAILQ_FOREACH_REVERSE(ifma, &ifp->if_multiaddrs, ifmultihead, ifma_link) { 434 if (ifma->ifma_addr->sa_family != AF_LINK) 435 continue; 436 /* 437 * Program the first 15 multicast groups 438 * into the perfect filter. For all others, 439 * use the hash table. 440 */ 441 if (i < SF_RXFILT_PERFECT_CNT) { 442 sf_setperf(sc, i, 443 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 444 i++; 445 continue; 446 } 447 448 sf_sethash(sc, 449 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 0); 450 } 451 } 452} 453 454/* 455 * Set media options. 456 */ 457static int 458sf_ifmedia_upd(ifp) 459 struct ifnet *ifp; 460{ 461 struct sf_softc *sc; 462 struct mii_data *mii; 463 464 sc = ifp->if_softc; 465 mii = device_get_softc(sc->sf_miibus); 466 sc->sf_link = 0; 467 if (mii->mii_instance) { 468 struct mii_softc *miisc; 469 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 470 mii_phy_reset(miisc); 471 } 472 mii_mediachg(mii); 473 474 return(0); 475} 476 477/* 478 * Report current media status. 479 */ 480static void 481sf_ifmedia_sts(ifp, ifmr) 482 struct ifnet *ifp; 483 struct ifmediareq *ifmr; 484{ 485 struct sf_softc *sc; 486 struct mii_data *mii; 487 488 sc = ifp->if_softc; 489 mii = device_get_softc(sc->sf_miibus); 490 491 mii_pollstat(mii); 492 ifmr->ifm_active = mii->mii_media_active; 493 ifmr->ifm_status = mii->mii_media_status; 494} 495 496static int 497sf_ioctl(ifp, command, data) 498 struct ifnet *ifp; 499 u_long command; 500 caddr_t data; 501{ 502 struct sf_softc *sc = ifp->if_softc; 503 struct ifreq *ifr = (struct ifreq *) data; 504 struct mii_data *mii; 505 int error = 0; 506 507 SF_LOCK(sc); 508 509 switch(command) { 510 case SIOCSIFFLAGS: 511 if (ifp->if_flags & IFF_UP) { 512 if (ifp->if_flags & IFF_RUNNING && 513 ifp->if_flags & IFF_PROMISC && 514 !(sc->sf_if_flags & IFF_PROMISC)) { 515 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 516 } else if (ifp->if_flags & IFF_RUNNING && 517 !(ifp->if_flags & IFF_PROMISC) && 518 sc->sf_if_flags & IFF_PROMISC) { 519 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 520 } else if (!(ifp->if_flags & IFF_RUNNING)) 521 sf_init(sc); 522 } else { 523 if (ifp->if_flags & IFF_RUNNING) 524 sf_stop(sc); 525 } 526 sc->sf_if_flags = ifp->if_flags; 527 error = 0; 528 break; 529 case SIOCADDMULTI: 530 case SIOCDELMULTI: 531 sf_setmulti(sc); 532 error = 0; 533 break; 534 case SIOCGIFMEDIA: 535 case SIOCSIFMEDIA: 536 mii = device_get_softc(sc->sf_miibus); 537 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 538 break; 539 case SIOCSIFCAP: 540 ifp->if_capenable &= ~IFCAP_POLLING; 541 ifp->if_capenable |= ifr->ifr_reqcap & IFCAP_POLLING; 542 break; 543 default: 544 error = ether_ioctl(ifp, command, data); 545 break; 546 } 547 548 SF_UNLOCK(sc); 549 550 return(error); 551} 552 553static void 554sf_reset(sc) 555 struct sf_softc *sc; 556{ 557 register int i; 558 559 csr_write_4(sc, SF_GEN_ETH_CTL, 0); 560 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 561 DELAY(1000); 562 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 563 564 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_RESET); 565 566 for (i = 0; i < SF_TIMEOUT; i++) { 567 DELAY(10); 568 if (!(csr_read_4(sc, SF_PCI_DEVCFG) & SF_PCIDEVCFG_RESET)) 569 break; 570 } 571 572 if (i == SF_TIMEOUT) 573 printf("sf%d: reset never completed!\n", sc->sf_unit); 574 575 /* Wait a little while for the chip to get its brains in order. */ 576 DELAY(1000); 577} 578 579/* 580 * Probe for an Adaptec AIC-6915 chip. Check the PCI vendor and device 581 * IDs against our list and return a device name if we find a match. 582 * We also check the subsystem ID so that we can identify exactly which 583 * NIC has been found, if possible. 584 */ 585static int 586sf_probe(dev) 587 device_t dev; 588{ 589 struct sf_type *t; 590 591 t = sf_devs; 592 593 while(t->sf_name != NULL) { 594 if ((pci_get_vendor(dev) == t->sf_vid) && 595 (pci_get_device(dev) == t->sf_did)) { 596 switch((pci_read_config(dev, 597 SF_PCI_SUBVEN_ID, 4) >> 16) & 0xFFFF) { 598 case AD_SUBSYSID_62011_REV0: 599 case AD_SUBSYSID_62011_REV1: 600 device_set_desc(dev, 601 "Adaptec ANA-62011 10/100BaseTX"); 602 return (BUS_PROBE_DEFAULT); 603 case AD_SUBSYSID_62022: 604 device_set_desc(dev, 605 "Adaptec ANA-62022 10/100BaseTX"); 606 return (BUS_PROBE_DEFAULT); 607 case AD_SUBSYSID_62044_REV0: 608 case AD_SUBSYSID_62044_REV1: 609 device_set_desc(dev, 610 "Adaptec ANA-62044 10/100BaseTX"); 611 return (BUS_PROBE_DEFAULT); 612 case AD_SUBSYSID_62020: 613 device_set_desc(dev, 614 "Adaptec ANA-62020 10/100BaseFX"); 615 return (BUS_PROBE_DEFAULT); 616 case AD_SUBSYSID_69011: 617 device_set_desc(dev, 618 "Adaptec ANA-69011 10/100BaseTX"); 619 return (BUS_PROBE_DEFAULT); 620 default: 621 device_set_desc(dev, t->sf_name); 622 return (BUS_PROBE_DEFAULT); 623 break; 624 } 625 } 626 t++; 627 } 628 629 return(ENXIO); 630} 631 632/* 633 * Attach the interface. Allocate softc structures, do ifmedia 634 * setup and ethernet/BPF attach. 635 */ 636static int 637sf_attach(dev) 638 device_t dev; 639{ 640 int i; 641 struct sf_softc *sc; 642 struct ifnet *ifp; 643 int unit, rid, error = 0; 644 645 sc = device_get_softc(dev); 646 unit = device_get_unit(dev); 647 648 mtx_init(&sc->sf_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 649 MTX_DEF | MTX_RECURSE); 650 /* 651 * Map control/status registers. 652 */ 653 pci_enable_busmaster(dev); 654 655 rid = SF_RID; 656 sc->sf_res = bus_alloc_resource_any(dev, SF_RES, &rid, RF_ACTIVE); 657 658 if (sc->sf_res == NULL) { 659 printf ("sf%d: couldn't map ports\n", unit); 660 error = ENXIO; 661 goto fail; 662 } 663 664 sc->sf_btag = rman_get_bustag(sc->sf_res); 665 sc->sf_bhandle = rman_get_bushandle(sc->sf_res); 666 667 /* Allocate interrupt */ 668 rid = 0; 669 sc->sf_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 670 RF_SHAREABLE | RF_ACTIVE); 671 672 if (sc->sf_irq == NULL) { 673 printf("sf%d: couldn't map interrupt\n", unit); 674 error = ENXIO; 675 goto fail; 676 } 677 678 callout_handle_init(&sc->sf_stat_ch); 679 /* Reset the adapter. */ 680 sf_reset(sc); 681 682 /* 683 * Get station address from the EEPROM. 684 */ 685 for (i = 0; i < ETHER_ADDR_LEN; i++) 686 sc->arpcom.ac_enaddr[i] = 687 sf_read_eeprom(sc, SF_EE_NODEADDR + ETHER_ADDR_LEN - i); 688 689 sc->sf_unit = unit; 690 691 /* Allocate the descriptor queues. */ 692 sc->sf_ldata = contigmalloc(sizeof(struct sf_list_data), M_DEVBUF, 693 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 694 695 if (sc->sf_ldata == NULL) { 696 printf("sf%d: no memory for list buffers!\n", unit); 697 error = ENXIO; 698 goto fail; 699 } 700 701 bzero(sc->sf_ldata, sizeof(struct sf_list_data)); 702 703 /* Do MII setup. */ 704 if (mii_phy_probe(dev, &sc->sf_miibus, 705 sf_ifmedia_upd, sf_ifmedia_sts)) { 706 printf("sf%d: MII without any phy!\n", sc->sf_unit); 707 error = ENXIO; 708 goto fail; 709 } 710 711 ifp = &sc->arpcom.ac_if; 712 ifp->if_softc = sc; 713 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 714 ifp->if_mtu = ETHERMTU; 715 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST | 716 IFF_NEEDSGIANT; 717 ifp->if_ioctl = sf_ioctl; 718 ifp->if_start = sf_start; 719 ifp->if_watchdog = sf_watchdog; 720 ifp->if_init = sf_init; 721 ifp->if_baudrate = 10000000; 722 IFQ_SET_MAXLEN(&ifp->if_snd, SF_TX_DLIST_CNT - 1); 723 ifp->if_snd.ifq_drv_maxlen = SF_TX_DLIST_CNT - 1; 724 IFQ_SET_READY(&ifp->if_snd); 725#ifdef DEVICE_POLLING 726 ifp->if_capabilities |= IFCAP_POLLING; 727#endif /* DEVICE_POLLING */ 728 ifp->if_capenable = ifp->if_capabilities; 729 730 /* 731 * Call MI attach routine. 732 */ 733 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 734 735 /* Hook interrupt last to avoid having to lock softc */ 736 error = bus_setup_intr(dev, sc->sf_irq, INTR_TYPE_NET, 737 sf_intr, sc, &sc->sf_intrhand); 738 739 if (error) { 740 printf("sf%d: couldn't set up irq\n", unit); 741 ether_ifdetach(ifp); 742 goto fail; 743 } 744 745fail: 746 if (error) 747 sf_detach(dev); 748 749 return(error); 750} 751 752/* 753 * Shutdown hardware and free up resources. This can be called any 754 * time after the mutex has been initialized. It is called in both 755 * the error case in attach and the normal detach case so it needs 756 * to be careful about only freeing resources that have actually been 757 * allocated. 758 */ 759static int 760sf_detach(dev) 761 device_t dev; 762{ 763 struct sf_softc *sc; 764 struct ifnet *ifp; 765 766 sc = device_get_softc(dev); 767 KASSERT(mtx_initialized(&sc->sf_mtx), ("sf mutex not initialized")); 768 SF_LOCK(sc); 769 ifp = &sc->arpcom.ac_if; 770 771 /* These should only be active if attach succeeded */ 772 if (device_is_attached(dev)) { 773 sf_stop(sc); 774 ether_ifdetach(ifp); 775 } 776 if (sc->sf_miibus) 777 device_delete_child(dev, sc->sf_miibus); 778 bus_generic_detach(dev); 779 780 if (sc->sf_intrhand) 781 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand); 782 if (sc->sf_irq) 783 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq); 784 if (sc->sf_res) 785 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 786 787 if (sc->sf_ldata) 788 contigfree(sc->sf_ldata, sizeof(struct sf_list_data), M_DEVBUF); 789 790 SF_UNLOCK(sc); 791 mtx_destroy(&sc->sf_mtx); 792 793 return(0); 794} 795 796static int 797sf_init_rx_ring(sc) 798 struct sf_softc *sc; 799{ 800 struct sf_list_data *ld; 801 int i; 802 803 ld = sc->sf_ldata; 804 805 bzero((char *)ld->sf_rx_dlist_big, 806 sizeof(struct sf_rx_bufdesc_type0) * SF_RX_DLIST_CNT); 807 bzero((char *)ld->sf_rx_clist, 808 sizeof(struct sf_rx_cmpdesc_type3) * SF_RX_CLIST_CNT); 809 810 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 811 if (sf_newbuf(sc, &ld->sf_rx_dlist_big[i], NULL) == ENOBUFS) 812 return(ENOBUFS); 813 } 814 815 return(0); 816} 817 818static void 819sf_init_tx_ring(sc) 820 struct sf_softc *sc; 821{ 822 struct sf_list_data *ld; 823 int i; 824 825 ld = sc->sf_ldata; 826 827 bzero((char *)ld->sf_tx_dlist, 828 sizeof(struct sf_tx_bufdesc_type0) * SF_TX_DLIST_CNT); 829 bzero((char *)ld->sf_tx_clist, 830 sizeof(struct sf_tx_cmpdesc_type0) * SF_TX_CLIST_CNT); 831 832 for (i = 0; i < SF_TX_DLIST_CNT; i++) 833 ld->sf_tx_dlist[i].sf_id = SF_TX_BUFDESC_ID; 834 for (i = 0; i < SF_TX_CLIST_CNT; i++) 835 ld->sf_tx_clist[i].sf_type = SF_TXCMPTYPE_TX; 836 837 ld->sf_tx_dlist[SF_TX_DLIST_CNT - 1].sf_end = 1; 838 sc->sf_tx_cnt = 0; 839} 840 841static int 842sf_newbuf(sc, c, m) 843 struct sf_softc *sc; 844 struct sf_rx_bufdesc_type0 *c; 845 struct mbuf *m; 846{ 847 struct mbuf *m_new = NULL; 848 849 if (m == NULL) { 850 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 851 if (m_new == NULL) 852 return(ENOBUFS); 853 854 MCLGET(m_new, M_DONTWAIT); 855 if (!(m_new->m_flags & M_EXT)) { 856 m_freem(m_new); 857 return(ENOBUFS); 858 } 859 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 860 } else { 861 m_new = m; 862 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 863 m_new->m_data = m_new->m_ext.ext_buf; 864 } 865 866 m_adj(m_new, sizeof(u_int64_t)); 867 868 c->sf_mbuf = m_new; 869 c->sf_addrlo = SF_RX_HOSTADDR(vtophys(mtod(m_new, caddr_t))); 870 c->sf_valid = 1; 871 872 return(0); 873} 874 875/* 876 * The starfire is programmed to use 'normal' mode for packet reception, 877 * which means we use the consumer/producer model for both the buffer 878 * descriptor queue and the completion descriptor queue. The only problem 879 * with this is that it involves a lot of register accesses: we have to 880 * read the RX completion consumer and producer indexes and the RX buffer 881 * producer index, plus the RX completion consumer and RX buffer producer 882 * indexes have to be updated. It would have been easier if Adaptec had 883 * put each index in a separate register, especially given that the damn 884 * NIC has a 512K register space. 885 * 886 * In spite of all the lovely features that Adaptec crammed into the 6915, 887 * it is marred by one truly stupid design flaw, which is that receive 888 * buffer addresses must be aligned on a longword boundary. This forces 889 * the packet payload to be unaligned, which is suboptimal on the x86 and 890 * completely unuseable on the Alpha. Our only recourse is to copy received 891 * packets into properly aligned buffers before handing them off. 892 */ 893 894static void 895sf_rxeof(sc) 896 struct sf_softc *sc; 897{ 898 struct mbuf *m; 899 struct ifnet *ifp; 900 struct sf_rx_bufdesc_type0 *desc; 901 struct sf_rx_cmpdesc_type3 *cur_rx; 902 u_int32_t rxcons, rxprod; 903 int cmpprodidx, cmpconsidx, bufprodidx; 904 905 SF_LOCK_ASSERT(sc); 906 907 ifp = &sc->arpcom.ac_if; 908 909 rxcons = csr_read_4(sc, SF_CQ_CONSIDX); 910 rxprod = csr_read_4(sc, SF_RXDQ_PTR_Q1); 911 cmpprodidx = SF_IDX_LO(csr_read_4(sc, SF_CQ_PRODIDX)); 912 cmpconsidx = SF_IDX_LO(rxcons); 913 bufprodidx = SF_IDX_LO(rxprod); 914 915 while (cmpconsidx != cmpprodidx) { 916 struct mbuf *m0; 917 918#ifdef DEVICE_POLLING 919 if (ifp->if_flags & IFF_POLLING) { 920 if (sc->rxcycles <= 0) 921 break; 922 sc->rxcycles--; 923 } 924#endif /* DEVICE_POLLING */ 925 926 cur_rx = &sc->sf_ldata->sf_rx_clist[cmpconsidx]; 927 desc = &sc->sf_ldata->sf_rx_dlist_big[cur_rx->sf_endidx]; 928 m = desc->sf_mbuf; 929 SF_INC(cmpconsidx, SF_RX_CLIST_CNT); 930 SF_INC(bufprodidx, SF_RX_DLIST_CNT); 931 932 if (!(cur_rx->sf_status1 & SF_RXSTAT1_OK)) { 933 ifp->if_ierrors++; 934 sf_newbuf(sc, desc, m); 935 continue; 936 } 937 938 m0 = m_devget(mtod(m, char *), cur_rx->sf_len, ETHER_ALIGN, 939 ifp, NULL); 940 sf_newbuf(sc, desc, m); 941 if (m0 == NULL) { 942 ifp->if_ierrors++; 943 continue; 944 } 945 m = m0; 946 947 ifp->if_ipackets++; 948 SF_UNLOCK(sc); 949 (*ifp->if_input)(ifp, m); 950 SF_LOCK(sc); 951 } 952 953 csr_write_4(sc, SF_CQ_CONSIDX, 954 (rxcons & ~SF_CQ_CONSIDX_RXQ1) | cmpconsidx); 955 csr_write_4(sc, SF_RXDQ_PTR_Q1, 956 (rxprod & ~SF_RXDQ_PRODIDX) | bufprodidx); 957} 958 959/* 960 * Read the transmit status from the completion queue and release 961 * mbufs. Note that the buffer descriptor index in the completion 962 * descriptor is an offset from the start of the transmit buffer 963 * descriptor list in bytes. This is important because the manual 964 * gives the impression that it should match the producer/consumer 965 * index, which is the offset in 8 byte blocks. 966 */ 967static void 968sf_txeof(sc) 969 struct sf_softc *sc; 970{ 971 int txcons, cmpprodidx, cmpconsidx; 972 struct sf_tx_cmpdesc_type1 *cur_cmp; 973 struct sf_tx_bufdesc_type0 *cur_tx; 974 struct ifnet *ifp; 975 976 ifp = &sc->arpcom.ac_if; 977 978 txcons = csr_read_4(sc, SF_CQ_CONSIDX); 979 cmpprodidx = SF_IDX_HI(csr_read_4(sc, SF_CQ_PRODIDX)); 980 cmpconsidx = SF_IDX_HI(txcons); 981 982 while (cmpconsidx != cmpprodidx) { 983 cur_cmp = &sc->sf_ldata->sf_tx_clist[cmpconsidx]; 984 cur_tx = &sc->sf_ldata->sf_tx_dlist[cur_cmp->sf_index >> 7]; 985 986 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_OK) 987 ifp->if_opackets++; 988 else { 989 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_UNDERRUN) 990 sf_txthresh_adjust(sc); 991 ifp->if_oerrors++; 992 } 993 994 sc->sf_tx_cnt--; 995 if (cur_tx->sf_mbuf != NULL) { 996 m_freem(cur_tx->sf_mbuf); 997 cur_tx->sf_mbuf = NULL; 998 } else 999 break; 1000 SF_INC(cmpconsidx, SF_TX_CLIST_CNT); 1001 } 1002 1003 ifp->if_timer = 0; 1004 ifp->if_flags &= ~IFF_OACTIVE; 1005 1006 csr_write_4(sc, SF_CQ_CONSIDX, 1007 (txcons & ~SF_CQ_CONSIDX_TXQ) | 1008 ((cmpconsidx << 16) & 0xFFFF0000)); 1009} 1010 1011static void 1012sf_txthresh_adjust(sc) 1013 struct sf_softc *sc; 1014{ 1015 u_int32_t txfctl; 1016 u_int8_t txthresh; 1017 1018 txfctl = csr_read_4(sc, SF_TX_FRAMCTL); 1019 txthresh = txfctl & SF_TXFRMCTL_TXTHRESH; 1020 if (txthresh < 0xFF) { 1021 txthresh++; 1022 txfctl &= ~SF_TXFRMCTL_TXTHRESH; 1023 txfctl |= txthresh; 1024#ifdef DIAGNOSTIC 1025 printf("sf%d: tx underrun, increasing " 1026 "tx threshold to %d bytes\n", 1027 sc->sf_unit, txthresh * 4); 1028#endif 1029 csr_write_4(sc, SF_TX_FRAMCTL, txfctl); 1030 } 1031} 1032 1033#ifdef DEVICE_POLLING 1034static void 1035sf_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1036{ 1037 struct sf_softc *sc = ifp->if_softc; 1038 1039 SF_LOCK(sc); 1040 sf_poll_locked(ifp, cmd, count); 1041 SF_UNLOCK(sc); 1042} 1043 1044static void 1045sf_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 1046{ 1047 struct sf_softc *sc = ifp->if_softc; 1048 1049 SF_LOCK_ASSERT(sc); 1050 1051 if (!(ifp->if_capenable & IFCAP_POLLING)) { 1052 ether_poll_deregister(ifp); 1053 cmd = POLL_DEREGISTER; 1054 } 1055 1056 if (cmd == POLL_DEREGISTER) { 1057 /* Final call, enable interrupts. */ 1058 csr_write_4(sc, SF_IMR, SF_INTRS); 1059 return; 1060 } 1061 1062 sc->rxcycles = count; 1063 sf_rxeof(sc); 1064 sf_txeof(sc); 1065 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1066 sf_start(ifp); 1067 1068 if (cmd == POLL_AND_CHECK_STATUS) { 1069 u_int32_t status; 1070 1071 status = csr_read_4(sc, SF_ISR); 1072 if (status) 1073 csr_write_4(sc, SF_ISR, status); 1074 1075 if (status & SF_ISR_TX_LOFIFO) 1076 sf_txthresh_adjust(sc); 1077 1078 if (status & SF_ISR_ABNORMALINTR) { 1079 if (status & SF_ISR_STATSOFLOW) { 1080 untimeout(sf_stats_update, sc, 1081 sc->sf_stat_ch); 1082 sf_stats_update(sc); 1083 } else 1084 sf_init(sc); 1085 } 1086 } 1087} 1088#endif /* DEVICE_POLLING */ 1089 1090static void 1091sf_intr(arg) 1092 void *arg; 1093{ 1094 struct sf_softc *sc; 1095 struct ifnet *ifp; 1096 u_int32_t status; 1097 1098 sc = arg; 1099 SF_LOCK(sc); 1100 1101 ifp = &sc->arpcom.ac_if; 1102 1103#ifdef DEVICE_POLLING 1104 if (ifp->if_flags & IFF_POLLING) 1105 goto done_locked; 1106 1107 if ((ifp->if_capenable & IFCAP_POLLING) && 1108 ether_poll_register(sf_poll, ifp)) { 1109 /* OK, disable interrupts. */ 1110 csr_write_4(sc, SF_IMR, 0x00000000); 1111 sf_poll_locked(ifp, 0, 1); 1112 goto done_locked; 1113 } 1114#endif /* DEVICE_POLLING */ 1115 1116 if (!(csr_read_4(sc, SF_ISR_SHADOW) & SF_ISR_PCIINT_ASSERTED)) { 1117 SF_UNLOCK(sc); 1118 return; 1119 } 1120 1121 /* Disable interrupts. */ 1122 csr_write_4(sc, SF_IMR, 0x00000000); 1123 1124 for (;;) { 1125 status = csr_read_4(sc, SF_ISR); 1126 if (status) 1127 csr_write_4(sc, SF_ISR, status); 1128 1129 if (!(status & SF_INTRS)) 1130 break; 1131 1132 if (status & SF_ISR_RXDQ1_DMADONE) 1133 sf_rxeof(sc); 1134 1135 if (status & SF_ISR_TX_TXDONE || 1136 status & SF_ISR_TX_DMADONE || 1137 status & SF_ISR_TX_QUEUEDONE) 1138 sf_txeof(sc); 1139 1140 if (status & SF_ISR_TX_LOFIFO) 1141 sf_txthresh_adjust(sc); 1142 1143 if (status & SF_ISR_ABNORMALINTR) { 1144 if (status & SF_ISR_STATSOFLOW) { 1145 untimeout(sf_stats_update, sc, 1146 sc->sf_stat_ch); 1147 sf_stats_update(sc); 1148 } else 1149 sf_init(sc); 1150 } 1151 } 1152 1153 /* Re-enable interrupts. */ 1154 csr_write_4(sc, SF_IMR, SF_INTRS); 1155 1156 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1157 sf_start(ifp); 1158 1159#ifdef DEVICE_POLLING 1160done_locked: 1161#endif /* DEVICE_POLLING */ 1162 SF_UNLOCK(sc); 1163} 1164 1165static void 1166sf_init(xsc) 1167 void *xsc; 1168{ 1169 struct sf_softc *sc; 1170 struct ifnet *ifp; 1171 struct mii_data *mii; 1172 int i; 1173 1174 sc = xsc; 1175 SF_LOCK(sc); 1176 ifp = &sc->arpcom.ac_if; 1177 mii = device_get_softc(sc->sf_miibus); 1178 1179 sf_stop(sc); 1180 sf_reset(sc); 1181 1182 /* Init all the receive filter registers */ 1183 for (i = SF_RXFILT_PERFECT_BASE; 1184 i < (SF_RXFILT_HASH_MAX + 1); i += 4) 1185 csr_write_4(sc, i, 0); 1186 1187 /* Empty stats counter registers. */ 1188 for (i = 0; i < sizeof(struct sf_stats)/sizeof(u_int32_t); i++) 1189 csr_write_4(sc, SF_STATS_BASE + 1190 (i + sizeof(u_int32_t)), 0); 1191 1192 /* Init our MAC address */ 1193 csr_write_4(sc, SF_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1194 csr_write_4(sc, SF_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1195 sf_setperf(sc, 0, (caddr_t)&sc->arpcom.ac_enaddr); 1196 1197 if (sf_init_rx_ring(sc) == ENOBUFS) { 1198 printf("sf%d: initialization failed: no " 1199 "memory for rx buffers\n", sc->sf_unit); 1200 SF_UNLOCK(sc); 1201 return; 1202 } 1203 1204 sf_init_tx_ring(sc); 1205 1206 csr_write_4(sc, SF_RXFILT, SF_PERFMODE_NORMAL|SF_HASHMODE_WITHVLAN); 1207 1208 /* If we want promiscuous mode, set the allframes bit. */ 1209 if (ifp->if_flags & IFF_PROMISC) { 1210 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 1211 } else { 1212 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 1213 } 1214 1215 if (ifp->if_flags & IFF_BROADCAST) { 1216 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_BROAD); 1217 } else { 1218 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_BROAD); 1219 } 1220 1221 /* 1222 * Load the multicast filter. 1223 */ 1224 sf_setmulti(sc); 1225 1226 /* Init the completion queue indexes */ 1227 csr_write_4(sc, SF_CQ_CONSIDX, 0); 1228 csr_write_4(sc, SF_CQ_PRODIDX, 0); 1229 1230 /* Init the RX completion queue */ 1231 csr_write_4(sc, SF_RXCQ_CTL_1, 1232 vtophys(sc->sf_ldata->sf_rx_clist) & SF_RXCQ_ADDR); 1233 SF_SETBIT(sc, SF_RXCQ_CTL_1, SF_RXCQTYPE_3); 1234 1235 /* Init RX DMA control. */ 1236 SF_SETBIT(sc, SF_RXDMA_CTL, SF_RXDMA_REPORTBADPKTS); 1237 1238 /* Init the RX buffer descriptor queue. */ 1239 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 1240 vtophys(sc->sf_ldata->sf_rx_dlist_big)); 1241 csr_write_4(sc, SF_RXDQ_CTL_1, (MCLBYTES << 16) | SF_DESCSPACE_16BYTES); 1242 csr_write_4(sc, SF_RXDQ_PTR_Q1, SF_RX_DLIST_CNT - 1); 1243 1244 /* Init the TX completion queue */ 1245 csr_write_4(sc, SF_TXCQ_CTL, 1246 vtophys(sc->sf_ldata->sf_tx_clist) & SF_RXCQ_ADDR); 1247 1248 /* Init the TX buffer descriptor queue. */ 1249 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 1250 vtophys(sc->sf_ldata->sf_tx_dlist)); 1251 SF_SETBIT(sc, SF_TX_FRAMCTL, SF_TXFRMCTL_CPLAFTERTX); 1252 csr_write_4(sc, SF_TXDQ_CTL, 1253 SF_TXBUFDESC_TYPE0|SF_TXMINSPACE_128BYTES|SF_TXSKIPLEN_8BYTES); 1254 SF_SETBIT(sc, SF_TXDQ_CTL, SF_TXDQCTL_NODMACMP); 1255 1256 /* Enable autopadding of short TX frames. */ 1257 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_AUTOPAD); 1258 1259#ifdef DEVICE_POLLING 1260 /* Disable interrupts if we are polling. */ 1261 if (ifp->if_flags & IFF_POLLING) 1262 csr_write_4(sc, SF_IMR, 0x00000000); 1263 else 1264#endif /* DEVICE_POLLING */ 1265 1266 /* Enable interrupts. */ 1267 csr_write_4(sc, SF_IMR, SF_INTRS); 1268 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_INTR_ENB); 1269 1270 /* Enable the RX and TX engines. */ 1271 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_RX_ENB|SF_ETHCTL_RXDMA_ENB); 1272 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_TX_ENB|SF_ETHCTL_TXDMA_ENB); 1273 1274 /*mii_mediachg(mii);*/ 1275 sf_ifmedia_upd(ifp); 1276 1277 ifp->if_flags |= IFF_RUNNING; 1278 ifp->if_flags &= ~IFF_OACTIVE; 1279 1280 sc->sf_stat_ch = timeout(sf_stats_update, sc, hz); 1281 1282 SF_UNLOCK(sc); 1283} 1284 1285static int 1286sf_encap(sc, c, m_head) 1287 struct sf_softc *sc; 1288 struct sf_tx_bufdesc_type0 *c; 1289 struct mbuf *m_head; 1290{ 1291 int frag = 0; 1292 struct sf_frag *f = NULL; 1293 struct mbuf *m; 1294 1295 m = m_head; 1296 1297 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1298 if (m->m_len != 0) { 1299 if (frag == SF_MAXFRAGS) 1300 break; 1301 f = &c->sf_frags[frag]; 1302 if (frag == 0) 1303 f->sf_pktlen = m_head->m_pkthdr.len; 1304 f->sf_fraglen = m->m_len; 1305 f->sf_addr = vtophys(mtod(m, vm_offset_t)); 1306 frag++; 1307 } 1308 } 1309 1310 if (m != NULL) { 1311 struct mbuf *m_new = NULL; 1312 1313 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1314 if (m_new == NULL) { 1315 printf("sf%d: no memory for tx list\n", sc->sf_unit); 1316 return(1); 1317 } 1318 1319 if (m_head->m_pkthdr.len > MHLEN) { 1320 MCLGET(m_new, M_DONTWAIT); 1321 if (!(m_new->m_flags & M_EXT)) { 1322 m_freem(m_new); 1323 printf("sf%d: no memory for tx list\n", 1324 sc->sf_unit); 1325 return(1); 1326 } 1327 } 1328 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1329 mtod(m_new, caddr_t)); 1330 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1331 m_freem(m_head); 1332 m_head = m_new; 1333 f = &c->sf_frags[0]; 1334 f->sf_fraglen = f->sf_pktlen = m_head->m_pkthdr.len; 1335 f->sf_addr = vtophys(mtod(m_head, caddr_t)); 1336 frag = 1; 1337 } 1338 1339 c->sf_mbuf = m_head; 1340 c->sf_id = SF_TX_BUFDESC_ID; 1341 c->sf_fragcnt = frag; 1342 c->sf_intr = 1; 1343 c->sf_caltcp = 0; 1344 c->sf_crcen = 1; 1345 1346 return(0); 1347} 1348 1349static void 1350sf_start(ifp) 1351 struct ifnet *ifp; 1352{ 1353 struct sf_softc *sc; 1354 struct sf_tx_bufdesc_type0 *cur_tx = NULL; 1355 struct mbuf *m_head = NULL; 1356 int i, txprod; 1357 1358 sc = ifp->if_softc; 1359 SF_LOCK(sc); 1360 1361 if (!sc->sf_link && ifp->if_snd.ifq_len < 10) { 1362 SF_UNLOCK(sc); 1363 return; 1364 } 1365 1366 if (ifp->if_flags & IFF_OACTIVE) { 1367 SF_UNLOCK(sc); 1368 return; 1369 } 1370 1371 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX); 1372 i = SF_IDX_HI(txprod) >> 4; 1373 1374 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) { 1375 printf("sf%d: TX ring full, resetting\n", sc->sf_unit); 1376 sf_init(sc); 1377 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX); 1378 i = SF_IDX_HI(txprod) >> 4; 1379 } 1380 1381 while(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf == NULL) { 1382 if (sc->sf_tx_cnt >= (SF_TX_DLIST_CNT - 5)) { 1383 ifp->if_flags |= IFF_OACTIVE; 1384 cur_tx = NULL; 1385 break; 1386 } 1387 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1388 if (m_head == NULL) 1389 break; 1390 1391 cur_tx = &sc->sf_ldata->sf_tx_dlist[i]; 1392 if (sf_encap(sc, cur_tx, m_head)) { 1393 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1394 ifp->if_flags |= IFF_OACTIVE; 1395 cur_tx = NULL; 1396 break; 1397 } 1398 1399 /* 1400 * If there's a BPF listener, bounce a copy of this frame 1401 * to him. 1402 */ 1403 BPF_MTAP(ifp, m_head); 1404 1405 SF_INC(i, SF_TX_DLIST_CNT); 1406 sc->sf_tx_cnt++; 1407 /* 1408 * Don't get the TX DMA queue get too full. 1409 */ 1410 if (sc->sf_tx_cnt > 64) 1411 break; 1412 } 1413 1414 if (cur_tx == NULL) { 1415 SF_UNLOCK(sc); 1416 return; 1417 } 1418 1419 /* Transmit */ 1420 csr_write_4(sc, SF_TXDQ_PRODIDX, 1421 (txprod & ~SF_TXDQ_PRODIDX_HIPRIO) | 1422 ((i << 20) & 0xFFFF0000)); 1423 1424 ifp->if_timer = 5; 1425 1426 SF_UNLOCK(sc); 1427} 1428 1429static void 1430sf_stop(sc) 1431 struct sf_softc *sc; 1432{ 1433 int i; 1434 struct ifnet *ifp; 1435 1436 SF_LOCK(sc); 1437 1438 ifp = &sc->arpcom.ac_if; 1439 1440 untimeout(sf_stats_update, sc, sc->sf_stat_ch); 1441 1442#ifdef DEVICE_POLLING 1443 ether_poll_deregister(ifp); 1444#endif /* DEVICE_POLLING */ 1445 1446 csr_write_4(sc, SF_GEN_ETH_CTL, 0); 1447 csr_write_4(sc, SF_CQ_CONSIDX, 0); 1448 csr_write_4(sc, SF_CQ_PRODIDX, 0); 1449 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 0); 1450 csr_write_4(sc, SF_RXDQ_CTL_1, 0); 1451 csr_write_4(sc, SF_RXDQ_PTR_Q1, 0); 1452 csr_write_4(sc, SF_TXCQ_CTL, 0); 1453 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 0); 1454 csr_write_4(sc, SF_TXDQ_CTL, 0); 1455 sf_reset(sc); 1456 1457 sc->sf_link = 0; 1458 1459 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 1460 if (sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf != NULL) { 1461 m_freem(sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf); 1462 sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf = NULL; 1463 } 1464 } 1465 1466 for (i = 0; i < SF_TX_DLIST_CNT; i++) { 1467 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) { 1468 m_freem(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf); 1469 sc->sf_ldata->sf_tx_dlist[i].sf_mbuf = NULL; 1470 } 1471 } 1472 1473 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 1474 SF_UNLOCK(sc); 1475} 1476 1477/* 1478 * Note: it is important that this function not be interrupted. We 1479 * use a two-stage register access scheme: if we are interrupted in 1480 * between setting the indirect address register and reading from the 1481 * indirect data register, the contents of the address register could 1482 * be changed out from under us. 1483 */ 1484static void 1485sf_stats_update(xsc) 1486 void *xsc; 1487{ 1488 struct sf_softc *sc; 1489 struct ifnet *ifp; 1490 struct mii_data *mii; 1491 struct sf_stats stats; 1492 u_int32_t *ptr; 1493 int i; 1494 1495 sc = xsc; 1496 SF_LOCK(sc); 1497 ifp = &sc->arpcom.ac_if; 1498 mii = device_get_softc(sc->sf_miibus); 1499 1500 ptr = (u_int32_t *)&stats; 1501 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++) 1502 ptr[i] = csr_read_4(sc, SF_STATS_BASE + 1503 (i + sizeof(u_int32_t))); 1504 1505 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++) 1506 csr_write_4(sc, SF_STATS_BASE + 1507 (i + sizeof(u_int32_t)), 0); 1508 1509 ifp->if_collisions += stats.sf_tx_single_colls + 1510 stats.sf_tx_multi_colls + stats.sf_tx_excess_colls; 1511 1512 mii_tick(mii); 1513 1514 if (!sc->sf_link && mii->mii_media_status & IFM_ACTIVE && 1515 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1516 sc->sf_link++; 1517 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1518 sf_start(ifp); 1519 } 1520 1521 sc->sf_stat_ch = timeout(sf_stats_update, sc, hz); 1522 1523 SF_UNLOCK(sc); 1524} 1525 1526static void 1527sf_watchdog(ifp) 1528 struct ifnet *ifp; 1529{ 1530 struct sf_softc *sc; 1531 1532 sc = ifp->if_softc; 1533 1534 SF_LOCK(sc); 1535 1536 ifp->if_oerrors++; 1537 printf("sf%d: watchdog timeout\n", sc->sf_unit); 1538 1539 sf_stop(sc); 1540 sf_reset(sc); 1541 sf_init(sc); 1542 1543 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1544 sf_start(ifp); 1545 1546 SF_UNLOCK(sc); 1547} 1548 1549static void 1550sf_shutdown(dev) 1551 device_t dev; 1552{ 1553 struct sf_softc *sc; 1554 1555 sc = device_get_softc(dev); 1556 1557 sf_stop(sc); 1558} 1559