if_sf.c revision 131656
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/sf/if_sf.c 131656 2004-07-05 22:50:52Z bms $"); 35 36/* 37 * Adaptec AIC-6915 "Starfire" PCI fast ethernet driver for FreeBSD. 38 * Programming manual is available from: 39 * ftp.adaptec.com:/pub/BBS/userguides/aic6915_pg.pdf. 40 * 41 * Written by Bill Paul <wpaul@ctr.columbia.edu> 42 * Department of Electical Engineering 43 * Columbia University, New York City 44 */ 45/* 46 * The Adaptec AIC-6915 "Starfire" is a 64-bit 10/100 PCI ethernet 47 * controller designed with flexibility and reducing CPU load in mind. 48 * The Starfire offers high and low priority buffer queues, a 49 * producer/consumer index mechanism and several different buffer 50 * queue and completion queue descriptor types. Any one of a number 51 * of different driver designs can be used, depending on system and 52 * OS requirements. This driver makes use of type0 transmit frame 53 * descriptors (since BSD fragments packets across an mbuf chain) 54 * and two RX buffer queues prioritized on size (one queue for small 55 * frames that will fit into a single mbuf, another with full size 56 * mbuf clusters for everything else). The producer/consumer indexes 57 * and completion queues are also used. 58 * 59 * One downside to the Starfire has to do with alignment: buffer 60 * queues must be aligned on 256-byte boundaries, and receive buffers 61 * must be aligned on longword boundaries. The receive buffer alignment 62 * causes problems on the Alpha platform, where the packet payload 63 * should be longword aligned. There is no simple way around this. 64 * 65 * For receive filtering, the Starfire offers 16 perfect filter slots 66 * and a 512-bit hash table. 67 * 68 * The Starfire has no internal transceiver, relying instead on an 69 * external MII-based transceiver. Accessing registers on external 70 * PHYs is done through a special register map rather than with the 71 * usual bitbang MDIO method. 72 * 73 * Acesssing the registers on the Starfire is a little tricky. The 74 * Starfire has a 512K internal register space. When programmed for 75 * PCI memory mapped mode, the entire register space can be accessed 76 * directly. However in I/O space mode, only 256 bytes are directly 77 * mapped into PCI I/O space. The other registers can be accessed 78 * indirectly using the SF_INDIRECTIO_ADDR and SF_INDIRECTIO_DATA 79 * registers inside the 256-byte I/O window. 80 */ 81 82#include <sys/param.h> 83#include <sys/systm.h> 84#include <sys/sockio.h> 85#include <sys/mbuf.h> 86#include <sys/malloc.h> 87#include <sys/kernel.h> 88#include <sys/module.h> 89#include <sys/socket.h> 90 91#include <net/if.h> 92#include <net/if_arp.h> 93#include <net/ethernet.h> 94#include <net/if_dl.h> 95#include <net/if_media.h> 96 97#include <net/bpf.h> 98 99#include <vm/vm.h> /* for vtophys */ 100#include <vm/pmap.h> /* for vtophys */ 101#include <machine/bus_pio.h> 102#include <machine/bus_memio.h> 103#include <machine/bus.h> 104#include <machine/resource.h> 105#include <sys/bus.h> 106#include <sys/rman.h> 107 108#include <dev/mii/mii.h> 109#include <dev/mii/miivar.h> 110 111/* "controller miibus0" required. See GENERIC if you get errors here. */ 112#include "miibus_if.h" 113 114#include <dev/pci/pcireg.h> 115#include <dev/pci/pcivar.h> 116 117#define SF_USEIOSPACE 118 119#include <pci/if_sfreg.h> 120 121MODULE_DEPEND(sf, pci, 1, 1, 1); 122MODULE_DEPEND(sf, ether, 1, 1, 1); 123MODULE_DEPEND(sf, miibus, 1, 1, 1); 124 125static struct sf_type sf_devs[] = { 126 { AD_VENDORID, AD_DEVICEID_STARFIRE, 127 "Adaptec AIC-6915 10/100BaseTX" }, 128 { 0, 0, NULL } 129}; 130 131static int sf_probe (device_t); 132static int sf_attach (device_t); 133static int sf_detach (device_t); 134static void sf_intr (void *); 135static void sf_stats_update (void *); 136static void sf_rxeof (struct sf_softc *); 137static void sf_txeof (struct sf_softc *); 138static int sf_encap (struct sf_softc *, 139 struct sf_tx_bufdesc_type0 *, 140 struct mbuf *); 141static void sf_start (struct ifnet *); 142static int sf_ioctl (struct ifnet *, u_long, caddr_t); 143static void sf_init (void *); 144static void sf_stop (struct sf_softc *); 145static void sf_watchdog (struct ifnet *); 146static void sf_shutdown (device_t); 147static int sf_ifmedia_upd (struct ifnet *); 148static void sf_ifmedia_sts (struct ifnet *, struct ifmediareq *); 149static void sf_reset (struct sf_softc *); 150static int sf_init_rx_ring (struct sf_softc *); 151static void sf_init_tx_ring (struct sf_softc *); 152static int sf_newbuf (struct sf_softc *, 153 struct sf_rx_bufdesc_type0 *, 154 struct mbuf *); 155static void sf_setmulti (struct sf_softc *); 156static int sf_setperf (struct sf_softc *, int, caddr_t); 157static int sf_sethash (struct sf_softc *, caddr_t, int); 158#ifdef notdef 159static int sf_setvlan (struct sf_softc *, int, u_int32_t); 160#endif 161 162static u_int8_t sf_read_eeprom (struct sf_softc *, int); 163 164static int sf_miibus_readreg (device_t, int, int); 165static int sf_miibus_writereg (device_t, int, int, int); 166static void sf_miibus_statchg (device_t); 167 168static u_int32_t csr_read_4 (struct sf_softc *, int); 169static void csr_write_4 (struct sf_softc *, int, u_int32_t); 170static void sf_txthresh_adjust (struct sf_softc *); 171 172#ifdef SF_USEIOSPACE 173#define SF_RES SYS_RES_IOPORT 174#define SF_RID SF_PCI_LOIO 175#else 176#define SF_RES SYS_RES_MEMORY 177#define SF_RID SF_PCI_LOMEM 178#endif 179 180static device_method_t sf_methods[] = { 181 /* Device interface */ 182 DEVMETHOD(device_probe, sf_probe), 183 DEVMETHOD(device_attach, sf_attach), 184 DEVMETHOD(device_detach, sf_detach), 185 DEVMETHOD(device_shutdown, sf_shutdown), 186 187 /* bus interface */ 188 DEVMETHOD(bus_print_child, bus_generic_print_child), 189 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 190 191 /* MII interface */ 192 DEVMETHOD(miibus_readreg, sf_miibus_readreg), 193 DEVMETHOD(miibus_writereg, sf_miibus_writereg), 194 DEVMETHOD(miibus_statchg, sf_miibus_statchg), 195 196 { 0, 0 } 197}; 198 199static driver_t sf_driver = { 200 "sf", 201 sf_methods, 202 sizeof(struct sf_softc), 203}; 204 205static devclass_t sf_devclass; 206 207DRIVER_MODULE(sf, pci, sf_driver, sf_devclass, 0, 0); 208DRIVER_MODULE(miibus, sf, miibus_driver, miibus_devclass, 0, 0); 209 210#define SF_SETBIT(sc, reg, x) \ 211 csr_write_4(sc, reg, csr_read_4(sc, reg) | (x)) 212 213#define SF_CLRBIT(sc, reg, x) \ 214 csr_write_4(sc, reg, csr_read_4(sc, reg) & ~(x)) 215 216static u_int32_t 217csr_read_4(sc, reg) 218 struct sf_softc *sc; 219 int reg; 220{ 221 u_int32_t val; 222 223#ifdef SF_USEIOSPACE 224 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); 225 val = CSR_READ_4(sc, SF_INDIRECTIO_DATA); 226#else 227 val = CSR_READ_4(sc, (reg + SF_RMAP_INTREG_BASE)); 228#endif 229 230 return(val); 231} 232 233static u_int8_t 234sf_read_eeprom(sc, reg) 235 struct sf_softc *sc; 236 int reg; 237{ 238 u_int8_t val; 239 240 val = (csr_read_4(sc, SF_EEADDR_BASE + 241 (reg & 0xFFFFFFFC)) >> (8 * (reg & 3))) & 0xFF; 242 243 return(val); 244} 245 246static void 247csr_write_4(sc, reg, val) 248 struct sf_softc *sc; 249 int reg; 250 u_int32_t val; 251{ 252#ifdef SF_USEIOSPACE 253 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); 254 CSR_WRITE_4(sc, SF_INDIRECTIO_DATA, val); 255#else 256 CSR_WRITE_4(sc, (reg + SF_RMAP_INTREG_BASE), val); 257#endif 258} 259 260/* 261 * Copy the address 'mac' into the perfect RX filter entry at 262 * offset 'idx.' The perfect filter only has 16 entries so do 263 * some sanity tests. 264 */ 265static int 266sf_setperf(sc, idx, mac) 267 struct sf_softc *sc; 268 int idx; 269 caddr_t mac; 270{ 271 u_int16_t *p; 272 273 if (idx < 0 || idx > SF_RXFILT_PERFECT_CNT) 274 return(EINVAL); 275 276 if (mac == NULL) 277 return(EINVAL); 278 279 p = (u_int16_t *)mac; 280 281 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 282 (idx * SF_RXFILT_PERFECT_SKIP), htons(p[2])); 283 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 284 (idx * SF_RXFILT_PERFECT_SKIP) + 4, htons(p[1])); 285 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 286 (idx * SF_RXFILT_PERFECT_SKIP) + 8, htons(p[0])); 287 288 return(0); 289} 290 291/* 292 * Set the bit in the 512-bit hash table that corresponds to the 293 * specified mac address 'mac.' If 'prio' is nonzero, update the 294 * priority hash table instead of the filter hash table. 295 */ 296static int 297sf_sethash(sc, mac, prio) 298 struct sf_softc *sc; 299 caddr_t mac; 300 int prio; 301{ 302 u_int32_t h; 303 304 if (mac == NULL) 305 return(EINVAL); 306 307 h = ether_crc32_be(mac, ETHER_ADDR_LEN) >> 23; 308 309 if (prio) { 310 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_PRIOOFF + 311 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); 312 } else { 313 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_ADDROFF + 314 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); 315 } 316 317 return(0); 318} 319 320#ifdef notdef 321/* 322 * Set a VLAN tag in the receive filter. 323 */ 324static int 325sf_setvlan(sc, idx, vlan) 326 struct sf_softc *sc; 327 int idx; 328 u_int32_t vlan; 329{ 330 if (idx < 0 || idx >> SF_RXFILT_HASH_CNT) 331 return(EINVAL); 332 333 csr_write_4(sc, SF_RXFILT_HASH_BASE + 334 (idx * SF_RXFILT_HASH_SKIP) + SF_RXFILT_HASH_VLANOFF, vlan); 335 336 return(0); 337} 338#endif 339 340static int 341sf_miibus_readreg(dev, phy, reg) 342 device_t dev; 343 int phy, reg; 344{ 345 struct sf_softc *sc; 346 int i; 347 u_int32_t val = 0; 348 349 sc = device_get_softc(dev); 350 351 for (i = 0; i < SF_TIMEOUT; i++) { 352 val = csr_read_4(sc, SF_PHY_REG(phy, reg)); 353 if (val & SF_MII_DATAVALID) 354 break; 355 } 356 357 if (i == SF_TIMEOUT) 358 return(0); 359 360 if ((val & 0x0000FFFF) == 0xFFFF) 361 return(0); 362 363 return(val & 0x0000FFFF); 364} 365 366static int 367sf_miibus_writereg(dev, phy, reg, val) 368 device_t dev; 369 int phy, reg, val; 370{ 371 struct sf_softc *sc; 372 int i; 373 int busy; 374 375 sc = device_get_softc(dev); 376 377 csr_write_4(sc, SF_PHY_REG(phy, reg), val); 378 379 for (i = 0; i < SF_TIMEOUT; i++) { 380 busy = csr_read_4(sc, SF_PHY_REG(phy, reg)); 381 if (!(busy & SF_MII_BUSY)) 382 break; 383 } 384 385 return(0); 386} 387 388static void 389sf_miibus_statchg(dev) 390 device_t dev; 391{ 392 struct sf_softc *sc; 393 struct mii_data *mii; 394 395 sc = device_get_softc(dev); 396 mii = device_get_softc(sc->sf_miibus); 397 398 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 399 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 400 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_FDX); 401 } else { 402 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 403 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_HDX); 404 } 405} 406 407static void 408sf_setmulti(sc) 409 struct sf_softc *sc; 410{ 411 struct ifnet *ifp; 412 int i; 413 struct ifmultiaddr *ifma; 414 u_int8_t dummy[] = { 0, 0, 0, 0, 0, 0 }; 415 416 ifp = &sc->arpcom.ac_if; 417 418 /* First zot all the existing filters. */ 419 for (i = 1; i < SF_RXFILT_PERFECT_CNT; i++) 420 sf_setperf(sc, i, (char *)&dummy); 421 for (i = SF_RXFILT_HASH_BASE; 422 i < (SF_RXFILT_HASH_MAX + 1); i += 4) 423 csr_write_4(sc, i, 0); 424 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI); 425 426 /* Now program new ones. */ 427 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 428 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI); 429 } else { 430 i = 1; 431 TAILQ_FOREACH_REVERSE(ifma, &ifp->if_multiaddrs, ifmultihead, ifma_link) { 432 if (ifma->ifma_addr->sa_family != AF_LINK) 433 continue; 434 /* 435 * Program the first 15 multicast groups 436 * into the perfect filter. For all others, 437 * use the hash table. 438 */ 439 if (i < SF_RXFILT_PERFECT_CNT) { 440 sf_setperf(sc, i, 441 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 442 i++; 443 continue; 444 } 445 446 sf_sethash(sc, 447 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 0); 448 } 449 } 450} 451 452/* 453 * Set media options. 454 */ 455static int 456sf_ifmedia_upd(ifp) 457 struct ifnet *ifp; 458{ 459 struct sf_softc *sc; 460 struct mii_data *mii; 461 462 sc = ifp->if_softc; 463 mii = device_get_softc(sc->sf_miibus); 464 sc->sf_link = 0; 465 if (mii->mii_instance) { 466 struct mii_softc *miisc; 467 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 468 mii_phy_reset(miisc); 469 } 470 mii_mediachg(mii); 471 472 return(0); 473} 474 475/* 476 * Report current media status. 477 */ 478static void 479sf_ifmedia_sts(ifp, ifmr) 480 struct ifnet *ifp; 481 struct ifmediareq *ifmr; 482{ 483 struct sf_softc *sc; 484 struct mii_data *mii; 485 486 sc = ifp->if_softc; 487 mii = device_get_softc(sc->sf_miibus); 488 489 mii_pollstat(mii); 490 ifmr->ifm_active = mii->mii_media_active; 491 ifmr->ifm_status = mii->mii_media_status; 492} 493 494static int 495sf_ioctl(ifp, command, data) 496 struct ifnet *ifp; 497 u_long command; 498 caddr_t data; 499{ 500 struct sf_softc *sc = ifp->if_softc; 501 struct ifreq *ifr = (struct ifreq *) data; 502 struct mii_data *mii; 503 int error = 0; 504 505 SF_LOCK(sc); 506 507 switch(command) { 508 case SIOCSIFFLAGS: 509 if (ifp->if_flags & IFF_UP) { 510 if (ifp->if_flags & IFF_RUNNING && 511 ifp->if_flags & IFF_PROMISC && 512 !(sc->sf_if_flags & IFF_PROMISC)) { 513 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 514 } else if (ifp->if_flags & IFF_RUNNING && 515 !(ifp->if_flags & IFF_PROMISC) && 516 sc->sf_if_flags & IFF_PROMISC) { 517 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 518 } else if (!(ifp->if_flags & IFF_RUNNING)) 519 sf_init(sc); 520 } else { 521 if (ifp->if_flags & IFF_RUNNING) 522 sf_stop(sc); 523 } 524 sc->sf_if_flags = ifp->if_flags; 525 error = 0; 526 break; 527 case SIOCADDMULTI: 528 case SIOCDELMULTI: 529 sf_setmulti(sc); 530 error = 0; 531 break; 532 case SIOCGIFMEDIA: 533 case SIOCSIFMEDIA: 534 mii = device_get_softc(sc->sf_miibus); 535 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 536 break; 537 default: 538 error = ether_ioctl(ifp, command, data); 539 break; 540 } 541 542 SF_UNLOCK(sc); 543 544 return(error); 545} 546 547static void 548sf_reset(sc) 549 struct sf_softc *sc; 550{ 551 register int i; 552 553 csr_write_4(sc, SF_GEN_ETH_CTL, 0); 554 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 555 DELAY(1000); 556 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 557 558 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_RESET); 559 560 for (i = 0; i < SF_TIMEOUT; i++) { 561 DELAY(10); 562 if (!(csr_read_4(sc, SF_PCI_DEVCFG) & SF_PCIDEVCFG_RESET)) 563 break; 564 } 565 566 if (i == SF_TIMEOUT) 567 printf("sf%d: reset never completed!\n", sc->sf_unit); 568 569 /* Wait a little while for the chip to get its brains in order. */ 570 DELAY(1000); 571} 572 573/* 574 * Probe for an Adaptec AIC-6915 chip. Check the PCI vendor and device 575 * IDs against our list and return a device name if we find a match. 576 * We also check the subsystem ID so that we can identify exactly which 577 * NIC has been found, if possible. 578 */ 579static int 580sf_probe(dev) 581 device_t dev; 582{ 583 struct sf_type *t; 584 585 t = sf_devs; 586 587 while(t->sf_name != NULL) { 588 if ((pci_get_vendor(dev) == t->sf_vid) && 589 (pci_get_device(dev) == t->sf_did)) { 590 switch((pci_read_config(dev, 591 SF_PCI_SUBVEN_ID, 4) >> 16) & 0xFFFF) { 592 case AD_SUBSYSID_62011_REV0: 593 case AD_SUBSYSID_62011_REV1: 594 device_set_desc(dev, 595 "Adaptec ANA-62011 10/100BaseTX"); 596 return(0); 597 case AD_SUBSYSID_62022: 598 device_set_desc(dev, 599 "Adaptec ANA-62022 10/100BaseTX"); 600 return(0); 601 case AD_SUBSYSID_62044_REV0: 602 case AD_SUBSYSID_62044_REV1: 603 device_set_desc(dev, 604 "Adaptec ANA-62044 10/100BaseTX"); 605 return(0); 606 case AD_SUBSYSID_62020: 607 device_set_desc(dev, 608 "Adaptec ANA-62020 10/100BaseFX"); 609 return(0); 610 case AD_SUBSYSID_69011: 611 device_set_desc(dev, 612 "Adaptec ANA-69011 10/100BaseTX"); 613 return(0); 614 default: 615 device_set_desc(dev, t->sf_name); 616 return(0); 617 break; 618 } 619 } 620 t++; 621 } 622 623 return(ENXIO); 624} 625 626/* 627 * Attach the interface. Allocate softc structures, do ifmedia 628 * setup and ethernet/BPF attach. 629 */ 630static int 631sf_attach(dev) 632 device_t dev; 633{ 634 int i; 635 struct sf_softc *sc; 636 struct ifnet *ifp; 637 int unit, rid, error = 0; 638 639 sc = device_get_softc(dev); 640 unit = device_get_unit(dev); 641 642 mtx_init(&sc->sf_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 643 MTX_DEF | MTX_RECURSE); 644 /* 645 * Map control/status registers. 646 */ 647 pci_enable_busmaster(dev); 648 649 rid = SF_RID; 650 sc->sf_res = bus_alloc_resource_any(dev, SF_RES, &rid, RF_ACTIVE); 651 652 if (sc->sf_res == NULL) { 653 printf ("sf%d: couldn't map ports\n", unit); 654 error = ENXIO; 655 goto fail; 656 } 657 658 sc->sf_btag = rman_get_bustag(sc->sf_res); 659 sc->sf_bhandle = rman_get_bushandle(sc->sf_res); 660 661 /* Allocate interrupt */ 662 rid = 0; 663 sc->sf_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 664 RF_SHAREABLE | RF_ACTIVE); 665 666 if (sc->sf_irq == NULL) { 667 printf("sf%d: couldn't map interrupt\n", unit); 668 error = ENXIO; 669 goto fail; 670 } 671 672 callout_handle_init(&sc->sf_stat_ch); 673 /* Reset the adapter. */ 674 sf_reset(sc); 675 676 /* 677 * Get station address from the EEPROM. 678 */ 679 for (i = 0; i < ETHER_ADDR_LEN; i++) 680 sc->arpcom.ac_enaddr[i] = 681 sf_read_eeprom(sc, SF_EE_NODEADDR + ETHER_ADDR_LEN - i); 682 683 sc->sf_unit = unit; 684 685 /* Allocate the descriptor queues. */ 686 sc->sf_ldata = contigmalloc(sizeof(struct sf_list_data), M_DEVBUF, 687 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 688 689 if (sc->sf_ldata == NULL) { 690 printf("sf%d: no memory for list buffers!\n", unit); 691 error = ENXIO; 692 goto fail; 693 } 694 695 bzero(sc->sf_ldata, sizeof(struct sf_list_data)); 696 697 /* Do MII setup. */ 698 if (mii_phy_probe(dev, &sc->sf_miibus, 699 sf_ifmedia_upd, sf_ifmedia_sts)) { 700 printf("sf%d: MII without any phy!\n", sc->sf_unit); 701 error = ENXIO; 702 goto fail; 703 } 704 705 ifp = &sc->arpcom.ac_if; 706 ifp->if_softc = sc; 707 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 708 ifp->if_mtu = ETHERMTU; 709 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 710 ifp->if_ioctl = sf_ioctl; 711 ifp->if_start = sf_start; 712 ifp->if_watchdog = sf_watchdog; 713 ifp->if_init = sf_init; 714 ifp->if_baudrate = 10000000; 715 ifp->if_snd.ifq_maxlen = SF_TX_DLIST_CNT - 1; 716 717 /* 718 * Call MI attach routine. 719 */ 720 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 721 722 /* Hook interrupt last to avoid having to lock softc */ 723 error = bus_setup_intr(dev, sc->sf_irq, INTR_TYPE_NET, 724 sf_intr, sc, &sc->sf_intrhand); 725 726 if (error) { 727 printf("sf%d: couldn't set up irq\n", unit); 728 ether_ifdetach(ifp); 729 goto fail; 730 } 731 732fail: 733 if (error) 734 sf_detach(dev); 735 736 return(error); 737} 738 739/* 740 * Shutdown hardware and free up resources. This can be called any 741 * time after the mutex has been initialized. It is called in both 742 * the error case in attach and the normal detach case so it needs 743 * to be careful about only freeing resources that have actually been 744 * allocated. 745 */ 746static int 747sf_detach(dev) 748 device_t dev; 749{ 750 struct sf_softc *sc; 751 struct ifnet *ifp; 752 753 sc = device_get_softc(dev); 754 KASSERT(mtx_initialized(&sc->sf_mtx), ("sf mutex not initialized")); 755 SF_LOCK(sc); 756 ifp = &sc->arpcom.ac_if; 757 758 /* These should only be active if attach succeeded */ 759 if (device_is_attached(dev)) { 760 sf_stop(sc); 761 ether_ifdetach(ifp); 762 } 763 if (sc->sf_miibus) 764 device_delete_child(dev, sc->sf_miibus); 765 bus_generic_detach(dev); 766 767 if (sc->sf_intrhand) 768 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand); 769 if (sc->sf_irq) 770 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq); 771 if (sc->sf_res) 772 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 773 774 if (sc->sf_ldata) 775 contigfree(sc->sf_ldata, sizeof(struct sf_list_data), M_DEVBUF); 776 777 SF_UNLOCK(sc); 778 mtx_destroy(&sc->sf_mtx); 779 780 return(0); 781} 782 783static int 784sf_init_rx_ring(sc) 785 struct sf_softc *sc; 786{ 787 struct sf_list_data *ld; 788 int i; 789 790 ld = sc->sf_ldata; 791 792 bzero((char *)ld->sf_rx_dlist_big, 793 sizeof(struct sf_rx_bufdesc_type0) * SF_RX_DLIST_CNT); 794 bzero((char *)ld->sf_rx_clist, 795 sizeof(struct sf_rx_cmpdesc_type3) * SF_RX_CLIST_CNT); 796 797 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 798 if (sf_newbuf(sc, &ld->sf_rx_dlist_big[i], NULL) == ENOBUFS) 799 return(ENOBUFS); 800 } 801 802 return(0); 803} 804 805static void 806sf_init_tx_ring(sc) 807 struct sf_softc *sc; 808{ 809 struct sf_list_data *ld; 810 int i; 811 812 ld = sc->sf_ldata; 813 814 bzero((char *)ld->sf_tx_dlist, 815 sizeof(struct sf_tx_bufdesc_type0) * SF_TX_DLIST_CNT); 816 bzero((char *)ld->sf_tx_clist, 817 sizeof(struct sf_tx_cmpdesc_type0) * SF_TX_CLIST_CNT); 818 819 for (i = 0; i < SF_TX_DLIST_CNT; i++) 820 ld->sf_tx_dlist[i].sf_id = SF_TX_BUFDESC_ID; 821 for (i = 0; i < SF_TX_CLIST_CNT; i++) 822 ld->sf_tx_clist[i].sf_type = SF_TXCMPTYPE_TX; 823 824 ld->sf_tx_dlist[SF_TX_DLIST_CNT - 1].sf_end = 1; 825 sc->sf_tx_cnt = 0; 826} 827 828static int 829sf_newbuf(sc, c, m) 830 struct sf_softc *sc; 831 struct sf_rx_bufdesc_type0 *c; 832 struct mbuf *m; 833{ 834 struct mbuf *m_new = NULL; 835 836 if (m == NULL) { 837 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 838 if (m_new == NULL) 839 return(ENOBUFS); 840 841 MCLGET(m_new, M_DONTWAIT); 842 if (!(m_new->m_flags & M_EXT)) { 843 m_freem(m_new); 844 return(ENOBUFS); 845 } 846 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 847 } else { 848 m_new = m; 849 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 850 m_new->m_data = m_new->m_ext.ext_buf; 851 } 852 853 m_adj(m_new, sizeof(u_int64_t)); 854 855 c->sf_mbuf = m_new; 856 c->sf_addrlo = SF_RX_HOSTADDR(vtophys(mtod(m_new, caddr_t))); 857 c->sf_valid = 1; 858 859 return(0); 860} 861 862/* 863 * The starfire is programmed to use 'normal' mode for packet reception, 864 * which means we use the consumer/producer model for both the buffer 865 * descriptor queue and the completion descriptor queue. The only problem 866 * with this is that it involves a lot of register accesses: we have to 867 * read the RX completion consumer and producer indexes and the RX buffer 868 * producer index, plus the RX completion consumer and RX buffer producer 869 * indexes have to be updated. It would have been easier if Adaptec had 870 * put each index in a separate register, especially given that the damn 871 * NIC has a 512K register space. 872 * 873 * In spite of all the lovely features that Adaptec crammed into the 6915, 874 * it is marred by one truly stupid design flaw, which is that receive 875 * buffer addresses must be aligned on a longword boundary. This forces 876 * the packet payload to be unaligned, which is suboptimal on the x86 and 877 * completely unuseable on the Alpha. Our only recourse is to copy received 878 * packets into properly aligned buffers before handing them off. 879 */ 880 881static void 882sf_rxeof(sc) 883 struct sf_softc *sc; 884{ 885 struct mbuf *m; 886 struct ifnet *ifp; 887 struct sf_rx_bufdesc_type0 *desc; 888 struct sf_rx_cmpdesc_type3 *cur_rx; 889 u_int32_t rxcons, rxprod; 890 int cmpprodidx, cmpconsidx, bufprodidx; 891 892 SF_LOCK_ASSERT(sc); 893 894 ifp = &sc->arpcom.ac_if; 895 896 rxcons = csr_read_4(sc, SF_CQ_CONSIDX); 897 rxprod = csr_read_4(sc, SF_RXDQ_PTR_Q1); 898 cmpprodidx = SF_IDX_LO(csr_read_4(sc, SF_CQ_PRODIDX)); 899 cmpconsidx = SF_IDX_LO(rxcons); 900 bufprodidx = SF_IDX_LO(rxprod); 901 902 while (cmpconsidx != cmpprodidx) { 903 struct mbuf *m0; 904 905 cur_rx = &sc->sf_ldata->sf_rx_clist[cmpconsidx]; 906 desc = &sc->sf_ldata->sf_rx_dlist_big[cur_rx->sf_endidx]; 907 m = desc->sf_mbuf; 908 SF_INC(cmpconsidx, SF_RX_CLIST_CNT); 909 SF_INC(bufprodidx, SF_RX_DLIST_CNT); 910 911 if (!(cur_rx->sf_status1 & SF_RXSTAT1_OK)) { 912 ifp->if_ierrors++; 913 sf_newbuf(sc, desc, m); 914 continue; 915 } 916 917 m0 = m_devget(mtod(m, char *), cur_rx->sf_len, ETHER_ALIGN, 918 ifp, NULL); 919 sf_newbuf(sc, desc, m); 920 if (m0 == NULL) { 921 ifp->if_ierrors++; 922 continue; 923 } 924 m = m0; 925 926 ifp->if_ipackets++; 927 SF_UNLOCK(sc); 928 (*ifp->if_input)(ifp, m); 929 SF_LOCK(sc); 930 } 931 932 csr_write_4(sc, SF_CQ_CONSIDX, 933 (rxcons & ~SF_CQ_CONSIDX_RXQ1) | cmpconsidx); 934 csr_write_4(sc, SF_RXDQ_PTR_Q1, 935 (rxprod & ~SF_RXDQ_PRODIDX) | bufprodidx); 936} 937 938/* 939 * Read the transmit status from the completion queue and release 940 * mbufs. Note that the buffer descriptor index in the completion 941 * descriptor is an offset from the start of the transmit buffer 942 * descriptor list in bytes. This is important because the manual 943 * gives the impression that it should match the producer/consumer 944 * index, which is the offset in 8 byte blocks. 945 */ 946static void 947sf_txeof(sc) 948 struct sf_softc *sc; 949{ 950 int txcons, cmpprodidx, cmpconsidx; 951 struct sf_tx_cmpdesc_type1 *cur_cmp; 952 struct sf_tx_bufdesc_type0 *cur_tx; 953 struct ifnet *ifp; 954 955 ifp = &sc->arpcom.ac_if; 956 957 txcons = csr_read_4(sc, SF_CQ_CONSIDX); 958 cmpprodidx = SF_IDX_HI(csr_read_4(sc, SF_CQ_PRODIDX)); 959 cmpconsidx = SF_IDX_HI(txcons); 960 961 while (cmpconsidx != cmpprodidx) { 962 cur_cmp = &sc->sf_ldata->sf_tx_clist[cmpconsidx]; 963 cur_tx = &sc->sf_ldata->sf_tx_dlist[cur_cmp->sf_index >> 7]; 964 965 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_OK) 966 ifp->if_opackets++; 967 else { 968 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_UNDERRUN) 969 sf_txthresh_adjust(sc); 970 ifp->if_oerrors++; 971 } 972 973 sc->sf_tx_cnt--; 974 if (cur_tx->sf_mbuf != NULL) { 975 m_freem(cur_tx->sf_mbuf); 976 cur_tx->sf_mbuf = NULL; 977 } else 978 break; 979 SF_INC(cmpconsidx, SF_TX_CLIST_CNT); 980 } 981 982 ifp->if_timer = 0; 983 ifp->if_flags &= ~IFF_OACTIVE; 984 985 csr_write_4(sc, SF_CQ_CONSIDX, 986 (txcons & ~SF_CQ_CONSIDX_TXQ) | 987 ((cmpconsidx << 16) & 0xFFFF0000)); 988} 989 990static void 991sf_txthresh_adjust(sc) 992 struct sf_softc *sc; 993{ 994 u_int32_t txfctl; 995 u_int8_t txthresh; 996 997 txfctl = csr_read_4(sc, SF_TX_FRAMCTL); 998 txthresh = txfctl & SF_TXFRMCTL_TXTHRESH; 999 if (txthresh < 0xFF) { 1000 txthresh++; 1001 txfctl &= ~SF_TXFRMCTL_TXTHRESH; 1002 txfctl |= txthresh; 1003#ifdef DIAGNOSTIC 1004 printf("sf%d: tx underrun, increasing " 1005 "tx threshold to %d bytes\n", 1006 sc->sf_unit, txthresh * 4); 1007#endif 1008 csr_write_4(sc, SF_TX_FRAMCTL, txfctl); 1009 } 1010} 1011 1012static void 1013sf_intr(arg) 1014 void *arg; 1015{ 1016 struct sf_softc *sc; 1017 struct ifnet *ifp; 1018 u_int32_t status; 1019 1020 sc = arg; 1021 SF_LOCK(sc); 1022 1023 ifp = &sc->arpcom.ac_if; 1024 1025 if (!(csr_read_4(sc, SF_ISR_SHADOW) & SF_ISR_PCIINT_ASSERTED)) { 1026 SF_UNLOCK(sc); 1027 return; 1028 } 1029 1030 /* Disable interrupts. */ 1031 csr_write_4(sc, SF_IMR, 0x00000000); 1032 1033 for (;;) { 1034 status = csr_read_4(sc, SF_ISR); 1035 if (status) 1036 csr_write_4(sc, SF_ISR, status); 1037 1038 if (!(status & SF_INTRS)) 1039 break; 1040 1041 if (status & SF_ISR_RXDQ1_DMADONE) 1042 sf_rxeof(sc); 1043 1044 if (status & SF_ISR_TX_TXDONE || 1045 status & SF_ISR_TX_DMADONE || 1046 status & SF_ISR_TX_QUEUEDONE) 1047 sf_txeof(sc); 1048 1049 if (status & SF_ISR_TX_LOFIFO) 1050 sf_txthresh_adjust(sc); 1051 1052 if (status & SF_ISR_ABNORMALINTR) { 1053 if (status & SF_ISR_STATSOFLOW) { 1054 untimeout(sf_stats_update, sc, 1055 sc->sf_stat_ch); 1056 sf_stats_update(sc); 1057 } else 1058 sf_init(sc); 1059 } 1060 } 1061 1062 /* Re-enable interrupts. */ 1063 csr_write_4(sc, SF_IMR, SF_INTRS); 1064 1065 if (ifp->if_snd.ifq_head != NULL) 1066 sf_start(ifp); 1067 1068 SF_UNLOCK(sc); 1069} 1070 1071static void 1072sf_init(xsc) 1073 void *xsc; 1074{ 1075 struct sf_softc *sc; 1076 struct ifnet *ifp; 1077 struct mii_data *mii; 1078 int i; 1079 1080 sc = xsc; 1081 SF_LOCK(sc); 1082 ifp = &sc->arpcom.ac_if; 1083 mii = device_get_softc(sc->sf_miibus); 1084 1085 sf_stop(sc); 1086 sf_reset(sc); 1087 1088 /* Init all the receive filter registers */ 1089 for (i = SF_RXFILT_PERFECT_BASE; 1090 i < (SF_RXFILT_HASH_MAX + 1); i += 4) 1091 csr_write_4(sc, i, 0); 1092 1093 /* Empty stats counter registers. */ 1094 for (i = 0; i < sizeof(struct sf_stats)/sizeof(u_int32_t); i++) 1095 csr_write_4(sc, SF_STATS_BASE + 1096 (i + sizeof(u_int32_t)), 0); 1097 1098 /* Init our MAC address */ 1099 csr_write_4(sc, SF_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1100 csr_write_4(sc, SF_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1101 sf_setperf(sc, 0, (caddr_t)&sc->arpcom.ac_enaddr); 1102 1103 if (sf_init_rx_ring(sc) == ENOBUFS) { 1104 printf("sf%d: initialization failed: no " 1105 "memory for rx buffers\n", sc->sf_unit); 1106 SF_UNLOCK(sc); 1107 return; 1108 } 1109 1110 sf_init_tx_ring(sc); 1111 1112 csr_write_4(sc, SF_RXFILT, SF_PERFMODE_NORMAL|SF_HASHMODE_WITHVLAN); 1113 1114 /* If we want promiscuous mode, set the allframes bit. */ 1115 if (ifp->if_flags & IFF_PROMISC) { 1116 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 1117 } else { 1118 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 1119 } 1120 1121 if (ifp->if_flags & IFF_BROADCAST) { 1122 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_BROAD); 1123 } else { 1124 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_BROAD); 1125 } 1126 1127 /* 1128 * Load the multicast filter. 1129 */ 1130 sf_setmulti(sc); 1131 1132 /* Init the completion queue indexes */ 1133 csr_write_4(sc, SF_CQ_CONSIDX, 0); 1134 csr_write_4(sc, SF_CQ_PRODIDX, 0); 1135 1136 /* Init the RX completion queue */ 1137 csr_write_4(sc, SF_RXCQ_CTL_1, 1138 vtophys(sc->sf_ldata->sf_rx_clist) & SF_RXCQ_ADDR); 1139 SF_SETBIT(sc, SF_RXCQ_CTL_1, SF_RXCQTYPE_3); 1140 1141 /* Init RX DMA control. */ 1142 SF_SETBIT(sc, SF_RXDMA_CTL, SF_RXDMA_REPORTBADPKTS); 1143 1144 /* Init the RX buffer descriptor queue. */ 1145 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 1146 vtophys(sc->sf_ldata->sf_rx_dlist_big)); 1147 csr_write_4(sc, SF_RXDQ_CTL_1, (MCLBYTES << 16) | SF_DESCSPACE_16BYTES); 1148 csr_write_4(sc, SF_RXDQ_PTR_Q1, SF_RX_DLIST_CNT - 1); 1149 1150 /* Init the TX completion queue */ 1151 csr_write_4(sc, SF_TXCQ_CTL, 1152 vtophys(sc->sf_ldata->sf_tx_clist) & SF_RXCQ_ADDR); 1153 1154 /* Init the TX buffer descriptor queue. */ 1155 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 1156 vtophys(sc->sf_ldata->sf_tx_dlist)); 1157 SF_SETBIT(sc, SF_TX_FRAMCTL, SF_TXFRMCTL_CPLAFTERTX); 1158 csr_write_4(sc, SF_TXDQ_CTL, 1159 SF_TXBUFDESC_TYPE0|SF_TXMINSPACE_128BYTES|SF_TXSKIPLEN_8BYTES); 1160 SF_SETBIT(sc, SF_TXDQ_CTL, SF_TXDQCTL_NODMACMP); 1161 1162 /* Enable autopadding of short TX frames. */ 1163 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_AUTOPAD); 1164 1165 /* Enable interrupts. */ 1166 csr_write_4(sc, SF_IMR, SF_INTRS); 1167 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_INTR_ENB); 1168 1169 /* Enable the RX and TX engines. */ 1170 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_RX_ENB|SF_ETHCTL_RXDMA_ENB); 1171 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_TX_ENB|SF_ETHCTL_TXDMA_ENB); 1172 1173 /*mii_mediachg(mii);*/ 1174 sf_ifmedia_upd(ifp); 1175 1176 ifp->if_flags |= IFF_RUNNING; 1177 ifp->if_flags &= ~IFF_OACTIVE; 1178 1179 sc->sf_stat_ch = timeout(sf_stats_update, sc, hz); 1180 1181 SF_UNLOCK(sc); 1182} 1183 1184static int 1185sf_encap(sc, c, m_head) 1186 struct sf_softc *sc; 1187 struct sf_tx_bufdesc_type0 *c; 1188 struct mbuf *m_head; 1189{ 1190 int frag = 0; 1191 struct sf_frag *f = NULL; 1192 struct mbuf *m; 1193 1194 m = m_head; 1195 1196 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1197 if (m->m_len != 0) { 1198 if (frag == SF_MAXFRAGS) 1199 break; 1200 f = &c->sf_frags[frag]; 1201 if (frag == 0) 1202 f->sf_pktlen = m_head->m_pkthdr.len; 1203 f->sf_fraglen = m->m_len; 1204 f->sf_addr = vtophys(mtod(m, vm_offset_t)); 1205 frag++; 1206 } 1207 } 1208 1209 if (m != NULL) { 1210 struct mbuf *m_new = NULL; 1211 1212 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1213 if (m_new == NULL) { 1214 printf("sf%d: no memory for tx list\n", sc->sf_unit); 1215 return(1); 1216 } 1217 1218 if (m_head->m_pkthdr.len > MHLEN) { 1219 MCLGET(m_new, M_DONTWAIT); 1220 if (!(m_new->m_flags & M_EXT)) { 1221 m_freem(m_new); 1222 printf("sf%d: no memory for tx list\n", 1223 sc->sf_unit); 1224 return(1); 1225 } 1226 } 1227 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1228 mtod(m_new, caddr_t)); 1229 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1230 m_freem(m_head); 1231 m_head = m_new; 1232 f = &c->sf_frags[0]; 1233 f->sf_fraglen = f->sf_pktlen = m_head->m_pkthdr.len; 1234 f->sf_addr = vtophys(mtod(m_head, caddr_t)); 1235 frag = 1; 1236 } 1237 1238 c->sf_mbuf = m_head; 1239 c->sf_id = SF_TX_BUFDESC_ID; 1240 c->sf_fragcnt = frag; 1241 c->sf_intr = 1; 1242 c->sf_caltcp = 0; 1243 c->sf_crcen = 1; 1244 1245 return(0); 1246} 1247 1248static void 1249sf_start(ifp) 1250 struct ifnet *ifp; 1251{ 1252 struct sf_softc *sc; 1253 struct sf_tx_bufdesc_type0 *cur_tx = NULL; 1254 struct mbuf *m_head = NULL; 1255 int i, txprod; 1256 1257 sc = ifp->if_softc; 1258 SF_LOCK(sc); 1259 1260 if (!sc->sf_link && ifp->if_snd.ifq_len < 10) { 1261 SF_UNLOCK(sc); 1262 return; 1263 } 1264 1265 if (ifp->if_flags & IFF_OACTIVE) { 1266 SF_UNLOCK(sc); 1267 return; 1268 } 1269 1270 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX); 1271 i = SF_IDX_HI(txprod) >> 4; 1272 1273 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) { 1274 printf("sf%d: TX ring full, resetting\n", sc->sf_unit); 1275 sf_init(sc); 1276 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX); 1277 i = SF_IDX_HI(txprod) >> 4; 1278 } 1279 1280 while(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf == NULL) { 1281 if (sc->sf_tx_cnt >= (SF_TX_DLIST_CNT - 5)) { 1282 ifp->if_flags |= IFF_OACTIVE; 1283 cur_tx = NULL; 1284 break; 1285 } 1286 IF_DEQUEUE(&ifp->if_snd, m_head); 1287 if (m_head == NULL) 1288 break; 1289 1290 cur_tx = &sc->sf_ldata->sf_tx_dlist[i]; 1291 if (sf_encap(sc, cur_tx, m_head)) { 1292 IF_PREPEND(&ifp->if_snd, m_head); 1293 ifp->if_flags |= IFF_OACTIVE; 1294 cur_tx = NULL; 1295 break; 1296 } 1297 1298 /* 1299 * If there's a BPF listener, bounce a copy of this frame 1300 * to him. 1301 */ 1302 BPF_MTAP(ifp, m_head); 1303 1304 SF_INC(i, SF_TX_DLIST_CNT); 1305 sc->sf_tx_cnt++; 1306 /* 1307 * Don't get the TX DMA queue get too full. 1308 */ 1309 if (sc->sf_tx_cnt > 64) 1310 break; 1311 } 1312 1313 if (cur_tx == NULL) { 1314 SF_UNLOCK(sc); 1315 return; 1316 } 1317 1318 /* Transmit */ 1319 csr_write_4(sc, SF_TXDQ_PRODIDX, 1320 (txprod & ~SF_TXDQ_PRODIDX_HIPRIO) | 1321 ((i << 20) & 0xFFFF0000)); 1322 1323 ifp->if_timer = 5; 1324 1325 SF_UNLOCK(sc); 1326} 1327 1328static void 1329sf_stop(sc) 1330 struct sf_softc *sc; 1331{ 1332 int i; 1333 struct ifnet *ifp; 1334 1335 SF_LOCK(sc); 1336 1337 ifp = &sc->arpcom.ac_if; 1338 1339 untimeout(sf_stats_update, sc, sc->sf_stat_ch); 1340 1341 csr_write_4(sc, SF_GEN_ETH_CTL, 0); 1342 csr_write_4(sc, SF_CQ_CONSIDX, 0); 1343 csr_write_4(sc, SF_CQ_PRODIDX, 0); 1344 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 0); 1345 csr_write_4(sc, SF_RXDQ_CTL_1, 0); 1346 csr_write_4(sc, SF_RXDQ_PTR_Q1, 0); 1347 csr_write_4(sc, SF_TXCQ_CTL, 0); 1348 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 0); 1349 csr_write_4(sc, SF_TXDQ_CTL, 0); 1350 sf_reset(sc); 1351 1352 sc->sf_link = 0; 1353 1354 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 1355 if (sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf != NULL) { 1356 m_freem(sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf); 1357 sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf = NULL; 1358 } 1359 } 1360 1361 for (i = 0; i < SF_TX_DLIST_CNT; i++) { 1362 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) { 1363 m_freem(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf); 1364 sc->sf_ldata->sf_tx_dlist[i].sf_mbuf = NULL; 1365 } 1366 } 1367 1368 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 1369 SF_UNLOCK(sc); 1370} 1371 1372/* 1373 * Note: it is important that this function not be interrupted. We 1374 * use a two-stage register access scheme: if we are interrupted in 1375 * between setting the indirect address register and reading from the 1376 * indirect data register, the contents of the address register could 1377 * be changed out from under us. 1378 */ 1379static void 1380sf_stats_update(xsc) 1381 void *xsc; 1382{ 1383 struct sf_softc *sc; 1384 struct ifnet *ifp; 1385 struct mii_data *mii; 1386 struct sf_stats stats; 1387 u_int32_t *ptr; 1388 int i; 1389 1390 sc = xsc; 1391 SF_LOCK(sc); 1392 ifp = &sc->arpcom.ac_if; 1393 mii = device_get_softc(sc->sf_miibus); 1394 1395 ptr = (u_int32_t *)&stats; 1396 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++) 1397 ptr[i] = csr_read_4(sc, SF_STATS_BASE + 1398 (i + sizeof(u_int32_t))); 1399 1400 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++) 1401 csr_write_4(sc, SF_STATS_BASE + 1402 (i + sizeof(u_int32_t)), 0); 1403 1404 ifp->if_collisions += stats.sf_tx_single_colls + 1405 stats.sf_tx_multi_colls + stats.sf_tx_excess_colls; 1406 1407 mii_tick(mii); 1408 1409 if (!sc->sf_link && mii->mii_media_status & IFM_ACTIVE && 1410 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1411 sc->sf_link++; 1412 if (ifp->if_snd.ifq_head != NULL) 1413 sf_start(ifp); 1414 } 1415 1416 sc->sf_stat_ch = timeout(sf_stats_update, sc, hz); 1417 1418 SF_UNLOCK(sc); 1419} 1420 1421static void 1422sf_watchdog(ifp) 1423 struct ifnet *ifp; 1424{ 1425 struct sf_softc *sc; 1426 1427 sc = ifp->if_softc; 1428 1429 SF_LOCK(sc); 1430 1431 ifp->if_oerrors++; 1432 printf("sf%d: watchdog timeout\n", sc->sf_unit); 1433 1434 sf_stop(sc); 1435 sf_reset(sc); 1436 sf_init(sc); 1437 1438 if (ifp->if_snd.ifq_head != NULL) 1439 sf_start(ifp); 1440 1441 SF_UNLOCK(sc); 1442} 1443 1444static void 1445sf_shutdown(dev) 1446 device_t dev; 1447{ 1448 struct sf_softc *sc; 1449 1450 sc = device_get_softc(dev); 1451 1452 sf_stop(sc); 1453} 1454