if_sf.c revision 131253
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/sf/if_sf.c 131253 2004-06-28 20:07:03Z imp $"); 35 36/* 37 * Adaptec AIC-6915 "Starfire" PCI fast ethernet driver for FreeBSD. 38 * Programming manual is available from: 39 * ftp.adaptec.com:/pub/BBS/userguides/aic6915_pg.pdf. 40 * 41 * Written by Bill Paul <wpaul@ctr.columbia.edu> 42 * Department of Electical Engineering 43 * Columbia University, New York City 44 */ 45/* 46 * The Adaptec AIC-6915 "Starfire" is a 64-bit 10/100 PCI ethernet 47 * controller designed with flexibility and reducing CPU load in mind. 48 * The Starfire offers high and low priority buffer queues, a 49 * producer/consumer index mechanism and several different buffer 50 * queue and completion queue descriptor types. Any one of a number 51 * of different driver designs can be used, depending on system and 52 * OS requirements. This driver makes use of type0 transmit frame 53 * descriptors (since BSD fragments packets across an mbuf chain) 54 * and two RX buffer queues prioritized on size (one queue for small 55 * frames that will fit into a single mbuf, another with full size 56 * mbuf clusters for everything else). The producer/consumer indexes 57 * and completion queues are also used. 58 * 59 * One downside to the Starfire has to do with alignment: buffer 60 * queues must be aligned on 256-byte boundaries, and receive buffers 61 * must be aligned on longword boundaries. The receive buffer alignment 62 * causes problems on the Alpha platform, where the packet payload 63 * should be longword aligned. There is no simple way around this. 64 * 65 * For receive filtering, the Starfire offers 16 perfect filter slots 66 * and a 512-bit hash table. 67 * 68 * The Starfire has no internal transceiver, relying instead on an 69 * external MII-based transceiver. Accessing registers on external 70 * PHYs is done through a special register map rather than with the 71 * usual bitbang MDIO method. 72 * 73 * Acesssing the registers on the Starfire is a little tricky. The 74 * Starfire has a 512K internal register space. When programmed for 75 * PCI memory mapped mode, the entire register space can be accessed 76 * directly. However in I/O space mode, only 256 bytes are directly 77 * mapped into PCI I/O space. The other registers can be accessed 78 * indirectly using the SF_INDIRECTIO_ADDR and SF_INDIRECTIO_DATA 79 * registers inside the 256-byte I/O window. 80 */ 81 82#include <sys/param.h> 83#include <sys/systm.h> 84#include <sys/sockio.h> 85#include <sys/mbuf.h> 86#include <sys/malloc.h> 87#include <sys/kernel.h> 88#include <sys/module.h> 89#include <sys/socket.h> 90 91#include <net/if.h> 92#include <net/if_arp.h> 93#include <net/ethernet.h> 94#include <net/if_dl.h> 95#include <net/if_media.h> 96 97#include <net/bpf.h> 98 99#include <vm/vm.h> /* for vtophys */ 100#include <vm/pmap.h> /* for vtophys */ 101#include <machine/bus_pio.h> 102#include <machine/bus_memio.h> 103#include <machine/bus.h> 104#include <machine/resource.h> 105#include <sys/bus.h> 106#include <sys/rman.h> 107 108#include <dev/mii/mii.h> 109#include <dev/mii/miivar.h> 110 111/* "controller miibus0" required. See GENERIC if you get errors here. */ 112#include "miibus_if.h" 113 114#include <dev/pci/pcireg.h> 115#include <dev/pci/pcivar.h> 116 117#define SF_USEIOSPACE 118 119#include <pci/if_sfreg.h> 120 121MODULE_DEPEND(sf, pci, 1, 1, 1); 122MODULE_DEPEND(sf, ether, 1, 1, 1); 123MODULE_DEPEND(sf, miibus, 1, 1, 1); 124 125static struct sf_type sf_devs[] = { 126 { AD_VENDORID, AD_DEVICEID_STARFIRE, 127 "Adaptec AIC-6915 10/100BaseTX" }, 128 { 0, 0, NULL } 129}; 130 131static int sf_probe (device_t); 132static int sf_attach (device_t); 133static int sf_detach (device_t); 134static void sf_intr (void *); 135static void sf_stats_update (void *); 136static void sf_rxeof (struct sf_softc *); 137static void sf_txeof (struct sf_softc *); 138static int sf_encap (struct sf_softc *, 139 struct sf_tx_bufdesc_type0 *, 140 struct mbuf *); 141static void sf_start (struct ifnet *); 142static int sf_ioctl (struct ifnet *, u_long, caddr_t); 143static void sf_init (void *); 144static void sf_stop (struct sf_softc *); 145static void sf_watchdog (struct ifnet *); 146static void sf_shutdown (device_t); 147static int sf_ifmedia_upd (struct ifnet *); 148static void sf_ifmedia_sts (struct ifnet *, struct ifmediareq *); 149static void sf_reset (struct sf_softc *); 150static int sf_init_rx_ring (struct sf_softc *); 151static void sf_init_tx_ring (struct sf_softc *); 152static int sf_newbuf (struct sf_softc *, 153 struct sf_rx_bufdesc_type0 *, 154 struct mbuf *); 155static void sf_setmulti (struct sf_softc *); 156static int sf_setperf (struct sf_softc *, int, caddr_t); 157static int sf_sethash (struct sf_softc *, caddr_t, int); 158#ifdef notdef 159static int sf_setvlan (struct sf_softc *, int, u_int32_t); 160#endif 161 162static u_int8_t sf_read_eeprom (struct sf_softc *, int); 163 164static int sf_miibus_readreg (device_t, int, int); 165static int sf_miibus_writereg (device_t, int, int, int); 166static void sf_miibus_statchg (device_t); 167 168static u_int32_t csr_read_4 (struct sf_softc *, int); 169static void csr_write_4 (struct sf_softc *, int, u_int32_t); 170static void sf_txthresh_adjust (struct sf_softc *); 171 172#ifdef SF_USEIOSPACE 173#define SF_RES SYS_RES_IOPORT 174#define SF_RID SF_PCI_LOIO 175#else 176#define SF_RES SYS_RES_MEMORY 177#define SF_RID SF_PCI_LOMEM 178#endif 179 180static device_method_t sf_methods[] = { 181 /* Device interface */ 182 DEVMETHOD(device_probe, sf_probe), 183 DEVMETHOD(device_attach, sf_attach), 184 DEVMETHOD(device_detach, sf_detach), 185 DEVMETHOD(device_shutdown, sf_shutdown), 186 187 /* bus interface */ 188 DEVMETHOD(bus_print_child, bus_generic_print_child), 189 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 190 191 /* MII interface */ 192 DEVMETHOD(miibus_readreg, sf_miibus_readreg), 193 DEVMETHOD(miibus_writereg, sf_miibus_writereg), 194 DEVMETHOD(miibus_statchg, sf_miibus_statchg), 195 196 { 0, 0 } 197}; 198 199static driver_t sf_driver = { 200 "sf", 201 sf_methods, 202 sizeof(struct sf_softc), 203}; 204 205static devclass_t sf_devclass; 206 207DRIVER_MODULE(sf, pci, sf_driver, sf_devclass, 0, 0); 208DRIVER_MODULE(miibus, sf, miibus_driver, miibus_devclass, 0, 0); 209 210#define SF_SETBIT(sc, reg, x) \ 211 csr_write_4(sc, reg, csr_read_4(sc, reg) | (x)) 212 213#define SF_CLRBIT(sc, reg, x) \ 214 csr_write_4(sc, reg, csr_read_4(sc, reg) & ~(x)) 215 216static u_int32_t 217csr_read_4(sc, reg) 218 struct sf_softc *sc; 219 int reg; 220{ 221 u_int32_t val; 222 223#ifdef SF_USEIOSPACE 224 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); 225 val = CSR_READ_4(sc, SF_INDIRECTIO_DATA); 226#else 227 val = CSR_READ_4(sc, (reg + SF_RMAP_INTREG_BASE)); 228#endif 229 230 return(val); 231} 232 233static u_int8_t 234sf_read_eeprom(sc, reg) 235 struct sf_softc *sc; 236 int reg; 237{ 238 u_int8_t val; 239 240 val = (csr_read_4(sc, SF_EEADDR_BASE + 241 (reg & 0xFFFFFFFC)) >> (8 * (reg & 3))) & 0xFF; 242 243 return(val); 244} 245 246static void 247csr_write_4(sc, reg, val) 248 struct sf_softc *sc; 249 int reg; 250 u_int32_t val; 251{ 252#ifdef SF_USEIOSPACE 253 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); 254 CSR_WRITE_4(sc, SF_INDIRECTIO_DATA, val); 255#else 256 CSR_WRITE_4(sc, (reg + SF_RMAP_INTREG_BASE), val); 257#endif 258 return; 259} 260 261/* 262 * Copy the address 'mac' into the perfect RX filter entry at 263 * offset 'idx.' The perfect filter only has 16 entries so do 264 * some sanity tests. 265 */ 266static int 267sf_setperf(sc, idx, mac) 268 struct sf_softc *sc; 269 int idx; 270 caddr_t mac; 271{ 272 u_int16_t *p; 273 274 if (idx < 0 || idx > SF_RXFILT_PERFECT_CNT) 275 return(EINVAL); 276 277 if (mac == NULL) 278 return(EINVAL); 279 280 p = (u_int16_t *)mac; 281 282 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 283 (idx * SF_RXFILT_PERFECT_SKIP), htons(p[2])); 284 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 285 (idx * SF_RXFILT_PERFECT_SKIP) + 4, htons(p[1])); 286 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 287 (idx * SF_RXFILT_PERFECT_SKIP) + 8, htons(p[0])); 288 289 return(0); 290} 291 292/* 293 * Set the bit in the 512-bit hash table that corresponds to the 294 * specified mac address 'mac.' If 'prio' is nonzero, update the 295 * priority hash table instead of the filter hash table. 296 */ 297static int 298sf_sethash(sc, mac, prio) 299 struct sf_softc *sc; 300 caddr_t mac; 301 int prio; 302{ 303 u_int32_t h; 304 305 if (mac == NULL) 306 return(EINVAL); 307 308 h = ether_crc32_be(mac, ETHER_ADDR_LEN) >> 23; 309 310 if (prio) { 311 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_PRIOOFF + 312 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); 313 } else { 314 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_ADDROFF + 315 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); 316 } 317 318 return(0); 319} 320 321#ifdef notdef 322/* 323 * Set a VLAN tag in the receive filter. 324 */ 325static int 326sf_setvlan(sc, idx, vlan) 327 struct sf_softc *sc; 328 int idx; 329 u_int32_t vlan; 330{ 331 if (idx < 0 || idx >> SF_RXFILT_HASH_CNT) 332 return(EINVAL); 333 334 csr_write_4(sc, SF_RXFILT_HASH_BASE + 335 (idx * SF_RXFILT_HASH_SKIP) + SF_RXFILT_HASH_VLANOFF, vlan); 336 337 return(0); 338} 339#endif 340 341static int 342sf_miibus_readreg(dev, phy, reg) 343 device_t dev; 344 int phy, reg; 345{ 346 struct sf_softc *sc; 347 int i; 348 u_int32_t val = 0; 349 350 sc = device_get_softc(dev); 351 352 for (i = 0; i < SF_TIMEOUT; i++) { 353 val = csr_read_4(sc, SF_PHY_REG(phy, reg)); 354 if (val & SF_MII_DATAVALID) 355 break; 356 } 357 358 if (i == SF_TIMEOUT) 359 return(0); 360 361 if ((val & 0x0000FFFF) == 0xFFFF) 362 return(0); 363 364 return(val & 0x0000FFFF); 365} 366 367static int 368sf_miibus_writereg(dev, phy, reg, val) 369 device_t dev; 370 int phy, reg, val; 371{ 372 struct sf_softc *sc; 373 int i; 374 int busy; 375 376 sc = device_get_softc(dev); 377 378 csr_write_4(sc, SF_PHY_REG(phy, reg), val); 379 380 for (i = 0; i < SF_TIMEOUT; i++) { 381 busy = csr_read_4(sc, SF_PHY_REG(phy, reg)); 382 if (!(busy & SF_MII_BUSY)) 383 break; 384 } 385 386 return(0); 387} 388 389static void 390sf_miibus_statchg(dev) 391 device_t dev; 392{ 393 struct sf_softc *sc; 394 struct mii_data *mii; 395 396 sc = device_get_softc(dev); 397 mii = device_get_softc(sc->sf_miibus); 398 399 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 400 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 401 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_FDX); 402 } else { 403 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 404 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_HDX); 405 } 406 407 return; 408} 409 410static void 411sf_setmulti(sc) 412 struct sf_softc *sc; 413{ 414 struct ifnet *ifp; 415 int i; 416 struct ifmultiaddr *ifma; 417 u_int8_t dummy[] = { 0, 0, 0, 0, 0, 0 }; 418 419 ifp = &sc->arpcom.ac_if; 420 421 /* First zot all the existing filters. */ 422 for (i = 1; i < SF_RXFILT_PERFECT_CNT; i++) 423 sf_setperf(sc, i, (char *)&dummy); 424 for (i = SF_RXFILT_HASH_BASE; 425 i < (SF_RXFILT_HASH_MAX + 1); i += 4) 426 csr_write_4(sc, i, 0); 427 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI); 428 429 /* Now program new ones. */ 430 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 431 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI); 432 } else { 433 i = 1; 434 TAILQ_FOREACH_REVERSE(ifma, &ifp->if_multiaddrs, ifmultihead, ifma_link) { 435 if (ifma->ifma_addr->sa_family != AF_LINK) 436 continue; 437 /* 438 * Program the first 15 multicast groups 439 * into the perfect filter. For all others, 440 * use the hash table. 441 */ 442 if (i < SF_RXFILT_PERFECT_CNT) { 443 sf_setperf(sc, i, 444 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 445 i++; 446 continue; 447 } 448 449 sf_sethash(sc, 450 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 0); 451 } 452 } 453 454 return; 455} 456 457/* 458 * Set media options. 459 */ 460static int 461sf_ifmedia_upd(ifp) 462 struct ifnet *ifp; 463{ 464 struct sf_softc *sc; 465 struct mii_data *mii; 466 467 sc = ifp->if_softc; 468 mii = device_get_softc(sc->sf_miibus); 469 sc->sf_link = 0; 470 if (mii->mii_instance) { 471 struct mii_softc *miisc; 472 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 473 mii_phy_reset(miisc); 474 } 475 mii_mediachg(mii); 476 477 return(0); 478} 479 480/* 481 * Report current media status. 482 */ 483static void 484sf_ifmedia_sts(ifp, ifmr) 485 struct ifnet *ifp; 486 struct ifmediareq *ifmr; 487{ 488 struct sf_softc *sc; 489 struct mii_data *mii; 490 491 sc = ifp->if_softc; 492 mii = device_get_softc(sc->sf_miibus); 493 494 mii_pollstat(mii); 495 ifmr->ifm_active = mii->mii_media_active; 496 ifmr->ifm_status = mii->mii_media_status; 497 498 return; 499} 500 501static int 502sf_ioctl(ifp, command, data) 503 struct ifnet *ifp; 504 u_long command; 505 caddr_t data; 506{ 507 struct sf_softc *sc = ifp->if_softc; 508 struct ifreq *ifr = (struct ifreq *) data; 509 struct mii_data *mii; 510 int error = 0; 511 512 SF_LOCK(sc); 513 514 switch(command) { 515 case SIOCSIFFLAGS: 516 if (ifp->if_flags & IFF_UP) { 517 if (ifp->if_flags & IFF_RUNNING && 518 ifp->if_flags & IFF_PROMISC && 519 !(sc->sf_if_flags & IFF_PROMISC)) { 520 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 521 } else if (ifp->if_flags & IFF_RUNNING && 522 !(ifp->if_flags & IFF_PROMISC) && 523 sc->sf_if_flags & IFF_PROMISC) { 524 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 525 } else if (!(ifp->if_flags & IFF_RUNNING)) 526 sf_init(sc); 527 } else { 528 if (ifp->if_flags & IFF_RUNNING) 529 sf_stop(sc); 530 } 531 sc->sf_if_flags = ifp->if_flags; 532 error = 0; 533 break; 534 case SIOCADDMULTI: 535 case SIOCDELMULTI: 536 sf_setmulti(sc); 537 error = 0; 538 break; 539 case SIOCGIFMEDIA: 540 case SIOCSIFMEDIA: 541 mii = device_get_softc(sc->sf_miibus); 542 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 543 break; 544 default: 545 error = ether_ioctl(ifp, command, data); 546 break; 547 } 548 549 SF_UNLOCK(sc); 550 551 return(error); 552} 553 554static void 555sf_reset(sc) 556 struct sf_softc *sc; 557{ 558 register int i; 559 560 csr_write_4(sc, SF_GEN_ETH_CTL, 0); 561 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 562 DELAY(1000); 563 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 564 565 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_RESET); 566 567 for (i = 0; i < SF_TIMEOUT; i++) { 568 DELAY(10); 569 if (!(csr_read_4(sc, SF_PCI_DEVCFG) & SF_PCIDEVCFG_RESET)) 570 break; 571 } 572 573 if (i == SF_TIMEOUT) 574 printf("sf%d: reset never completed!\n", sc->sf_unit); 575 576 /* Wait a little while for the chip to get its brains in order. */ 577 DELAY(1000); 578 return; 579} 580 581/* 582 * Probe for an Adaptec AIC-6915 chip. Check the PCI vendor and device 583 * IDs against our list and return a device name if we find a match. 584 * We also check the subsystem ID so that we can identify exactly which 585 * NIC has been found, if possible. 586 */ 587static int 588sf_probe(dev) 589 device_t dev; 590{ 591 struct sf_type *t; 592 593 t = sf_devs; 594 595 while(t->sf_name != NULL) { 596 if ((pci_get_vendor(dev) == t->sf_vid) && 597 (pci_get_device(dev) == t->sf_did)) { 598 switch((pci_read_config(dev, 599 SF_PCI_SUBVEN_ID, 4) >> 16) & 0xFFFF) { 600 case AD_SUBSYSID_62011_REV0: 601 case AD_SUBSYSID_62011_REV1: 602 device_set_desc(dev, 603 "Adaptec ANA-62011 10/100BaseTX"); 604 return(0); 605 case AD_SUBSYSID_62022: 606 device_set_desc(dev, 607 "Adaptec ANA-62022 10/100BaseTX"); 608 return(0); 609 case AD_SUBSYSID_62044_REV0: 610 case AD_SUBSYSID_62044_REV1: 611 device_set_desc(dev, 612 "Adaptec ANA-62044 10/100BaseTX"); 613 return(0); 614 case AD_SUBSYSID_62020: 615 device_set_desc(dev, 616 "Adaptec ANA-62020 10/100BaseFX"); 617 return(0); 618 case AD_SUBSYSID_69011: 619 device_set_desc(dev, 620 "Adaptec ANA-69011 10/100BaseTX"); 621 return(0); 622 default: 623 device_set_desc(dev, t->sf_name); 624 return(0); 625 break; 626 } 627 } 628 t++; 629 } 630 631 return(ENXIO); 632} 633 634/* 635 * Attach the interface. Allocate softc structures, do ifmedia 636 * setup and ethernet/BPF attach. 637 */ 638static int 639sf_attach(dev) 640 device_t dev; 641{ 642 int i; 643 struct sf_softc *sc; 644 struct ifnet *ifp; 645 int unit, rid, error = 0; 646 647 sc = device_get_softc(dev); 648 unit = device_get_unit(dev); 649 650 mtx_init(&sc->sf_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 651 MTX_DEF | MTX_RECURSE); 652 /* 653 * Map control/status registers. 654 */ 655 pci_enable_busmaster(dev); 656 657 rid = SF_RID; 658 sc->sf_res = bus_alloc_resource_any(dev, SF_RES, &rid, RF_ACTIVE); 659 660 if (sc->sf_res == NULL) { 661 printf ("sf%d: couldn't map ports\n", unit); 662 error = ENXIO; 663 goto fail; 664 } 665 666 sc->sf_btag = rman_get_bustag(sc->sf_res); 667 sc->sf_bhandle = rman_get_bushandle(sc->sf_res); 668 669 /* Allocate interrupt */ 670 rid = 0; 671 sc->sf_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 672 RF_SHAREABLE | RF_ACTIVE); 673 674 if (sc->sf_irq == NULL) { 675 printf("sf%d: couldn't map interrupt\n", unit); 676 error = ENXIO; 677 goto fail; 678 } 679 680 callout_handle_init(&sc->sf_stat_ch); 681 /* Reset the adapter. */ 682 sf_reset(sc); 683 684 /* 685 * Get station address from the EEPROM. 686 */ 687 for (i = 0; i < ETHER_ADDR_LEN; i++) 688 sc->arpcom.ac_enaddr[i] = 689 sf_read_eeprom(sc, SF_EE_NODEADDR + ETHER_ADDR_LEN - i); 690 691 sc->sf_unit = unit; 692 693 /* Allocate the descriptor queues. */ 694 sc->sf_ldata = contigmalloc(sizeof(struct sf_list_data), M_DEVBUF, 695 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 696 697 if (sc->sf_ldata == NULL) { 698 printf("sf%d: no memory for list buffers!\n", unit); 699 error = ENXIO; 700 goto fail; 701 } 702 703 bzero(sc->sf_ldata, sizeof(struct sf_list_data)); 704 705 /* Do MII setup. */ 706 if (mii_phy_probe(dev, &sc->sf_miibus, 707 sf_ifmedia_upd, sf_ifmedia_sts)) { 708 printf("sf%d: MII without any phy!\n", sc->sf_unit); 709 error = ENXIO; 710 goto fail; 711 } 712 713 ifp = &sc->arpcom.ac_if; 714 ifp->if_softc = sc; 715 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 716 ifp->if_mtu = ETHERMTU; 717 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 718 ifp->if_ioctl = sf_ioctl; 719 ifp->if_start = sf_start; 720 ifp->if_watchdog = sf_watchdog; 721 ifp->if_init = sf_init; 722 ifp->if_baudrate = 10000000; 723 ifp->if_snd.ifq_maxlen = SF_TX_DLIST_CNT - 1; 724 725 /* 726 * Call MI attach routine. 727 */ 728 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 729 730 /* Hook interrupt last to avoid having to lock softc */ 731 error = bus_setup_intr(dev, sc->sf_irq, INTR_TYPE_NET, 732 sf_intr, sc, &sc->sf_intrhand); 733 734 if (error) { 735 printf("sf%d: couldn't set up irq\n", unit); 736 ether_ifdetach(ifp); 737 goto fail; 738 } 739 740fail: 741 if (error) 742 sf_detach(dev); 743 744 return(error); 745} 746 747/* 748 * Shutdown hardware and free up resources. This can be called any 749 * time after the mutex has been initialized. It is called in both 750 * the error case in attach and the normal detach case so it needs 751 * to be careful about only freeing resources that have actually been 752 * allocated. 753 */ 754static int 755sf_detach(dev) 756 device_t dev; 757{ 758 struct sf_softc *sc; 759 struct ifnet *ifp; 760 761 sc = device_get_softc(dev); 762 KASSERT(mtx_initialized(&sc->sf_mtx), ("sf mutex not initialized")); 763 SF_LOCK(sc); 764 ifp = &sc->arpcom.ac_if; 765 766 /* These should only be active if attach succeeded */ 767 if (device_is_attached(dev)) { 768 sf_stop(sc); 769 ether_ifdetach(ifp); 770 } 771 if (sc->sf_miibus) 772 device_delete_child(dev, sc->sf_miibus); 773 bus_generic_detach(dev); 774 775 if (sc->sf_intrhand) 776 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand); 777 if (sc->sf_irq) 778 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq); 779 if (sc->sf_res) 780 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 781 782 if (sc->sf_ldata) 783 contigfree(sc->sf_ldata, sizeof(struct sf_list_data), M_DEVBUF); 784 785 SF_UNLOCK(sc); 786 mtx_destroy(&sc->sf_mtx); 787 788 return(0); 789} 790 791static int 792sf_init_rx_ring(sc) 793 struct sf_softc *sc; 794{ 795 struct sf_list_data *ld; 796 int i; 797 798 ld = sc->sf_ldata; 799 800 bzero((char *)ld->sf_rx_dlist_big, 801 sizeof(struct sf_rx_bufdesc_type0) * SF_RX_DLIST_CNT); 802 bzero((char *)ld->sf_rx_clist, 803 sizeof(struct sf_rx_cmpdesc_type3) * SF_RX_CLIST_CNT); 804 805 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 806 if (sf_newbuf(sc, &ld->sf_rx_dlist_big[i], NULL) == ENOBUFS) 807 return(ENOBUFS); 808 } 809 810 return(0); 811} 812 813static void 814sf_init_tx_ring(sc) 815 struct sf_softc *sc; 816{ 817 struct sf_list_data *ld; 818 int i; 819 820 ld = sc->sf_ldata; 821 822 bzero((char *)ld->sf_tx_dlist, 823 sizeof(struct sf_tx_bufdesc_type0) * SF_TX_DLIST_CNT); 824 bzero((char *)ld->sf_tx_clist, 825 sizeof(struct sf_tx_cmpdesc_type0) * SF_TX_CLIST_CNT); 826 827 for (i = 0; i < SF_TX_DLIST_CNT; i++) 828 ld->sf_tx_dlist[i].sf_id = SF_TX_BUFDESC_ID; 829 for (i = 0; i < SF_TX_CLIST_CNT; i++) 830 ld->sf_tx_clist[i].sf_type = SF_TXCMPTYPE_TX; 831 832 ld->sf_tx_dlist[SF_TX_DLIST_CNT - 1].sf_end = 1; 833 sc->sf_tx_cnt = 0; 834 835 return; 836} 837 838static int 839sf_newbuf(sc, c, m) 840 struct sf_softc *sc; 841 struct sf_rx_bufdesc_type0 *c; 842 struct mbuf *m; 843{ 844 struct mbuf *m_new = NULL; 845 846 if (m == NULL) { 847 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 848 if (m_new == NULL) 849 return(ENOBUFS); 850 851 MCLGET(m_new, M_DONTWAIT); 852 if (!(m_new->m_flags & M_EXT)) { 853 m_freem(m_new); 854 return(ENOBUFS); 855 } 856 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 857 } else { 858 m_new = m; 859 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 860 m_new->m_data = m_new->m_ext.ext_buf; 861 } 862 863 m_adj(m_new, sizeof(u_int64_t)); 864 865 c->sf_mbuf = m_new; 866 c->sf_addrlo = SF_RX_HOSTADDR(vtophys(mtod(m_new, caddr_t))); 867 c->sf_valid = 1; 868 869 return(0); 870} 871 872/* 873 * The starfire is programmed to use 'normal' mode for packet reception, 874 * which means we use the consumer/producer model for both the buffer 875 * descriptor queue and the completion descriptor queue. The only problem 876 * with this is that it involves a lot of register accesses: we have to 877 * read the RX completion consumer and producer indexes and the RX buffer 878 * producer index, plus the RX completion consumer and RX buffer producer 879 * indexes have to be updated. It would have been easier if Adaptec had 880 * put each index in a separate register, especially given that the damn 881 * NIC has a 512K register space. 882 * 883 * In spite of all the lovely features that Adaptec crammed into the 6915, 884 * it is marred by one truly stupid design flaw, which is that receive 885 * buffer addresses must be aligned on a longword boundary. This forces 886 * the packet payload to be unaligned, which is suboptimal on the x86 and 887 * completely unuseable on the Alpha. Our only recourse is to copy received 888 * packets into properly aligned buffers before handing them off. 889 */ 890 891static void 892sf_rxeof(sc) 893 struct sf_softc *sc; 894{ 895 struct mbuf *m; 896 struct ifnet *ifp; 897 struct sf_rx_bufdesc_type0 *desc; 898 struct sf_rx_cmpdesc_type3 *cur_rx; 899 u_int32_t rxcons, rxprod; 900 int cmpprodidx, cmpconsidx, bufprodidx; 901 902 SF_LOCK_ASSERT(sc); 903 904 ifp = &sc->arpcom.ac_if; 905 906 rxcons = csr_read_4(sc, SF_CQ_CONSIDX); 907 rxprod = csr_read_4(sc, SF_RXDQ_PTR_Q1); 908 cmpprodidx = SF_IDX_LO(csr_read_4(sc, SF_CQ_PRODIDX)); 909 cmpconsidx = SF_IDX_LO(rxcons); 910 bufprodidx = SF_IDX_LO(rxprod); 911 912 while (cmpconsidx != cmpprodidx) { 913 struct mbuf *m0; 914 915 cur_rx = &sc->sf_ldata->sf_rx_clist[cmpconsidx]; 916 desc = &sc->sf_ldata->sf_rx_dlist_big[cur_rx->sf_endidx]; 917 m = desc->sf_mbuf; 918 SF_INC(cmpconsidx, SF_RX_CLIST_CNT); 919 SF_INC(bufprodidx, SF_RX_DLIST_CNT); 920 921 if (!(cur_rx->sf_status1 & SF_RXSTAT1_OK)) { 922 ifp->if_ierrors++; 923 sf_newbuf(sc, desc, m); 924 continue; 925 } 926 927 m0 = m_devget(mtod(m, char *), cur_rx->sf_len, ETHER_ALIGN, 928 ifp, NULL); 929 sf_newbuf(sc, desc, m); 930 if (m0 == NULL) { 931 ifp->if_ierrors++; 932 continue; 933 } 934 m = m0; 935 936 ifp->if_ipackets++; 937 SF_UNLOCK(sc); 938 (*ifp->if_input)(ifp, m); 939 SF_LOCK(sc); 940 } 941 942 csr_write_4(sc, SF_CQ_CONSIDX, 943 (rxcons & ~SF_CQ_CONSIDX_RXQ1) | cmpconsidx); 944 csr_write_4(sc, SF_RXDQ_PTR_Q1, 945 (rxprod & ~SF_RXDQ_PRODIDX) | bufprodidx); 946 947 return; 948} 949 950/* 951 * Read the transmit status from the completion queue and release 952 * mbufs. Note that the buffer descriptor index in the completion 953 * descriptor is an offset from the start of the transmit buffer 954 * descriptor list in bytes. This is important because the manual 955 * gives the impression that it should match the producer/consumer 956 * index, which is the offset in 8 byte blocks. 957 */ 958static void 959sf_txeof(sc) 960 struct sf_softc *sc; 961{ 962 int txcons, cmpprodidx, cmpconsidx; 963 struct sf_tx_cmpdesc_type1 *cur_cmp; 964 struct sf_tx_bufdesc_type0 *cur_tx; 965 struct ifnet *ifp; 966 967 ifp = &sc->arpcom.ac_if; 968 969 txcons = csr_read_4(sc, SF_CQ_CONSIDX); 970 cmpprodidx = SF_IDX_HI(csr_read_4(sc, SF_CQ_PRODIDX)); 971 cmpconsidx = SF_IDX_HI(txcons); 972 973 while (cmpconsidx != cmpprodidx) { 974 cur_cmp = &sc->sf_ldata->sf_tx_clist[cmpconsidx]; 975 cur_tx = &sc->sf_ldata->sf_tx_dlist[cur_cmp->sf_index >> 7]; 976 977 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_OK) 978 ifp->if_opackets++; 979 else { 980 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_UNDERRUN) 981 sf_txthresh_adjust(sc); 982 ifp->if_oerrors++; 983 } 984 985 sc->sf_tx_cnt--; 986 if (cur_tx->sf_mbuf != NULL) { 987 m_freem(cur_tx->sf_mbuf); 988 cur_tx->sf_mbuf = NULL; 989 } else 990 break; 991 SF_INC(cmpconsidx, SF_TX_CLIST_CNT); 992 } 993 994 ifp->if_timer = 0; 995 ifp->if_flags &= ~IFF_OACTIVE; 996 997 csr_write_4(sc, SF_CQ_CONSIDX, 998 (txcons & ~SF_CQ_CONSIDX_TXQ) | 999 ((cmpconsidx << 16) & 0xFFFF0000)); 1000 1001 return; 1002} 1003 1004static void 1005sf_txthresh_adjust(sc) 1006 struct sf_softc *sc; 1007{ 1008 u_int32_t txfctl; 1009 u_int8_t txthresh; 1010 1011 txfctl = csr_read_4(sc, SF_TX_FRAMCTL); 1012 txthresh = txfctl & SF_TXFRMCTL_TXTHRESH; 1013 if (txthresh < 0xFF) { 1014 txthresh++; 1015 txfctl &= ~SF_TXFRMCTL_TXTHRESH; 1016 txfctl |= txthresh; 1017#ifdef DIAGNOSTIC 1018 printf("sf%d: tx underrun, increasing " 1019 "tx threshold to %d bytes\n", 1020 sc->sf_unit, txthresh * 4); 1021#endif 1022 csr_write_4(sc, SF_TX_FRAMCTL, txfctl); 1023 } 1024 1025 return; 1026} 1027 1028static void 1029sf_intr(arg) 1030 void *arg; 1031{ 1032 struct sf_softc *sc; 1033 struct ifnet *ifp; 1034 u_int32_t status; 1035 1036 sc = arg; 1037 SF_LOCK(sc); 1038 1039 ifp = &sc->arpcom.ac_if; 1040 1041 if (!(csr_read_4(sc, SF_ISR_SHADOW) & SF_ISR_PCIINT_ASSERTED)) { 1042 SF_UNLOCK(sc); 1043 return; 1044 } 1045 1046 /* Disable interrupts. */ 1047 csr_write_4(sc, SF_IMR, 0x00000000); 1048 1049 for (;;) { 1050 status = csr_read_4(sc, SF_ISR); 1051 if (status) 1052 csr_write_4(sc, SF_ISR, status); 1053 1054 if (!(status & SF_INTRS)) 1055 break; 1056 1057 if (status & SF_ISR_RXDQ1_DMADONE) 1058 sf_rxeof(sc); 1059 1060 if (status & SF_ISR_TX_TXDONE || 1061 status & SF_ISR_TX_DMADONE || 1062 status & SF_ISR_TX_QUEUEDONE) 1063 sf_txeof(sc); 1064 1065 if (status & SF_ISR_TX_LOFIFO) 1066 sf_txthresh_adjust(sc); 1067 1068 if (status & SF_ISR_ABNORMALINTR) { 1069 if (status & SF_ISR_STATSOFLOW) { 1070 untimeout(sf_stats_update, sc, 1071 sc->sf_stat_ch); 1072 sf_stats_update(sc); 1073 } else 1074 sf_init(sc); 1075 } 1076 } 1077 1078 /* Re-enable interrupts. */ 1079 csr_write_4(sc, SF_IMR, SF_INTRS); 1080 1081 if (ifp->if_snd.ifq_head != NULL) 1082 sf_start(ifp); 1083 1084 SF_UNLOCK(sc); 1085 return; 1086} 1087 1088static void 1089sf_init(xsc) 1090 void *xsc; 1091{ 1092 struct sf_softc *sc; 1093 struct ifnet *ifp; 1094 struct mii_data *mii; 1095 int i; 1096 1097 sc = xsc; 1098 SF_LOCK(sc); 1099 ifp = &sc->arpcom.ac_if; 1100 mii = device_get_softc(sc->sf_miibus); 1101 1102 sf_stop(sc); 1103 sf_reset(sc); 1104 1105 /* Init all the receive filter registers */ 1106 for (i = SF_RXFILT_PERFECT_BASE; 1107 i < (SF_RXFILT_HASH_MAX + 1); i += 4) 1108 csr_write_4(sc, i, 0); 1109 1110 /* Empty stats counter registers. */ 1111 for (i = 0; i < sizeof(struct sf_stats)/sizeof(u_int32_t); i++) 1112 csr_write_4(sc, SF_STATS_BASE + 1113 (i + sizeof(u_int32_t)), 0); 1114 1115 /* Init our MAC address */ 1116 csr_write_4(sc, SF_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1117 csr_write_4(sc, SF_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1118 sf_setperf(sc, 0, (caddr_t)&sc->arpcom.ac_enaddr); 1119 1120 if (sf_init_rx_ring(sc) == ENOBUFS) { 1121 printf("sf%d: initialization failed: no " 1122 "memory for rx buffers\n", sc->sf_unit); 1123 SF_UNLOCK(sc); 1124 return; 1125 } 1126 1127 sf_init_tx_ring(sc); 1128 1129 csr_write_4(sc, SF_RXFILT, SF_PERFMODE_NORMAL|SF_HASHMODE_WITHVLAN); 1130 1131 /* If we want promiscuous mode, set the allframes bit. */ 1132 if (ifp->if_flags & IFF_PROMISC) { 1133 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 1134 } else { 1135 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 1136 } 1137 1138 if (ifp->if_flags & IFF_BROADCAST) { 1139 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_BROAD); 1140 } else { 1141 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_BROAD); 1142 } 1143 1144 /* 1145 * Load the multicast filter. 1146 */ 1147 sf_setmulti(sc); 1148 1149 /* Init the completion queue indexes */ 1150 csr_write_4(sc, SF_CQ_CONSIDX, 0); 1151 csr_write_4(sc, SF_CQ_PRODIDX, 0); 1152 1153 /* Init the RX completion queue */ 1154 csr_write_4(sc, SF_RXCQ_CTL_1, 1155 vtophys(sc->sf_ldata->sf_rx_clist) & SF_RXCQ_ADDR); 1156 SF_SETBIT(sc, SF_RXCQ_CTL_1, SF_RXCQTYPE_3); 1157 1158 /* Init RX DMA control. */ 1159 SF_SETBIT(sc, SF_RXDMA_CTL, SF_RXDMA_REPORTBADPKTS); 1160 1161 /* Init the RX buffer descriptor queue. */ 1162 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 1163 vtophys(sc->sf_ldata->sf_rx_dlist_big)); 1164 csr_write_4(sc, SF_RXDQ_CTL_1, (MCLBYTES << 16) | SF_DESCSPACE_16BYTES); 1165 csr_write_4(sc, SF_RXDQ_PTR_Q1, SF_RX_DLIST_CNT - 1); 1166 1167 /* Init the TX completion queue */ 1168 csr_write_4(sc, SF_TXCQ_CTL, 1169 vtophys(sc->sf_ldata->sf_tx_clist) & SF_RXCQ_ADDR); 1170 1171 /* Init the TX buffer descriptor queue. */ 1172 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 1173 vtophys(sc->sf_ldata->sf_tx_dlist)); 1174 SF_SETBIT(sc, SF_TX_FRAMCTL, SF_TXFRMCTL_CPLAFTERTX); 1175 csr_write_4(sc, SF_TXDQ_CTL, 1176 SF_TXBUFDESC_TYPE0|SF_TXMINSPACE_128BYTES|SF_TXSKIPLEN_8BYTES); 1177 SF_SETBIT(sc, SF_TXDQ_CTL, SF_TXDQCTL_NODMACMP); 1178 1179 /* Enable autopadding of short TX frames. */ 1180 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_AUTOPAD); 1181 1182 /* Enable interrupts. */ 1183 csr_write_4(sc, SF_IMR, SF_INTRS); 1184 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_INTR_ENB); 1185 1186 /* Enable the RX and TX engines. */ 1187 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_RX_ENB|SF_ETHCTL_RXDMA_ENB); 1188 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_TX_ENB|SF_ETHCTL_TXDMA_ENB); 1189 1190 /*mii_mediachg(mii);*/ 1191 sf_ifmedia_upd(ifp); 1192 1193 ifp->if_flags |= IFF_RUNNING; 1194 ifp->if_flags &= ~IFF_OACTIVE; 1195 1196 sc->sf_stat_ch = timeout(sf_stats_update, sc, hz); 1197 1198 SF_UNLOCK(sc); 1199 1200 return; 1201} 1202 1203static int 1204sf_encap(sc, c, m_head) 1205 struct sf_softc *sc; 1206 struct sf_tx_bufdesc_type0 *c; 1207 struct mbuf *m_head; 1208{ 1209 int frag = 0; 1210 struct sf_frag *f = NULL; 1211 struct mbuf *m; 1212 1213 m = m_head; 1214 1215 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1216 if (m->m_len != 0) { 1217 if (frag == SF_MAXFRAGS) 1218 break; 1219 f = &c->sf_frags[frag]; 1220 if (frag == 0) 1221 f->sf_pktlen = m_head->m_pkthdr.len; 1222 f->sf_fraglen = m->m_len; 1223 f->sf_addr = vtophys(mtod(m, vm_offset_t)); 1224 frag++; 1225 } 1226 } 1227 1228 if (m != NULL) { 1229 struct mbuf *m_new = NULL; 1230 1231 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1232 if (m_new == NULL) { 1233 printf("sf%d: no memory for tx list\n", sc->sf_unit); 1234 return(1); 1235 } 1236 1237 if (m_head->m_pkthdr.len > MHLEN) { 1238 MCLGET(m_new, M_DONTWAIT); 1239 if (!(m_new->m_flags & M_EXT)) { 1240 m_freem(m_new); 1241 printf("sf%d: no memory for tx list\n", 1242 sc->sf_unit); 1243 return(1); 1244 } 1245 } 1246 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1247 mtod(m_new, caddr_t)); 1248 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1249 m_freem(m_head); 1250 m_head = m_new; 1251 f = &c->sf_frags[0]; 1252 f->sf_fraglen = f->sf_pktlen = m_head->m_pkthdr.len; 1253 f->sf_addr = vtophys(mtod(m_head, caddr_t)); 1254 frag = 1; 1255 } 1256 1257 c->sf_mbuf = m_head; 1258 c->sf_id = SF_TX_BUFDESC_ID; 1259 c->sf_fragcnt = frag; 1260 c->sf_intr = 1; 1261 c->sf_caltcp = 0; 1262 c->sf_crcen = 1; 1263 1264 return(0); 1265} 1266 1267static void 1268sf_start(ifp) 1269 struct ifnet *ifp; 1270{ 1271 struct sf_softc *sc; 1272 struct sf_tx_bufdesc_type0 *cur_tx = NULL; 1273 struct mbuf *m_head = NULL; 1274 int i, txprod; 1275 1276 sc = ifp->if_softc; 1277 SF_LOCK(sc); 1278 1279 if (!sc->sf_link && ifp->if_snd.ifq_len < 10) { 1280 SF_UNLOCK(sc); 1281 return; 1282 } 1283 1284 if (ifp->if_flags & IFF_OACTIVE) { 1285 SF_UNLOCK(sc); 1286 return; 1287 } 1288 1289 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX); 1290 i = SF_IDX_HI(txprod) >> 4; 1291 1292 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) { 1293 printf("sf%d: TX ring full, resetting\n", sc->sf_unit); 1294 sf_init(sc); 1295 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX); 1296 i = SF_IDX_HI(txprod) >> 4; 1297 } 1298 1299 while(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf == NULL) { 1300 if (sc->sf_tx_cnt >= (SF_TX_DLIST_CNT - 5)) { 1301 ifp->if_flags |= IFF_OACTIVE; 1302 cur_tx = NULL; 1303 break; 1304 } 1305 IF_DEQUEUE(&ifp->if_snd, m_head); 1306 if (m_head == NULL) 1307 break; 1308 1309 cur_tx = &sc->sf_ldata->sf_tx_dlist[i]; 1310 if (sf_encap(sc, cur_tx, m_head)) { 1311 IF_PREPEND(&ifp->if_snd, m_head); 1312 ifp->if_flags |= IFF_OACTIVE; 1313 cur_tx = NULL; 1314 break; 1315 } 1316 1317 /* 1318 * If there's a BPF listener, bounce a copy of this frame 1319 * to him. 1320 */ 1321 BPF_MTAP(ifp, m_head); 1322 1323 SF_INC(i, SF_TX_DLIST_CNT); 1324 sc->sf_tx_cnt++; 1325 /* 1326 * Don't get the TX DMA queue get too full. 1327 */ 1328 if (sc->sf_tx_cnt > 64) 1329 break; 1330 } 1331 1332 if (cur_tx == NULL) { 1333 SF_UNLOCK(sc); 1334 return; 1335 } 1336 1337 /* Transmit */ 1338 csr_write_4(sc, SF_TXDQ_PRODIDX, 1339 (txprod & ~SF_TXDQ_PRODIDX_HIPRIO) | 1340 ((i << 20) & 0xFFFF0000)); 1341 1342 ifp->if_timer = 5; 1343 1344 SF_UNLOCK(sc); 1345 1346 return; 1347} 1348 1349static void 1350sf_stop(sc) 1351 struct sf_softc *sc; 1352{ 1353 int i; 1354 struct ifnet *ifp; 1355 1356 SF_LOCK(sc); 1357 1358 ifp = &sc->arpcom.ac_if; 1359 1360 untimeout(sf_stats_update, sc, sc->sf_stat_ch); 1361 1362 csr_write_4(sc, SF_GEN_ETH_CTL, 0); 1363 csr_write_4(sc, SF_CQ_CONSIDX, 0); 1364 csr_write_4(sc, SF_CQ_PRODIDX, 0); 1365 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 0); 1366 csr_write_4(sc, SF_RXDQ_CTL_1, 0); 1367 csr_write_4(sc, SF_RXDQ_PTR_Q1, 0); 1368 csr_write_4(sc, SF_TXCQ_CTL, 0); 1369 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 0); 1370 csr_write_4(sc, SF_TXDQ_CTL, 0); 1371 sf_reset(sc); 1372 1373 sc->sf_link = 0; 1374 1375 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 1376 if (sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf != NULL) { 1377 m_freem(sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf); 1378 sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf = NULL; 1379 } 1380 } 1381 1382 for (i = 0; i < SF_TX_DLIST_CNT; i++) { 1383 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) { 1384 m_freem(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf); 1385 sc->sf_ldata->sf_tx_dlist[i].sf_mbuf = NULL; 1386 } 1387 } 1388 1389 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 1390 SF_UNLOCK(sc); 1391 1392 return; 1393} 1394 1395/* 1396 * Note: it is important that this function not be interrupted. We 1397 * use a two-stage register access scheme: if we are interrupted in 1398 * between setting the indirect address register and reading from the 1399 * indirect data register, the contents of the address register could 1400 * be changed out from under us. 1401 */ 1402static void 1403sf_stats_update(xsc) 1404 void *xsc; 1405{ 1406 struct sf_softc *sc; 1407 struct ifnet *ifp; 1408 struct mii_data *mii; 1409 struct sf_stats stats; 1410 u_int32_t *ptr; 1411 int i; 1412 1413 sc = xsc; 1414 SF_LOCK(sc); 1415 ifp = &sc->arpcom.ac_if; 1416 mii = device_get_softc(sc->sf_miibus); 1417 1418 ptr = (u_int32_t *)&stats; 1419 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++) 1420 ptr[i] = csr_read_4(sc, SF_STATS_BASE + 1421 (i + sizeof(u_int32_t))); 1422 1423 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++) 1424 csr_write_4(sc, SF_STATS_BASE + 1425 (i + sizeof(u_int32_t)), 0); 1426 1427 ifp->if_collisions += stats.sf_tx_single_colls + 1428 stats.sf_tx_multi_colls + stats.sf_tx_excess_colls; 1429 1430 mii_tick(mii); 1431 1432 if (!sc->sf_link && mii->mii_media_status & IFM_ACTIVE && 1433 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1434 sc->sf_link++; 1435 if (ifp->if_snd.ifq_head != NULL) 1436 sf_start(ifp); 1437 } 1438 1439 sc->sf_stat_ch = timeout(sf_stats_update, sc, hz); 1440 1441 SF_UNLOCK(sc); 1442 1443 return; 1444} 1445 1446static void 1447sf_watchdog(ifp) 1448 struct ifnet *ifp; 1449{ 1450 struct sf_softc *sc; 1451 1452 sc = ifp->if_softc; 1453 1454 SF_LOCK(sc); 1455 1456 ifp->if_oerrors++; 1457 printf("sf%d: watchdog timeout\n", sc->sf_unit); 1458 1459 sf_stop(sc); 1460 sf_reset(sc); 1461 sf_init(sc); 1462 1463 if (ifp->if_snd.ifq_head != NULL) 1464 sf_start(ifp); 1465 1466 SF_UNLOCK(sc); 1467 1468 return; 1469} 1470 1471static void 1472sf_shutdown(dev) 1473 device_t dev; 1474{ 1475 struct sf_softc *sc; 1476 1477 sc = device_get_softc(dev); 1478 1479 sf_stop(sc); 1480 1481 return; 1482} 1483