if_sf.c revision 130270
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/sf/if_sf.c 130270 2004-06-09 14:34:04Z naddy $"); 35 36/* 37 * Adaptec AIC-6915 "Starfire" PCI fast ethernet driver for FreeBSD. 38 * Programming manual is available from: 39 * ftp.adaptec.com:/pub/BBS/userguides/aic6915_pg.pdf. 40 * 41 * Written by Bill Paul <wpaul@ctr.columbia.edu> 42 * Department of Electical Engineering 43 * Columbia University, New York City 44 */ 45/* 46 * The Adaptec AIC-6915 "Starfire" is a 64-bit 10/100 PCI ethernet 47 * controller designed with flexibility and reducing CPU load in mind. 48 * The Starfire offers high and low priority buffer queues, a 49 * producer/consumer index mechanism and several different buffer 50 * queue and completion queue descriptor types. Any one of a number 51 * of different driver designs can be used, depending on system and 52 * OS requirements. This driver makes use of type0 transmit frame 53 * descriptors (since BSD fragments packets across an mbuf chain) 54 * and two RX buffer queues prioritized on size (one queue for small 55 * frames that will fit into a single mbuf, another with full size 56 * mbuf clusters for everything else). The producer/consumer indexes 57 * and completion queues are also used. 58 * 59 * One downside to the Starfire has to do with alignment: buffer 60 * queues must be aligned on 256-byte boundaries, and receive buffers 61 * must be aligned on longword boundaries. The receive buffer alignment 62 * causes problems on the Alpha platform, where the packet payload 63 * should be longword aligned. There is no simple way around this. 64 * 65 * For receive filtering, the Starfire offers 16 perfect filter slots 66 * and a 512-bit hash table. 67 * 68 * The Starfire has no internal transceiver, relying instead on an 69 * external MII-based transceiver. Accessing registers on external 70 * PHYs is done through a special register map rather than with the 71 * usual bitbang MDIO method. 72 * 73 * Acesssing the registers on the Starfire is a little tricky. The 74 * Starfire has a 512K internal register space. When programmed for 75 * PCI memory mapped mode, the entire register space can be accessed 76 * directly. However in I/O space mode, only 256 bytes are directly 77 * mapped into PCI I/O space. The other registers can be accessed 78 * indirectly using the SF_INDIRECTIO_ADDR and SF_INDIRECTIO_DATA 79 * registers inside the 256-byte I/O window. 80 */ 81 82#include <sys/param.h> 83#include <sys/systm.h> 84#include <sys/sockio.h> 85#include <sys/mbuf.h> 86#include <sys/malloc.h> 87#include <sys/kernel.h> 88#include <sys/module.h> 89#include <sys/socket.h> 90 91#include <net/if.h> 92#include <net/if_arp.h> 93#include <net/ethernet.h> 94#include <net/if_dl.h> 95#include <net/if_media.h> 96 97#include <net/bpf.h> 98 99#include <vm/vm.h> /* for vtophys */ 100#include <vm/pmap.h> /* for vtophys */ 101#include <machine/bus_pio.h> 102#include <machine/bus_memio.h> 103#include <machine/bus.h> 104#include <machine/resource.h> 105#include <sys/bus.h> 106#include <sys/rman.h> 107 108#include <dev/mii/mii.h> 109#include <dev/mii/miivar.h> 110 111/* "controller miibus0" required. See GENERIC if you get errors here. */ 112#include "miibus_if.h" 113 114#include <dev/pci/pcireg.h> 115#include <dev/pci/pcivar.h> 116 117#define SF_USEIOSPACE 118 119#include <pci/if_sfreg.h> 120 121MODULE_DEPEND(sf, pci, 1, 1, 1); 122MODULE_DEPEND(sf, ether, 1, 1, 1); 123MODULE_DEPEND(sf, miibus, 1, 1, 1); 124 125static struct sf_type sf_devs[] = { 126 { AD_VENDORID, AD_DEVICEID_STARFIRE, 127 "Adaptec AIC-6915 10/100BaseTX" }, 128 { 0, 0, NULL } 129}; 130 131static int sf_probe (device_t); 132static int sf_attach (device_t); 133static int sf_detach (device_t); 134static void sf_intr (void *); 135static void sf_stats_update (void *); 136static void sf_rxeof (struct sf_softc *); 137static void sf_txeof (struct sf_softc *); 138static int sf_encap (struct sf_softc *, 139 struct sf_tx_bufdesc_type0 *, 140 struct mbuf *); 141static void sf_start (struct ifnet *); 142static int sf_ioctl (struct ifnet *, u_long, caddr_t); 143static void sf_init (void *); 144static void sf_stop (struct sf_softc *); 145static void sf_watchdog (struct ifnet *); 146static void sf_shutdown (device_t); 147static int sf_ifmedia_upd (struct ifnet *); 148static void sf_ifmedia_sts (struct ifnet *, struct ifmediareq *); 149static void sf_reset (struct sf_softc *); 150static int sf_init_rx_ring (struct sf_softc *); 151static void sf_init_tx_ring (struct sf_softc *); 152static int sf_newbuf (struct sf_softc *, 153 struct sf_rx_bufdesc_type0 *, 154 struct mbuf *); 155static void sf_setmulti (struct sf_softc *); 156static int sf_setperf (struct sf_softc *, int, caddr_t); 157static int sf_sethash (struct sf_softc *, caddr_t, int); 158#ifdef notdef 159static int sf_setvlan (struct sf_softc *, int, u_int32_t); 160#endif 161 162static u_int8_t sf_read_eeprom (struct sf_softc *, int); 163 164static int sf_miibus_readreg (device_t, int, int); 165static int sf_miibus_writereg (device_t, int, int, int); 166static void sf_miibus_statchg (device_t); 167 168static u_int32_t csr_read_4 (struct sf_softc *, int); 169static void csr_write_4 (struct sf_softc *, int, u_int32_t); 170static void sf_txthresh_adjust (struct sf_softc *); 171 172#ifdef SF_USEIOSPACE 173#define SF_RES SYS_RES_IOPORT 174#define SF_RID SF_PCI_LOIO 175#else 176#define SF_RES SYS_RES_MEMORY 177#define SF_RID SF_PCI_LOMEM 178#endif 179 180static device_method_t sf_methods[] = { 181 /* Device interface */ 182 DEVMETHOD(device_probe, sf_probe), 183 DEVMETHOD(device_attach, sf_attach), 184 DEVMETHOD(device_detach, sf_detach), 185 DEVMETHOD(device_shutdown, sf_shutdown), 186 187 /* bus interface */ 188 DEVMETHOD(bus_print_child, bus_generic_print_child), 189 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 190 191 /* MII interface */ 192 DEVMETHOD(miibus_readreg, sf_miibus_readreg), 193 DEVMETHOD(miibus_writereg, sf_miibus_writereg), 194 DEVMETHOD(miibus_statchg, sf_miibus_statchg), 195 196 { 0, 0 } 197}; 198 199static driver_t sf_driver = { 200 "sf", 201 sf_methods, 202 sizeof(struct sf_softc), 203}; 204 205static devclass_t sf_devclass; 206 207DRIVER_MODULE(sf, pci, sf_driver, sf_devclass, 0, 0); 208DRIVER_MODULE(miibus, sf, miibus_driver, miibus_devclass, 0, 0); 209 210#define SF_SETBIT(sc, reg, x) \ 211 csr_write_4(sc, reg, csr_read_4(sc, reg) | (x)) 212 213#define SF_CLRBIT(sc, reg, x) \ 214 csr_write_4(sc, reg, csr_read_4(sc, reg) & ~(x)) 215 216static u_int32_t 217csr_read_4(sc, reg) 218 struct sf_softc *sc; 219 int reg; 220{ 221 u_int32_t val; 222 223#ifdef SF_USEIOSPACE 224 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); 225 val = CSR_READ_4(sc, SF_INDIRECTIO_DATA); 226#else 227 val = CSR_READ_4(sc, (reg + SF_RMAP_INTREG_BASE)); 228#endif 229 230 return(val); 231} 232 233static u_int8_t 234sf_read_eeprom(sc, reg) 235 struct sf_softc *sc; 236 int reg; 237{ 238 u_int8_t val; 239 240 val = (csr_read_4(sc, SF_EEADDR_BASE + 241 (reg & 0xFFFFFFFC)) >> (8 * (reg & 3))) & 0xFF; 242 243 return(val); 244} 245 246static void 247csr_write_4(sc, reg, val) 248 struct sf_softc *sc; 249 int reg; 250 u_int32_t val; 251{ 252#ifdef SF_USEIOSPACE 253 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); 254 CSR_WRITE_4(sc, SF_INDIRECTIO_DATA, val); 255#else 256 CSR_WRITE_4(sc, (reg + SF_RMAP_INTREG_BASE), val); 257#endif 258 return; 259} 260 261/* 262 * Copy the address 'mac' into the perfect RX filter entry at 263 * offset 'idx.' The perfect filter only has 16 entries so do 264 * some sanity tests. 265 */ 266static int 267sf_setperf(sc, idx, mac) 268 struct sf_softc *sc; 269 int idx; 270 caddr_t mac; 271{ 272 u_int16_t *p; 273 274 if (idx < 0 || idx > SF_RXFILT_PERFECT_CNT) 275 return(EINVAL); 276 277 if (mac == NULL) 278 return(EINVAL); 279 280 p = (u_int16_t *)mac; 281 282 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 283 (idx * SF_RXFILT_PERFECT_SKIP), htons(p[2])); 284 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 285 (idx * SF_RXFILT_PERFECT_SKIP) + 4, htons(p[1])); 286 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 287 (idx * SF_RXFILT_PERFECT_SKIP) + 8, htons(p[0])); 288 289 return(0); 290} 291 292/* 293 * Set the bit in the 512-bit hash table that corresponds to the 294 * specified mac address 'mac.' If 'prio' is nonzero, update the 295 * priority hash table instead of the filter hash table. 296 */ 297static int 298sf_sethash(sc, mac, prio) 299 struct sf_softc *sc; 300 caddr_t mac; 301 int prio; 302{ 303 u_int32_t h; 304 305 if (mac == NULL) 306 return(EINVAL); 307 308 h = ether_crc32_be(mac, ETHER_ADDR_LEN) >> 23; 309 310 if (prio) { 311 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_PRIOOFF + 312 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); 313 } else { 314 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_ADDROFF + 315 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); 316 } 317 318 return(0); 319} 320 321#ifdef notdef 322/* 323 * Set a VLAN tag in the receive filter. 324 */ 325static int 326sf_setvlan(sc, idx, vlan) 327 struct sf_softc *sc; 328 int idx; 329 u_int32_t vlan; 330{ 331 if (idx < 0 || idx >> SF_RXFILT_HASH_CNT) 332 return(EINVAL); 333 334 csr_write_4(sc, SF_RXFILT_HASH_BASE + 335 (idx * SF_RXFILT_HASH_SKIP) + SF_RXFILT_HASH_VLANOFF, vlan); 336 337 return(0); 338} 339#endif 340 341static int 342sf_miibus_readreg(dev, phy, reg) 343 device_t dev; 344 int phy, reg; 345{ 346 struct sf_softc *sc; 347 int i; 348 u_int32_t val = 0; 349 350 sc = device_get_softc(dev); 351 352 for (i = 0; i < SF_TIMEOUT; i++) { 353 val = csr_read_4(sc, SF_PHY_REG(phy, reg)); 354 if (val & SF_MII_DATAVALID) 355 break; 356 } 357 358 if (i == SF_TIMEOUT) 359 return(0); 360 361 if ((val & 0x0000FFFF) == 0xFFFF) 362 return(0); 363 364 return(val & 0x0000FFFF); 365} 366 367static int 368sf_miibus_writereg(dev, phy, reg, val) 369 device_t dev; 370 int phy, reg, val; 371{ 372 struct sf_softc *sc; 373 int i; 374 int busy; 375 376 sc = device_get_softc(dev); 377 378 csr_write_4(sc, SF_PHY_REG(phy, reg), val); 379 380 for (i = 0; i < SF_TIMEOUT; i++) { 381 busy = csr_read_4(sc, SF_PHY_REG(phy, reg)); 382 if (!(busy & SF_MII_BUSY)) 383 break; 384 } 385 386 return(0); 387} 388 389static void 390sf_miibus_statchg(dev) 391 device_t dev; 392{ 393 struct sf_softc *sc; 394 struct mii_data *mii; 395 396 sc = device_get_softc(dev); 397 mii = device_get_softc(sc->sf_miibus); 398 399 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 400 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 401 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_FDX); 402 } else { 403 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 404 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_HDX); 405 } 406 407 return; 408} 409 410static void 411sf_setmulti(sc) 412 struct sf_softc *sc; 413{ 414 struct ifnet *ifp; 415 int i; 416 struct ifmultiaddr *ifma; 417 u_int8_t dummy[] = { 0, 0, 0, 0, 0, 0 }; 418 419 ifp = &sc->arpcom.ac_if; 420 421 /* First zot all the existing filters. */ 422 for (i = 1; i < SF_RXFILT_PERFECT_CNT; i++) 423 sf_setperf(sc, i, (char *)&dummy); 424 for (i = SF_RXFILT_HASH_BASE; 425 i < (SF_RXFILT_HASH_MAX + 1); i += 4) 426 csr_write_4(sc, i, 0); 427 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI); 428 429 /* Now program new ones. */ 430 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 431 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI); 432 } else { 433 i = 1; 434 TAILQ_FOREACH_REVERSE(ifma, &ifp->if_multiaddrs, ifmultihead, ifma_link) { 435 if (ifma->ifma_addr->sa_family != AF_LINK) 436 continue; 437 /* 438 * Program the first 15 multicast groups 439 * into the perfect filter. For all others, 440 * use the hash table. 441 */ 442 if (i < SF_RXFILT_PERFECT_CNT) { 443 sf_setperf(sc, i, 444 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 445 i++; 446 continue; 447 } 448 449 sf_sethash(sc, 450 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 0); 451 } 452 } 453 454 return; 455} 456 457/* 458 * Set media options. 459 */ 460static int 461sf_ifmedia_upd(ifp) 462 struct ifnet *ifp; 463{ 464 struct sf_softc *sc; 465 struct mii_data *mii; 466 467 sc = ifp->if_softc; 468 mii = device_get_softc(sc->sf_miibus); 469 sc->sf_link = 0; 470 if (mii->mii_instance) { 471 struct mii_softc *miisc; 472 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 473 mii_phy_reset(miisc); 474 } 475 mii_mediachg(mii); 476 477 return(0); 478} 479 480/* 481 * Report current media status. 482 */ 483static void 484sf_ifmedia_sts(ifp, ifmr) 485 struct ifnet *ifp; 486 struct ifmediareq *ifmr; 487{ 488 struct sf_softc *sc; 489 struct mii_data *mii; 490 491 sc = ifp->if_softc; 492 mii = device_get_softc(sc->sf_miibus); 493 494 mii_pollstat(mii); 495 ifmr->ifm_active = mii->mii_media_active; 496 ifmr->ifm_status = mii->mii_media_status; 497 498 return; 499} 500 501static int 502sf_ioctl(ifp, command, data) 503 struct ifnet *ifp; 504 u_long command; 505 caddr_t data; 506{ 507 struct sf_softc *sc = ifp->if_softc; 508 struct ifreq *ifr = (struct ifreq *) data; 509 struct mii_data *mii; 510 int error = 0; 511 512 SF_LOCK(sc); 513 514 switch(command) { 515 case SIOCSIFFLAGS: 516 if (ifp->if_flags & IFF_UP) { 517 if (ifp->if_flags & IFF_RUNNING && 518 ifp->if_flags & IFF_PROMISC && 519 !(sc->sf_if_flags & IFF_PROMISC)) { 520 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 521 } else if (ifp->if_flags & IFF_RUNNING && 522 !(ifp->if_flags & IFF_PROMISC) && 523 sc->sf_if_flags & IFF_PROMISC) { 524 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 525 } else if (!(ifp->if_flags & IFF_RUNNING)) 526 sf_init(sc); 527 } else { 528 if (ifp->if_flags & IFF_RUNNING) 529 sf_stop(sc); 530 } 531 sc->sf_if_flags = ifp->if_flags; 532 error = 0; 533 break; 534 case SIOCADDMULTI: 535 case SIOCDELMULTI: 536 sf_setmulti(sc); 537 error = 0; 538 break; 539 case SIOCGIFMEDIA: 540 case SIOCSIFMEDIA: 541 mii = device_get_softc(sc->sf_miibus); 542 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 543 break; 544 default: 545 error = ether_ioctl(ifp, command, data); 546 break; 547 } 548 549 SF_UNLOCK(sc); 550 551 return(error); 552} 553 554static void 555sf_reset(sc) 556 struct sf_softc *sc; 557{ 558 register int i; 559 560 csr_write_4(sc, SF_GEN_ETH_CTL, 0); 561 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 562 DELAY(1000); 563 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 564 565 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_RESET); 566 567 for (i = 0; i < SF_TIMEOUT; i++) { 568 DELAY(10); 569 if (!(csr_read_4(sc, SF_PCI_DEVCFG) & SF_PCIDEVCFG_RESET)) 570 break; 571 } 572 573 if (i == SF_TIMEOUT) 574 printf("sf%d: reset never completed!\n", sc->sf_unit); 575 576 /* Wait a little while for the chip to get its brains in order. */ 577 DELAY(1000); 578 return; 579} 580 581/* 582 * Probe for an Adaptec AIC-6915 chip. Check the PCI vendor and device 583 * IDs against our list and return a device name if we find a match. 584 * We also check the subsystem ID so that we can identify exactly which 585 * NIC has been found, if possible. 586 */ 587static int 588sf_probe(dev) 589 device_t dev; 590{ 591 struct sf_type *t; 592 593 t = sf_devs; 594 595 while(t->sf_name != NULL) { 596 if ((pci_get_vendor(dev) == t->sf_vid) && 597 (pci_get_device(dev) == t->sf_did)) { 598 switch((pci_read_config(dev, 599 SF_PCI_SUBVEN_ID, 4) >> 16) & 0xFFFF) { 600 case AD_SUBSYSID_62011_REV0: 601 case AD_SUBSYSID_62011_REV1: 602 device_set_desc(dev, 603 "Adaptec ANA-62011 10/100BaseTX"); 604 return(0); 605 case AD_SUBSYSID_62022: 606 device_set_desc(dev, 607 "Adaptec ANA-62022 10/100BaseTX"); 608 return(0); 609 case AD_SUBSYSID_62044_REV0: 610 case AD_SUBSYSID_62044_REV1: 611 device_set_desc(dev, 612 "Adaptec ANA-62044 10/100BaseTX"); 613 return(0); 614 case AD_SUBSYSID_62020: 615 device_set_desc(dev, 616 "Adaptec ANA-62020 10/100BaseFX"); 617 return(0); 618 case AD_SUBSYSID_69011: 619 device_set_desc(dev, 620 "Adaptec ANA-69011 10/100BaseTX"); 621 return(0); 622 default: 623 device_set_desc(dev, t->sf_name); 624 return(0); 625 break; 626 } 627 } 628 t++; 629 } 630 631 return(ENXIO); 632} 633 634/* 635 * Attach the interface. Allocate softc structures, do ifmedia 636 * setup and ethernet/BPF attach. 637 */ 638static int 639sf_attach(dev) 640 device_t dev; 641{ 642 int i; 643 struct sf_softc *sc; 644 struct ifnet *ifp; 645 int unit, rid, error = 0; 646 647 sc = device_get_softc(dev); 648 unit = device_get_unit(dev); 649 650 mtx_init(&sc->sf_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 651 MTX_DEF | MTX_RECURSE); 652#ifndef BURN_BRIDGES 653 /* 654 * Handle power management nonsense. 655 */ 656 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 657 u_int32_t iobase, membase, irq; 658 659 /* Save important PCI config data. */ 660 iobase = pci_read_config(dev, SF_PCI_LOIO, 4); 661 membase = pci_read_config(dev, SF_PCI_LOMEM, 4); 662 irq = pci_read_config(dev, SF_PCI_INTLINE, 4); 663 664 /* Reset the power state. */ 665 printf("sf%d: chip is in D%d power mode " 666 "-- setting to D0\n", unit, 667 pci_get_powerstate(dev)); 668 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 669 670 /* Restore PCI config data. */ 671 pci_write_config(dev, SF_PCI_LOIO, iobase, 4); 672 pci_write_config(dev, SF_PCI_LOMEM, membase, 4); 673 pci_write_config(dev, SF_PCI_INTLINE, irq, 4); 674 } 675#endif 676 /* 677 * Map control/status registers. 678 */ 679 pci_enable_busmaster(dev); 680 681 rid = SF_RID; 682 sc->sf_res = bus_alloc_resource_any(dev, SF_RES, &rid, RF_ACTIVE); 683 684 if (sc->sf_res == NULL) { 685 printf ("sf%d: couldn't map ports\n", unit); 686 error = ENXIO; 687 goto fail; 688 } 689 690 sc->sf_btag = rman_get_bustag(sc->sf_res); 691 sc->sf_bhandle = rman_get_bushandle(sc->sf_res); 692 693 /* Allocate interrupt */ 694 rid = 0; 695 sc->sf_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 696 RF_SHAREABLE | RF_ACTIVE); 697 698 if (sc->sf_irq == NULL) { 699 printf("sf%d: couldn't map interrupt\n", unit); 700 error = ENXIO; 701 goto fail; 702 } 703 704 callout_handle_init(&sc->sf_stat_ch); 705 /* Reset the adapter. */ 706 sf_reset(sc); 707 708 /* 709 * Get station address from the EEPROM. 710 */ 711 for (i = 0; i < ETHER_ADDR_LEN; i++) 712 sc->arpcom.ac_enaddr[i] = 713 sf_read_eeprom(sc, SF_EE_NODEADDR + ETHER_ADDR_LEN - i); 714 715 sc->sf_unit = unit; 716 717 /* Allocate the descriptor queues. */ 718 sc->sf_ldata = contigmalloc(sizeof(struct sf_list_data), M_DEVBUF, 719 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 720 721 if (sc->sf_ldata == NULL) { 722 printf("sf%d: no memory for list buffers!\n", unit); 723 error = ENXIO; 724 goto fail; 725 } 726 727 bzero(sc->sf_ldata, sizeof(struct sf_list_data)); 728 729 /* Do MII setup. */ 730 if (mii_phy_probe(dev, &sc->sf_miibus, 731 sf_ifmedia_upd, sf_ifmedia_sts)) { 732 printf("sf%d: MII without any phy!\n", sc->sf_unit); 733 error = ENXIO; 734 goto fail; 735 } 736 737 ifp = &sc->arpcom.ac_if; 738 ifp->if_softc = sc; 739 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 740 ifp->if_mtu = ETHERMTU; 741 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 742 ifp->if_ioctl = sf_ioctl; 743 ifp->if_start = sf_start; 744 ifp->if_watchdog = sf_watchdog; 745 ifp->if_init = sf_init; 746 ifp->if_baudrate = 10000000; 747 ifp->if_snd.ifq_maxlen = SF_TX_DLIST_CNT - 1; 748 749 /* 750 * Call MI attach routine. 751 */ 752 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 753 754 /* Hook interrupt last to avoid having to lock softc */ 755 error = bus_setup_intr(dev, sc->sf_irq, INTR_TYPE_NET, 756 sf_intr, sc, &sc->sf_intrhand); 757 758 if (error) { 759 printf("sf%d: couldn't set up irq\n", unit); 760 ether_ifdetach(ifp); 761 goto fail; 762 } 763 764fail: 765 if (error) 766 sf_detach(dev); 767 768 return(error); 769} 770 771/* 772 * Shutdown hardware and free up resources. This can be called any 773 * time after the mutex has been initialized. It is called in both 774 * the error case in attach and the normal detach case so it needs 775 * to be careful about only freeing resources that have actually been 776 * allocated. 777 */ 778static int 779sf_detach(dev) 780 device_t dev; 781{ 782 struct sf_softc *sc; 783 struct ifnet *ifp; 784 785 sc = device_get_softc(dev); 786 KASSERT(mtx_initialized(&sc->sf_mtx), ("sf mutex not initialized")); 787 SF_LOCK(sc); 788 ifp = &sc->arpcom.ac_if; 789 790 /* These should only be active if attach succeeded */ 791 if (device_is_attached(dev)) { 792 sf_stop(sc); 793 ether_ifdetach(ifp); 794 } 795 if (sc->sf_miibus) 796 device_delete_child(dev, sc->sf_miibus); 797 bus_generic_detach(dev); 798 799 if (sc->sf_intrhand) 800 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand); 801 if (sc->sf_irq) 802 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq); 803 if (sc->sf_res) 804 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 805 806 if (sc->sf_ldata) 807 contigfree(sc->sf_ldata, sizeof(struct sf_list_data), M_DEVBUF); 808 809 SF_UNLOCK(sc); 810 mtx_destroy(&sc->sf_mtx); 811 812 return(0); 813} 814 815static int 816sf_init_rx_ring(sc) 817 struct sf_softc *sc; 818{ 819 struct sf_list_data *ld; 820 int i; 821 822 ld = sc->sf_ldata; 823 824 bzero((char *)ld->sf_rx_dlist_big, 825 sizeof(struct sf_rx_bufdesc_type0) * SF_RX_DLIST_CNT); 826 bzero((char *)ld->sf_rx_clist, 827 sizeof(struct sf_rx_cmpdesc_type3) * SF_RX_CLIST_CNT); 828 829 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 830 if (sf_newbuf(sc, &ld->sf_rx_dlist_big[i], NULL) == ENOBUFS) 831 return(ENOBUFS); 832 } 833 834 return(0); 835} 836 837static void 838sf_init_tx_ring(sc) 839 struct sf_softc *sc; 840{ 841 struct sf_list_data *ld; 842 int i; 843 844 ld = sc->sf_ldata; 845 846 bzero((char *)ld->sf_tx_dlist, 847 sizeof(struct sf_tx_bufdesc_type0) * SF_TX_DLIST_CNT); 848 bzero((char *)ld->sf_tx_clist, 849 sizeof(struct sf_tx_cmpdesc_type0) * SF_TX_CLIST_CNT); 850 851 for (i = 0; i < SF_TX_DLIST_CNT; i++) 852 ld->sf_tx_dlist[i].sf_id = SF_TX_BUFDESC_ID; 853 for (i = 0; i < SF_TX_CLIST_CNT; i++) 854 ld->sf_tx_clist[i].sf_type = SF_TXCMPTYPE_TX; 855 856 ld->sf_tx_dlist[SF_TX_DLIST_CNT - 1].sf_end = 1; 857 sc->sf_tx_cnt = 0; 858 859 return; 860} 861 862static int 863sf_newbuf(sc, c, m) 864 struct sf_softc *sc; 865 struct sf_rx_bufdesc_type0 *c; 866 struct mbuf *m; 867{ 868 struct mbuf *m_new = NULL; 869 870 if (m == NULL) { 871 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 872 if (m_new == NULL) 873 return(ENOBUFS); 874 875 MCLGET(m_new, M_DONTWAIT); 876 if (!(m_new->m_flags & M_EXT)) { 877 m_freem(m_new); 878 return(ENOBUFS); 879 } 880 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 881 } else { 882 m_new = m; 883 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 884 m_new->m_data = m_new->m_ext.ext_buf; 885 } 886 887 m_adj(m_new, sizeof(u_int64_t)); 888 889 c->sf_mbuf = m_new; 890 c->sf_addrlo = SF_RX_HOSTADDR(vtophys(mtod(m_new, caddr_t))); 891 c->sf_valid = 1; 892 893 return(0); 894} 895 896/* 897 * The starfire is programmed to use 'normal' mode for packet reception, 898 * which means we use the consumer/producer model for both the buffer 899 * descriptor queue and the completion descriptor queue. The only problem 900 * with this is that it involves a lot of register accesses: we have to 901 * read the RX completion consumer and producer indexes and the RX buffer 902 * producer index, plus the RX completion consumer and RX buffer producer 903 * indexes have to be updated. It would have been easier if Adaptec had 904 * put each index in a separate register, especially given that the damn 905 * NIC has a 512K register space. 906 * 907 * In spite of all the lovely features that Adaptec crammed into the 6915, 908 * it is marred by one truly stupid design flaw, which is that receive 909 * buffer addresses must be aligned on a longword boundary. This forces 910 * the packet payload to be unaligned, which is suboptimal on the x86 and 911 * completely unuseable on the Alpha. Our only recourse is to copy received 912 * packets into properly aligned buffers before handing them off. 913 */ 914 915static void 916sf_rxeof(sc) 917 struct sf_softc *sc; 918{ 919 struct mbuf *m; 920 struct ifnet *ifp; 921 struct sf_rx_bufdesc_type0 *desc; 922 struct sf_rx_cmpdesc_type3 *cur_rx; 923 u_int32_t rxcons, rxprod; 924 int cmpprodidx, cmpconsidx, bufprodidx; 925 926 SF_LOCK_ASSERT(sc); 927 928 ifp = &sc->arpcom.ac_if; 929 930 rxcons = csr_read_4(sc, SF_CQ_CONSIDX); 931 rxprod = csr_read_4(sc, SF_RXDQ_PTR_Q1); 932 cmpprodidx = SF_IDX_LO(csr_read_4(sc, SF_CQ_PRODIDX)); 933 cmpconsidx = SF_IDX_LO(rxcons); 934 bufprodidx = SF_IDX_LO(rxprod); 935 936 while (cmpconsidx != cmpprodidx) { 937 struct mbuf *m0; 938 939 cur_rx = &sc->sf_ldata->sf_rx_clist[cmpconsidx]; 940 desc = &sc->sf_ldata->sf_rx_dlist_big[cur_rx->sf_endidx]; 941 m = desc->sf_mbuf; 942 SF_INC(cmpconsidx, SF_RX_CLIST_CNT); 943 SF_INC(bufprodidx, SF_RX_DLIST_CNT); 944 945 if (!(cur_rx->sf_status1 & SF_RXSTAT1_OK)) { 946 ifp->if_ierrors++; 947 sf_newbuf(sc, desc, m); 948 continue; 949 } 950 951 m0 = m_devget(mtod(m, char *), cur_rx->sf_len, ETHER_ALIGN, 952 ifp, NULL); 953 sf_newbuf(sc, desc, m); 954 if (m0 == NULL) { 955 ifp->if_ierrors++; 956 continue; 957 } 958 m = m0; 959 960 ifp->if_ipackets++; 961 SF_UNLOCK(sc); 962 (*ifp->if_input)(ifp, m); 963 SF_LOCK(sc); 964 } 965 966 csr_write_4(sc, SF_CQ_CONSIDX, 967 (rxcons & ~SF_CQ_CONSIDX_RXQ1) | cmpconsidx); 968 csr_write_4(sc, SF_RXDQ_PTR_Q1, 969 (rxprod & ~SF_RXDQ_PRODIDX) | bufprodidx); 970 971 return; 972} 973 974/* 975 * Read the transmit status from the completion queue and release 976 * mbufs. Note that the buffer descriptor index in the completion 977 * descriptor is an offset from the start of the transmit buffer 978 * descriptor list in bytes. This is important because the manual 979 * gives the impression that it should match the producer/consumer 980 * index, which is the offset in 8 byte blocks. 981 */ 982static void 983sf_txeof(sc) 984 struct sf_softc *sc; 985{ 986 int txcons, cmpprodidx, cmpconsidx; 987 struct sf_tx_cmpdesc_type1 *cur_cmp; 988 struct sf_tx_bufdesc_type0 *cur_tx; 989 struct ifnet *ifp; 990 991 ifp = &sc->arpcom.ac_if; 992 993 txcons = csr_read_4(sc, SF_CQ_CONSIDX); 994 cmpprodidx = SF_IDX_HI(csr_read_4(sc, SF_CQ_PRODIDX)); 995 cmpconsidx = SF_IDX_HI(txcons); 996 997 while (cmpconsidx != cmpprodidx) { 998 cur_cmp = &sc->sf_ldata->sf_tx_clist[cmpconsidx]; 999 cur_tx = &sc->sf_ldata->sf_tx_dlist[cur_cmp->sf_index >> 7]; 1000 1001 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_OK) 1002 ifp->if_opackets++; 1003 else { 1004 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_UNDERRUN) 1005 sf_txthresh_adjust(sc); 1006 ifp->if_oerrors++; 1007 } 1008 1009 sc->sf_tx_cnt--; 1010 if (cur_tx->sf_mbuf != NULL) { 1011 m_freem(cur_tx->sf_mbuf); 1012 cur_tx->sf_mbuf = NULL; 1013 } else 1014 break; 1015 SF_INC(cmpconsidx, SF_TX_CLIST_CNT); 1016 } 1017 1018 ifp->if_timer = 0; 1019 ifp->if_flags &= ~IFF_OACTIVE; 1020 1021 csr_write_4(sc, SF_CQ_CONSIDX, 1022 (txcons & ~SF_CQ_CONSIDX_TXQ) | 1023 ((cmpconsidx << 16) & 0xFFFF0000)); 1024 1025 return; 1026} 1027 1028static void 1029sf_txthresh_adjust(sc) 1030 struct sf_softc *sc; 1031{ 1032 u_int32_t txfctl; 1033 u_int8_t txthresh; 1034 1035 txfctl = csr_read_4(sc, SF_TX_FRAMCTL); 1036 txthresh = txfctl & SF_TXFRMCTL_TXTHRESH; 1037 if (txthresh < 0xFF) { 1038 txthresh++; 1039 txfctl &= ~SF_TXFRMCTL_TXTHRESH; 1040 txfctl |= txthresh; 1041#ifdef DIAGNOSTIC 1042 printf("sf%d: tx underrun, increasing " 1043 "tx threshold to %d bytes\n", 1044 sc->sf_unit, txthresh * 4); 1045#endif 1046 csr_write_4(sc, SF_TX_FRAMCTL, txfctl); 1047 } 1048 1049 return; 1050} 1051 1052static void 1053sf_intr(arg) 1054 void *arg; 1055{ 1056 struct sf_softc *sc; 1057 struct ifnet *ifp; 1058 u_int32_t status; 1059 1060 sc = arg; 1061 SF_LOCK(sc); 1062 1063 ifp = &sc->arpcom.ac_if; 1064 1065 if (!(csr_read_4(sc, SF_ISR_SHADOW) & SF_ISR_PCIINT_ASSERTED)) { 1066 SF_UNLOCK(sc); 1067 return; 1068 } 1069 1070 /* Disable interrupts. */ 1071 csr_write_4(sc, SF_IMR, 0x00000000); 1072 1073 for (;;) { 1074 status = csr_read_4(sc, SF_ISR); 1075 if (status) 1076 csr_write_4(sc, SF_ISR, status); 1077 1078 if (!(status & SF_INTRS)) 1079 break; 1080 1081 if (status & SF_ISR_RXDQ1_DMADONE) 1082 sf_rxeof(sc); 1083 1084 if (status & SF_ISR_TX_TXDONE || 1085 status & SF_ISR_TX_DMADONE || 1086 status & SF_ISR_TX_QUEUEDONE) 1087 sf_txeof(sc); 1088 1089 if (status & SF_ISR_TX_LOFIFO) 1090 sf_txthresh_adjust(sc); 1091 1092 if (status & SF_ISR_ABNORMALINTR) { 1093 if (status & SF_ISR_STATSOFLOW) { 1094 untimeout(sf_stats_update, sc, 1095 sc->sf_stat_ch); 1096 sf_stats_update(sc); 1097 } else 1098 sf_init(sc); 1099 } 1100 } 1101 1102 /* Re-enable interrupts. */ 1103 csr_write_4(sc, SF_IMR, SF_INTRS); 1104 1105 if (ifp->if_snd.ifq_head != NULL) 1106 sf_start(ifp); 1107 1108 SF_UNLOCK(sc); 1109 return; 1110} 1111 1112static void 1113sf_init(xsc) 1114 void *xsc; 1115{ 1116 struct sf_softc *sc; 1117 struct ifnet *ifp; 1118 struct mii_data *mii; 1119 int i; 1120 1121 sc = xsc; 1122 SF_LOCK(sc); 1123 ifp = &sc->arpcom.ac_if; 1124 mii = device_get_softc(sc->sf_miibus); 1125 1126 sf_stop(sc); 1127 sf_reset(sc); 1128 1129 /* Init all the receive filter registers */ 1130 for (i = SF_RXFILT_PERFECT_BASE; 1131 i < (SF_RXFILT_HASH_MAX + 1); i += 4) 1132 csr_write_4(sc, i, 0); 1133 1134 /* Empty stats counter registers. */ 1135 for (i = 0; i < sizeof(struct sf_stats)/sizeof(u_int32_t); i++) 1136 csr_write_4(sc, SF_STATS_BASE + 1137 (i + sizeof(u_int32_t)), 0); 1138 1139 /* Init our MAC address */ 1140 csr_write_4(sc, SF_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1141 csr_write_4(sc, SF_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1142 sf_setperf(sc, 0, (caddr_t)&sc->arpcom.ac_enaddr); 1143 1144 if (sf_init_rx_ring(sc) == ENOBUFS) { 1145 printf("sf%d: initialization failed: no " 1146 "memory for rx buffers\n", sc->sf_unit); 1147 SF_UNLOCK(sc); 1148 return; 1149 } 1150 1151 sf_init_tx_ring(sc); 1152 1153 csr_write_4(sc, SF_RXFILT, SF_PERFMODE_NORMAL|SF_HASHMODE_WITHVLAN); 1154 1155 /* If we want promiscuous mode, set the allframes bit. */ 1156 if (ifp->if_flags & IFF_PROMISC) { 1157 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 1158 } else { 1159 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 1160 } 1161 1162 if (ifp->if_flags & IFF_BROADCAST) { 1163 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_BROAD); 1164 } else { 1165 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_BROAD); 1166 } 1167 1168 /* 1169 * Load the multicast filter. 1170 */ 1171 sf_setmulti(sc); 1172 1173 /* Init the completion queue indexes */ 1174 csr_write_4(sc, SF_CQ_CONSIDX, 0); 1175 csr_write_4(sc, SF_CQ_PRODIDX, 0); 1176 1177 /* Init the RX completion queue */ 1178 csr_write_4(sc, SF_RXCQ_CTL_1, 1179 vtophys(sc->sf_ldata->sf_rx_clist) & SF_RXCQ_ADDR); 1180 SF_SETBIT(sc, SF_RXCQ_CTL_1, SF_RXCQTYPE_3); 1181 1182 /* Init RX DMA control. */ 1183 SF_SETBIT(sc, SF_RXDMA_CTL, SF_RXDMA_REPORTBADPKTS); 1184 1185 /* Init the RX buffer descriptor queue. */ 1186 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 1187 vtophys(sc->sf_ldata->sf_rx_dlist_big)); 1188 csr_write_4(sc, SF_RXDQ_CTL_1, (MCLBYTES << 16) | SF_DESCSPACE_16BYTES); 1189 csr_write_4(sc, SF_RXDQ_PTR_Q1, SF_RX_DLIST_CNT - 1); 1190 1191 /* Init the TX completion queue */ 1192 csr_write_4(sc, SF_TXCQ_CTL, 1193 vtophys(sc->sf_ldata->sf_tx_clist) & SF_RXCQ_ADDR); 1194 1195 /* Init the TX buffer descriptor queue. */ 1196 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 1197 vtophys(sc->sf_ldata->sf_tx_dlist)); 1198 SF_SETBIT(sc, SF_TX_FRAMCTL, SF_TXFRMCTL_CPLAFTERTX); 1199 csr_write_4(sc, SF_TXDQ_CTL, 1200 SF_TXBUFDESC_TYPE0|SF_TXMINSPACE_128BYTES|SF_TXSKIPLEN_8BYTES); 1201 SF_SETBIT(sc, SF_TXDQ_CTL, SF_TXDQCTL_NODMACMP); 1202 1203 /* Enable autopadding of short TX frames. */ 1204 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_AUTOPAD); 1205 1206 /* Enable interrupts. */ 1207 csr_write_4(sc, SF_IMR, SF_INTRS); 1208 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_INTR_ENB); 1209 1210 /* Enable the RX and TX engines. */ 1211 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_RX_ENB|SF_ETHCTL_RXDMA_ENB); 1212 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_TX_ENB|SF_ETHCTL_TXDMA_ENB); 1213 1214 /*mii_mediachg(mii);*/ 1215 sf_ifmedia_upd(ifp); 1216 1217 ifp->if_flags |= IFF_RUNNING; 1218 ifp->if_flags &= ~IFF_OACTIVE; 1219 1220 sc->sf_stat_ch = timeout(sf_stats_update, sc, hz); 1221 1222 SF_UNLOCK(sc); 1223 1224 return; 1225} 1226 1227static int 1228sf_encap(sc, c, m_head) 1229 struct sf_softc *sc; 1230 struct sf_tx_bufdesc_type0 *c; 1231 struct mbuf *m_head; 1232{ 1233 int frag = 0; 1234 struct sf_frag *f = NULL; 1235 struct mbuf *m; 1236 1237 m = m_head; 1238 1239 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1240 if (m->m_len != 0) { 1241 if (frag == SF_MAXFRAGS) 1242 break; 1243 f = &c->sf_frags[frag]; 1244 if (frag == 0) 1245 f->sf_pktlen = m_head->m_pkthdr.len; 1246 f->sf_fraglen = m->m_len; 1247 f->sf_addr = vtophys(mtod(m, vm_offset_t)); 1248 frag++; 1249 } 1250 } 1251 1252 if (m != NULL) { 1253 struct mbuf *m_new = NULL; 1254 1255 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1256 if (m_new == NULL) { 1257 printf("sf%d: no memory for tx list\n", sc->sf_unit); 1258 return(1); 1259 } 1260 1261 if (m_head->m_pkthdr.len > MHLEN) { 1262 MCLGET(m_new, M_DONTWAIT); 1263 if (!(m_new->m_flags & M_EXT)) { 1264 m_freem(m_new); 1265 printf("sf%d: no memory for tx list\n", 1266 sc->sf_unit); 1267 return(1); 1268 } 1269 } 1270 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1271 mtod(m_new, caddr_t)); 1272 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1273 m_freem(m_head); 1274 m_head = m_new; 1275 f = &c->sf_frags[0]; 1276 f->sf_fraglen = f->sf_pktlen = m_head->m_pkthdr.len; 1277 f->sf_addr = vtophys(mtod(m_head, caddr_t)); 1278 frag = 1; 1279 } 1280 1281 c->sf_mbuf = m_head; 1282 c->sf_id = SF_TX_BUFDESC_ID; 1283 c->sf_fragcnt = frag; 1284 c->sf_intr = 1; 1285 c->sf_caltcp = 0; 1286 c->sf_crcen = 1; 1287 1288 return(0); 1289} 1290 1291static void 1292sf_start(ifp) 1293 struct ifnet *ifp; 1294{ 1295 struct sf_softc *sc; 1296 struct sf_tx_bufdesc_type0 *cur_tx = NULL; 1297 struct mbuf *m_head = NULL; 1298 int i, txprod; 1299 1300 sc = ifp->if_softc; 1301 SF_LOCK(sc); 1302 1303 if (!sc->sf_link && ifp->if_snd.ifq_len < 10) { 1304 SF_UNLOCK(sc); 1305 return; 1306 } 1307 1308 if (ifp->if_flags & IFF_OACTIVE) { 1309 SF_UNLOCK(sc); 1310 return; 1311 } 1312 1313 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX); 1314 i = SF_IDX_HI(txprod) >> 4; 1315 1316 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) { 1317 printf("sf%d: TX ring full, resetting\n", sc->sf_unit); 1318 sf_init(sc); 1319 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX); 1320 i = SF_IDX_HI(txprod) >> 4; 1321 } 1322 1323 while(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf == NULL) { 1324 if (sc->sf_tx_cnt >= (SF_TX_DLIST_CNT - 5)) { 1325 ifp->if_flags |= IFF_OACTIVE; 1326 cur_tx = NULL; 1327 break; 1328 } 1329 IF_DEQUEUE(&ifp->if_snd, m_head); 1330 if (m_head == NULL) 1331 break; 1332 1333 cur_tx = &sc->sf_ldata->sf_tx_dlist[i]; 1334 if (sf_encap(sc, cur_tx, m_head)) { 1335 IF_PREPEND(&ifp->if_snd, m_head); 1336 ifp->if_flags |= IFF_OACTIVE; 1337 cur_tx = NULL; 1338 break; 1339 } 1340 1341 /* 1342 * If there's a BPF listener, bounce a copy of this frame 1343 * to him. 1344 */ 1345 BPF_MTAP(ifp, m_head); 1346 1347 SF_INC(i, SF_TX_DLIST_CNT); 1348 sc->sf_tx_cnt++; 1349 /* 1350 * Don't get the TX DMA queue get too full. 1351 */ 1352 if (sc->sf_tx_cnt > 64) 1353 break; 1354 } 1355 1356 if (cur_tx == NULL) { 1357 SF_UNLOCK(sc); 1358 return; 1359 } 1360 1361 /* Transmit */ 1362 csr_write_4(sc, SF_TXDQ_PRODIDX, 1363 (txprod & ~SF_TXDQ_PRODIDX_HIPRIO) | 1364 ((i << 20) & 0xFFFF0000)); 1365 1366 ifp->if_timer = 5; 1367 1368 SF_UNLOCK(sc); 1369 1370 return; 1371} 1372 1373static void 1374sf_stop(sc) 1375 struct sf_softc *sc; 1376{ 1377 int i; 1378 struct ifnet *ifp; 1379 1380 SF_LOCK(sc); 1381 1382 ifp = &sc->arpcom.ac_if; 1383 1384 untimeout(sf_stats_update, sc, sc->sf_stat_ch); 1385 1386 csr_write_4(sc, SF_GEN_ETH_CTL, 0); 1387 csr_write_4(sc, SF_CQ_CONSIDX, 0); 1388 csr_write_4(sc, SF_CQ_PRODIDX, 0); 1389 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 0); 1390 csr_write_4(sc, SF_RXDQ_CTL_1, 0); 1391 csr_write_4(sc, SF_RXDQ_PTR_Q1, 0); 1392 csr_write_4(sc, SF_TXCQ_CTL, 0); 1393 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 0); 1394 csr_write_4(sc, SF_TXDQ_CTL, 0); 1395 sf_reset(sc); 1396 1397 sc->sf_link = 0; 1398 1399 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 1400 if (sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf != NULL) { 1401 m_freem(sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf); 1402 sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf = NULL; 1403 } 1404 } 1405 1406 for (i = 0; i < SF_TX_DLIST_CNT; i++) { 1407 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) { 1408 m_freem(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf); 1409 sc->sf_ldata->sf_tx_dlist[i].sf_mbuf = NULL; 1410 } 1411 } 1412 1413 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 1414 SF_UNLOCK(sc); 1415 1416 return; 1417} 1418 1419/* 1420 * Note: it is important that this function not be interrupted. We 1421 * use a two-stage register access scheme: if we are interrupted in 1422 * between setting the indirect address register and reading from the 1423 * indirect data register, the contents of the address register could 1424 * be changed out from under us. 1425 */ 1426static void 1427sf_stats_update(xsc) 1428 void *xsc; 1429{ 1430 struct sf_softc *sc; 1431 struct ifnet *ifp; 1432 struct mii_data *mii; 1433 struct sf_stats stats; 1434 u_int32_t *ptr; 1435 int i; 1436 1437 sc = xsc; 1438 SF_LOCK(sc); 1439 ifp = &sc->arpcom.ac_if; 1440 mii = device_get_softc(sc->sf_miibus); 1441 1442 ptr = (u_int32_t *)&stats; 1443 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++) 1444 ptr[i] = csr_read_4(sc, SF_STATS_BASE + 1445 (i + sizeof(u_int32_t))); 1446 1447 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++) 1448 csr_write_4(sc, SF_STATS_BASE + 1449 (i + sizeof(u_int32_t)), 0); 1450 1451 ifp->if_collisions += stats.sf_tx_single_colls + 1452 stats.sf_tx_multi_colls + stats.sf_tx_excess_colls; 1453 1454 mii_tick(mii); 1455 1456 if (!sc->sf_link && mii->mii_media_status & IFM_ACTIVE && 1457 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1458 sc->sf_link++; 1459 if (ifp->if_snd.ifq_head != NULL) 1460 sf_start(ifp); 1461 } 1462 1463 sc->sf_stat_ch = timeout(sf_stats_update, sc, hz); 1464 1465 SF_UNLOCK(sc); 1466 1467 return; 1468} 1469 1470static void 1471sf_watchdog(ifp) 1472 struct ifnet *ifp; 1473{ 1474 struct sf_softc *sc; 1475 1476 sc = ifp->if_softc; 1477 1478 SF_LOCK(sc); 1479 1480 ifp->if_oerrors++; 1481 printf("sf%d: watchdog timeout\n", sc->sf_unit); 1482 1483 sf_stop(sc); 1484 sf_reset(sc); 1485 sf_init(sc); 1486 1487 if (ifp->if_snd.ifq_head != NULL) 1488 sf_start(ifp); 1489 1490 SF_UNLOCK(sc); 1491 1492 return; 1493} 1494 1495static void 1496sf_shutdown(dev) 1497 device_t dev; 1498{ 1499 struct sf_softc *sc; 1500 1501 sc = device_get_softc(dev); 1502 1503 sf_stop(sc); 1504 1505 return; 1506} 1507