if_sf.c revision 129878
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/sf/if_sf.c 129878 2004-05-30 20:00:41Z phk $"); 35 36/* 37 * Adaptec AIC-6915 "Starfire" PCI fast ethernet driver for FreeBSD. 38 * Programming manual is available from: 39 * ftp.adaptec.com:/pub/BBS/userguides/aic6915_pg.pdf. 40 * 41 * Written by Bill Paul <wpaul@ctr.columbia.edu> 42 * Department of Electical Engineering 43 * Columbia University, New York City 44 */ 45/* 46 * The Adaptec AIC-6915 "Starfire" is a 64-bit 10/100 PCI ethernet 47 * controller designed with flexibility and reducing CPU load in mind. 48 * The Starfire offers high and low priority buffer queues, a 49 * producer/consumer index mechanism and several different buffer 50 * queue and completion queue descriptor types. Any one of a number 51 * of different driver designs can be used, depending on system and 52 * OS requirements. This driver makes use of type0 transmit frame 53 * descriptors (since BSD fragments packets across an mbuf chain) 54 * and two RX buffer queues prioritized on size (one queue for small 55 * frames that will fit into a single mbuf, another with full size 56 * mbuf clusters for everything else). The producer/consumer indexes 57 * and completion queues are also used. 58 * 59 * One downside to the Starfire has to do with alignment: buffer 60 * queues must be aligned on 256-byte boundaries, and receive buffers 61 * must be aligned on longword boundaries. The receive buffer alignment 62 * causes problems on the Alpha platform, where the packet payload 63 * should be longword aligned. There is no simple way around this. 64 * 65 * For receive filtering, the Starfire offers 16 perfect filter slots 66 * and a 512-bit hash table. 67 * 68 * The Starfire has no internal transceiver, relying instead on an 69 * external MII-based transceiver. Accessing registers on external 70 * PHYs is done through a special register map rather than with the 71 * usual bitbang MDIO method. 72 * 73 * Acesssing the registers on the Starfire is a little tricky. The 74 * Starfire has a 512K internal register space. When programmed for 75 * PCI memory mapped mode, the entire register space can be accessed 76 * directly. However in I/O space mode, only 256 bytes are directly 77 * mapped into PCI I/O space. The other registers can be accessed 78 * indirectly using the SF_INDIRECTIO_ADDR and SF_INDIRECTIO_DATA 79 * registers inside the 256-byte I/O window. 80 */ 81 82#include <sys/param.h> 83#include <sys/systm.h> 84#include <sys/sockio.h> 85#include <sys/mbuf.h> 86#include <sys/malloc.h> 87#include <sys/kernel.h> 88#include <sys/module.h> 89#include <sys/socket.h> 90 91#include <net/if.h> 92#include <net/if_arp.h> 93#include <net/ethernet.h> 94#include <net/if_dl.h> 95#include <net/if_media.h> 96 97#include <net/bpf.h> 98 99#include <vm/vm.h> /* for vtophys */ 100#include <vm/pmap.h> /* for vtophys */ 101#include <machine/bus_pio.h> 102#include <machine/bus_memio.h> 103#include <machine/bus.h> 104#include <machine/resource.h> 105#include <sys/bus.h> 106#include <sys/rman.h> 107 108#include <dev/mii/mii.h> 109#include <dev/mii/miivar.h> 110 111/* "controller miibus0" required. See GENERIC if you get errors here. */ 112#include "miibus_if.h" 113 114#include <dev/pci/pcireg.h> 115#include <dev/pci/pcivar.h> 116 117#define SF_USEIOSPACE 118 119#include <pci/if_sfreg.h> 120 121MODULE_DEPEND(sf, pci, 1, 1, 1); 122MODULE_DEPEND(sf, ether, 1, 1, 1); 123MODULE_DEPEND(sf, miibus, 1, 1, 1); 124 125static struct sf_type sf_devs[] = { 126 { AD_VENDORID, AD_DEVICEID_STARFIRE, 127 "Adaptec AIC-6915 10/100BaseTX" }, 128 { 0, 0, NULL } 129}; 130 131static int sf_probe (device_t); 132static int sf_attach (device_t); 133static int sf_detach (device_t); 134static void sf_intr (void *); 135static void sf_stats_update (void *); 136static void sf_rxeof (struct sf_softc *); 137static void sf_txeof (struct sf_softc *); 138static int sf_encap (struct sf_softc *, 139 struct sf_tx_bufdesc_type0 *, 140 struct mbuf *); 141static void sf_start (struct ifnet *); 142static int sf_ioctl (struct ifnet *, u_long, caddr_t); 143static void sf_init (void *); 144static void sf_stop (struct sf_softc *); 145static void sf_watchdog (struct ifnet *); 146static void sf_shutdown (device_t); 147static int sf_ifmedia_upd (struct ifnet *); 148static void sf_ifmedia_sts (struct ifnet *, struct ifmediareq *); 149static void sf_reset (struct sf_softc *); 150static int sf_init_rx_ring (struct sf_softc *); 151static void sf_init_tx_ring (struct sf_softc *); 152static int sf_newbuf (struct sf_softc *, 153 struct sf_rx_bufdesc_type0 *, 154 struct mbuf *); 155static void sf_setmulti (struct sf_softc *); 156static int sf_setperf (struct sf_softc *, int, caddr_t); 157static int sf_sethash (struct sf_softc *, caddr_t, int); 158#ifdef notdef 159static int sf_setvlan (struct sf_softc *, int, u_int32_t); 160#endif 161 162static u_int8_t sf_read_eeprom (struct sf_softc *, int); 163static uint32_t sf_mchash (const uint8_t *); 164 165static int sf_miibus_readreg (device_t, int, int); 166static int sf_miibus_writereg (device_t, int, int, int); 167static void sf_miibus_statchg (device_t); 168 169static u_int32_t csr_read_4 (struct sf_softc *, int); 170static void csr_write_4 (struct sf_softc *, int, u_int32_t); 171static void sf_txthresh_adjust (struct sf_softc *); 172 173#ifdef SF_USEIOSPACE 174#define SF_RES SYS_RES_IOPORT 175#define SF_RID SF_PCI_LOIO 176#else 177#define SF_RES SYS_RES_MEMORY 178#define SF_RID SF_PCI_LOMEM 179#endif 180 181static device_method_t sf_methods[] = { 182 /* Device interface */ 183 DEVMETHOD(device_probe, sf_probe), 184 DEVMETHOD(device_attach, sf_attach), 185 DEVMETHOD(device_detach, sf_detach), 186 DEVMETHOD(device_shutdown, sf_shutdown), 187 188 /* bus interface */ 189 DEVMETHOD(bus_print_child, bus_generic_print_child), 190 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 191 192 /* MII interface */ 193 DEVMETHOD(miibus_readreg, sf_miibus_readreg), 194 DEVMETHOD(miibus_writereg, sf_miibus_writereg), 195 DEVMETHOD(miibus_statchg, sf_miibus_statchg), 196 197 { 0, 0 } 198}; 199 200static driver_t sf_driver = { 201 "sf", 202 sf_methods, 203 sizeof(struct sf_softc), 204}; 205 206static devclass_t sf_devclass; 207 208DRIVER_MODULE(sf, pci, sf_driver, sf_devclass, 0, 0); 209DRIVER_MODULE(miibus, sf, miibus_driver, miibus_devclass, 0, 0); 210 211#define SF_SETBIT(sc, reg, x) \ 212 csr_write_4(sc, reg, csr_read_4(sc, reg) | (x)) 213 214#define SF_CLRBIT(sc, reg, x) \ 215 csr_write_4(sc, reg, csr_read_4(sc, reg) & ~(x)) 216 217static u_int32_t 218csr_read_4(sc, reg) 219 struct sf_softc *sc; 220 int reg; 221{ 222 u_int32_t val; 223 224#ifdef SF_USEIOSPACE 225 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); 226 val = CSR_READ_4(sc, SF_INDIRECTIO_DATA); 227#else 228 val = CSR_READ_4(sc, (reg + SF_RMAP_INTREG_BASE)); 229#endif 230 231 return(val); 232} 233 234static u_int8_t 235sf_read_eeprom(sc, reg) 236 struct sf_softc *sc; 237 int reg; 238{ 239 u_int8_t val; 240 241 val = (csr_read_4(sc, SF_EEADDR_BASE + 242 (reg & 0xFFFFFFFC)) >> (8 * (reg & 3))) & 0xFF; 243 244 return(val); 245} 246 247static void 248csr_write_4(sc, reg, val) 249 struct sf_softc *sc; 250 int reg; 251 u_int32_t val; 252{ 253#ifdef SF_USEIOSPACE 254 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); 255 CSR_WRITE_4(sc, SF_INDIRECTIO_DATA, val); 256#else 257 CSR_WRITE_4(sc, (reg + SF_RMAP_INTREG_BASE), val); 258#endif 259 return; 260} 261 262static u_int32_t 263sf_mchash(addr) 264 const uint8_t *addr; 265{ 266 uint32_t crc, carry; 267 int idx, bit; 268 uint8_t data; 269 270 /* Compute CRC for the address value. */ 271 crc = 0xFFFFFFFF; /* initial value */ 272 273 for (idx = 0; idx < 6; idx++) { 274 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) { 275 carry = ((crc & 0x80000000) ? 1 : 0) ^ (data & 0x01); 276 crc <<= 1; 277 if (carry) 278 crc = (crc ^ 0x04c11db6) | carry; 279 } 280 } 281 282 /* return the filter bit position */ 283 return(crc >> 23 & 0x1FF); 284} 285 286/* 287 * Copy the address 'mac' into the perfect RX filter entry at 288 * offset 'idx.' The perfect filter only has 16 entries so do 289 * some sanity tests. 290 */ 291static int 292sf_setperf(sc, idx, mac) 293 struct sf_softc *sc; 294 int idx; 295 caddr_t mac; 296{ 297 u_int16_t *p; 298 299 if (idx < 0 || idx > SF_RXFILT_PERFECT_CNT) 300 return(EINVAL); 301 302 if (mac == NULL) 303 return(EINVAL); 304 305 p = (u_int16_t *)mac; 306 307 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 308 (idx * SF_RXFILT_PERFECT_SKIP), htons(p[2])); 309 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 310 (idx * SF_RXFILT_PERFECT_SKIP) + 4, htons(p[1])); 311 csr_write_4(sc, SF_RXFILT_PERFECT_BASE + 312 (idx * SF_RXFILT_PERFECT_SKIP) + 8, htons(p[0])); 313 314 return(0); 315} 316 317/* 318 * Set the bit in the 512-bit hash table that corresponds to the 319 * specified mac address 'mac.' If 'prio' is nonzero, update the 320 * priority hash table instead of the filter hash table. 321 */ 322static int 323sf_sethash(sc, mac, prio) 324 struct sf_softc *sc; 325 caddr_t mac; 326 int prio; 327{ 328 u_int32_t h = 0; 329 330 if (mac == NULL) 331 return(EINVAL); 332 333 h = sf_mchash(mac); 334 335 if (prio) { 336 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_PRIOOFF + 337 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); 338 } else { 339 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_ADDROFF + 340 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); 341 } 342 343 return(0); 344} 345 346#ifdef notdef 347/* 348 * Set a VLAN tag in the receive filter. 349 */ 350static int 351sf_setvlan(sc, idx, vlan) 352 struct sf_softc *sc; 353 int idx; 354 u_int32_t vlan; 355{ 356 if (idx < 0 || idx >> SF_RXFILT_HASH_CNT) 357 return(EINVAL); 358 359 csr_write_4(sc, SF_RXFILT_HASH_BASE + 360 (idx * SF_RXFILT_HASH_SKIP) + SF_RXFILT_HASH_VLANOFF, vlan); 361 362 return(0); 363} 364#endif 365 366static int 367sf_miibus_readreg(dev, phy, reg) 368 device_t dev; 369 int phy, reg; 370{ 371 struct sf_softc *sc; 372 int i; 373 u_int32_t val = 0; 374 375 sc = device_get_softc(dev); 376 377 for (i = 0; i < SF_TIMEOUT; i++) { 378 val = csr_read_4(sc, SF_PHY_REG(phy, reg)); 379 if (val & SF_MII_DATAVALID) 380 break; 381 } 382 383 if (i == SF_TIMEOUT) 384 return(0); 385 386 if ((val & 0x0000FFFF) == 0xFFFF) 387 return(0); 388 389 return(val & 0x0000FFFF); 390} 391 392static int 393sf_miibus_writereg(dev, phy, reg, val) 394 device_t dev; 395 int phy, reg, val; 396{ 397 struct sf_softc *sc; 398 int i; 399 int busy; 400 401 sc = device_get_softc(dev); 402 403 csr_write_4(sc, SF_PHY_REG(phy, reg), val); 404 405 for (i = 0; i < SF_TIMEOUT; i++) { 406 busy = csr_read_4(sc, SF_PHY_REG(phy, reg)); 407 if (!(busy & SF_MII_BUSY)) 408 break; 409 } 410 411 return(0); 412} 413 414static void 415sf_miibus_statchg(dev) 416 device_t dev; 417{ 418 struct sf_softc *sc; 419 struct mii_data *mii; 420 421 sc = device_get_softc(dev); 422 mii = device_get_softc(sc->sf_miibus); 423 424 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 425 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 426 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_FDX); 427 } else { 428 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); 429 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_HDX); 430 } 431 432 return; 433} 434 435static void 436sf_setmulti(sc) 437 struct sf_softc *sc; 438{ 439 struct ifnet *ifp; 440 int i; 441 struct ifmultiaddr *ifma; 442 u_int8_t dummy[] = { 0, 0, 0, 0, 0, 0 }; 443 444 ifp = &sc->arpcom.ac_if; 445 446 /* First zot all the existing filters. */ 447 for (i = 1; i < SF_RXFILT_PERFECT_CNT; i++) 448 sf_setperf(sc, i, (char *)&dummy); 449 for (i = SF_RXFILT_HASH_BASE; 450 i < (SF_RXFILT_HASH_MAX + 1); i += 4) 451 csr_write_4(sc, i, 0); 452 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI); 453 454 /* Now program new ones. */ 455 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 456 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI); 457 } else { 458 i = 1; 459 TAILQ_FOREACH_REVERSE(ifma, &ifp->if_multiaddrs, ifmultihead, ifma_link) { 460 if (ifma->ifma_addr->sa_family != AF_LINK) 461 continue; 462 /* 463 * Program the first 15 multicast groups 464 * into the perfect filter. For all others, 465 * use the hash table. 466 */ 467 if (i < SF_RXFILT_PERFECT_CNT) { 468 sf_setperf(sc, i, 469 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 470 i++; 471 continue; 472 } 473 474 sf_sethash(sc, 475 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 0); 476 } 477 } 478 479 return; 480} 481 482/* 483 * Set media options. 484 */ 485static int 486sf_ifmedia_upd(ifp) 487 struct ifnet *ifp; 488{ 489 struct sf_softc *sc; 490 struct mii_data *mii; 491 492 sc = ifp->if_softc; 493 mii = device_get_softc(sc->sf_miibus); 494 sc->sf_link = 0; 495 if (mii->mii_instance) { 496 struct mii_softc *miisc; 497 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 498 mii_phy_reset(miisc); 499 } 500 mii_mediachg(mii); 501 502 return(0); 503} 504 505/* 506 * Report current media status. 507 */ 508static void 509sf_ifmedia_sts(ifp, ifmr) 510 struct ifnet *ifp; 511 struct ifmediareq *ifmr; 512{ 513 struct sf_softc *sc; 514 struct mii_data *mii; 515 516 sc = ifp->if_softc; 517 mii = device_get_softc(sc->sf_miibus); 518 519 mii_pollstat(mii); 520 ifmr->ifm_active = mii->mii_media_active; 521 ifmr->ifm_status = mii->mii_media_status; 522 523 return; 524} 525 526static int 527sf_ioctl(ifp, command, data) 528 struct ifnet *ifp; 529 u_long command; 530 caddr_t data; 531{ 532 struct sf_softc *sc = ifp->if_softc; 533 struct ifreq *ifr = (struct ifreq *) data; 534 struct mii_data *mii; 535 int error = 0; 536 537 SF_LOCK(sc); 538 539 switch(command) { 540 case SIOCSIFFLAGS: 541 if (ifp->if_flags & IFF_UP) { 542 if (ifp->if_flags & IFF_RUNNING && 543 ifp->if_flags & IFF_PROMISC && 544 !(sc->sf_if_flags & IFF_PROMISC)) { 545 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 546 } else if (ifp->if_flags & IFF_RUNNING && 547 !(ifp->if_flags & IFF_PROMISC) && 548 sc->sf_if_flags & IFF_PROMISC) { 549 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 550 } else if (!(ifp->if_flags & IFF_RUNNING)) 551 sf_init(sc); 552 } else { 553 if (ifp->if_flags & IFF_RUNNING) 554 sf_stop(sc); 555 } 556 sc->sf_if_flags = ifp->if_flags; 557 error = 0; 558 break; 559 case SIOCADDMULTI: 560 case SIOCDELMULTI: 561 sf_setmulti(sc); 562 error = 0; 563 break; 564 case SIOCGIFMEDIA: 565 case SIOCSIFMEDIA: 566 mii = device_get_softc(sc->sf_miibus); 567 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 568 break; 569 default: 570 error = ether_ioctl(ifp, command, data); 571 break; 572 } 573 574 SF_UNLOCK(sc); 575 576 return(error); 577} 578 579static void 580sf_reset(sc) 581 struct sf_softc *sc; 582{ 583 register int i; 584 585 csr_write_4(sc, SF_GEN_ETH_CTL, 0); 586 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 587 DELAY(1000); 588 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); 589 590 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_RESET); 591 592 for (i = 0; i < SF_TIMEOUT; i++) { 593 DELAY(10); 594 if (!(csr_read_4(sc, SF_PCI_DEVCFG) & SF_PCIDEVCFG_RESET)) 595 break; 596 } 597 598 if (i == SF_TIMEOUT) 599 printf("sf%d: reset never completed!\n", sc->sf_unit); 600 601 /* Wait a little while for the chip to get its brains in order. */ 602 DELAY(1000); 603 return; 604} 605 606/* 607 * Probe for an Adaptec AIC-6915 chip. Check the PCI vendor and device 608 * IDs against our list and return a device name if we find a match. 609 * We also check the subsystem ID so that we can identify exactly which 610 * NIC has been found, if possible. 611 */ 612static int 613sf_probe(dev) 614 device_t dev; 615{ 616 struct sf_type *t; 617 618 t = sf_devs; 619 620 while(t->sf_name != NULL) { 621 if ((pci_get_vendor(dev) == t->sf_vid) && 622 (pci_get_device(dev) == t->sf_did)) { 623 switch((pci_read_config(dev, 624 SF_PCI_SUBVEN_ID, 4) >> 16) & 0xFFFF) { 625 case AD_SUBSYSID_62011_REV0: 626 case AD_SUBSYSID_62011_REV1: 627 device_set_desc(dev, 628 "Adaptec ANA-62011 10/100BaseTX"); 629 return(0); 630 case AD_SUBSYSID_62022: 631 device_set_desc(dev, 632 "Adaptec ANA-62022 10/100BaseTX"); 633 return(0); 634 case AD_SUBSYSID_62044_REV0: 635 case AD_SUBSYSID_62044_REV1: 636 device_set_desc(dev, 637 "Adaptec ANA-62044 10/100BaseTX"); 638 return(0); 639 case AD_SUBSYSID_62020: 640 device_set_desc(dev, 641 "Adaptec ANA-62020 10/100BaseFX"); 642 return(0); 643 case AD_SUBSYSID_69011: 644 device_set_desc(dev, 645 "Adaptec ANA-69011 10/100BaseTX"); 646 return(0); 647 default: 648 device_set_desc(dev, t->sf_name); 649 return(0); 650 break; 651 } 652 } 653 t++; 654 } 655 656 return(ENXIO); 657} 658 659/* 660 * Attach the interface. Allocate softc structures, do ifmedia 661 * setup and ethernet/BPF attach. 662 */ 663static int 664sf_attach(dev) 665 device_t dev; 666{ 667 int i; 668 struct sf_softc *sc; 669 struct ifnet *ifp; 670 int unit, rid, error = 0; 671 672 sc = device_get_softc(dev); 673 unit = device_get_unit(dev); 674 675 mtx_init(&sc->sf_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 676 MTX_DEF | MTX_RECURSE); 677#ifndef BURN_BRIDGES 678 /* 679 * Handle power management nonsense. 680 */ 681 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 682 u_int32_t iobase, membase, irq; 683 684 /* Save important PCI config data. */ 685 iobase = pci_read_config(dev, SF_PCI_LOIO, 4); 686 membase = pci_read_config(dev, SF_PCI_LOMEM, 4); 687 irq = pci_read_config(dev, SF_PCI_INTLINE, 4); 688 689 /* Reset the power state. */ 690 printf("sf%d: chip is in D%d power mode " 691 "-- setting to D0\n", unit, 692 pci_get_powerstate(dev)); 693 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 694 695 /* Restore PCI config data. */ 696 pci_write_config(dev, SF_PCI_LOIO, iobase, 4); 697 pci_write_config(dev, SF_PCI_LOMEM, membase, 4); 698 pci_write_config(dev, SF_PCI_INTLINE, irq, 4); 699 } 700#endif 701 /* 702 * Map control/status registers. 703 */ 704 pci_enable_busmaster(dev); 705 706 rid = SF_RID; 707 sc->sf_res = bus_alloc_resource_any(dev, SF_RES, &rid, RF_ACTIVE); 708 709 if (sc->sf_res == NULL) { 710 printf ("sf%d: couldn't map ports\n", unit); 711 error = ENXIO; 712 goto fail; 713 } 714 715 sc->sf_btag = rman_get_bustag(sc->sf_res); 716 sc->sf_bhandle = rman_get_bushandle(sc->sf_res); 717 718 /* Allocate interrupt */ 719 rid = 0; 720 sc->sf_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 721 RF_SHAREABLE | RF_ACTIVE); 722 723 if (sc->sf_irq == NULL) { 724 printf("sf%d: couldn't map interrupt\n", unit); 725 error = ENXIO; 726 goto fail; 727 } 728 729 callout_handle_init(&sc->sf_stat_ch); 730 /* Reset the adapter. */ 731 sf_reset(sc); 732 733 /* 734 * Get station address from the EEPROM. 735 */ 736 for (i = 0; i < ETHER_ADDR_LEN; i++) 737 sc->arpcom.ac_enaddr[i] = 738 sf_read_eeprom(sc, SF_EE_NODEADDR + ETHER_ADDR_LEN - i); 739 740 sc->sf_unit = unit; 741 742 /* Allocate the descriptor queues. */ 743 sc->sf_ldata = contigmalloc(sizeof(struct sf_list_data), M_DEVBUF, 744 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 745 746 if (sc->sf_ldata == NULL) { 747 printf("sf%d: no memory for list buffers!\n", unit); 748 error = ENXIO; 749 goto fail; 750 } 751 752 bzero(sc->sf_ldata, sizeof(struct sf_list_data)); 753 754 /* Do MII setup. */ 755 if (mii_phy_probe(dev, &sc->sf_miibus, 756 sf_ifmedia_upd, sf_ifmedia_sts)) { 757 printf("sf%d: MII without any phy!\n", sc->sf_unit); 758 error = ENXIO; 759 goto fail; 760 } 761 762 ifp = &sc->arpcom.ac_if; 763 ifp->if_softc = sc; 764 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 765 ifp->if_mtu = ETHERMTU; 766 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 767 ifp->if_ioctl = sf_ioctl; 768 ifp->if_start = sf_start; 769 ifp->if_watchdog = sf_watchdog; 770 ifp->if_init = sf_init; 771 ifp->if_baudrate = 10000000; 772 ifp->if_snd.ifq_maxlen = SF_TX_DLIST_CNT - 1; 773 774 /* 775 * Call MI attach routine. 776 */ 777 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 778 779 /* Hook interrupt last to avoid having to lock softc */ 780 error = bus_setup_intr(dev, sc->sf_irq, INTR_TYPE_NET, 781 sf_intr, sc, &sc->sf_intrhand); 782 783 if (error) { 784 printf("sf%d: couldn't set up irq\n", unit); 785 ether_ifdetach(ifp); 786 goto fail; 787 } 788 789fail: 790 if (error) 791 sf_detach(dev); 792 793 return(error); 794} 795 796/* 797 * Shutdown hardware and free up resources. This can be called any 798 * time after the mutex has been initialized. It is called in both 799 * the error case in attach and the normal detach case so it needs 800 * to be careful about only freeing resources that have actually been 801 * allocated. 802 */ 803static int 804sf_detach(dev) 805 device_t dev; 806{ 807 struct sf_softc *sc; 808 struct ifnet *ifp; 809 810 sc = device_get_softc(dev); 811 KASSERT(mtx_initialized(&sc->sf_mtx), ("sf mutex not initialized")); 812 SF_LOCK(sc); 813 ifp = &sc->arpcom.ac_if; 814 815 /* These should only be active if attach succeeded */ 816 if (device_is_attached(dev)) { 817 sf_stop(sc); 818 ether_ifdetach(ifp); 819 } 820 if (sc->sf_miibus) 821 device_delete_child(dev, sc->sf_miibus); 822 bus_generic_detach(dev); 823 824 if (sc->sf_intrhand) 825 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand); 826 if (sc->sf_irq) 827 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq); 828 if (sc->sf_res) 829 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res); 830 831 if (sc->sf_ldata) 832 contigfree(sc->sf_ldata, sizeof(struct sf_list_data), M_DEVBUF); 833 834 SF_UNLOCK(sc); 835 mtx_destroy(&sc->sf_mtx); 836 837 return(0); 838} 839 840static int 841sf_init_rx_ring(sc) 842 struct sf_softc *sc; 843{ 844 struct sf_list_data *ld; 845 int i; 846 847 ld = sc->sf_ldata; 848 849 bzero((char *)ld->sf_rx_dlist_big, 850 sizeof(struct sf_rx_bufdesc_type0) * SF_RX_DLIST_CNT); 851 bzero((char *)ld->sf_rx_clist, 852 sizeof(struct sf_rx_cmpdesc_type3) * SF_RX_CLIST_CNT); 853 854 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 855 if (sf_newbuf(sc, &ld->sf_rx_dlist_big[i], NULL) == ENOBUFS) 856 return(ENOBUFS); 857 } 858 859 return(0); 860} 861 862static void 863sf_init_tx_ring(sc) 864 struct sf_softc *sc; 865{ 866 struct sf_list_data *ld; 867 int i; 868 869 ld = sc->sf_ldata; 870 871 bzero((char *)ld->sf_tx_dlist, 872 sizeof(struct sf_tx_bufdesc_type0) * SF_TX_DLIST_CNT); 873 bzero((char *)ld->sf_tx_clist, 874 sizeof(struct sf_tx_cmpdesc_type0) * SF_TX_CLIST_CNT); 875 876 for (i = 0; i < SF_TX_DLIST_CNT; i++) 877 ld->sf_tx_dlist[i].sf_id = SF_TX_BUFDESC_ID; 878 for (i = 0; i < SF_TX_CLIST_CNT; i++) 879 ld->sf_tx_clist[i].sf_type = SF_TXCMPTYPE_TX; 880 881 ld->sf_tx_dlist[SF_TX_DLIST_CNT - 1].sf_end = 1; 882 sc->sf_tx_cnt = 0; 883 884 return; 885} 886 887static int 888sf_newbuf(sc, c, m) 889 struct sf_softc *sc; 890 struct sf_rx_bufdesc_type0 *c; 891 struct mbuf *m; 892{ 893 struct mbuf *m_new = NULL; 894 895 if (m == NULL) { 896 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 897 if (m_new == NULL) 898 return(ENOBUFS); 899 900 MCLGET(m_new, M_DONTWAIT); 901 if (!(m_new->m_flags & M_EXT)) { 902 m_freem(m_new); 903 return(ENOBUFS); 904 } 905 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 906 } else { 907 m_new = m; 908 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 909 m_new->m_data = m_new->m_ext.ext_buf; 910 } 911 912 m_adj(m_new, sizeof(u_int64_t)); 913 914 c->sf_mbuf = m_new; 915 c->sf_addrlo = SF_RX_HOSTADDR(vtophys(mtod(m_new, caddr_t))); 916 c->sf_valid = 1; 917 918 return(0); 919} 920 921/* 922 * The starfire is programmed to use 'normal' mode for packet reception, 923 * which means we use the consumer/producer model for both the buffer 924 * descriptor queue and the completion descriptor queue. The only problem 925 * with this is that it involves a lot of register accesses: we have to 926 * read the RX completion consumer and producer indexes and the RX buffer 927 * producer index, plus the RX completion consumer and RX buffer producer 928 * indexes have to be updated. It would have been easier if Adaptec had 929 * put each index in a separate register, especially given that the damn 930 * NIC has a 512K register space. 931 * 932 * In spite of all the lovely features that Adaptec crammed into the 6915, 933 * it is marred by one truly stupid design flaw, which is that receive 934 * buffer addresses must be aligned on a longword boundary. This forces 935 * the packet payload to be unaligned, which is suboptimal on the x86 and 936 * completely unuseable on the Alpha. Our only recourse is to copy received 937 * packets into properly aligned buffers before handing them off. 938 */ 939 940static void 941sf_rxeof(sc) 942 struct sf_softc *sc; 943{ 944 struct mbuf *m; 945 struct ifnet *ifp; 946 struct sf_rx_bufdesc_type0 *desc; 947 struct sf_rx_cmpdesc_type3 *cur_rx; 948 u_int32_t rxcons, rxprod; 949 int cmpprodidx, cmpconsidx, bufprodidx; 950 951 SF_LOCK_ASSERT(sc); 952 953 ifp = &sc->arpcom.ac_if; 954 955 rxcons = csr_read_4(sc, SF_CQ_CONSIDX); 956 rxprod = csr_read_4(sc, SF_RXDQ_PTR_Q1); 957 cmpprodidx = SF_IDX_LO(csr_read_4(sc, SF_CQ_PRODIDX)); 958 cmpconsidx = SF_IDX_LO(rxcons); 959 bufprodidx = SF_IDX_LO(rxprod); 960 961 while (cmpconsidx != cmpprodidx) { 962 struct mbuf *m0; 963 964 cur_rx = &sc->sf_ldata->sf_rx_clist[cmpconsidx]; 965 desc = &sc->sf_ldata->sf_rx_dlist_big[cur_rx->sf_endidx]; 966 m = desc->sf_mbuf; 967 SF_INC(cmpconsidx, SF_RX_CLIST_CNT); 968 SF_INC(bufprodidx, SF_RX_DLIST_CNT); 969 970 if (!(cur_rx->sf_status1 & SF_RXSTAT1_OK)) { 971 ifp->if_ierrors++; 972 sf_newbuf(sc, desc, m); 973 continue; 974 } 975 976 m0 = m_devget(mtod(m, char *), cur_rx->sf_len, ETHER_ALIGN, 977 ifp, NULL); 978 sf_newbuf(sc, desc, m); 979 if (m0 == NULL) { 980 ifp->if_ierrors++; 981 continue; 982 } 983 m = m0; 984 985 ifp->if_ipackets++; 986 SF_UNLOCK(sc); 987 (*ifp->if_input)(ifp, m); 988 SF_LOCK(sc); 989 } 990 991 csr_write_4(sc, SF_CQ_CONSIDX, 992 (rxcons & ~SF_CQ_CONSIDX_RXQ1) | cmpconsidx); 993 csr_write_4(sc, SF_RXDQ_PTR_Q1, 994 (rxprod & ~SF_RXDQ_PRODIDX) | bufprodidx); 995 996 return; 997} 998 999/* 1000 * Read the transmit status from the completion queue and release 1001 * mbufs. Note that the buffer descriptor index in the completion 1002 * descriptor is an offset from the start of the transmit buffer 1003 * descriptor list in bytes. This is important because the manual 1004 * gives the impression that it should match the producer/consumer 1005 * index, which is the offset in 8 byte blocks. 1006 */ 1007static void 1008sf_txeof(sc) 1009 struct sf_softc *sc; 1010{ 1011 int txcons, cmpprodidx, cmpconsidx; 1012 struct sf_tx_cmpdesc_type1 *cur_cmp; 1013 struct sf_tx_bufdesc_type0 *cur_tx; 1014 struct ifnet *ifp; 1015 1016 ifp = &sc->arpcom.ac_if; 1017 1018 txcons = csr_read_4(sc, SF_CQ_CONSIDX); 1019 cmpprodidx = SF_IDX_HI(csr_read_4(sc, SF_CQ_PRODIDX)); 1020 cmpconsidx = SF_IDX_HI(txcons); 1021 1022 while (cmpconsidx != cmpprodidx) { 1023 cur_cmp = &sc->sf_ldata->sf_tx_clist[cmpconsidx]; 1024 cur_tx = &sc->sf_ldata->sf_tx_dlist[cur_cmp->sf_index >> 7]; 1025 1026 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_OK) 1027 ifp->if_opackets++; 1028 else { 1029 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_UNDERRUN) 1030 sf_txthresh_adjust(sc); 1031 ifp->if_oerrors++; 1032 } 1033 1034 sc->sf_tx_cnt--; 1035 if (cur_tx->sf_mbuf != NULL) { 1036 m_freem(cur_tx->sf_mbuf); 1037 cur_tx->sf_mbuf = NULL; 1038 } else 1039 break; 1040 SF_INC(cmpconsidx, SF_TX_CLIST_CNT); 1041 } 1042 1043 ifp->if_timer = 0; 1044 ifp->if_flags &= ~IFF_OACTIVE; 1045 1046 csr_write_4(sc, SF_CQ_CONSIDX, 1047 (txcons & ~SF_CQ_CONSIDX_TXQ) | 1048 ((cmpconsidx << 16) & 0xFFFF0000)); 1049 1050 return; 1051} 1052 1053static void 1054sf_txthresh_adjust(sc) 1055 struct sf_softc *sc; 1056{ 1057 u_int32_t txfctl; 1058 u_int8_t txthresh; 1059 1060 txfctl = csr_read_4(sc, SF_TX_FRAMCTL); 1061 txthresh = txfctl & SF_TXFRMCTL_TXTHRESH; 1062 if (txthresh < 0xFF) { 1063 txthresh++; 1064 txfctl &= ~SF_TXFRMCTL_TXTHRESH; 1065 txfctl |= txthresh; 1066#ifdef DIAGNOSTIC 1067 printf("sf%d: tx underrun, increasing " 1068 "tx threshold to %d bytes\n", 1069 sc->sf_unit, txthresh * 4); 1070#endif 1071 csr_write_4(sc, SF_TX_FRAMCTL, txfctl); 1072 } 1073 1074 return; 1075} 1076 1077static void 1078sf_intr(arg) 1079 void *arg; 1080{ 1081 struct sf_softc *sc; 1082 struct ifnet *ifp; 1083 u_int32_t status; 1084 1085 sc = arg; 1086 SF_LOCK(sc); 1087 1088 ifp = &sc->arpcom.ac_if; 1089 1090 if (!(csr_read_4(sc, SF_ISR_SHADOW) & SF_ISR_PCIINT_ASSERTED)) { 1091 SF_UNLOCK(sc); 1092 return; 1093 } 1094 1095 /* Disable interrupts. */ 1096 csr_write_4(sc, SF_IMR, 0x00000000); 1097 1098 for (;;) { 1099 status = csr_read_4(sc, SF_ISR); 1100 if (status) 1101 csr_write_4(sc, SF_ISR, status); 1102 1103 if (!(status & SF_INTRS)) 1104 break; 1105 1106 if (status & SF_ISR_RXDQ1_DMADONE) 1107 sf_rxeof(sc); 1108 1109 if (status & SF_ISR_TX_TXDONE || 1110 status & SF_ISR_TX_DMADONE || 1111 status & SF_ISR_TX_QUEUEDONE) 1112 sf_txeof(sc); 1113 1114 if (status & SF_ISR_TX_LOFIFO) 1115 sf_txthresh_adjust(sc); 1116 1117 if (status & SF_ISR_ABNORMALINTR) { 1118 if (status & SF_ISR_STATSOFLOW) { 1119 untimeout(sf_stats_update, sc, 1120 sc->sf_stat_ch); 1121 sf_stats_update(sc); 1122 } else 1123 sf_init(sc); 1124 } 1125 } 1126 1127 /* Re-enable interrupts. */ 1128 csr_write_4(sc, SF_IMR, SF_INTRS); 1129 1130 if (ifp->if_snd.ifq_head != NULL) 1131 sf_start(ifp); 1132 1133 SF_UNLOCK(sc); 1134 return; 1135} 1136 1137static void 1138sf_init(xsc) 1139 void *xsc; 1140{ 1141 struct sf_softc *sc; 1142 struct ifnet *ifp; 1143 struct mii_data *mii; 1144 int i; 1145 1146 sc = xsc; 1147 SF_LOCK(sc); 1148 ifp = &sc->arpcom.ac_if; 1149 mii = device_get_softc(sc->sf_miibus); 1150 1151 sf_stop(sc); 1152 sf_reset(sc); 1153 1154 /* Init all the receive filter registers */ 1155 for (i = SF_RXFILT_PERFECT_BASE; 1156 i < (SF_RXFILT_HASH_MAX + 1); i += 4) 1157 csr_write_4(sc, i, 0); 1158 1159 /* Empty stats counter registers. */ 1160 for (i = 0; i < sizeof(struct sf_stats)/sizeof(u_int32_t); i++) 1161 csr_write_4(sc, SF_STATS_BASE + 1162 (i + sizeof(u_int32_t)), 0); 1163 1164 /* Init our MAC address */ 1165 csr_write_4(sc, SF_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1166 csr_write_4(sc, SF_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1167 sf_setperf(sc, 0, (caddr_t)&sc->arpcom.ac_enaddr); 1168 1169 if (sf_init_rx_ring(sc) == ENOBUFS) { 1170 printf("sf%d: initialization failed: no " 1171 "memory for rx buffers\n", sc->sf_unit); 1172 SF_UNLOCK(sc); 1173 return; 1174 } 1175 1176 sf_init_tx_ring(sc); 1177 1178 csr_write_4(sc, SF_RXFILT, SF_PERFMODE_NORMAL|SF_HASHMODE_WITHVLAN); 1179 1180 /* If we want promiscuous mode, set the allframes bit. */ 1181 if (ifp->if_flags & IFF_PROMISC) { 1182 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 1183 } else { 1184 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); 1185 } 1186 1187 if (ifp->if_flags & IFF_BROADCAST) { 1188 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_BROAD); 1189 } else { 1190 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_BROAD); 1191 } 1192 1193 /* 1194 * Load the multicast filter. 1195 */ 1196 sf_setmulti(sc); 1197 1198 /* Init the completion queue indexes */ 1199 csr_write_4(sc, SF_CQ_CONSIDX, 0); 1200 csr_write_4(sc, SF_CQ_PRODIDX, 0); 1201 1202 /* Init the RX completion queue */ 1203 csr_write_4(sc, SF_RXCQ_CTL_1, 1204 vtophys(sc->sf_ldata->sf_rx_clist) & SF_RXCQ_ADDR); 1205 SF_SETBIT(sc, SF_RXCQ_CTL_1, SF_RXCQTYPE_3); 1206 1207 /* Init RX DMA control. */ 1208 SF_SETBIT(sc, SF_RXDMA_CTL, SF_RXDMA_REPORTBADPKTS); 1209 1210 /* Init the RX buffer descriptor queue. */ 1211 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 1212 vtophys(sc->sf_ldata->sf_rx_dlist_big)); 1213 csr_write_4(sc, SF_RXDQ_CTL_1, (MCLBYTES << 16) | SF_DESCSPACE_16BYTES); 1214 csr_write_4(sc, SF_RXDQ_PTR_Q1, SF_RX_DLIST_CNT - 1); 1215 1216 /* Init the TX completion queue */ 1217 csr_write_4(sc, SF_TXCQ_CTL, 1218 vtophys(sc->sf_ldata->sf_tx_clist) & SF_RXCQ_ADDR); 1219 1220 /* Init the TX buffer descriptor queue. */ 1221 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 1222 vtophys(sc->sf_ldata->sf_tx_dlist)); 1223 SF_SETBIT(sc, SF_TX_FRAMCTL, SF_TXFRMCTL_CPLAFTERTX); 1224 csr_write_4(sc, SF_TXDQ_CTL, 1225 SF_TXBUFDESC_TYPE0|SF_TXMINSPACE_128BYTES|SF_TXSKIPLEN_8BYTES); 1226 SF_SETBIT(sc, SF_TXDQ_CTL, SF_TXDQCTL_NODMACMP); 1227 1228 /* Enable autopadding of short TX frames. */ 1229 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_AUTOPAD); 1230 1231 /* Enable interrupts. */ 1232 csr_write_4(sc, SF_IMR, SF_INTRS); 1233 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_INTR_ENB); 1234 1235 /* Enable the RX and TX engines. */ 1236 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_RX_ENB|SF_ETHCTL_RXDMA_ENB); 1237 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_TX_ENB|SF_ETHCTL_TXDMA_ENB); 1238 1239 /*mii_mediachg(mii);*/ 1240 sf_ifmedia_upd(ifp); 1241 1242 ifp->if_flags |= IFF_RUNNING; 1243 ifp->if_flags &= ~IFF_OACTIVE; 1244 1245 sc->sf_stat_ch = timeout(sf_stats_update, sc, hz); 1246 1247 SF_UNLOCK(sc); 1248 1249 return; 1250} 1251 1252static int 1253sf_encap(sc, c, m_head) 1254 struct sf_softc *sc; 1255 struct sf_tx_bufdesc_type0 *c; 1256 struct mbuf *m_head; 1257{ 1258 int frag = 0; 1259 struct sf_frag *f = NULL; 1260 struct mbuf *m; 1261 1262 m = m_head; 1263 1264 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1265 if (m->m_len != 0) { 1266 if (frag == SF_MAXFRAGS) 1267 break; 1268 f = &c->sf_frags[frag]; 1269 if (frag == 0) 1270 f->sf_pktlen = m_head->m_pkthdr.len; 1271 f->sf_fraglen = m->m_len; 1272 f->sf_addr = vtophys(mtod(m, vm_offset_t)); 1273 frag++; 1274 } 1275 } 1276 1277 if (m != NULL) { 1278 struct mbuf *m_new = NULL; 1279 1280 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1281 if (m_new == NULL) { 1282 printf("sf%d: no memory for tx list\n", sc->sf_unit); 1283 return(1); 1284 } 1285 1286 if (m_head->m_pkthdr.len > MHLEN) { 1287 MCLGET(m_new, M_DONTWAIT); 1288 if (!(m_new->m_flags & M_EXT)) { 1289 m_freem(m_new); 1290 printf("sf%d: no memory for tx list\n", 1291 sc->sf_unit); 1292 return(1); 1293 } 1294 } 1295 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1296 mtod(m_new, caddr_t)); 1297 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1298 m_freem(m_head); 1299 m_head = m_new; 1300 f = &c->sf_frags[0]; 1301 f->sf_fraglen = f->sf_pktlen = m_head->m_pkthdr.len; 1302 f->sf_addr = vtophys(mtod(m_head, caddr_t)); 1303 frag = 1; 1304 } 1305 1306 c->sf_mbuf = m_head; 1307 c->sf_id = SF_TX_BUFDESC_ID; 1308 c->sf_fragcnt = frag; 1309 c->sf_intr = 1; 1310 c->sf_caltcp = 0; 1311 c->sf_crcen = 1; 1312 1313 return(0); 1314} 1315 1316static void 1317sf_start(ifp) 1318 struct ifnet *ifp; 1319{ 1320 struct sf_softc *sc; 1321 struct sf_tx_bufdesc_type0 *cur_tx = NULL; 1322 struct mbuf *m_head = NULL; 1323 int i, txprod; 1324 1325 sc = ifp->if_softc; 1326 SF_LOCK(sc); 1327 1328 if (!sc->sf_link && ifp->if_snd.ifq_len < 10) { 1329 SF_UNLOCK(sc); 1330 return; 1331 } 1332 1333 if (ifp->if_flags & IFF_OACTIVE) { 1334 SF_UNLOCK(sc); 1335 return; 1336 } 1337 1338 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX); 1339 i = SF_IDX_HI(txprod) >> 4; 1340 1341 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) { 1342 printf("sf%d: TX ring full, resetting\n", sc->sf_unit); 1343 sf_init(sc); 1344 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX); 1345 i = SF_IDX_HI(txprod) >> 4; 1346 } 1347 1348 while(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf == NULL) { 1349 if (sc->sf_tx_cnt >= (SF_TX_DLIST_CNT - 5)) { 1350 ifp->if_flags |= IFF_OACTIVE; 1351 cur_tx = NULL; 1352 break; 1353 } 1354 IF_DEQUEUE(&ifp->if_snd, m_head); 1355 if (m_head == NULL) 1356 break; 1357 1358 cur_tx = &sc->sf_ldata->sf_tx_dlist[i]; 1359 if (sf_encap(sc, cur_tx, m_head)) { 1360 IF_PREPEND(&ifp->if_snd, m_head); 1361 ifp->if_flags |= IFF_OACTIVE; 1362 cur_tx = NULL; 1363 break; 1364 } 1365 1366 /* 1367 * If there's a BPF listener, bounce a copy of this frame 1368 * to him. 1369 */ 1370 BPF_MTAP(ifp, m_head); 1371 1372 SF_INC(i, SF_TX_DLIST_CNT); 1373 sc->sf_tx_cnt++; 1374 /* 1375 * Don't get the TX DMA queue get too full. 1376 */ 1377 if (sc->sf_tx_cnt > 64) 1378 break; 1379 } 1380 1381 if (cur_tx == NULL) { 1382 SF_UNLOCK(sc); 1383 return; 1384 } 1385 1386 /* Transmit */ 1387 csr_write_4(sc, SF_TXDQ_PRODIDX, 1388 (txprod & ~SF_TXDQ_PRODIDX_HIPRIO) | 1389 ((i << 20) & 0xFFFF0000)); 1390 1391 ifp->if_timer = 5; 1392 1393 SF_UNLOCK(sc); 1394 1395 return; 1396} 1397 1398static void 1399sf_stop(sc) 1400 struct sf_softc *sc; 1401{ 1402 int i; 1403 struct ifnet *ifp; 1404 1405 SF_LOCK(sc); 1406 1407 ifp = &sc->arpcom.ac_if; 1408 1409 untimeout(sf_stats_update, sc, sc->sf_stat_ch); 1410 1411 csr_write_4(sc, SF_GEN_ETH_CTL, 0); 1412 csr_write_4(sc, SF_CQ_CONSIDX, 0); 1413 csr_write_4(sc, SF_CQ_PRODIDX, 0); 1414 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 0); 1415 csr_write_4(sc, SF_RXDQ_CTL_1, 0); 1416 csr_write_4(sc, SF_RXDQ_PTR_Q1, 0); 1417 csr_write_4(sc, SF_TXCQ_CTL, 0); 1418 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 0); 1419 csr_write_4(sc, SF_TXDQ_CTL, 0); 1420 sf_reset(sc); 1421 1422 sc->sf_link = 0; 1423 1424 for (i = 0; i < SF_RX_DLIST_CNT; i++) { 1425 if (sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf != NULL) { 1426 m_freem(sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf); 1427 sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf = NULL; 1428 } 1429 } 1430 1431 for (i = 0; i < SF_TX_DLIST_CNT; i++) { 1432 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) { 1433 m_freem(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf); 1434 sc->sf_ldata->sf_tx_dlist[i].sf_mbuf = NULL; 1435 } 1436 } 1437 1438 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 1439 SF_UNLOCK(sc); 1440 1441 return; 1442} 1443 1444/* 1445 * Note: it is important that this function not be interrupted. We 1446 * use a two-stage register access scheme: if we are interrupted in 1447 * between setting the indirect address register and reading from the 1448 * indirect data register, the contents of the address register could 1449 * be changed out from under us. 1450 */ 1451static void 1452sf_stats_update(xsc) 1453 void *xsc; 1454{ 1455 struct sf_softc *sc; 1456 struct ifnet *ifp; 1457 struct mii_data *mii; 1458 struct sf_stats stats; 1459 u_int32_t *ptr; 1460 int i; 1461 1462 sc = xsc; 1463 SF_LOCK(sc); 1464 ifp = &sc->arpcom.ac_if; 1465 mii = device_get_softc(sc->sf_miibus); 1466 1467 ptr = (u_int32_t *)&stats; 1468 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++) 1469 ptr[i] = csr_read_4(sc, SF_STATS_BASE + 1470 (i + sizeof(u_int32_t))); 1471 1472 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++) 1473 csr_write_4(sc, SF_STATS_BASE + 1474 (i + sizeof(u_int32_t)), 0); 1475 1476 ifp->if_collisions += stats.sf_tx_single_colls + 1477 stats.sf_tx_multi_colls + stats.sf_tx_excess_colls; 1478 1479 mii_tick(mii); 1480 1481 if (!sc->sf_link && mii->mii_media_status & IFM_ACTIVE && 1482 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1483 sc->sf_link++; 1484 if (ifp->if_snd.ifq_head != NULL) 1485 sf_start(ifp); 1486 } 1487 1488 sc->sf_stat_ch = timeout(sf_stats_update, sc, hz); 1489 1490 SF_UNLOCK(sc); 1491 1492 return; 1493} 1494 1495static void 1496sf_watchdog(ifp) 1497 struct ifnet *ifp; 1498{ 1499 struct sf_softc *sc; 1500 1501 sc = ifp->if_softc; 1502 1503 SF_LOCK(sc); 1504 1505 ifp->if_oerrors++; 1506 printf("sf%d: watchdog timeout\n", sc->sf_unit); 1507 1508 sf_stop(sc); 1509 sf_reset(sc); 1510 sf_init(sc); 1511 1512 if (ifp->if_snd.ifq_head != NULL) 1513 sf_start(ifp); 1514 1515 SF_UNLOCK(sc); 1516 1517 return; 1518} 1519 1520static void 1521sf_shutdown(dev) 1522 device_t dev; 1523{ 1524 struct sf_softc *sc; 1525 1526 sc = device_get_softc(dev); 1527 1528 sf_stop(sc); 1529 1530 return; 1531} 1532